S32K3XX

S32K3xx Data Sheet

Supports S32K344, S32K324, S32K314, S32K312, S32K311, S32K310,
S32K341, S32K342, S32K322, S32K328, S32K338, S32K348, S32K358 and
S32K388. Data is preliminary for S32K389
Rev. 10 — 07/2024 Data Sheet: Technical Data

• Operating characteristics • Memory and memory interfaces

— Voltage range: 2.97 V to 5.5 V — Up to 12 MB program flash memory with ECC
— Ambient temperature range: -40 °C to 125 °C for all — Up to 256 KB of flexible program or data flash
power modes memory
• Arm™ Cortex-M7 core, 32-bit CPU — Up to 2304 KB SRAM with ECC, includes 384 KB
of TCM RAM ensuring maximum CPU performance
— M7 supports up to 320 MHz frequency with 2.14
of fast control loops with minimal latency
DMIPS / MHz
— Data and instruction cache for each core to
— Arm Core based on the Armv7 and Thumb®-2 ISA
minimize performance impact of memory access
— Integrated Digital Signal Processor (DSP) latencies
— Configurable Nested Vectored Interrupt Controller — QuadSPI support
(NVIC)
• Mixed-signal analog
— Single Precision Floating Point Unit (FPU)
— Up to three 12-bit Analog-to-Digital Converters
• Clock interfaces (ADC) with up to 24 channel analog inputs per
— 8 - 40 MHz Fast External Oscillator (FXOSC) module

— 48 MHz Fast Internal RC oscillator (FIRC) — One Temperature Sensor (TempSense)

— 32 kHz Low Power Oscillator (SIRC) — Up to three Analog Comparators (CMP), with each
comparator having an internal 8-bit DAC
— 32 kHz Slow External Oscillator (SXOSC)
• Human-Machine Interface (HMI)
— System Phased Lock Loop (SPLL)
— Up to 320 GPIO pins
• I/O and package
— Non-Maskable Interrupt (NMI)
— MAPBGA437 , LQFP48, HDQFP100, HDQFP172,
MAPBGA257, MAPBGA289, HDQFP172 with — Up to 60 pins with wakeup capability
Exposed pad (EP) package options — Up to 32 pins with interrupt support
• Up to 32-channel DMA with up to 128 request sources
using DMAMUX

NXP reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products.
NXP Semiconductors

• Power management • Debug functionality

— Low-power Arm Cortex-M7 core with excellent — Serial Wire JTAG debug Port (SWJ-DP), with 2 pin
energy efficiency, balanced with performance Serial Wire Debug (SWD) for external debugger
— Power Management Controller (PMC) with — Debug Watchpoint and Trace (DWT), with four
simplified mode management (RUN and configurable comparators as hardware watchpoints
STANDBY)
— Serial Wire Output (SWO)-synchronous trace data
— Supports peripheral specific clock gating. Only support
specific peripherals remain working in low power
— Instrumentation Trace Macrocell (ITM) with
modes.
software and hardware trace, plus time stamping
• Communications interfaces
— CoreSight AHB Trace Macrocell (HTM)
— Up to 16 serial communication interface (LPUART)
— Flash Patch and Breakpoints (FPB) with ability to
modules, with LIN, UART and DMA support
patch code and data from code space to system
— Up to six Low Power Serial Peripheral Interface space
(LPSPI) modules with DMA support
— Serial Wire Viewer (SWV): A trace capability
— Up to two Low Power Inter-Integrated Circuit providing displays of reads, writes, exceptions, PC
(LPI2C) modules with DMA support Samples and print
— Up to twelve FlexCAN modules (with optional CAN- — Full data trace for up to 16 output wide
FD support)
— Embedded Cross Trigger (ECT) is used for
— FlexIO module for flexible and high performance multicore run-control and trace cross triggering,
serial interfaces using CoreSight Cross Trigger Interface (CTI)
— Up to two Ethernet modules • Timing and control
— Up to two Synchronous Audio Interface (SAI) — Up to three enhanced modular I/O system (eMIOS),
modules offering up to 72 timer channels (IC/OC/PWM)
• Reliability, safety and security — Up to two System Timer Modules (STM)
— Hardware Security Engine (HSE_B) - Supports AES — Up to two Logic Control Units (LCU)
accelerator(for K388 and K389 only)
— Full cross triggering support for ADC / timer (BCTU)
— Up to two Internal Software Watchdog Timers
— One Trigger MUX Control (TRGMUX) module
(SWT)
— Up to three Periodic Interrupt Timer (PIT) modules
— Error-Correcting Code (ECC) on all memories
— 32-bit Real Time Counter (RTC) with autonomous
— Error Detection Code (EDC) on data path
periodic interrupt (API) function
— Cyclic Redundancy Check (CRC) module
— 120-bit Unique Identification (ID) number
— Extended Cross domain Domain Controller
(XRDC), providing protection for master core
access rights
— Virtualization Wrapper (VIRT_WRAPPER),
providing I/O protection

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 2 / 152
 Contents

1 Overview............................................................ 5 10 Analog modules................................................84

2 Block diagram.....................................................5 10.1 SAR_ADC..................................................... 84
3 Feature comparison......................................... 12 10.2 Supply Diagnosis.......................................... 86
4 Ordering information.........................................19 10.3 Low Power Comparator (LPCMP)................ 86
4.1 Determining valid orderable parts ................ 19 10.4 Temperature Sensor..................................... 90
5 General.............................................................19 11 Clocking modules............................................. 91
5.1 Absolute maximum ratings............................20 11.1 FIRC..............................................................91
5.2 Voltage and current operating requirements.22 11.2 SIRC............................................................. 91
5.3 Thermal operating characteristics................. 24 11.3 PLL................................................................91
5.4 ESD and Latch-up Protection Characteristics 11.4 FXOSC..........................................................93
...................................................................... 24 11.5 SXOSC......................................................... 95
6 Power management......................................... 25 12 Communication interfaces................................96
6.1 Power mode transition operating behaviors..25 12.1 LPSPI............................................................96
6.1.1 Power mode transition operating behavior... 25 12.2 LPSPI0 20 MHz and 15 MHz Combinations101
6.1.2 Boot time, HSE firmware not installed.......... 26 12.3 LPSPI2 and LPSPI5 20MHz combination for
6.1.3 Boot time, HSE firmware installed................ 26 S32K388 and S32K389.............................. 101
6.1.4 HSE firmware memory verification time 12.4 Communication between two S32K388
examples.......................................................27 devices........................................................102
6.2 Supply Monitoring......................................... 31 12.4.1 Timing specification for S32K388 to S32K388
6.3 Recommended Decoupling Capacitors........ 33 communication............................................104
6.3.1 Recommended Decoupling Capacitor 12.5 I2C............................................................... 104
diagrams....................................................... 34 12.6 FlexCAN characteristics..............................104
6.4 V15 regulator (SMPS option) electrical 12.7 SAI electrical specifications........................ 104
specifications................................................ 48 12.7.1 SAI Electrical Characteristics, Slave Mode. 105
6.5 V15 regulator (BJT option, NPN ballast 12.7.2 SAI Electrical Characteristics, Master Mode106
transistor control) electrical specifications.... 49 12.8 Ethernet characteristics.............................. 107
6.6 V11 regulator (NMOS ballast transistor control) 12.8.1 Ethernet MII (10/100 Mbps)........................ 107
electrical specifications................................. 50 12.8.2 Ethernet MII (200 Mbps)............................. 109
6.7 Supply currents............................................. 50 12.8.3 Ethernet RMII (10/100 Mbps)......................111
6.8 Operating mode............................................ 64 12.8.4 Ethernet RGMII........................................... 113
6.9 Cyclic wake-up current .................................66 12.8.5 MDIO timing specifications......................... 114
7 I/O parameters................................................. 67 12.9 QuadSPI..................................................... 115
7.1 GPIO DC electrical specifications, 3.3V Range 12.9.1 QuadSPI Quad 3.3V SDR 120MHz............ 115
(2.97V - 3.63V)..............................................67 12.9.2 QuadSPI Octal 3.3V DDR 100MHz............ 117
7.2 GPIO DC electrical specifications, 5.0V (4.5V - 12.9.3 QuadSPI Quad 3.3V SDR 103.33MHz....... 118
5.5V)............................................................. 71 12.9.4 QuadSPI Octal 3.3V DDR 120MHz............ 119
7.3 5.0V (4.5V - 5.5V) GPIO Output AC 12.9.5 QuadSPI Quad 3.3V SDR 125MHz............ 120
Specification..................................................75 12.10 uSDHC........................................................121
7.4 3.3V (2.97V - 3.63V) GPIO Output AC 12.10.1 uSDHC SDR electrical specifications......... 121
Specification..................................................77 12.10.2 uSDHC DDR electrical specifications......... 123
8 Glitch Filter....................................................... 79 12.11 LPUART specifications............................... 124
9 Flash memory specification.............................. 79 13 Debug modules.............................................. 124
9.1 Flash memory program and erase 13.1 Debug trace timing specifications............... 124
specifications................................................ 79 13.2 SWD electrical specifications...................... 125
9.2 Flash memory Array Integrity and Margin Read 13.3 JTAG electrical specifications..................... 127
specifications................................................ 80 14 Thermal Attributes.......................................... 129
9.3 Flash memory module life specifications...... 81 14.1 Description.................................................. 129
9.3.1 Data retention vs program/erase cycles....... 82 14.2 Thermal characteristics............................... 129
9.4 Flash memory AC timing specifications........ 82 15 Dimensions.....................................................132
9.5 Flash memory read timing parameters......... 83 15.1 Obtaining package dimensions...................132
16 Revision history.............................................. 132 Chapter Legal information............................................149
NXP Semiconductors
Overview

1 Overview
The S32K3xx product series further extends the highly-scalable portfolio of Arm ® Cortex ® - M0+/M4F S32K1xx chips in the
automotive industry with the Arm Cortex-M7 core at higher frequency, more memory, ASIL-B and D rating and advanced security
module. With a focus on automotive environment robustness, the S32K3xx product series devices are well suited to a wide range
of applications in electrical harsh environments, and are optimized for cost-sensitive applications offering new, space saving
package options. The S32K3xx series offers a broad range of memory, peripherals and performance options. Devices in this
series share common peripherals and pin-out, allowing developers to migrate easily within a chip series or among other chip series
to take advantage of more memory or feature integration.

CAUTION
S32K389 specific information is preliminary until this device is qualified and may change without notice.

2 Block diagram
The following figures show the S32K3xx product series block diagrams:

Memory CPU Platform Security: HSE-B

512 KB Pflash with ECC
Security
Cortex-M0+ RAM • HW accl for AES 256,
Cortex-M7
64 KB Dflash with ECC Single RSA 4096, ECC 521
Asymmetric Hardware Accelerators
120Mhz • Firmware included,
112 KB RAM with ECC
Core
FPU, DSP upgradable
include 96 KB TCM Symmetric Hardware Accelerators
I-Cache • Side-channel physical
D-cache
XRDC Lifecycle protection
System Access control Management • Meet Evita Full
FXOSC (8-40MHz) Fabric TRNG/PRNG function goal
Xbar (64bit)
FIRC (48MHz)

Network Communication Analog/Timers Functional Safety

SIRC (32KHz)
Safety
16ch FlexIO 2 x 24ch 12bit ADC
Emulating
• HW redundancy
PLL UART, I2C, SPI, BCTU (Body Control Trigger Unit) • MBIST/LBIST/Self Test
I2S, SENT, PWM CMU FCCU • Clock/Voltage monitor
12ch DMA LCU (Logic Control Unit) • Centralized error
3 x FlexCAN, 4 x LPSPI MPU SWT
all ch support CAN FD
2x24ch 16bit eMIOS Timer detection
32ch ext. INT/WKUP
2 x LPI2C EIM/ERM CRC STCU • ASIL B compliant
1 x LPCMP 32bit RTC
Debug/Trace (SWD/JTAG/ETB) 4 x LPUART (LIN)

CPU Platform Network/ Motor Control

Memory • Scalable Arm M7 • Future Proof Security/OTA
• OTA ready - core in lockstep Communication • On-chip motor
• ISO26262 Compliant Safety System
• CAN/ CAN FD, LIN control sub-
RWW, A/B swap • Optimized for Real- • Scalable Arm platform
• Flexible IO emulation system
time with zero wait • Optimized for LOW power
• Offloading CPU
I/D-TCM • Rich Network/Communication Interface

Figure 1. S32K310: ASIL B Single Core 512 KB General Purpose MCU

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NXP Semiconductors
Block diagram

Memory CPU Platform Security: HSE-B

1 MB Pflash with ECC Cortex-M0+ RAM

Cortex-M7
Security
64 kB Dflash with ECC
120 MHz Asymmetric Hardware Accelerators
Single Core • HW accl for AES 256,
128 kB RAM with ECC
FPU, DSP RSA 4096, ECC 521
Include 96 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache upgradable
D-cache • Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

Network Communication Analog/Timers Functional Safety

SIRC (32 KHz) 16 ch FlexIO Safety

Emulating 2 x 24 ch 12 bit ADC
UART, I2C, SPI
PLL • HW redundancy
I2S, SENT, PWM
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
• Clock/Voltage monitor
12ch DMA 3 x FlexCAN • Centralized error
all ch support CAN FD 4 x LPSPI LCU (Logic Control Unit) MPU SWT
detection
• ASIL B compliant
32ch ext. INT/WKUP 2 x LPI2C 2 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2

4 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 1 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Single Arm M7 • CAN/CAN FD, LIN • On-chip motor • Future Proof Security/OTA
RWW, A/B swap core • Flexible IO emulation control subsystem • ISO26262 Compliant Safety System
• Optimized for Real- • Offloading CPU • Scalable Arm platform
time with zero wait • Optimized for LOW power
I/D-TCM • Rich Network/Communication Interface

Figure 2. S32K311: ASIL B Single Core 1MB General Purpose MCU

Memory CPU Platform Security: HSE-B

2 MB Pflash with ECC Cortex-M0+ RAM

Cortex-M7
Security
128 kB Dflash with ECC
120 MHz Asymmetric Hardware Accelerators
Single Core • HW accl for AES 256,
192 kB RAM with ECC
FPU, DSP RSA 4096, ECC 521
Include 96 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache upgradable
D-cache • Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

Emulating 2 x 24 ch 12 bit ADC
UART, I2C, SPI
PLL • HW redundancy
I2S, SENT, PWM
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
• Clock/Voltage monitor
12ch DMA 6 x FlexCAN • Centralized error
all ch support CAN FD 4 x LPSPI LCU (Logic Control Unit) MPU SWT
detection
• ASIL B compliant
32ch ext. INT/WKUP 2 x LPI2C 2 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2

8 x LPUART (LIN) 32-bit RTC

Debug/Trace (SWD/JTAG/ETB) 2 x LPCMP

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Single Arm M7 • CAN/CAN FD, LIN • On-chip motor • Future Proof Security/OTA
RWW, A/B swap core • Flexible IO emulation control subsystem • ISO26262 Compliant Safety System
• Optimized for Real- • Offloading CPU • Scalable Arm platform
time with zero wait • Optimized for LOW power
I/D-TCM • Rich Network/Communication Interface

Figure 3. S32K312: ASIL B Single Core 2MB General Purpose MCU

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NXP Semiconductors
Block diagram

Memory External Memory IF CPU Platform Security: HSE-B

2 MB Pflash with ECC 1 x QuadSPI Cortex-M0+ RAM

Cortex-M7 Cortex-M7
Security
128 kB Dflash with ECC Up to 480 Mbps 160 MHz 160 MHz Asymmetric Hardware Accelerators
4 bit data width Dual Core
256 kB RAM with ECC • HW accl for AES 256,
FPU, DSP FPU, DSP RSA 4096, ECC 521
Include 192 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache I-cache
upgradable
D-cache D-cache
• Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 100 Mbps
Emulating 2 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
PLL I2S, SENT, PWM • HW redundancy
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
• Clock/Voltage monitor
32ch DMA 4 x FlexCAN 4 x LPSPI • Centralized error
all ch support CAN FD LCU (Logic Control Unit) MPU SWT
detection
2 x LPI2C
• ASIL B compliant
32ch ext. INT/WKUP 2 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2
2 x SAI (TDM, I2S)
4 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 2 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Two independent • Ethernet (TSN), CAN/ • On-chip motor • Future Proof Security/OTA
RWW, A/B swap Arm M7 cores CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • Optimized for Real- • SAI for Audio • Offloading CPU • Scalable Arm platform
Flash/Ram time with zero wait • Flexible IO emulation • Optimized for LOW power
expansion by I/D-TCM • Rich Network/Communication Interface
QuadSPI

Figure 4. S32K322: ASIL B Dual Core 2MB General Purpose MCU

Memory External Memory IF CPU Platform Security: HSE-B

1 MB Pflash with ECC 1 x QuadSPI Cortex-M0+ RAM

Cortex-M7 Cortex-M7
Security
128 kB Dflash with ECC Up to 480 Mbps 160 MHz 160 MHz Asymmetric Hardware Accelerators
4 bit data width Lockstep Core
256 kB RAM with ECC • HW accl for AES 256,
FPU, DSP FPU, DSP RSA 4096, ECC 521
Include 192 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache I-cache upgradable
D-cache D-cache • Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 100 Mbps
Emulating 2 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
PLL I2S, SENT, PWM • HW redundancy
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
• Clock/Voltage monitor
32ch DMA 4 x FlexCAN 4 x LPSPI • Centralized error
all ch support CAN FD LCU (Logic Control Unit) MPU SWT
detection
2 x LPI2C
• ASIL D compliant
32ch ext. INT/WKUP 2 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2
2 x SAI (TDM, I2S)
4 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 2 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Scalable Arm M7 • Ethernet (TSN), CAN/ • On-chip motor • Future Proof Security/OTA
RWW, A/B swap core in Lockstep CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • Optimized for Real- • SAI for Audio • Offloading CPU • Scalable Arm platform
Flash/Ram time with zero wait • Flexible IO emulation • Optimized for LOW power
expansion by I/D-TCM • Rich Network/Communication Interface
QuadSPI

Figure 5. S32K341: ASIL D Lockstep Core 1MB General Purpose MCU

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NXP Semiconductors
Block diagram

Memory External Memory IF CPU Platform Security: HSE-B

2 MB Pflash with ECC 1 x QuadSPI Cortex-M0+ RAM

Cortex-M7 Cortex-M7
Security
128 kB Dflash with ECC Up to 480 Mbps 160 MHz 160 MHz Asymmetric Hardware Accelerators
4 bit data width Lockstep Core
256 kB RAM with ECC • HW accl for AES 256,
FPU, DSP FPU, DSP RSA 4096, ECC 521
Include 192 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache I-cache upgradable
D-cache D-cache • Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 100 Mbps
Emulating 2 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
PLL I2S, SENT, PWM • HW redundancy
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
• Clock/Voltage monitor
32ch DMA 4 x FlexCAN 4 x LPSPI • Centralized error
all ch support CAN FD LCU (Logic Control Unit) MPU SWT
detection
2 x LPI2C
• ASIL D compliant
32ch ext. INT/WUP 2 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2
2 x SAI (TDM, I2S)
4 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 2 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Scalable Arm M7 • Ethernet (TSN), CAN/ • On-chip motor • Future Proof Security/OTA
RWW, A/B swap core in Lockstep CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • Optimized for Real- • SAI for Audio • Offloading CPU • Scalable Arm platform
Flash/Ram time with zero wait • Flexible IO emulation • Optimized for LOW power
expansion by I/D-TCM • Rich Network/Communication Interface
QuadSPI

Figure 6. S32K342: ASIL D Lockstep Core 2MB General Purpose MCU

Memory External Memory IF CPU Platform Security: HSE-B

4 MB Pflash with ECC 1 x QuadSPI Cortex-M0+ RAM

Cortex-M7
Security
128 kB Dflash with ECC Up to 480 Mbps 160 MHz Asymmetric Hardware Accelerators
4 bit data width Single Core
512 kB RAM with ECC • HW accl for AES 256,
FPU, DSP RSA 4096, ECC 521
Include 96 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache upgradable
D-cache • Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 100 Mbps
Emulating 3 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
PLL • HW redundancy
I2S, SENT, PWM
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
• Clock/Voltage monitor
32ch DMA 6 x FlexCAN • Centralized error
all ch support CAN FD 6 x LPSPI LCU (Logic Control Unit) MPU SWT
detection
• ASIL B compliant
32ch ext. INT/WKUP 2 x LPI2C 3 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2

16 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 2 x SAI (TDM, I2S) 3 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Single Arm M7 • Ethernet (TSN), CAN/ • On-chip motor • Future Proof Security/OTA
RWW, A/B swap core CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • Optimized for Real- • SAI for Audio • Offloading CPU • Scalable Arm platform
Flash/Ram time with zero wait • Flexible IO emulation • Optimized for LOW power
expansion by I/D-TCM • Rich Network/Communication Interface
QuadSPI

Figure 7. S32K314: ASIL B Single Core 4MB General Purpose MCU

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NXP Semiconductors
Block diagram

Memory External Memory IF CPU Platform Security: HSE-B

4 MB Pflash with ECC 1 x QuadSPI Cortex-M0+ RAM

Cortex-M7 Cortex-M7 Security
128 kB Dflash with ECC Up to 480 Mbps 160 MHz 160 MHz Asymmetric Hardware Accelerators
4 bit data width Dual Core
512 kB RAM with ECC • HW accl for AES 256,
FPU, DSP FPU, DSP RSA 4096, ECC 521
Include 192 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache I-cache upgradable
D-cache D-cache • Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 100 Mbps
Emulating 3 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
PLL • HW redundancy
I2S, SENT, PWM
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
• Clock/Voltage monitor
32ch DMAMUX 6 x FlexCAN • Centralized error
all ch support CAN FD 6 x LPSPI LCU (Logic Control Unit) MPU SWT
detection
• ASIL B compliant
32ch ext. INT/WKUP 2 x LPI2C 3 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2

16 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 2 x SAI (TDM, I2S) 3 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Two independent • Ethernet (TSN), CAN/ • On-chip motor • Future Proof Security/OTA
RWW, A/B swap Arm M7 cores CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • Optimized for Real- • SAI for Audio • Offloading CPU • Scalable Arm platform
Flash/Ram time with zero wait • Flexible IO emulation • Optimized for LOW power
expansion by I/D-TCM • Rich Network/Communication Interface
QuadSPI

Figure 8. S32K324: ASIL B Dual Core 4MB General Purpose MCU

Memory External Memory IF CPU Platform Security: HSE-B

4 MB Pflash with ECC 1 x QuadSPI Cortex-M0+ RAM

Cortex-M7 Cortex-M7
Security
128 kB Dflash with ECC Up to 480 Mbps 160 MHz 160 MHz Asymmetric Hardware Accelerators
4 bit data width Lockstep Core
512 kB RAM with ECC • HW accl for AES 256,
FPU, DSP FPU, DSP RSA 4096, ECC 521
Include 192 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache I-cache upgradable
D-cache D-cache • Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 100 Mbps
Emulating 3 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
PLL • HW redundancy
I2S, SENT, PWM
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
• Clock/Voltage monitor
32ch DMA and DMAMUX 6 x FlexCAN • Centralized error
all ch support CAN FD 6 x LPSPI LCU(Logic Control Unit) MPU SWT
detection
• ASIL D compliant
32ch ext. INT/WUP 2 x LPI2C 3 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2

16 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 2 x SAI (TDM, I2S) 3 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Scalable Arm M7 • Ethernet (TSN), CAN/ On-chip motor • Future Proof Security/OTA
RWW, A/B swap core in Lockstep CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • Optimized for Real- • SAI for Audio Offloading CPU • Scalable Arm platform
Flash/Ram time with zero wait • Flexible IO emulation • Optimized for LOW power
expansion by I/D-TCM • Rich Network/Communication Interface
QuadSPI

Figure 9. S32K344: ASIL D Lockstep Core 4MB General Purpose MCU

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 9 / 152
NXP Semiconductors
Block diagram

Memory External Memory IF CPU Platform Security: HSE-B

8 MB Pflash with ECC Cortex-M0+ RAM

1 x QuadSPI Cortex-M7 Cortex-M7
Security
128 kB Dflash with ECC Up to 2 Gbps 240 MHz
240 MHz Asymmetric Hardware Accelerators
1152 kB RAM with ECC 8 bit data width • HW accl for AES 256,
FPU, DSP FPU, DSP RSA 4096, ECC 521
Include 192 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache I-cache upgradable
D-cache D-cache • Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 1 Gbps
Emulating 3 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
2 x PLL I2S, SENT, PWM • HW redundancy
1 x uSDHC BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
• Clock/Voltage monitor
32ch DMAMUX 6 x LPSPI • Centralized error
LCU (Logic Control Unit) MPU SWT
8 x FlexCAN detection
2 x LPI2C
all ch support CAN FD • ASIL B compliant
32ch ext. INT/WKUP 3 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2
2 x SAI (TDM, I2S)
16 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 3 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Two independent • Ethernet (TSN), CAN/ • On-chip motor • Future Proof Security/OTA
RWW, A/B swap Arm M7 cores CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • Optimized for Real- • SAI for Audio • Offloading CPU • Scalable Arm platform
Flash/Ram time with zero wait • Flexible IO emulation • Optimized for LOW power
expansion by I/D-TCM • Rich Network/Communication Interface
QuadSPI

Figure 10. S32K328: ASIL B Dual Core 8MB General Purpose MCU

Memory External Memory IF CPU Platform Security: HSE-B

8 MB Pflash with ECC Cortex-M0+ RAM

1 x QuadSPI Cortex-M7 Cortex-M7 Cortex-M7
Security
128 kB Dflash with ECC Up to 2 Gbps
240 MHz 240 MHz 240 MHz Asymmetric Hardware Accelerators
8 bit data width • HW accl for AES 256,
1152 kB RAM with ECC
FPU, DSP FPU, DSP FPU, DSP RSA 4096, ECC 521
Include 384 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache I-cache I-cache upgradable
D-cache D-cache D-cache • Side-channel physical
System protection
XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 1 Gbps
Emulating 3 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
2 x PLL I2S, SENT, PWM • HW redundancy
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
1 x uSDHC
• Clock/Voltage monitor
32ch DMA and DMAMUX 6 x LPSPI • Centralized error
LCU (Logic Control Unitl MPU SWT
8 x FlexCAN detection
all ch support CAN FD 2 x LPI2C
• ASIL D compliant
32ch ext. INT/WKUP 3 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2
2 x SAI (TDM, I2S)
16 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 3 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Three independent • Ethernet (TSN), CAN/ • On-chip motor • Future Proof Security/OTA
RWW, A/B swap Arm M7 cores CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • Optimized for Real- • SAI for Audio • Offloading CPU • Scalable Arm platform
Flash/Ram time with zero wait • Flexible IO emulation • Optimized for LOW power
expansion by I/D-TCM • Rich Network/Communication Interface
QuadSPI

Figure 11. S32K338: ASIL B Three Core 8MB General Purpose MCU

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 10 / 152
NXP Semiconductors
Block diagram

Memory External Memory IF CPU Platform Security: HSE-B

8 MB Pflash with ECC Cortex-M0+ RAM

1 x QuadSPI Cortex-M7 Cortex-M7
Security
128 kB Dflash with ECC Up to 2 Gbps 240 MHz 240 MHz Asymmetric Hardware Accelerators
1152 kB RAM with ECC 8 bit data width • HW accl for AES 256,
FPU, DSP FPU, DSP RSA 4096, ECC 521
Include 192 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache I-cache upgradable
D-cache D-cache • Side-channel physical
System protection
Lockstep Core XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 1 Gbps
Emulating 3 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
2 x PLL I2S, SENT, PWM • HW redundancy
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
1 x uSDHC
• Clock/Voltage monitor
32ch DMA and DMAMUX 6 x LPSPI • Centralized error
LCU (Logic Control Unit) MPU SWT
8 x FlexCAN detection
2 x LPI2C
all ch support CAN FD • ASIL D compliant
32ch ext. INT/WKUP 3 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2
2 x SAI (TDM, I2S)
16 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 3 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Arm M7 cores in • Ethernet (TSN), CAN/ • On-chip motor • Future Proof Security/OTA
RWW, A/B swap lockstep CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • Optimized for Real- • SAI for Audio • Offloading CPU • Scalable Arm platform
Flash/Ram time with zero wait • Flexible IO emulation • Optimized for LOW power
expansion by I/D-TCM • Rich Network/Communication Interface
QuadSPI

Figure 12. S32K348: ASIL D Lockstep Core 8MB General Purpose MCU

Memory External Memory IF CPU Platform Security: HSE-B

8 MB Pflash with ECC Cortex-M0+ RAM

1 x QuadSPI Cortex-M7 Cortex-M7 Cortex-M7
Security
128 kB Dflash with ECC Upto 2 Gbps
8 bit data width 240 MHz 240 MHz 240 MHz Asymmetric Hardware Accelerators
1152 kB RAM with ECC • HW accl for AES 256,
FPU, DSP FPU, DSP FPU, DSP RSA 4096, ECC 521
Include 384 kB TCM Symmetric Hardware Accelerators
• Firmware included,
I-cache I-cache I-cache upgradable
D-cache D-cache D-cache • Side-channel physical
System protection
Lockstep Core XRDC Lifecycle • Meet Evita Full
Access control Management function goal
FXOSC (8-40 MHz)
Fabric
Xbar (64 bit) TRNG/PRNG
FIRC (48 MHz)

SIRC (32 kHz) Network Communication Analog/Timers Functional Safety

SXOSC (32 kHz) 32 ch FlexIO Safety

1 x Ethernet, 1 Gbps
Emulating 3 x 24 ch 12 bit ADC
AVB/TSN
UART, I2C, SPI
2 x PLL I2S, SENT, PWM • HW redundancy
BCTU (Body Control Trigger Unit) CMU FCCU • MBIST/LBIST/Self Test
1 x uSDHC
• Clock/Voltage monitor
32ch DMA 6 x LPSPI • Centralized error
LCU (Logic Control Unit) MPU SWT
8 x FlexCAN detection
2 x LPI2C
all ch support CAN FD • ASIL D compliant
32ch ext. INT/WKUP 3 x 24 ch 16 bit eMIOS Timer EIM/ERM CRC STCU2
2 x SAI (TDM, I2S)
16 x LPUART (LIN)
Debug/Trace (SWD/JTAG/ETB) 3 x LPCMP 32 bit RTC

Memory CPU Platform Network/ Motor Control

Communication
• OTA ready - • Arm M7 cores in • Ethernet (TSN), CAN/ • On-chip motor • Future Proof Security/OTA
RWW, A/B swap lockstep CAN FD, LIN control subsystem • ISO26262 Compliant Safety System
• External • One independent • SAI for Audio • Offloading CPU • Scalable Arm platform
Flash/Ram Arm M7 for real • Flexible IO emulation • Optimized for LOW power
expansion by time processing • Rich Network/Communication Interface
QuadSPI • Optimized for Real-
time with zero wait
I/D-TCM

Figure 13. S32K358: ASIL D Lockstep Core + One, 8MB General Purpose MCU

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 11 / 152
NXP Semiconductors
Feature comparison

CPU Platform Security: HSE -B

Memory External Memory IF Permanent Lock
8 MB Pflash with ECC Cortex- M0+ RAM
Cortex-M7
Lock- Step or Split- Lock
1 x QuadSPI
300 MHz Cortex-M7 Cortex-M7 Cortex-M7
128 KB Dflash with ECC Cortex-M7 Asymmetric Hardware Accelerators
4 bit data width 320 MHz
FPU, DSP 320 MHz 320 MHz
320 MHz
1152 KB RAM with ECC I-cache FPU, DSP FPU, DSP FPU, DSP Symmetric Hardware Accelerators
FPU, DSP
D-cache
Incl 384 KB TCM I-cache I-cache I-cache
I-cache D-cache D-cache D-cache
D-cache XRDC Lifecycle
Access control Management
System
FXOSC (8 - 40MHz) Fabric TRNG/PRNG AES Accelerator
Xbar (64bit) AES Accelerator optimized for
FIRC (48MHz) Dedicated to Communications
Low Latency
SIRC (32KHz) Network Communication Analog/Timers Performance
2 x Ethernet, 1Gbps 32ch FlexIO
SXOSC (32KHz) AVB/TSN Emulating 3 x 24ch 12bit ADC Functional Safety
UART, I2C, SPI,
2 x PLL I2S, SENT, PWM BCTU (Body Control Trigger Unit)
CMU FCCU
32ch DMA 6 x LPSPI LCU (Logic Control Unit)
8 x FlexCAN, MPU SWT
all ch support CAN FD 2 x LPI2C
32ch ext. INT/WUP 3x24ch 16bit eMIOS Timer
EIM/ERM CRC STCU
3x LPCMP 32 bit RTC
Debug/Trace (SWD/JTAG/ETB) 16 x LPUART (LIN)
2 x SAI (TDM, I2S)

Figure 14. S32K388: ASIL D 8MB MCU

CPU Platform Security: HSE-B

Memory External Memory IF Permanent Lock
12 MB Pflash with ECC Cortex-M0+ RAM
Cortex-M7 Lock-Step or Split-Lock
+FLASH 1 x QuadSPI 32kB I-cache 32kB D-
256 KB Dflash with ECC Cortex-M7 Cortex-M7
Cortex-M7 Cortex-M7 Asymmetric Hardware Accelerators
+SRAM 32kB TCM32kB TCM
4bit data width 16 KB I-cache 16 KB D-cache 16
16 KB I-cache 3216KB
16 KBI-cache
KB I-I-cache1616
D-cache KB
32 16D-cache
32
KB
KB KB I-cache
KB I-cache1616
I-cache
D-cache KB
32 KBD-
KB I-cache
D-cache

2.25MB SRAM with ECC NEON

TCM: 32K-I, 64K-D Symmetric Hardware Accelerators
TCM: 32K-I, 64K-D TCM: 32K-I, 64K-D
TCM: 32K-I, 64K-D

DP-FPU, DSP DP-FPU, DSP DP-FPU, DSP DP-FPU, DSP

XRDC Lifecycle
System Access control Management

FXOSC (8-40MHz) Fabric TRNG/PRNG

Xbar (64bit) AES Accelerator

FIRC (48MHz) Dedicated to Communications

SIRC (32KHz) Network Communication Analog/Timers

2 x Ethernet, 1Gbps 32ch FlexIO
SXOSC (32KHz) AVB/TSN Emulating 3 x 24ch 12bit ADC Functional Safety
UART, I2C, SPI,
PLL I2S, SENT, PWM BCTU (Body Control Trigger Unit)
CMU FCCU
32ch DMA 6 x LPSPI LCU (Logic Control Unit)
12x FlexCAN, MPU SWT
all ch support CAN FD 2 x LPI2C
32ch ext. INT/WUP 3x24ch 24bit eMIOS Timer
EIM/ERM CRC STCU
16 x LPUART (LIN) 3x LPCMP
Debug/Trace (SWD/JTAG/ETB)
2 x SAI (TDM, I2S)

437BGA Package +FLEXCANs

Figure 15. S32K389: ASIL D 12MB MCU

3 Feature comparison
The following table compares some of the prominent features related to memory and package options of these chips from the
S32K3xx family/product series:
• S32K310
• S32K311
• S32K312
• S32K322
• S32K341
• S32K342
• S32K314
• S32K324
• S32K344
• S32K328
• S32K338

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 12 / 152
NXP Semiconductors
Feature comparison

• S32K348
• S32K358
• S32K388
• S32K389

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 13 / 152
Data Sheet: Technical Data

NXP Semiconductors
Table 1. S32K3xx chip's feature comparison

Feature Chip

S32K310

S32K311

S32K312

S32K322

S32K341

S32K342

S32K314

S32K324

S32K344

S32K328

S32K338

S32K348

S32K358

S32K388

S32K3891
Safety/ B B D B D B B D D D D
ASIL

Program 512 KB 1 MB 2 MB 1 MB 2 MB 4 MB 8 MB 8 MB 12 MB
flash
memory

Data flash 64 64 128 128 128 256

memory
S32K3xx Data Sheet, Rev. 10, 07/2024
Preliminary Information for S32K389

(KB)

Total 112KB 128KB 192KB 256KB (incl. 192KB TCM) 512KB 512KB (incl. 1152KB 1152KB 1152KB 1152KB 1152KB 2304KB
RAM (KB) (incl. (incl. (incl. (includin 192KB TCM) (incl. (incl. (incl. (incl. incl. (incl.
96KB 96KB 96KB g 96KB 192KB 384KB 192KB 384KB 384KB 384KB
TCM) TCM) TCM) TCM) TCM) TCM) TCM) TCM) TCM) TCM)

Standby 16 KB 32 KB 64 KB
RAM

Security HSE_B HSE B +

AES_ACCEL

Core 1 x M7 2 x M7 1 x M7 LS 1 x M7 2 x M7 1 x M7 2 x M7 3 x M7 1 x M7 1xM7 1xM7 LS+3xM7 or

quantity LS LS LS + 2xM7 LS+1xM7
1xM7

Frequenc 120 160 240 320 300

y (MHz)

DMA 12 32 32 32
channels

ASIL–B 277–387-760 739– — 369– 739– — 1108- 1663– — 554– 739- 693-

Feature comparison
DMIPS 2 3 1033- 516- 1033- 1550- 2325- 775- 1033- 969-
2028 1014 2028 3043 4564 1521 2028 4 19024
14 / 152

Table continues on the next page...

Data Sheet: Technical Data

NXP Semiconductors
Table 1. S32K3xx chip's feature comparison (continued)

Feature Chip

S32K310

S32K311

S32K312

S32K322

S32K341

S32K342

S32K314

S32K324

S32K344

S32K328

S32K338

S32K348

S32K358

S32K388

S32K3891
2217- 2079-
3100- 2907-
6086 5 5706 5

ASIL–D — 369–516-1014 — 369– — 554– 775- 1478- 1386-

DMIPS 2 3 516- 775- 1521- 2066- 1938-
1014 1521 1269 4057 4 38044
S32K3xx Data Sheet, Rev. 10, 07/2024
Preliminary Information for S32K389

739- 693-
1033- 969-
2028 5 1902 5

ASIL–B 634 1692 — 846 1692 — 2539 3808 — 1269 1692 4 1587 4
CoreMark
5078 5 4761 5
score 2 6

ASIL–D — 846 — 846 — 1269 1269 3385 4 31744

CoreMark
1692 5 15875
score 2 6

FlexCAN 3 6 4 6 8 8 12
instances

EMAC — 1 —
instances

GMAC — 1 2
instances

SAI — 2
instances

Feature comparison
LPUART 4 8 4 16
instances
15 / 152

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Data Sheet: Technical Data

NXP Semiconductors
Table 1. S32K3xx chip's feature comparison (continued)

Feature Chip

S32K310

S32K311

S32K312

S32K322

S32K341

S32K342

S32K314

S32K324

S32K344

S32K328

S32K338

S32K348

S32K358

S32K388

S32K3891
LPSPI 4 6
instances

I2C 2
instances

FlexIO 16 32
(incl.
SENT
S32K3xx Data Sheet, Rev. 10, 07/2024
Preliminary Information for S32K389

support)
channels

QuadSPI — 17 18 17 17
instances

uSDHC — 1 —
instances

ADC 2 3 3
instances

LPCMP 1 2 3 3
instances

PIT 2 3 3 4
instances

SWT 1 2 1 2 1 2 3 1 2 4
instances

STM 1 2 3 4
instances

Feature comparison
LCU 2
instances

Table continues on the next page...

16 / 152
Data Sheet: Technical Data

NXP Semiconductors
Table 1. S32K3xx chip's feature comparison (continued)

Feature Chip

S32K310

S32K311

S32K312

S32K322

S32K341

S32K342

S32K314

S32K324

S32K344

S32K328

S32K338

S32K348

S32K358

S32K388

S32K3891
BCTU 1
instances

TRGMUX 1
instances

eMIOS 2 3
instances
S32K3xx Data Sheet, Rev. 10, 07/2024

RTC 1
Preliminary Information for S32K389

instances

437-ball No Yes
MAPBGA
package

289-ball No Yes Yes No

MAPBGA
package

257-ball No Yes No
MAPBGA
package

172- No Yes No
HDQFP
package

172- No Yes No
HDQFP -
EP
package

Feature comparison
100- Yes No
HDQFP
package
17 / 152

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Data Sheet: Technical Data

NXP Semiconductors
Table 1. S32K3xx chip's feature comparison (continued)

Feature Chip

S32K310

S32K311

S32K312

S32K322

S32K341

S32K342

S32K314

S32K324

S32K344

S32K328

S32K338

S32K348

S32K358

S32K388

S32K3891
48-pin Yes No
LQFP —
package

1. This feature set is under evaluation and subject to change.

2. ASIL-B and ASIL-D performance is available simultaneously. ASIL-D performance can also be used for ASIL-B performance.
3. The first result abides by all of the "ground rules" out in Dhrystone documentation, the second permits inlining of functions, not just permitted C strings libraries,
while the third additionally permits simultaneous ("multi-file") compilation. All are with the original (K and R) v2.1 of Dhrystone. Arm Compiler 6.17. See https://
developer.arm.com/Processors/Cortex-M7 for details.
S32K3xx Data Sheet, Rev. 10, 07/2024
Preliminary Information for S32K389

4. Core configuration is 2xLS + 1 independent core

5. Core configuration is 1xLS + 3 independent cores
6. Results depends on specific compiler version, contact NXP sales representative for more details.
7. 4-bit data width, SDR mode only
8. 8-bit data width, SDR and DDR mode

Feature comparison
18 / 152
NXP Semiconductors
Ordering information

4 Ordering information

Figure 16. Ordering information

P/S 32 K 3 9 6 E H T0 M JB S T

Product status

Product type/brand

Product line

Series/family

Core platform

Memory size

Features

Security

Fab and mask rev letter

Temperature suffix

Package suffix
Software
configuration
Tape and reel
Indicator

Product status for ordering and marking Extra feature Package suffix
P: Prototype pins BGA MaxQFP MaxQFP-EP LQFP
No ethernet 100 Mbps ethernet 1 Gbps 2 x 1 Gbps
S: Qualified ordering P/N
MAC MAC ethernet MAC ethernet MAC 48 LF
N E G H 100 PA
Product type/brand
172 PB PC
32: Automotive 32-bit MCU/MPU
176 KU
Security
257 MM
Product line HSE B standard 289 JB
Premium security
K: General purpose MCU security 437 JG
H G, V
Series/family
Software configuration
3: K3 product family/Arm CortexM7 based
S: Standard family SW package, including:
Core platform · Real time driver including Autosar MCAL
Fab and mask rev letter and non Autosar driver package (ISO26262
1: 1 x M7 core
2: 2 x M7 cores Tx: Global foundry compliant, crypto driver included)
3: 3 x M7 cores x0: 1st mask revision · Standard security firmware
4: 1 x M7 lockstep core x1: 2nd mask revision · Safety peripheral driver (SPD)
5: 1 x M7 lockstep core plus 1 x M7 core · Inter-core communication framework (IPCF)
6: 1 x M7 LS core + 1 x M7 core + DSP + 2 x eTPU
7: 1 x M7 LS core + 2 x M7 split-lock cores + DSP Ambient temperature (Ta) I: ISELED SW licensed + standard family SW package
8: 2 x M7 lockstep + 1 x M7 core or 1 x M7 lockstep + additional solution specific SW TBD
3 x M7 cores V: -40 °C to 105 °C
9: 1 x M7 LS core + 2 x M7 split-lock cores + 1 x DSP + M: -40 °C to 125 °C
Tape and reel
2 x eTPU
T: Trays/tubes
R: Tape and reel
Memory size

0 1 2 4 6 8 9
P-Flash 512 kB 1 MB 2 MB 4 MB 6 MB 8 MB 12 MB

4.1 Determining valid orderable parts

To determine the orderable part numbers for this device, please contact NXP sales representative.

5 General

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 19 / 152
NXP Semiconductors
General

5.1 Absolute maximum ratings

CAUTION
When the MCU is in an unpowered state, current injected through the chip pins may bias internal chip structures
(for example, ESD diodes) and incorrectly power up these internal structures through inadvertent paths. The
presence of such residual voltage may influence different chip-internal blocks in an unpredictable manner and
may ultimately result in unpredictable chip behavior (for example, POR flag not set). Once in the illegal state,
powering up the chip further and then applying reset will clear the illegal state. Injection current specified for the
chip under the aspect of absolute maximum ratings represent the capability of the internal circuitry to withstand
such condition without causing physical damage. Functional operation of the chip under conditions - specified
as absolute maximum ratings - is not implied.

NOTE
Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in the following table
for specific conditions. Stress beyond the listed maximum values may affect device reliability or cause permanent
damage to the device. All the limits defined in the datasheet specification must be honored together and any
violation to any one or more will not guarantee desired operation. Unless otherwise specified, all maximum and
minimum values in the datasheet are across process, voltage, and temperature.

The VDD_HV_B and V15 voltage supply domains are only present in certain devices and packages
(S32K388, S32K389, S32K358, S32K348, S32K338, S32K328, S32K344, S32K324, S32K314, S32K342, S32K341, S32K322).
The VDD_DCDC supply voltage is only present in certain devices and packages (S32K358, S32K348, S32K338, S32K328,
S32K388 and S32K389).

Table 2. Absolute maximum ratings

Symbol Description Min Typ Max Unit Condition Spec

Number

VDD_HV_A Main I/O and -0.3 — 6.0 V — —

analog supply
voltage 1,2

VDD_HV_B Secondary I/O -0.3 — 6.0 V — —

supply voltage 1,2

VDD_DCDC Supply voltage for -0.3 — 6.0 V — —

the SMPS gate
driver 1,2,3

V15 Voltage sensing -0.3 — 2.75 V For S32K388 and —

input 1,2 S32K389

V15 High-current -0.3 — 2.75 V For S32K358, —

logic supply S32K348, S32K338
voltage 1,2 and S32K328

V15 High-current -0.3 — 6.0 V For all S32K3xx —

logic supply variants except
voltage 1,2 S32K388, S32K389,
S32K358, S32K348,
S32K338 and S32K328

V25 Flash memory -0.3 — 2.9 V — —

supply (2.5 V),
internally regulated 2

Table continues on the next page...

S32K3xx Data Sheet, Rev. 10, 07/2024

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NXP Semiconductors
General

Table 2. Absolute maximum ratings (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

V11 High-current core -0.3 — 1.26 V For S32K388 and —

logic supply input 2 S32K389

V11 Core logic -0.3 — 1.26 V For all S32K3xx —

voltage supply variants except
(1.1 V), internally S32K388 and S32K389
regulated 2

VREFH ADC high reference -0.3 — 6.0 V — —

voltage 1,2

VREFL ADC low reference -0.3 — 0.3 V — —

voltage 2

VGPIO_trans Transient - — 6.0 V — —

overshoot voltage
allowed on I/
O pin 1,2,4

I_INJPAD_DC_ Continuous DC -3 — 3 mA — —
ABS input current
(positive/negative)
that can be injected
into an I/O pin 5

I_INJSUM_DC_ Sum of absolute — — 30 mA — —

ABS value of injected
currents on all the
I/O pins (continuous
DC limit) 5,6

TSTG Storage ambient -55 — 150 °C — —

temperature 7

1. 6.0 V maximum for 10 hours over lifetime; 7.0 V maximum for 60 seconds over lifetime.
2. All voltages are referred to VSS unless otherwise specified.
3. Voltage at VDD_DCDC cannot be higher than VDD_HV_A.
4. When a low impedance voltage source, without current limitation, is connected to one or more I/O pins, the VGPIO_trans
absolute max rating must be honored. During current injection, the voltage at the I/O pin or pins could go beyond this limit if
(and ONLY IF) the injected current is being limited (I_INJPAD_DC_ABS is respected).
5. When the input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, plus /minus the forward
voltage of ESD diodes, practically, no current is being injected. When these limits are exceeded, the maximum input
current spec must be met. See S32K3 Hardware Design Guidelines for more details and recommendations for protecting
the devices against injection current.
6. If a positive injection current is present in one or more I/O pins when the device is in Low Speed RUN or STANDBY mode,
the voltage in the respective I/O power domain (VDD_HV_A or VDD_HV_B) would increase and may cause damage to the
MCU. It is recommended to add external circuitry (which are explained in the S32K3XX Hardware Design Guidelines) to
protect the MCU against injection current.
7. TSTG specifies the storage temperature range. It is not the operating temperature range. Please refer to the Thermal
operating characteristics table.

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5.2 Voltage and current operating requirements

NOTE
Device functionality is guaranteed down to the LVR assert level, however electrical performance of 12-bit ADC,
CMP with 8-bit DAC, IO electrical characteristics, and communication modules electrical characteristics will be
degraded when voltage drops below 2.97 V.

The VDD_HV_B and V15 voltage supply domains are only present in certain devices and packages
(S32K388, S32K389, S32K358, S32K348, S32K338, S32K328, S32K344, S32K324, S32K314, S32K342, S32K341, S32K322).
The VDD_DCDC supply voltage is only present in certain devices and packages (S32K358, S32K348, S32K338, S32K328,
S32K388 and S32K389).

Table 3. Voltage and current operating requirements

Symbol Description Min Typ Max Unit Condition Spec

Number

VDD_HV_A Main I/O and analog 2.97 3.3 or 5.0 5.5 V — —

supply voltage 1

VDD_HV_B Secondary I/O 2.97 3.3 or 5.0 5.5 V — —

supply voltage 1

VDD_DCDC Supply voltage for 2.97 3.3 or 5.0 5.5 V — —

the SMPS gate
driver 1,2

V15 Voltage sensing 1.425 1.5 1.65 V For S32K388 and —

input 1,3 S32K389

V15 High-current logic 1.425 1.5 1.65 V For all S32K3xx —

supply input variants except
voltage 1,3 S32K388 and S32K389

V15_extended High-current logic 1.425 3.3 or 5.0 5.5 V For S32K322, —

supply input S32K341, S32K342,
voltage, extended S32K314, S32K324,
range 1,3,4,5 S32K344

VREFH ADC high reference 2.97 3.3 or 5.0 5.5 V — —

voltage 1,6

VREFL ADC low reference -0.1 0 0.1 V — —

voltage 1

VSS_DCDC Power ground for the -0.1 0 0.1 V — —

SMPS gate driver 1

V25 Flash memory — 2.5 — V — —

and clock
supply (2.5 V),
internally regulated 1

V11 High-current core — 1.14 — V For S32K388 and —

logic supply input 1 S32K389

V11 Core logic supply — 1.14 — V For all S32K3xx —

(1.1 V), internally variants except
regulated 1 S32K388 and S32K389

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Table 3. Voltage and current operating requirements (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

VGPIO Input voltage range -0.3 — VDD_HV V — —

at any I/O or analog _A/B +
pin 1,7 0.3

VODPU Open-drain pull-up — — VDD_HV V — —

voltage 1,8 _A/B

IINJPAD_DC_OP Continuous DC input -3 — 3 mA VDD_HV_A >= 3.6V —

current (positive/
negative) that can be
injected into an I/O
pin 9

IINJPAD_DC_OP Continuous DC input -2 — 3 mA VDD_HV_A >= 2.97V —

current (positive/
negative) that can be
injected into an I/O
pin 9

IINJSUM_DC_OP Sum of -30 — 30 mA VDD_HV_A >= 3.6V —

absolute value of
injected currents
on all the I/O
pins (continuous
DC limit) 9,10

IINJSUM_DC_OP Sum of -20 — 30 mA VDD_HV_A >= 2.97V —

absolute value of
injected currents
on all the I/O
pins (continuous
DC limit) 9,10

Vramp_slow Supply ramp rate 0.5 — — V/min — —

(slow) 1,11

Vramp_fast Supply ramp rate — — 100 V/ms — —

(fast) 1,11

1. All voltages are referred to VSS unless otherwise specified.

2. Voltage at VDD_DCDC cannot be higher than VDD_HV_A.
3. Min and Max values are applicable only for non-SMPS mode where V15 is sourced externally.
4. If total power dissipation and maximum junction temperature allows. Please refer to Thermal operating characteristics
table for the maximum junction temperature, and Thermal characteristics table for the thermal characteristics, to determine
the maximum power dissipation allowed for a given package.
5. You must ensure that the junction temperature in the application must not exceed the maximum specified Tj.
6. VREFH should always be equal to or less than VDD_HV_A +0.1. Any positive differential voltage between VREFH and
VDD_HV_A i.e., VDD_HV_A < VREFH <= VDD_HV_A + 0.1V) is for RF-AC only. Appropriate decoupling capacitors should
be used to filter noise on the supplies. See application note AN5032 for reference supply design for SAR_ADC
7. Keeping the input voltage between this range practically ensures that no (noticeable) current is being injected. When
exceeding these limits, the current being injected must be lower than IINJPAD_DC_OP, all the time.
8. Open-drain outputs must be pulled respectively to their supply rail (VDD_HV_A or VDD_HV_B).
9. When the input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, plus /minus the forward
voltage of ESD diodes, practically, no current is being injected. When these limits are exceeded, the maximum input
current spec must be honored. Refer to the S32K3 Hardware Design Guidelines AN for more details and recommendations
for protecting the devices against injection current.

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10. If a positive injection current is present in one or more I/O pins, and the device is in Low-Speed RUN or STANDBY mode,
the VDD_HV_A (or respectively, VDD_HV_B) may lift and cause unexpected behavior. Therefore, it is recommended to
add external protection hardware, to safely cover this scenario.
11. The MCU supply ramp rate parameter must be applicable to the MCU input/external supplies. The ramp rate
assumes that the S32K3xx HW design guidelines available on www.nxp.com are followed.

5.3 Thermal operating characteristics

Table 4. Thermal operating characteristics

Symbol Description Min Typ Max Unit Condition Spec

Number

Tamb Ambient temperature -40 — 105 °C V- Grade —

Tamb Ambient temperature -40 — 125 °C M- Grade —

TJ Junction -40 — 150 °C — —

temperature

For S32K388 and S32K389, applications running at 125°C Tamb, thermal management schemes at PCB level will have to be
deployed to keep TJ below 150°C.

5.4 ESD and Latch-up Protection Characteristics

Table 5. ESD and Latch-up Protection Characteristics

Symbol Description Min Typ Max Unit Condition Spec

Number

Vhbm Electrostatic -2000 — 2000 V — —

discharge voltage,
human body model
(HBM) 1,2,3

Vcdm Electrostatic -500 — 500 V — —

discharge voltage,
charged-device
model (CDM),
all pins except
corner 1,2,4

Vcdm Electrostatic -750 — 750 V — —

discharge voltage,
charged-device
model (CDM), corner
pins 1,2,4

Ilat Latch-up current at -100 — 100 mA — —

ambient temperature
of 125°C 5

1. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet specification requirements."
2. All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
3. This parameter is tested in conformity with AEC-Q100-002.
4. This parameter is tested in conformity with AEC-Q100-011.
5. This parameter is tested in conformity with AEC-Q100-004.

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6 Power management

6.1 Power mode transition operating behaviors

6.1.1 Power mode transition operating behavior

The values in the table below are provided for reference only.

Table 6. Power mode transition operating behavior

Symbol Description Min Typ Max Unit Condition Spec

Number

tMODE_ RUN --> — 1035 — ns For S32K388 and —

STDBYENTRY STANDBY transition S32K389
time

tMODE_ RUN --> STANDBY — 955 — ns — —

STDBYENTRY transition time

tMODE_ STANDBY --> RUN — 85.5 — us For S32K328, —

STDBYEXIT_FAST transition time, Fast S32K338, S32K348
Recovery, V15 and S32K358
SMPS with trickle
LDO disabled

tMODE_ STANDBY --> RUN — 58.6 — us For S32K328, —

STDBYEXIT_FAST transition time, Fast S32K338, S32K348
Recovery, V15 and S32K358
SMPS with trickle
LDO enabled

tMODE_ STANDBY --> — 58.5 — us For S32K328, —

STDBYEXIT_FAST RUN transition S32K338, S32K348
time, FastRecovery, and S32K358
V15External

tMODE_ STANDBY --> RUN — 53 — us FIRC ON @48MHz —

STDBYEXIT_FAST transition time, Fast in Standby mode, For
Recovery exit all S32K3xx devices
except S32K3x8 and
S32K389

tMODE_ STANDBY --> RUN — 80 — us For all S32K3xx —

STDBYEXIT transition time, devices except
normal recovery exit S32K3x8 and S32K389

tMODE_ STANDBY --> RUN — 140 — us For S32K328, —

STDBYEXIT transition time, S32K338, S32K348
Normal Recovery, and S32K358
V15 External

tMODE_ STANDBY --> — 186 — us For S32K388 and —

STDBYEXIT RUN transition S32K389
time, V15 SMPS
with trickle LDO
enabled

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Table 6. Power mode transition operating behavior (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tMODE_ STANDBY --> RUN — 212 — us For S32K388 and —

STDBYEXIT transition time, with S32K389
SMPS trickle LDO
disabled 1

tMODE_ STANDBY --> RUN — 154 — us For S32K328, —

STDBYEXIT transition, time S32K338, S32K348
Normal Recovery, and S32K358
V15 SMPS

1. S32K388 and S32K389 doesn’t support the FAST STANDBY EXIT recovery

6.1.2 Boot time, HSE firmware not installed

Table 7. Boot time, HSE firmware not installed

Symbol Description Min Typ Max Unit Condition Spec

Number

tBOOT_noHSE After a POR event, — 2 — ms Device running from —

amount of time to FIRC (clocking option
execution of the D). CORE_CLK = 48
first instruction of MHz; HSE_CLK = 48
the application core, MHz.
when HSE firmware
is not installed. (HSE
FW feature flag is
disabled)

6.1.3 Boot time, HSE firmware installed

The following table provides the boot time of the S32K3 SBAF and Firmware initialization. To obtain the total boot time, the
corresponding user code verification time must be added.

Table 8. Boot time, HSE firmware installed

Symbol Description Min Typ Max Unit Condition Spec

Number

tBOOT_HSE_ After a POR event, — — 3 ms Device running from —

NONSECURE amount of time to FIRC (clocking option
execution of the D). CORE_CLK = 48
first instruction of MHz; HSE_CLK = 48
the application core, MHz.
when HSE firmware
is installed. (BOOT
SEQ = 0)

tBOOT_HSE After a POR event, — 12.36 — ms Device running from —

amount of time to FIRC (clocking option
execution of the D). CORE_CLK = 48
first instruction of

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Table 8. Boot time, HSE firmware installed (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

the application core, MHz; HSE_CLK = 48

when HSE firmware MHz.
is installed.

tBOOT_HSE After a POR event, — 9.51 — ms Device running from —

amount of time to PLL (clocking option
execution of the B). CORE_CLK = 120
first instruction of MHz; HSE_CLK = 120
the application core, MHz.
when HSE firmware
is installed.

tBOOT_HSE After a POR event, — 10.91 — ms Device running from —

amount of time to PLL (clocking option
execution of the A). CORE_CLK = 160
first instruction of MHz; HSE_CLK = 80
the application core, MHz.
when HSE firmware
is installed.

6.1.4 HSE firmware memory verification time examples

Table 9. HSE firmware memory verification time examples

Symbol Description Min Typ Max Unit Condition Spec

Number

tCMAC_64KB Memory verification — 11.3 — ms Device running from —

of 64 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using AES-128 MHz; HSE_CLK = 48
CMAC cipher. MHz.

tCMAC_1024KB Memory verification — 176 — ms Device running from —

of 1024 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using AES-128 MHz; HSE_CLK = 48
CMAC cipher. MHz.

tGMAC_64KB Memory verification — 3.2 — ms Device running from —

of 64 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using AES-128 MHz; HSE_CLK = 48
GMAC cipher. MHz.

tGMAC_1024KB Memory verification — 46.8 — ms Device running from —

of 1024 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using AES-128 MHz; HSE_CLK = 48
GMAC cipher. MHz.

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Table 9. HSE firmware memory verification time examples (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tHMAC_64KB Memory verification — 1.74 — ms Device running from —

of 64 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using AES-128 MHz; HSE_CLK = 48
HMAC cipher. MHz.

tHMAC_1024KB Memory verification — 22.87 — ms Device running from —

of 1024 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using AES-128 MHz; HSE_CLK = 48
HMAC cipher. MHz.

tRSA_64KB Memory verification — 31.03 — ms Device running from —

of 64 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using RSA 2048 MHz; HSE_CLK = 48
cipher. MHz.

tRSA_1024KB Memory verification — 52.15 — ms Device running from —

of 1024 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using RSA 2048 MHz; HSE_CLK = 48
cipher. MHz.

tECDSA_64KB Memory verification — 126.46 — ms Device running from —

of 64 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using ECDSA 521 MHz; HSE_CLK = 48
bits cipher. MHz.

tECDSA_1024KB Memory verification — 147.53 — ms Device running from —

of 1024 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using ECDSA 521 MHz; HSE_CLK = 48
bits cipher. MHz.

tSHA2_256_64KB Memory verification — 1.62 — ms Device running from —

of 64 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using SHA2 256 bits MHz; HSE_CLK = 48
bits cipher. MHz.

tSHA2_256_ Memory verification — 22.73 — ms Device running from —

1024KB of 1024 KB of FIRC (clocking option
application firmware, D). CORE_CLK = 48
using SHA2 256 bits MHz; HSE_CLK = 48
bits cipher. MHz.

tCMAC_64KB Memory verification — 6.67 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160

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Table 9. HSE firmware memory verification time examples (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

using AES-128 MHz; HSE_CLK = 80

CMAC cipher. MHz.

tCMAC_1024KB Memory verification — 105.24 — ms Device running from —

of 1024 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using AES-128 MHz; HSE_CLK = 80
CMAC cipher. MHz.

tGMAC_64KB Memory verification — 1.85 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using AES-128 MHz; HSE_CLK = 80
GMAC cipher. MHz.

tGMAC_1024KB Memory verification — 28.03 — ms Device running from —

of 1024 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using AES-128 MHz; HSE_CLK = 80
GMAC cipher. MHz.

tHMAC_64KB Memory verification — 0.98 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using AES-128 MHz; HSE_CLK = 80
HMAC cipher. MHz.

tHMAC_1024KB Memory verification — 13.68 — ms Device running from —

of 1024 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using AES-128 MHz; HSE_CLK = 80
HMAC cipher. MHz.

tRSA_64KB Memory verification — 17.39 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using RSA 2048 MHz; HSE_CLK = 80
cipher. MHz.

tRSA_1024KB Memory verification — 23.32 — ms Device running from —

of 1024 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using RSA 2048 MHz; HSE_CLK = 80
cipher. MHz.

tECDSA_64KB Memory verification — 72.2 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using ECDSA 521 MHz; HSE_CLK = 80
bits cipher. MHz.

tECDSA_1024KB Memory verification — 84.91 — ms Device running from —

of 1024 KB of PLL (clocking option

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Table 9. HSE firmware memory verification time examples (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

application firmware, A). CORE_CLK = 160

using ECDSA 521 MHz; HSE_CLK = 80
bits cipher. MHz.

tSHA2_256_64KB Memory verification — 0.9 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using SHA2 256 bits MHz; HSE_CLK = 80
bits cipher. MHz.

tSHA2_256_ Memory verification — 13.6 — ms Device running from —

1024KB of 1024 KB of PLL (clocking option
application firmware, A). CORE_CLK = 160
using SHA2 256 bits MHz; HSE_CLK = 80
bits cipher. MHz.

tCMAC_64KB Memory verification — 4.5 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using AES-128 MHz; HSE_CLK = 120
CMAC cipher. MHz.

tCMAC_1024KB Memory verification — 69.9 — ms Device running from —

of 1024 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using AES-128 MHz; HSE_CLK = 120
CMAC cipher. MHz.

tGMAC_64KB Memory verification — 1.3 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using AES-128 MHz; HSE_CLK = 120
GMAC cipher. MHz.

tGMAC_1024KB Memory verification — 18.7 — ms Device running from —

of 1024 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using AES-128 MHz; HSE_CLK = 120
GMAC cipher. MHz.

tHMAC_64KB Memory verification — 0.7 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using AES-128 MHz; HSE_CLK = 120
HMAC cipher. MHz.

tHMAC_1024KB Memory verification — 9.12 — ms Device running from —

of 1024 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using AES-128 MHz; HSE_CLK = 120
HMAC cipher. MHz.

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Table 9. HSE firmware memory verification time examples (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tRSA_64KB Memory verification — 15.4 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using RSA 2048 MHz; HSE_CLK = 120
cipher. MHz.

tRSA_1024KB Memory verification — 23.8 — ms Device running from —

of 1024 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using RSA 2048 MHz; HSE_CLK = 120
cipher. MHz.

tECDSA_64KB Memory verification — 53.95 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using ECDSA 521 MHz; HSE_CLK = 120
bits cipher. MHz.

tECDSA_1024KB Memory verification — 62.34 — ms Device running from —

of 1024 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using ECDSA 521 MHz; HSE_CLK = 120
bits cipher. MHz.

tSHA2_256_64KB Memory verification — 0.64 — ms Device running from —

of 64 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using SHA2 256 bits MHz; HSE_CLK = 120
bits cipher. MHz.

tSHA2_256_ Memory verification — 9.07 — ms Device running from —

1024KB of 1024 KB of PLL (clocking option
application firmware, B). CORE_CLK = 120
using SHA2 256 bits MHz; HSE_CLK = 120
bits cipher. MHz.

6.2 Supply Monitoring

Certain monitors are present on certain devices. See Power Management chapter in reference manual.

Table 10. Supply Monitoring

Symbol Description Min Typ Max Unit Condition Spec

Number

LVD_V15 Low Voltage Detect 1.34 1.38 1.42 V — —

(LVD) on V15,
deassert threshold
(in FPM)

HVD_V15 High Voltage Detect — 2.5 — V — —

(HVD) on V15,

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Table 10. Supply Monitoring (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

assert threshold (in

FPM) 1

LVR_VDD_HV_A LVR on VDD_HV_A, 2.77 2.85 2.93 V — —

assert threshold (in
FPM)

LVR_VDD_HV_A LVR on VDD_HV_A, 2.77 2.85 2.93 V — —

assert threshold (in
RPM)

— VDD_HV_A LVR — 18.75 — mV — —

monitor hysteresis

HVD_VDD_HV_A HVD on VDD_HV_A, 5.787 5.887 5.987 V — —

assert threshold (in
FPM)

— VDD_HV_A HVD — 37.5 — mV — —

monitor hysteresis

LVR_VDD_HV_B LVR on VDD_HV_B, 2.77 2.85 2.93 V — —

assert threshold (in
FPM)

LVR_VDD_HV_B LVR on VDD_HV_B, 2.77 2.85 2.93 V — —

assert threshold (in
RPM)

— VDD_HV_B LVR — 18.75 — mV — —

monitor hysteresis

HVD_VDD_HV_B HVD on VDD_HV_B, 5.787 5.887 5.987 V — —

assert threshold (in
FPM)

— VDD_HV_B HVD — 37.5 — mV — —

monitor hysteresis

LVD_VDD_HV_A Low Voltage 4.33 4.41 4.49 V — —

Detect (LVD5A) on
VDD_HV_A, assert
threshold (in FPM)

— VDD_HV_A — 37.5 — mV — —
LVD monitor
hysteresis

VPOR_VDD_HV_A Power-On-Reset 0.9 1.5 2.2 V — —

(VPOR) on
VDD_HV_A,
deassert threshold

VREF12 Bandgap reference, 1.18 1.2 1.22 V — —

trimmed

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1. The HVD_V15 monitor is provided to indicate if the V15 rail is far above the standard V15 operating range , to ensure
failures in the V15 regulator are detected

6.3 Recommended Decoupling Capacitors

Table 11. Recommended Decoupling Capacitors

Symbol Description Min Typ Max Unit Condition Spec

Number

CDEC Decoupling capacitor 70 100 — nF — —

(one per supply
pin) 1,2,3

CBULK Input supply bulk — 4.7 — µF — —

capacitor 2,4,5,6

COUT_V15_NPN V15 (1.5V — 2.2 — µF — —

Regulator) output
capacitor 2,7

COUT_V11 V11 (1.1V — 2.2 — µF — —

Regulator)
output capacitor (all
chips, except
S32K312, S32K311,
S32K310 and
S32K388) 2

COUT_V11 V11 (1.1V — 1 — µF — —

Regulator)
output capacitor
(S32K312, S32K311
& S32K310) 2

COUT_V11 V11 (1.1V — 22 — uF — —

Regulator)
output capacitor
(S32K388) 2

COUT_V25 V25 (2.5V 140 220 — nF — —

Regulator) output
capacitor 1,2

1. These capacitors must be placed as close as possible to the corresponding supply and ground pins. For BGA
packages, the capacitors must be placed on the other side of the PCB to minimize the trace lengths.
2. All capacitors must be low ESR ceramic capacitors (for example, X7R). The minimum recommendation is after
considering component aging and tolerance.
3. Optionally, 1 nF capacitors can be added in parallel to the decoupling capacitors.
4. These capacitors must be placed close to the source.
5. For devices where the VDD_HV_B domain is present, if the VDD_HV_B supply is different supply from VDD_HV_A, a
dedicated bulk capacitor is needed.
6. It is also possible to use higher capacitance values (for example, 10 μF) in place of the 4.7 μF capacitor.
7. For devices where V15 is present, the V15 regulator output capacitor and the filter capacitors are required when using an
NPN bipolar ballast transistor for the regulation stage. When V15 is supplied from an external regulator, these capacitance
recommendations can be followed in addition to the capacitance requirements of the external voltage regulator.

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 33 / 152
NXP Semiconductors
Power management

6.3.1 Recommended Decoupling Capacitor diagrams

V25
6 V25
COUT_V25

V11
7 V11
COUT_V11

VREFL 4

VSS 8
VDD_HV_A
VSS 30
5 VDD_HV_A
CBULK CDEC 31 VDD_HV_A

VREFH
3 VREFH
CDEC

Figure 17. 48-pin LQFP decoupling capacitor pinout diagram (S32K311, S32K310)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 34 / 152
NXP Semiconductors
Power management

V25
11 V25
COUT_V25

V11
13 V11
COUT_V11 CDEC 60 V11
VREFL 9

VSS 12
VDD_HV_A
VSS 14
10 VDD_HV_A
VSS 16
CBULK CDEC CDEC CDEC 37 VDD_HV_A
VSS 38
62 VDD_HV_A
VSS 61
87 VDD_HV_A VSS 86

VREFH
8 VREFH
CDEC

Figure 18. 100-pin HDQFP decoupling capacitor pinout diagram (S32K312, S32K311, S32K310)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 35 / 152
NXP Semiconductors
Power management

V25
11 V25
COUT_V25

V11
13 V11
COUT_V11 CDEC 60 V11

V15
12 V15
CDEC CDEC 59 V15

VREFL 9
V15

COUT_V15_NPN RBTC15
VSS 14
Q_V15_NPN 7 VRC_CTRL VSS 16
VSS 24
VDD_HV_NPN
VSS 38
BJT option VSS 61
VSS 86

VDD_HV_B
25 VDD_HV_B
CBULK CDEC 37 VDD_HV_B

VDD_HV_A
10 VDD_HV_A
CBULK CDEC CDEC 62 VDD_HV_A
87 VDD_HV_A

VREFH
8 VREFH
CDEC

Figure 19. 100-pin HDQFP decoupling capacitor pinout diagram (S32K342, S32K341, S32K322)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 36 / 152
NXP Semiconductors
Power management

V25
19 V25
COUT_V25

V11
21 V11
COUT_V11 CDEC CDEC CDEC 59 V11
106 V11
VREFL 17
149 V11

VSS 20
VSS 22
VSS 24
VDD_HV_A VSS 37
18 VDD_HV_A VSS 58
CBULK CDEC CDEC CDEC CDEC CDEC 38 VDD_HV_A VSS 78
57 VDD_HV_A VSS 107
77 VDD_HV_A VSS 127
108 VDD_HV_A VSS 150
128 VDD_HV_A VSS 168
151 VDD_HV_A
169 VDD_HV_A

VREFH
16 VREFH
CDEC

Figure 20. 172-pin HDQFP decoupling capacitor pinout diagram (S32K312)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 37 / 152
NXP Semiconductors
Power management

V25
19 V25
COUT_V25

V11
21 V11
COUT_V11 CDEC CDEC CDEC 59 V11
106 V11
149 V11

V15
20 V15
CDEC CDEC CDEC 60 V15
105 V15
148 V15
VREFL 17

V15
VSS 22
COUT_V15_NPN RBTC15 VSS 24
VSS 37
Q_V15_NPN 11 VRC_CTRL VSS 58
VDD_HV_NPN VSS 78
VSS 107
BJT option
VSS 127
VSS 150
VDD_HV_B VSS 168
38 VDD_HV_B
CBULK CDEC CDEC 57 VDD_HV_B
77 VDD_HV_B

VDD_HV_A
18 VDD_HV_A
CBULK CDEC CDEC 108 VDD_HV_A
128 VDD_HV_A
151 VDD_HV_A
169 VDD_HV_A

VREFH
16 VREFH
CDEC

Figure 21. 172-pin HDQFP decoupling capacitor pinout diagram (S32K344, S32K324, S32K314, S32K342, S32K341
and S32K322)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 38 / 152
NXP Semiconductors
Power management

V25
J7 V25
COUT_V25

V11
H9 V11
COUT_V11 CDEC CDEC CDEC J8 V11
J10 V11
K9 V11

V15
H8 V15
CDEC CDEC H10 V15
VREFL J6
K8 V15
K10 V15
VSS B2
VSS B16
V15
VSS D4
COUT_V15_NPN RBTC15 VSS D9
VSS G7
Q_V15_NPN F1 VRC_CTRL VSS G11
VSS J1
VDD_HV_NPN
VSS J4
BJT option VSS J9
VSS J14
VSS L7
VDD_HV_B
VSS L11
N4 VDD_HV_B
VSS P4
CBULK CDEC CDEC R7 VDD_HV_B
VSS P14
R10 VDD_HV_B
VSS T2
VSS T7
VSS T10
VSS T16
VDD_HV_A
D14 VDD_HV_A
CBULK CDEC CDEC CDEC G10 VDD_HV_A
H7 VDD_HV_A
K11 VDD_HV_A
L8 VDD_HV_A

VREFH
H6 VREFH
CDEC

Figure 22. 257BGA package decoupling capacitor pinout diagram (S32K344, S32K324 and S32K314)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 39 / 152
NXP Semiconductors
Power management

V25
19 V25
COUT_V25

V11
21 V11
COUT_V11 CDEC CDEC CDEC 59 V11
106 V11
149 V11

V15
20 V15 VREFL 17
CDEC CDEC CDEC CDEC CDEC 36 V15
60 V15
VSS_DCDC 26
79 V15
105 V15
148 V15 VSS 22
V15
VSS 24
VSS 37
COUT_V15_NPN RBTC15 VSS 58
VSS 78
Q_V15_NPN 11 VRC_CTRL VSS 107
VDD_HV_NPN VSS 127
VSS 150
BJT option
VSS 168
VSS EP
VDD_HV_B
38 VDD_HV_B
CBULK CDEC CDEC CDEC 57 VDD_HV_B
77 VDD_HV_B
28 VDD_DCDC
NC 27 PMOS_CTRL

VDD_HV_A
18 VDD_HV_A
CBULK CDEC CDEC CDEC 108 VDD_HV_A
128 VDD_HV_A
151 VDD_HV_A
169 VDD_HV_A

VREFH
16 VREFH
CDEC

Figure 23. 172-pin HDQFP-EP decoupling capacitor pinout diagram (S32K358, S32K348, S32K338 and S32K328)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 40 / 152
NXP Semiconductors
Power management

V25
19 V25
COUT_V25

V11
21 V11
COUT_V11 CDEC CDEC CDEC 59 V11
106 V11
149 V11

V15
20 V15
CDEC CDEC CDEC CDEC CDEC 36 V15
60 V15 VREFL 17
79 V15
105 V15
VSS_DCDC 26
148 V15

SMPS option
VDD_DCDC L_SMPS V15 VSS 22
Q_SMPS
VSS 24
VSS 37
COUT_V15_SMPS
CBULK_SMPS D_SMPS VSS 58
NC 11 VRC_CTRL VSS 78
VSS 107
27 PMOS_CTRL VSS 127
28 VDD_DCDC VSS 150
VSS 168
VDD_HV_B VSS EP
38 VDD_HV_B
CBULK CDEC CDEC CDEC 57 VDD_HV_B
77 VDD_HV_B

VDD_HV_A
18 VDD_HV_A
CBULK CDEC CDEC CDEC 108 VDD_HV_A
128 VDD_HV_A
151 VDD_HV_A
169 VDD_HV_A

VREFH
16 VREFH
CDEC

Figure 24. 172-pin HDQFP-EP decoupling capacitor pinout diagram, SMPS (S32K358, S32K348, S32K338
and S32K328)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 41 / 152
NXP Semiconductors
Power management

V25
J7 V25
COUT_V25

V11
H9 V11
COUT_V11 CDEC CDEC CDEC J8 V11
J10 V11
K9 V11

V15
E9 V15 VREFL J6
CDEC CDEC CDEC CDEC CDEC H8 V15
H10 V15
VSS_DCDC J5
J13 V15
K8 V15
K10 V15 VSS B2
V15
N6 V15 VSS B16
N8 V15 VSS D4
COUT_V15_NPN RBTC15
VSS D9
VSS E13
Q_V15_NPN F1 VRC_CTRL
VSS G7
VDD_HV_NPN VSS G11
VSS J1
BJT option
VSS J4
VDD_HV_B VSS J9
N4 VDD_HV_B VSS J14
CBULK CDEC CDEC CDEC R7 VDD_HV_B VSS L7
R10 VDD_HV_B VSS L11
L5 VDD_DCDC VSS M5
NC K5 PMOS_CTRL VSS N7
VDD_HV_A
VSS N10
D14 VDD_HV_A VSS P4
CBULK CDEC CDEC CDEC CDEC CDEC CDEC E5 VDD_HV_A VSS P14
G10 VDD_HV_A VSS T2
H7 VDD_HV_A VSS T7
H13 VDD_HV_A VSS T10
K11 VDD_HV_A VSS T16
L8 VDD_HV_A
N5 VDD_HV_A
N9 VDD_HV_A

VREFH
H6 VREFH
CDEC

Figure 25. 289BGA package decoupling capacitor pinout diagram (S32K358, S32K348, S32K338 and S32K328)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 42 / 152
NXP Semiconductors
Power management

V25
J7 V25
COUT_V25

V11
H9 V11
COUT_V11 CDEC CDEC CDEC J8 V11
J10 V11
K9 V11

V15
E9 V15
CDEC CDEC CDEC CDEC CDEC H8 V15
H10 V15
J13 V15
K8 V15
K10 V15
N6 V15
SMPS option
VREFL J6
VDD_DCDC L_SMPS V15 N8 V15
Q_SMPS

CBULK_SMPS VSS_DCDC J5
D_SMPS COUT_V15_SMPS

NC F1 VRC_CTRL
VSS B2
VSS B16
K5 PMOS_CTRL VSS D4
L5 VDD_DCDC VSS D9
VSS E13
VDD_HV_B
VSS G7
N4 VDD_HV_B
VSS G11
CBULK CDEC CDEC R7 VDD_HV_B
VSS J1
R10 VDD_HV_B
VSS J4
VDD_HV_A VSS J9
D14 VDD_HV_A VSS J14
CBULK CDEC CDEC CDEC CDEC CDEC CDEC E5 VDD_HV_A VSS L7
G10 VDD_HV_A VSS L11
H7 VDD_HV_A VSS M5
H13 VDD_HV_A VSS N7
K11 VDD_HV_A VSS N10
L8 VDD_HV_A VSS P4
N5 VDD_HV_A VSS P14
N9 VDD_HV_A VSS T2
VSS T7
VSS T10
VREFH
VSS T16
H6 VREFH
CDEC

Figure 26. 289BGA package decoupling capacitor pinout diagram, SMPS (S32K358, S32K348, S32K338 and S32K328)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 43 / 152
NXP Semiconductors
Power management

V11
E9 V11
CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC H9 V11
H10 V11
J8 V11
J10 V11
J13 V11
K8 V11
K9 V11
V15 V11 K10 V11
N6 V11
COUT_V11_NFET N8 V11
LAST MILE VREFL J6

REGULATOR VSS_DCDC J5
F1 NMOS_CTRL

V15 PMIC option

EXTERNAL NFET VSS B2
H8 V15 VSS B16
CBULK CDEC
VSS D4
VSS D9
VSS E13
CBULK should be defined as per PMIC

V25
VSS G7
VSS G11
J7 V25
VSS J1
COUT_V25
VSS J4
VSS J9
VSS J14
VDD_HV_B
VSS L7
N4 VDD_HV_B
VSS L11
CBULK CDEC CDEC CDEC R7 VDD_HV_B
VSS M5
R10 VDD_HV_B
VSS N7
VSS N10
L5 VDD_DCDC
VSS P4
NC K5 PMOS_CTRL
VSS P14
VDD_HV_A
VSS T2
D14 VDD_HV_A
VSS T7
CBULK CDEC CDEC CDEC CDEC CDEC CDEC E5 VDD_HV_A
VSS T10
G10 G10
VSS T16
H7 H7
H13 H13
K11 K11
L8 L8
N5 N5
N9 N9

VREFH
H6 VREFH
CDEC

Figure 27. 289BGA package decoupling capacitor pinout diagram, (S32K388)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 44 / 152
NXP Semiconductors
Power management

V11
E9 V11
CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC H9 V11
H10 V11
J8 V11
J10 V11
J13 V11
K8 V11
K9 V11
V15 V11 K10 V11
N6 V11
COUT_V11_NFET N8 V11 VREFL J6
LAST MILE
REGULATOR
EXTERNAL NFET
VSS_DCDC J5
F1 NMOS_CTRL
SMPS option
VDD_DCDC L_SMPS V15
VSS B2
Q_SMPS
VSS B16
H8 V15
VSS D4
CBULK_SMPS CDEC
D_SMPS COUT_V15_SMPS VSS D9
VSS E13
VSS G7
K5 PMOS_CTRL VSS G11
L5 VDD_DCDC VSS J1
VSS J4
V25
VSS J9
J7 V25
VSS J14
COUT_V25
VSS L7
VSS L11
VDD_HV_B
VSS M5
N4 VDD_HV_B VSS N7
CBULK CDEC CDEC R7 VDD_HV_B VSS N10
R10 VDD_HV_B VSS P4
VSS P14
VDD_HV_A VSS T2
D14 VDD_HV_A VSS T7
CBULK CDEC CDEC CDEC CDEC CDEC CDEC E5 VDD_HV_A VSS T10
G10 VDD_HV_A VSS T16
H7 VDD_HV_A
H13 VDD_HV_A
K11 VDD_HV_A
L8 VDD_HV_A
N5 VDD_HV_A
N9 VDD_HV_A

VREFH
H6 VREFH
CDEC

Figure 28. 289BGA package decoupling capacitor pinout diagram, SMPS (S32K388)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 45 / 152
NXP Semiconductors
Power management

VREFH
V11
VREFH K8
B3 V11 CDEC
CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC B8 V11
B10 V11
B16 V11 VREFL L8
C20 V11
G11 V11
V11 VSS_DCDC J5
G20 V11
VSS A16
K11 V11
CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC VSS A20
K12 V11
VSS AA2
L10 V11
VSS AA11
L12 V11
VSS AA19
L15 V11
VSS B2
M10 V11
VSS B7
M11 V11
VSS B11
M12 V11
VSS B20
N2 V11
VSS D4
N20 V11
VSS D18
R2 V11
VSS E2
R8 V11
VSS F1
R10 V11
VSS F2
T20 V11
VSS F6
W2 V11
VSS F11
V15 V11 Y4 V11
VSS F20
Y8 V11
VSS G2
COUT_V11_NFET Y12 V11
VSS G15
LAST MILE Y17 V11
VSS H2
REGULATOR
EXTERNAL NFET VSS J1
E1 NMOS_CTRL VSS J2
V15 VSS J3
K10 V15 VSS J9
VSS J13
CDEC
VSS J21
VSS K2
VDD_HV_B VSS K3
R6 VDD_HV_B
VSS L2
CBULK CDEC CDEC CDEC CDEC CDEC U2 VDD_HV_B
VSS L3
U9 VDD_HV_B
VSS L6
U12 VDD_HV_B VSS L11
Y6 VDD_HV_B VSS L16
Y10 VDD_HV_B VSS M1
VDD_HV_A VSS M2
B6 VDD_HV_A VSS M20
CBULK CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC B12 VDD_HV_A VSS N9
B19 VDD_HV_A VSS N13
C2 VDD_HV_A VSS P7
E20 VDD_HV_A VSS R9
VDD_HV_A
F16 VDD_HV_A VSS R12
G7 VDD_HV_A VSS T2
CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC
J12 VDD_HV_A VSS T6
K9 VDD_HV_A VSS T16
K15 VDD_HV_A VSS U20
L20 VDD_HV_A VSS V2
M13 VDD_HV_A VSS V4
N10 VDD_HV_A VSS V9
R7 VDD_HV_A VSS V12
R11 VDD_HV_A VSS V18
V20 VDD_HV_A VSS Y2
Y15 VDD_HV_A VSS Y5
Y19 VDD_HV_A VSS Y9
VSS Y13
NC K5 PMOS_CTRL VSS Y16
NC N7 VDD_DCDC VSS Y20

V25
L9 V25
COUT_V25

Figure 29. 437BGA package decoupling capacitor pinout diagram(S32K389)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 46 / 152
NXP Semiconductors
Power management

V11 VREFH
B3 V11 VREFH K8
CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC B8 V11 CDEC
B10 V11
B16 V11 VREFL L8
C20 V11
G11 V11
V11 VSS_DCDC J5
G20 V11
VSS A16
K11 V11
CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC VSS A20
K12 V11
VSS AA2
L10 V11
VSS AA11
L12 V11
VSS AA19
L15 V11
VSS B2
M10 V11
VSS B7
M11 V11
VSS B11
M12 V11
VSS B20
N2 V11
VSS D4
N20 V11
VSS D18
R2 V11
VSS E2
R8 V11
VSS F1
R10 V11
VSS F2
T20 V11
VSS F6
W2 V11
VSS F11
V15 V11 Y4 V11
VSS F20
Y8 V11
VSS G2
COUT_V11_NFET Y12 V11
VSS G15
LAST MILE Y17 V11
VSS H2
REGULATOR
EXTERNAL NFET VSS J1
E1 NMOS_CTRL VSS J2
V15 VSS J3
K10 V15 VSS J9
VSS J13
VSS J21
VSS K2
VDD_HV_B VSS K3
R6 VDD_HV_B
VSS L2
CBULK CDEC CDEC CDEC CDEC CDEC U2 VDD_HV_B
VSS L3
U9 VDD_HV_B
VSS L6
U12 VDD_HV_B VSS L11
Y6 VDD_HV_B VSS L16
Y10 VDD_HV_B VSS M1
VDD_HV_A VSS M2
B6 VDD_HV_A VSS M20
CBULK CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC B12 VDD_HV_A VSS N9
B19 VDD_HV_A VSS N13
C2 VDD_HV_A VSS P7
E20 VDD_HV_A VSS R9
VDD_HV_A
F16 VDD_HV_A VSS R12
G7 VDD_HV_A VSS T2
CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC
J12 VDD_HV_A VSS T6
K9 VDD_HV_A VSS T16
K15 VDD_HV_A VSS U20
L20 VDD_HV_A VSS V2
M13 VDD_HV_A VSS V4
N10 VDD_HV_A VSS V9
R7 VDD_HV_A VSS V12
R11 VDD_HV_A VSS V18
VDD_DCDC Q_SMPS L_SMPS V15
V20 VDD_HV_A VSS Y2
Y15 VDD_HV_A VSS Y5
CBULK Y19 VDD_HV_A VSS Y9
D_SMPS COUT_V15_SMPS CDEC
VSS Y13
VSS Y16
M7 PMOS_CTRL VSS Y20
N7 VDD_DCDC
SMPS option

V25
L9 V25
COUT_V25

Figure 30. 437BGA package decoupling capacitor pinout diagram, SMPS(S32K389)

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 47 / 152
NXP Semiconductors
Power management

6.4 V15 regulator (SMPS option) electrical specifications

Some devices (S32K358, S32K348, S32K338, S32K328, S32K388 and S32K389) support a SMPS, DC-DC buck converter
stage, with a dedicated pin to control an external Power P-channel MOSFET. In addition to the PMOS, an external inductor and
a Schottky diode are required. See related figures in section "Recommended decoupling capacitors".
The chip hardware design guidelines document lists the recommended part numbers for PMOS, Schottky diode and inductor.

Table 12. V15 regulator (SMPS option) electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

V15 V15 output — 1.5 — V — —

L_SMPS External coil — 4.7 — uH — —

inductance

COUT_V15_SMPS External bypass — 20-22 — uF — —

capacitor

D_SMPS External Schottky — 2 — A — —

diode average
forward current

VR Schottky diode 5.0 — — V — —

reverse voltage

IF Schottky diode 1.0 — — A — —

forward current

— External P-channel — — 10 nC VDD_DCDC = 5V —

MOSFET total gate
charge

— External P-channel — — 2 V — —
MOSFET threshold
voltage

CBULK_SMPS Input supply bulk — 22 — µF — —

capacitor for internal
SMPS 1

1. Highly Recommended when internal SMPS is used to generate V15 and VDD_DCDC is supplied with isolated source from
VDD_HV_A or VDD_HV_B

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 48 / 152
NXP Semiconductors
Power management

L_SMPS
VDD_DCDC
Q_SMPS V15
High-current
Logic supply
(1.5 V)

CBULK_SMPS D_SMPS COUT_V15_SMPS

VDD_DCDC

PMOS_CTRL

VSS_DCDC

Figure 31. SMPS circuit

6.5 V15 regulator (BJT option, NPN ballast transistor control) electrical specifications
Some devices (S32K358, S32K348, S32K338, S32K328, S32K344, S32K324, S32K314, S32K342, S32K322, S32K341) support
a linear regulator stage, with a dedicated pin to control an external NPN bipolar transistor. The chip hardware design guidelines
document lists the recommended part numbers for the external devices.

Table 13. V15 regulator (BJT option, NPN ballast transistor control) electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

V15 V15 output — 1.51 — V — —

V15 V15 input — 1.5 — V — —

IBCTL IBCTL (V15 reg) 10 — — mA — —

source

IBCTL IBCTL (V15 reg) sink — — -50 uA — —

tsettle_lm Required setting 2 — — us — —

time from activating
last mile regulator to
load change

VDD_HV_NPN Input voltage supply 2.5 3.3 or 5 — V — —

for NPN external
ballast transistor

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 49 / 152
NXP Semiconductors
Power management

BJT option VDD_HV_NPN

IBCTL
PTE13 | VRC_CTRL Q_V15_NPN
External NPN
Ballast transistor
RBTC15
2.2k
V15 High-current
Logic supply (1.5V)
V15
COUT_V15_NPN
2.2uF

Figure 32. Ballast circuit

6.6 V11 regulator (NMOS ballast transistor control) electrical specifications

The chip hardware design guidelines document lists the recommended part number for NMOS. The S32K388 and S32K389
supports a linear regulator stage for the V11 supply, with a dedicated pin to control an external NMOS transistor.

Table 14. V11 regulator (NMOS ballast transistor control) electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

V11 V11 output — 1.14 — V — —

VTH_NMOS Vth of external — — 1.5 V For 3.3 V supply —

NMOS

VTH_NMOS Vth of external — — 2 V For 5.0 V supply —

NMOS

IDS_NMOS IDS of external 3 — — A — —

NMOS

tsettle_lm Required setting 10 — — us — —

time from V11 in
FPM to load change

CNMOS NMOS gate stability — 1 — nF — —

capacitor

6.7 Supply currents

NOTE
All data in this table is preliminary and based on first samples.

Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user
configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the
device), temperature = 25 °C, and typical silicon process unless otherwise stated. In STANDBY configuration, no current flows
through the V15 supply.

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Power management

Table 15. STANDBY mode supply currents

STANDBY 1

VDD_HV_A 2 VDD_HV_B 2

All clocks &

FIRC ON (24
peripherals SIRC ON All Config.
MHz)
OFF
(µA) (µA)
(mA)
Chip Ambient Temperature (°C) (µA)

S32K389 25, typ 3 TBD TBD TBD TBD

25, max 4 TBD TBD TBD TBD

85, typ 3 TBD TBD TBD TBD

85, max 4 TBD TBD TBD TBD

105, typ 3 TBD TBD TBD TBD

105, max 4 TBD TBD TBD TBD

125, max 4 TBD TBD TBD TBD

125, typ 3 TBD TBD TBD TBD

S32K388 25, typ 3 74.0 74.0 2.236 3.5

25, max 4 233.2 236.4 2.658 5.6

85, typ 3 390.3 390.9 2.557 7.5

85, max 4 1165.2 1206.3 3.327 17.6

105, typ 3 747.5 747.9 2.915 14.3

105, max 4 2277.7 2352.5 4.319 38.4

125, typ 3 1389.9 1390.1 3.558 30.7

125, max 4 4192.3 4243.1 6.044 85.4

S32K358, 25, typ 3 64.9 67.1 1.5137 1.9

S32K348,
S32K338, S32K328 25, max 4 194.0 204.9 2.0132 3.9

85, typ 3 326.5 326.4 1.7222 6.1

85, max 4 1586.3 1621.4 3.2009 17.9

105, typ 3 617.8 621.6 2.0290 12.3

105, max 4 2977.6 2997.1 4.4926 33.8

Table continues on the next page...

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Power management

Table 15. STANDBY mode supply currents (continued)

125, typ 3 1179.5 1180.2 2.5613 32.0

125, max 4 4997.2 5067.0 6.4388 77.8

S32K344, 25, typ 3 50 52 0.91 1.8

S32K324, S32K314
25, max 4 153 153 1.09 3.8

85, typ 3 315 316 1.18 6.1

85, max4 900 910 1.78 15.4

105, typ 3 498 530 1.40 8.5

105, max 4 1672 1682 2.55 26.2

125, typ 3 932 998 1.88 18.5

125, max 4 2638 2650 3.5 47.3

S32K342, 25, typ 3 46.5 49 0.900 1.8

S32K322, S32K341
25, max 4 88 94 1.090 3.5

85, typ 3 220.5 239.4 1.1619 5.4

85, max 4 627.0 642.9 1.587 13.9

105, typ 3 428.3 456.5 1.3638 7.3

105, max 4 1272.6 1301.6 2.2098 22.5

125, typ 3 715.2 745 1.6279 16.7

125, max 4 2113.4 2160.6 3.0016 41.6

S32K312 25, typ 3 40 41 0.887 NA

25, max 4 79 80 1.031

85, typ 3 178 178 1.027

85, max 4 496 497 1.422

105, typ 3 350 346 1.197

105, max 4 994 997 1.924

125, typ 3 620 611 1.457

125, max 4 1788 1792 2.761

Table continues on the next page...

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Power management

Table 15. STANDBY mode supply currents (continued)

S32K311, S32K310 25, typ 3 38.9 39.8 1.365 NA

25, max 4 77.2 79.8 1.823

85, typ 3 144.3 144.9 1.480

85, max 4 491.5 494.8 2.263

105, typ 3 263.8 264.2 1.559

105, max 4 937.4 947.1 2.597

125, typ 3 508.5 510 1.811

125, max 4 1740.1 1760.3 3.488

1. See the configurations in Table 21.

2. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the
application.
3. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =
5.0V, VDD_HV_B = 5.0V, for the typical silicon process..
4. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, for the fast silicon process.

NOTE
All data in this table is preliminary and based on first samples.

Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user
configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the
device), temperature = 25 °C, and typical silicon process unless otherwise stated.

Table 16. Low speed RUN mode supply currents

Low Speed RUN Mode (mA) 1

[Clock Option C] FIRC @ 24 MHz

[Clock Option C] FIRC @ 24 MHz

[Clock Option E] FIRC @3 MHz

[Clock Option E] FIRC @3 MHz

[Clock Option D] FIRC @48 MHz

[Clock Option D] FIRC @48 MHz

All Config2.
[Last Mile Disabled]

[Last Mile Enabled]

Low Speed RUN 2

Low Speed RUN 2

[Last Mile Disabled]

[Last Mile Enabled]

[Last Mile Disabled]

[Last Mile Enabled]

Low Speed RUN 2

Low Speed RUN 2

BOOT Mode 2

BOOT Mode 2
Ambient Temperature (°C)

VDD_HV_A 3, 4

VDD_HV_A 3, 4

VDD_HV_A 3, 4

VDD_HV_A 3, 4

VDD_HV_A 3, 4

VDD_HV_A 3, 4

VDD_HV_B 3
6

V15 5/ V116

V116

V15 5/ V116

V116

V15 5/ V116
V11

5/

5/
5/

V15

V15
V15

Chip

Table continues on the next page...

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Table 16. Low speed RUN mode supply currents (continued)

S32K389 25, typ 7 NA TBD TBD NA TBD TBD NA TBD TBD TBD

25, max 8 TBD TBD TBD TBD TBD TBD TBD

85, typ 7 TBD TBD TBD TBD TBD TBD TBD

105, typ 7 TBD TBD TBD TBD TBD TBD TBD

105, max 8 TBD TBD TBD TBD TBD TBD TBD

125, typ 7 TBD TBD TBD TBD TBD TBD TBD

125, TBD TBD TBD TBD TBD TBD TBD

max 8, 9

85, max 8 TBD TBD TBD TBD TBD TBD TBD

S32K388 25, typ 7 NA 2.7 43.0 NA 2.7 18.9 NA 2.7 70.4 2.4

25, max 8 3.8 153.6 3.1 129.2 3.9 180.7 2.8

85, typ 7 2.7 108.2 2.7 84.0 2.7 136.2 2.4

85, max 8 4.0 289.7 3.9 266.8 4.1 317.7 2.8

105, typ 7 2.8 216.8 2.8 192.7 2.9 243.7 2.4

105, max 8 4.2 534.9 4.2 516.1 4.3 558.8 2.8

125, typ 7 3.0 343.8 3.0 320.5 3.1 371.1 2.4

125, 5.5 936.1 5.3 915.7 5.6 960.0 2.8

max 8, 9

S32K358, 25, typ 7 NA 3.1 34.1 NA 3.0 8.5 NA 3.2 63.3 1.6
S32K348,
S32K338, 25, max 8 3.6 52.7 3.5 26.4 3.7 83.0 2.4
S32K328
85, typ 7 3.1 60.6 3.1 34.9 3.2 90.2 1.6

85, max 8 3.7 182.9 3.7 155.5 3.8 212.3 2.4

105, typ 7 3.2 88.4 3.2 62.4 3.3 117.8 1.6

105, max 8 3.9 297.2 3.9 273.9 4.0 323.4 2.4

125, typ 7 3.5 136.6 3.4 110.5 3.5 166.3 1.6

125, 4.5 494.9 4.4 468.6 4.7 521.0 2.4

max 8, 9

Table continues on the next page...

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NXP Semiconductors
Power management

Table 16. Low speed RUN mode supply currents (continued)

S32K344, 25, typ 7 20.5 - 2.8 17.9 6.4 - 2.8 4.5 37.2 - 2.9 34 0.6
S32K324,
S32K314 25, max8 29.4 - 3.3 27.2 14.8 - 3.3 12.6 46.8 - 3.4 46.6 0.8

85, typ 7 34.2 - 2.9 31.2 19.7 - 2.9 17.5 50.4 - 2.9 47.3 0.6

85, max 8 71.6 - 3.5 68.7 56.2 - 3.4 54 89.1 - 3.5 86.2 0.8

105, typ 7 46.1 - 2.9 43.1 31.7 - 2.9 29.3 62.2 - 2.9 59.2 0.6

105, max 8 114 - 3.7 111 99.1 - 3.6 96.1 131 - 3.9 128 0.8

125, typ 7 69.9 - 3.0 66.8 55.8 - 3.0 53.1 86 - 3.1 83 0.6

125, 161 - 4.2 159 148 - 4.1 145 178 - 4.3 176 0.8
max 8, 9

S32K342, 25, typ 7 19.6 - 2.8 17.6 6.0 - 2.8 4.0 36.2 - 2.9 33 0.5
S32K322,
S32K341 25, max 8 25 - 3.3 24.9 8.8 - 3.3 8.2 41.4 - 3.4 40.8 0.8

85, typ 7 28.8 - 2.9 26.8 15.2 - 2.9 13.4 45.7 - 2.9 42.4 0.5

85, max 8 41.8 - 3.5 39.6 27.7 - 3.4 25.9 58.7 - 3.5 55.3 0.8

105, typ 7 38.6 - 2.9 36.9 25 - 2.9 23.3 55.6 - 2.9 52.4 0.5

105, max 8 63.1 - 3.7 61.5 49 - 3.7 46.5 80.1 - 3.9 77.2 0.8

125, typ 7 50.7 - 2.9 49.6 37.2 - 2.9 35.5 67.9 - 3.0 64.7 0.5

125, 88.2 - 4.1 88.5 75.3 - 4.0 73.3 105.2 - 4.2 103.1 0.8
max 8, 9

S32K312 25, typ 7 15 NA NA 5 NA NA 26 NA NA NA

25, max 8 20 10 32

85, typ 7 20 10 31

85, max 8 35.2 24.6 46.4

105, typ 7 26.1 16.2 37

105, max 8 52.9 42.6 64.2

125, typ 7 35.3 25.3 46.4

125, 79.8 66.9 90.1

max 8, 9, 10

Table continues on the next page...

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NXP Semiconductors
Power management

Table 16. Low speed RUN mode supply currents (continued)

S32K311, 25, typ 7 12.9 NA NA 4.4 NA NA 22.4 NA NA NA

S32K310
25, max 8 14.9 6.0 24.8

85, typ 7 16.0 7.5 25.6

85, max 8 31.0 22.2 41.1

105, typ 7 19.1 10.5 28.7

105, max 8 45.8 36.8 55.6

125, typ 7 25.2 16.5 34.7

125, 73.2 64.3 82.4

max 8, 9, 10

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the example configurations in Table 21
3. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the
application.
4. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
5. RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail
6. For S32K388, the current from a V15 supply will flow through the external NMOS for the V11 regulation stage, and into the
V11 pins of the device.
7. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =
5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.
8. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process.
9. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum
specification, TJ < 150°C, to avoid self-heating.
10. If the total power dissipation would cause the junction temperature to be exceeded when VDD_HV_A is at 5V, then
VDD_HV_A should be limited to operate at 3.3V.

NOTE
All data in this table is preliminary and based on first samples.

Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user
configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the
device), temperature = 25 °C and typical silicon process unless otherwise stated.

Table 17. RUN mode supply currents (peripherals disabled) for S32K3x8, S32K34x, S32K32x and S32K314

Ambient RUN Mode (mA) 1

Temperature
Chip (°C)

Table continues on the next page...

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NXP Semiconductors
Power management

Table 17. RUN mode supply currents (peripherals disabled) for S32K3x8, S32K34x, S32K32x and S32K314 (continued)

Min. Config. 2 [Clock Option F]

Min. Config. 2 [Clock Option B]

Min. Config. 2 [Clock Option A]

Min. Config. 2 [Clock Option F]

Min. Config. 2 [Clock Option B]

Min. Config. 2 [Clock Option A]

Min. Config. 2 [Clock Option A+]

Min. Config. 2 [Clock Option A++]

All. Config. 2

All. Config. 2
Single Core @120 MHz

Single Core @160 MHz

Single Core @80 MHz

Dual Core @120 MHz

Dual Core @160 MHz

Triple Core @240 MHz

Dual Core @80 MHz

1xLS + 3xCores @320 MHz

VDD_HV_A 5, 6
VDD_HV_B 5
V15 3/ V11 4

V15 3/ V114

V15 3/ V114

V15 3/ V114

V15 3/ V114

V15 3/ V114

V15 3/ V114

V15 3/ V114
S32K389 25, typ 7,10 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

25, max 8,11 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

85, typ 10 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

85, max 11 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

105, typ 10 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

105, max 11 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

125, typ 10 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

125, TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
max11, 9,12

S32K388 25, typ 10 NA 196.2 NA 231.4 339.4 440.3 2.4 3.6

25, max 11 291.4 318.4 456.6 565.3 2.8 4.3

85, typ 10 277.1 312.6 420.9 520.5 2.4 3.7

85, max 11 500.8 533.3 634.3 745.9 2.8 4.6

105, typ 10 351.8 387.2 495.3 593.8 2.4 3.8

105, max 11 703.3 737.6 837.6 951.5 2.8 5.1

125, typ 10 468.7 503.5 610.4 707.9 2.4 4.0

125, 993.5 1040.0 1147.0 1254.1 2.8 5.7

max11, 12

Table continues on the next page...

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NXP Semiconductors
Power management

Table 17. RUN mode supply currents (peripherals disabled) for S32K3x8, S32K34x, S32K32x and S32K314 (continued)

S32K358, 25, typ10 100.6 118.9 144.8 103.3 124.1 166.6 NA NA 1.8 4.8
S32K348,
S32K338, 25, max11 119.8 138.9 165.6 122.8 144.4 186.3 3.0 5.4
S32K328
85, typ 10 126.9 145.3 171.6 129.8 150.9 193.8 1.8 6.1

85, max 11 248.1 267.7 294.4 250.8 274.3 317.6 3.0 6.7

105, typ 10 153.4 172.0 198.4 156.6 178.0 221.2 1.8 6.1

105, max 11 349.5 371.6 398.2 358.3 381.4 423.7 3.0 6.9

125, typ 10 199.3 218.2 245.0 203.3 225.0 268.3 1.8 6.4

125, 529.7 551.2 580.9 538.0 563.3 603.0 3.0 7.4

max11, 12

S32K344, 25, typ 10 51.3 54.8 69.6 62.7 75.1 97.5 NA NA 0.6 3.1
S32K324,
S32K314 25, max 11 60.2 64.5 80.4 73.3 86.8 110 0.8 3.6

85, typ 10 64.5 68.1 83.1 76.2 89 111 0.6 3.2

85, max 11 104 108 124 117 131 155 0.8 3.9

105, typ 10 75.4 79 93.9 87.3 100 122.6 0.6 3.2

105, max 11 145 149 166 159 173 197 0.8 4.0

125, typ 10 97.4 101.2 116.4 110 122.9 145.7 0.6 3.3

125, 191 196 212 206 220 245 0.8 4.3

max 11, 12

S32K342, 25, typ 10 49.5 52.2 66.3 58.9 72.7 93.7 0.5 3.0
S32K322,
S32K341 25, max 11 58.5 62.4 75.9 68.1 82.9 104.6 NA NA 0.8 3.6

85, typ 10 58.6 63.6 75.7 67.9 82.3 106.1 0.5 3.0

85, max 11 89.6 102.3 110.8 105.4 124.1 155 0.8 3.8

105, typ 10 68.3 76 85.6 80 92.3 119.3 0.5 3.1

105, max 11 124 143.4 157.5 150.5 164.5 191.6 0.8 4.0

125, typ 10 79.8 85.1 97.1 89.1 103.8 140.1 0.5 3.2

125, 146.7 164.7 178 171.3 188.7 235.6 0.8 4.2

max 11, 12

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the configurations in Table 22.
3. RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail.

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NXP Semiconductors
Power management

4. For S32K388, the current from a V15 supply will flow through the external NMOS for the V11 regulation stage, and into the
V11 pins of the device.
5. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the
application.
6. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
7. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =
5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.
8. "max" is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15= 1.65V, for the fast silicon process.
9. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum
specification, TJ < 150°C, to avoid self-heating.
10. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =
5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.
11. "max" is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15= 1.65V, for the fast silicon process.
12. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum
specification, TJ < 150°C, to avoid self-heating.

NOTE
The data in this table is preliminary and based on first samples.

Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user
configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the
device), temperature = 25 °C and typical silicon process unless otherwise stated.

Table 18. RUN mode supply currents (peripherals disabled) for S32K312, S32K311, S32K310

RUN Mode (mA) 1

Min. Config. 2 Min. Config. 2

Single Core @80 MHz Single Core @120 MHz
[Clock Option F] [Clock Option B]
VDD_HV_A 3, 4

VDD_HV_A 3, 4
V15 5/ V11

V15 5/ V11
Ambient
Chip Temperature (°C)

S32K312 25, typ 6 37 NA 37 NA

25, max 7 44 47

85, typ 6 42 43

85, max 7 58.5 59.7

105, typ 6 48.1 48.7

105, max 7 76.4 77.8

125, typ 6 56.5 57

125, max 7, 8, 9 98.7 99.9

Table continues on the next page...

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NXP Semiconductors
Power management

Table 18. RUN mode supply currents (peripherals disabled) for S32K312, S32K311, S32K310 (continued)

S32K311 , S32K310 25, typ 6 34.9 NA 36.5 NA

25, max 7 39.1 41.1

85, typ 6 38.1 39.8

85, max 7 54.2 55.9

105, typ 6 41.5 43.2

105, max 7 69.1 71.1

125, typ 6 47.7 49.4

125, max 7, 8, 9 97 99.1

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the configurations in Table 22.
3. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the
application.
4. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
5. RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail.
6. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =
5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.
7. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process.
8. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum
specification, TJ < 150°C, to avoid self-heating.
9. If the total power dissipation would cause the junction temperature to be exceeded when VDD_HV_A is at 5V, then
VDD_HV_A should be limited to operate at 3.3V.

NOTE
The data in this table is preliminary and based on first samples.

Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user
configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the
device), temperature = 25 °C and typical silicon process unless otherwise stated.

Table 19. Example RUN mode configuration supply currents for S32K3x8, S32K34x, S32K32x and S32K314

RUN Mode (mA) 1

Dual Core @160 MHz

Single Core @160 MHz

Dual Core @120 MHz

Single Core @120 MHz

Single Core @80 MHz

Dual Core @240 MHz

Triple Core @240 MHz

Config. 7 2

All Config. 2

All Config. 2
Config. 6-1 2

Config. 6-2 2
Config. 1 2

Config. 3 2

Config. 5 2
Config. 2 2

Config. 4 2

Ambient
Temperature
Chip (°C)

Table continues on the next page...

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NXP Semiconductors
Power management

Table 19. Example RUN mode configuration supply currents for S32K3x8, S32K34x, S32K32x and S32K314 (continued)

1xLS + 3x Core (with AES and

ENET2 enabled)@320 MHz

VDD_HV_A 5, 6
VDD_HV_B 5
V15 3/ V114

V15 3/ V114

V15 3/ V114

V15 3/ V114

V15 3/ V114

V15 3/ V114

V15 3/ V114
V15 3/V114

S32K389 25, typ 7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

25, max 8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

85, typ 7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

85, max 8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

105, typ 7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

125, typ 7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

125, max 8, 9 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

105, max 8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

S32K388 25, typ 7 255.4 241.3 NA 310.8 393.1 620.1 3.0 3.8

25, max 8 382.6 378.0 424.4 525.5 774.2 3.3 4.5

85, typ 7 324.3 309.5 392.6 474.5 701.5 3.0 3.8

85, max 8 499.7 501.2 610.4 712.3 952.4 3.3 4.7

105, typ 7 426.8 425.1 466.9 548.5 774.5 3.0 3.9

105, max 8 731.2 738.1 823.2 918.7 1160.6 3.3 5.2

125, typ 7 554.5 538.7 582.4 663.4 887.5 3.0 4.1

125, max 8, 9 1128.4 1121.0 1169.6 1227.0 1467.4 3.3 5.9

S32K358, 25, typ 7 207.6 168.6 177.5 146.8 114.9 313 380.2 NA 2.1 5.3
S32K348,
25, max 8 229.4 188.3 197.4 167.9 135.3 340 395.9 3.2 6.0

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Table 19. Example RUN mode configuration supply currents for S32K3x8, S32K34x, S32K32x and S32K314 (continued)

S32K338, 85, typ 7 235.5 195.9 205.1 174.0 141.6 333.4 413.6 2.1 6.3
S32K328
85, max 8 363.7 322.1 331.3 299.2 263.2 418.5 552.8 3.2 7.1

105, typ 7 263.5 223.5 233.0 201.5 168.9 360.4 446.1 2.1 6.4

105, max 8 472.4 429.8 438.8 407.1 369.8 516.5 682.8 3.2 7.1

125, typ 7 311.9 271.3 281.0 249.0 216.2 413.8 501.0 2.1 6.7

125, max 8, 9 661.0 618.2 624.6 588.8 554.2 707 844.0 3.2 7.9

S32K344, 25, typ 7 119 102 106 80 68 NA NA NA 0.6 3.1

S32K324,
S32K314 25, max 8 133 115 119 92 79 0.8 3.6

85, typ 7 134 116 120 94 81.8 0.6 3.2

85, max 8 180 160 165 137 123 0.8 3.9

105, typ 7 145 128 132 105 93 0.6 3.2

105, max 8 222 203 208 179 165 0.8 4.0

125, typ 7 169 151 155 128 116 0.6 3.3

125, max 8, 9 271 250 256 226 213 0.8 4.5

S32K342, 25, typ 7 115.3 93.2 96.1 79.6 64.1 NA NA NA 0.5 3.0
S32K322,
S32K341 25, max 8 128.9 109.3 109.8 90.9 74.5 0.8 3.6

85, typ 7 125.0 102.7 105.8 89.2 73.6 0.5 3.0

85, max 8 178.8 126.5 132.0 105.0 92.5 0.8 3.6

105, typ 7 135.2 111.9 115.5 98.6 83.4 0.5 3.1

105, max 8 219.6 184.6 188.5 168.5 152.5 0.8 3.8

125, typ 7 145.8 123.8 127.3 110.2 94.7 0.5 3.1

125, max 8, 9 258.1 235.2 243.9 206.9 183.7 0.8 4.3

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the configurations in Table 22.
3. RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail.
4. For S32K388, the current from a V15 supply will flow through the external NMOS for the V11 regulation stage, and into the
V11 pins of the device.
5. IO current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application.
6. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
7. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =
5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.
8. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process.

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9. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum
specification, TJ < 150°C, to avoid self-heating.

Table 20. Example RUN mode configuration supply currents for S32K312, S32K311, S32K311

RUN Mode (mA) 1

Config. 4 2 Config. 5 2
Single Core Single Core
@120 MHz @80 MHz

VDD_HV_A 3, 4

VDD_HV_A 3, 4

V15 5/ V11
V15 5/V11
Ambient
Chip Temperature (°C)

S32K312 25, typ 6 54 NA 44 NA

25, max 7 62 54

85, typ 6 60 49

85, max 7 76.4 66.3

105, typ 6 65.8 55

105, max 7 94.4 84.4

125, typ 6 78.6 64.7

125, max 7, 8, 9 120.7 110.5

S32K311, S32K310 25, typ 6 53.4 NA 43 NA

25, max 7 57.7 51.2

85, typ 6 56.8 50.8

85, max 7 73.2 66

105, typ 6 60.1 54

105, max 7 88.5 81.9

125, typ 6 66.3 60.2

125, max 7, 8,9 115.3 109.3

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the configurations in Table 22.
3. IO current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application.
4. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
5. RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail.
6. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A = 5.0V,
VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process

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7. "max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),
VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon proce
8. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum
specification, TJ < 150°C, to avoid self-heating.
9. If the total power dissipation would cause the junction temperature to be exceeded when VDD_HV_A is at 5V, then VDD_HV_A
should be limited to operate at 3.3V.

6.8 Operating mode

Table 21. STANDBY and low speed RUN configuration options

STANDBY STANDBY STANDBY BOOT Mode Low Speed RUN FIRC Mode
(OptionC1, FIRC (OptionE 1, FIRC
All OFF SIRC ON FIRC ON (OptionD 1, FIRC
@24 MHz) @ 3MHz)
MODULE @48 MHz)

Core M7_0/1 OFF OFF OFF 24 MHz 3 MHz 48 MHz

HSE_B OFF OFF OFF 24 MHz 3 MHz 48 MHz

FIRC OFF OFF 24 MHz 24 MHz 3 MHz 48 MHz

FXOSC OFF OFF OFF OFF OFF OFF

SIRC OFF ON OFF ON ON ON

PLL OFF OFF OFF OFF OFF OFF

Flash OFF OFF OFF ON ON ON

eDMA OFF OFF OFF ON ON ON

FlexCAN All OFF All OFF All OFF All OFF All OFF All OFF

LPUART All OFF All OFF All OFF All OFF All OFF All OFF

LPSPI All OFF All OFF All OFF All OFF All OFF All OFF

LPI2C All OFF All OFF All OFF All OFF All OFF All OFF

EMAC/GMAC OFF OFF OFF OFF OFF OFF

eMIOS All OFF All OFF All OFF All OFF All OFF All OFF

SAR_ADC All OFF All OFF All OFF All OFF All OFF All OFF

LPCMP All OFF All OFF All OFF All OFF All OFF All OFF

1. See clocking use case examples in the Clocking chapter of the S32K3xx Reference Manual.

Table 22. RUN mode configuration options

Min. Min. Min. Min. Min. Config. Config. Config. Config. Config. Config. Config. Config.
Config. Config. Config. Config. Config. 1 2 3 4 5 6-1 6-2 7
MODU
(Optio (Optio (Optio (Optio (Optio
LE nA+1), nA+

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Table 22. RUN mode configuration options (continued)

nF1), nB1), nA1), PLL@ +1), Dual Single Dual Single Single Dual Triple 1xLS +
PLL@ PLL@ PLL@ 240 PLL@ Core Core Core Core Core Core Core 3x
80 120 160 MHz 320 cores
MHz @160 @160 @120 @120 @80M @240 @240
MHz MHz MHz @320
MHz MHz MHz MHz Hz MHz MHz
MHz

Core 80 120 160 240 320 160 160 120 120 80 240 240 320
M7_0 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz

Core 80 120 160 240 320 160 - 120 - - 240 240 320
M7_1 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz

Core - - - 240 320 - - - - - - 240 320

M7_2 MHz MHz MHz MHz

Core - - - - 320 - - - - - - - 320

M7_3 MHz MHz

HSE_B 80 120 80 120 160 80 80 120 120 80 120 120 160

2 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz

FIRC ON ON ON ON ON ON ON ON ON ON ON ON ON

FXOS ON ON ON ON ON ON ON ON ON ON ON ON ON
C

SIRC ON ON ON ON ON ON ON ON ON ON ON ON ON

PLL ON ON ON ON ON ON ON ON ON ON ON ON ON

Flash ON ON ON ON ON ON ON ON ON ON ON ON ON

eDMA ON ON ON ON ON ON ON ON ON ON ON ON ON

FlexC All All All All All 6x 2x 4x 6x 1x 8x 8x 8x

AN3 OFF OFF OFF OFF OFF

LPUA All All All All All 16x 4x 10x 8x 7x 16x 16x 16x
RT4 OFF OFF OFF OFF OFF

LPSPI All All All All All 6x 4x 4x 4x 3x 5x 5x 5x

5 OFF OFF OFF OFF OFF

LPI2C6 All All All All All All 2x 2x 2x All 1x 1x 1x

OFF OFF OFF OFF OFF OFF OFF

EMAC/ OFF OFF OFF OFF OFF ON OFF ON OFF OFF ON ON ON

GMAC
7

SAI OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF

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Table 22. RUN mode configuration options (continued)

QSPI OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON

eMIOS All All All All All All 3x 3x 2x 2x 2x 2x 2x

8 OFF OFF OFF OFF OFF OFF

SAR_A All All All All All All 3x 3x 2x 2x 3x 3x 3x

DC9 OFF OFF OFF OFF OFF OFF

LPCM All All All All All All 2x 3x All All OFF OFF OFF
P10 OFF OFF OFF OFF OFF OFF OFF OFF

1. See clocking use case examples in the Clocking chapter of the S32K3xx Reference Manual.
2. HSE_B: After start-up, the HSE core is in WFI.
3. • FlexCAN0: Transmitting an 8-byte CAN-FD data frame at 5 Mbps, every 10 ms.
• FlexCAN1: Transmitting a 64-byte CAN-FD data frame at 2 Mbps, every 20 ms.
• FlexCAN2-5: Transmitting an 8-byte CAN data frame at 500 Kbps, every 20 ms.
4. LPUART0-15: Transmitting at 19200 bps, every 100ms.
5. • LPSPI0: Transmitting 32 bits at 20 Mbps (GPIO Fast pads), every 5 ms.
• LPSPI1-5: Transmitting 32 bits at 1 Mbps, every 5 ms.
6. LPI2C0-1: Transmitting 3 bytes at 400 Kbps, every 100ms.
7. EMAC/GMAC: ON for MII interface.
8. • eMIOS0: 6 channels in PWM mode @ 20 KHz.
• eMIOS1-2: 8 channels in PWM mode @ 400 Hz.
9. • SAR_ADC0: 16 channels at 400 Hz rate, BCTU triggered.
• SAR_ADC1-2: 4 channels at 20 KHz rate, BCTU triggered.
10. LPCMP0: 8 channels enabled; LPCMP1-2: 4 channels enabled.

6.9 Cyclic wake-up current

The cyclic wake-up current is the calculated average current consumption during the periodic switching between RUN mode and
STANDBY mode. This average current can be calculated with the following formula:
ICYCL = RUN Current According to Ratio + STANDBY Current According to Ratio
Where the Current According to Ratio value is calculated as follows:
Current According to Ratio = Supply Current × Ratio of Duration
As an example, the following data was obtained with an application that periodically (every 40ms) alternates between RUN mode,
for approximately 200μs to scan several GPIO inputs (51 GPIOS), and spends the rest of the time in STANDBY mode.

Table 23. Cyclic wake-up current example

Device Supply Current1 Duration 2 [ms] Ratio of Current ICYCL -

Chip Operating Mode [μA] Duration 3 According to Average current
Ratio 4 [μA] 5 [μA]

S32K314 RUN 20000 0.2 0.005 100 159.7

STANDBY 60 39.8 0.995 59.7

1. The supply current is obtained through the measurements of the current during the corresponding operating mode.
2. The duration is defined by the application (how much time will the device spend in the according operating mode).
3. The ratio of duration is obtained by dividing the duration of the corresponding operating mode by the total duration of the
application.
4. The current according to ratio is obtained by multiplying the supply current and the ratio of duration related to the proper
operating mode.

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5. The average current is calculated by the addition of each device operating mode’s current according to ratio.

7 I/O parameters

7.1 GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)

The leakage current on the GPIO pins is specified as a function of the pad type (Standard, Standard Plus, Medium, Fast, or GPI)
and the number of Analog functions (CMP and ADC channels) multiplexed per pin.
For S32K388, see the ILKG column in the Pinout section of the IOMUX file attached to the Reference Manual.
For other devices, the "Analog Function Count" is defined from the number of CMP and ADC channels multiplexed to a given
pin. This information can be obtained from the "Direct Signals" column in the IOMUX files attached to the Reference Manual. The
"Analog Function Count" is shown in the Condition column of the following table.

Table 24. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)

Symbol Description Min Typ Max Unit Condition Spec

Number

VIH Input high level DC 0.70 x — VDD_HV V VDD_HV_A/B = 3.3V —

voltage threshold VDD_HV _A/B +
_A/B 0.3

VIL Input low level DC VSS - 0.3 — 0.30 x V VDD_HV_A/B = 3.3V —

voltage threshold VDD_HV
_A/B

WFRST RESET Input — — 33 ns — —

Filtered pulse width 1

WNFRST RESET Input not 100 — — ns — —

filtered pulse width 2

ILKG_33_S0 3.3V input leakage -133 — 300 nA Pins with Analog —

current for Standard Function Count = 0
GPIO 3

ILKG_33_S1 3.3V input leakage -545 — 445 nA Pins with Analog —

current for Standard Function Count = 1
GPIO 3

ILKG_33_S2 3.3V input leakage -749 — 517 nA Pins with Analog —

current for Standard Function Count = 2,
GPIO 3 plus PTA12, PTD1

ILKG_33_S3 3.3V input leakage -1288 — 679 nA Pins with Analog —

current for Standard Function Count = 3,
GPIO 3 plus PTD0

ILKG_33_S_PTE13 3.3V input leakage -1935 — 483 nA PMC VRC_CTRL pin —

current for Standard
GPIO 3

ILKG_33_SP0 3.3V input leakage -370 — 575 nA Pins with Analog —

current for Standard Function Count = 0
Plus GPIO and
RESET IO 3

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Table 24. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

ILKG_33_SP1 3.3V input leakage -660 — 659 nA Pins with Analog —

current for Standard Function Count = 1
Plus GPIO and
RESET IO 3

ILKG_33_SP2 3.3V input leakage -1094 — 794 nA Pins with Analog —

current for Standard Function Count = 2
Plus GPIO and
RESET IO 3

ILKG_33_M0 3.3V GPIO input -792 — 750 nA Pins with Analog —

leakage current for Function Count = 0
Medium GPIO 3

ILKG_33_M1 3.3V GPIO input -989 — 824 nA Pins with Analog —

leakage current for Function Count = 1,
Medium GPIO 3 plus PTC16, PTD5

ILKG_33_M2 3.3V GPIO input -1233 — 1248 nA Pins PTD6 and PTE8 —
leakage current for
Medium GPIO 3

ILKG_33_F0 3.3V GPIO input -1139 — 1178 nA Pins with Analog —

leakage current for Function Count = 0
Fast GPIO 3

ILKG_33_F1 3.3V GPIO input -1464 — 1239 nA Pins with Analog —

leakage current for Function Count = 1
Fast GPIO 3

ILKG_33_I 3.3V input leakage -120 — 120 nA — —

current for GPI 3

VHYS_33 Input hysteresis 0.06 x — — mV Always Enabled, —

voltage 4 VDD_HV Applies to S32K34x,
_A/B S32K3x8, S32K32x
and S32K314 devices.

VHYS_33 Input hysteresis 0.06 x — — mV Always Enabled, —

voltage VDD_HV Applies to S32K311,
_A/B S32K312, and
S32K310 devices.

CIN GPIO Input 2 4 6 pF add 2pF for package/ —

capacitance parasitic

IPU_33 3.3V GPIO pull up/ 20 — 60 kΩ pull up @ 0.3 x VDD_ —

down resistance HV_A/B, pull down @
0.7 x VDD_HV_A/B

IOH_33_S 3.3V output 1.0 — — mA VOH >= VDD_HV_A/B —

high current for - 0.7V
Standard GPIO 5,6

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Table 24. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

IOH_33_SP 3.3V output high 1.5 — — mA DSE = 0, VOH >= —

current for Standard VDD_HV_A/B - 0.7V
Plus GPIO and
RESET IO 5,6

IOH_33_M 3.3V output high 3 — — mA DSE = 0, VOH >= —

current for Medium VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_33_F 3.3V output high 4.5 — — mA DSE = 0, VOH >= —

current for Fast VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_33_SP 3.3V output high 3 — — mA DSE = 1, VOH >= —

current for Standard VDD_HV_A/B - 0.7V
Plus GPIO and
RESET IO 5,6

IOH_33_M 3.3V output high 6 — — mA DSE = 1, VOH >= —

current for Medium VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_33_F 3.3V output high 9 — — mA DSE = 1, VOH >= —

current for Fast VDD_HV_A/B - 0.7V
GPIO 5,6

IOL_33_S 3.3V output low 1.0 — — mA VOL <= 0.7V —

current for Standard
GPIO 5,6

IOL_33_SP 3.3V output low 1.5 — — mA DSE =0, VOL <= 0.7V —
current for Standard
Plus GPIO and
RESET IO 5,6

IOL_33_M 3.3V output low 3.0 — — mA DSE =0, VOL <= 0.7V —
current for Medium
GPIO 5,6

IOL_33_F 3.3V output low 4.5 — — mA DSE =0, VOL <= 0.7V —
current for Fast
GPIO 5,6

IOL_33_SP 3.3V output low 3 — — mA DSE =1, VOL <= 0.7V —

current for Standard
Plus GPIO and
RESET IO 5,6

IOL_33_M 3.3V output low 6 — — mA DSE =1, VOL <= 0.7V —

current for Medium
GPIO 5,6

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Table 24. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

IOL_33_F 3.3V output low 9 — — mA DSE =1, VOL <= 0.7V —

current for Fast
GPIO 5,6

FMAX_33_S 3.3V maximum — — 10 MHz 2.9V - 3.6V CL(max) = —

frequency for 25pF
Standard GPIO 5,7

FMAX_33_SP 3.3V maximum — — 25 MHz 2.9V - 3.6V CL (max) = —

frequency for 25pF
Standard Plus
GPIO 5,7

FMAX_33_M 3.3V maximum — — 50 MHz 2.9V - 3.6V CL (max) = —

frequency for 25pF
Medium GPIO 5,7

FMAX_33_F 3.3V maximum — — 120 MHz 2.9V - 3.6V CL(max) = —

frequency for Fast 25pF, for all S32K3xx
GPIO 5,7 except S32K3x8
devices

FMAX_33_F 3.3V maximum — — 125 MHz 2.9V - 3.6V, CL (max) —

frequency for Fast = 25pF, for S32K3x8
GPIO 5,7 devices

IOHT Output high current — — 100 mA — —

total for all ports 8

1. Maximum length of RESET pulse will be filtered by an internal filter on this pin.
2. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.
3. A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage
flowing out the pin with the pin at ground.
4. Hysteresis spec does not apply to fast pad
5. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for
system level simulations, as discrete values for I/O transition times are not representative of the I/O pad behavior when
connected to an actual transmission line load.
6. I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating
Conditions of this document.
7. I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.
A lumped 8pF load is assumed in addition to a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/inch. For
signals with frequency greater than 63MHz, a maximum 2 inch PCB trace is assumed. For best signal integrity, the series
resistance in the transmission line should be matched closely to the selected output resistance (ROUT_*) of the I/O pad.
8. To determine total switching current on any I/O supply, current values per output pin should not be incrementally summed.
I/O interfaces on the device are asynchronous to each other, so not all switching occurs at the same instant. Actual use
case must be considered.

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MCUsee note 1 PCB External

device
5 in.
(4 layer FR4)
CPCB = ~3.3 pF/inch * 5 inch

RDSON
RPCB = RDSON

RDSON CL = 8 pF

Notes:
1. See IBIS models for further details.

Figure 33. Reference Load Diagram

7.2 GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)

The leakage current on the GPIO pins is specified as a function of the pad type (Standard, Standard Plus, Medium, Fast, or GPI)
and the number of Analog functions (CMP and ADC channels) multiplexed per pin.
For S32K388, see the ILKG column in the Pinout section of the IOMUX file attached to the Reference Manual.
For other devices, the "Analog Function Count" is defined from the number of CMP and ADC channels multiplexed to a given
pin. This information can be obtained from the "Direct Signals" column in the IOMUX files attached to the Reference Manual. The
"Analog Function Count" is shown in the Condition column of the following table.

Table 25. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)

Symbol Description Min Typ Max Unit Condition Spec

Number

VIH Input high level DC 0.65 x — VDD_HV V VDD_HV_A/B = 5.0V —

voltage threshold VDD_HV _A/B +
_A/B 0.3

VIL Input low level DC VSS - 0.3 — 0.35 x V VDD_HV_A/B = 5.0V —

voltage threshold VDD_HV
_A/B

WFRST RESET Input filtered — — 33 ns — —

pulse width 1

WNFRST RESET Input not 100 — — ns — —

filtered pulse width 2

ILKG_50_S0 5.0V input leakage -193 — 389 nA Pins with Analog —

current for Standard Function Count = 0
GPIO 3

ILKG_50_S1 5.0V input leakage -691 — 580 nA Pins with Analog —

current for Standard Function Count = 1
GPIO 3

ILKG_50_S2 5.0V input leakage -947 — 673 nA Pins with Analog —

current for Standard Function Count = 2,
GPIO 3 plus PTA12, PTD1

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Table 25. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

ILKG_50_S3 5.0V input leakage -1614 — 879 nA Pins with Analog —

current for Standard Function Count = 3,
GPIO 3 plus PTD0

ILKG_50_S_PTE13 5.0V input leakage -2335 — 619 nA PMC VRC_CTRL pin —

current for Standard
GPIO 3

ILKG_50_SP0 5.0V input leakage -553 — 736 nA Pins with Analog —

current for Standard Function Count = 0
Plus GPIO and
RESET IO 3

ILKG_50_SP1 5.0V input leakage -855 — 846 nA Pins with Analog —

current for Standard Function Count = 1
Plus GPIO and
RESET IO 3

ILKG_50_SP2 5.0V input leakage -1389 — 1017 nA Pins with Analog —

current for Standard Function Count = 2
Plus GPIO and
RESET IO 3

ILKG_50_M0 5.0V input leakage -1036 — 951 nA Pins with Analog —

current for Medium Function Count = 0
GPIO 3

ILKG_50_M1 5.0V input leakage -1284 — 1057 nA Pins with Analog —

current for Medium Function Count = 1,
GPIO 3 plus PTC16, PTD5

ILKG_50_M2 5.0V input leakage -1518 — 1298 nA Pins PTD6 and PTE8 —
current for Medium
GPIO 3

ILKG_50_F0 5.0V input leakage -1675 — 1497 nA Pins with Analog —

current for Fast Function Count = 0
GPIO 3

ILKG_50_F1 5.0V input leakage -1805 — 1573 nA Pins with Analog —

current for Fast Function Count = 1
GPIO 3

ILKG_50_I 5.0V input leakage -150 — 150 nA — —

current for GPI 3

VHYS_50 input hysteresis 0.06 x — — mV Always enabled, —

voltage 4 VDD_HV Applies to S32K34x,
_A/B S32K3x8, S32K32x
and S32K314

VHYS_50 input hysteresis 0.06 x — — mV Always enabled, —

voltage VDD_HV Applies to S32K311,
_A/B

Table continues on the next page...

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NXP Semiconductors
I/O parameters

Table 25. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

S32K312 and S32K310

devices.

CIN GPIO Input 2 4 6 pF add 2pF for package/ —

capacitance parasitic

IPU_50 5.0V GPIO pull up/ 20 — 55 kΩ pull up @ 0.3 * VDD_ —

down resistance HV_*, pull down @ 0.7
* VDD_HV_*

IOH_50_S 5.0V output 1.6 — — mA VOH >= VDD_HV_A/B —

high current - 0.7V
Standard GPIO 5,6

IOH_50_SP 5.0V output high 2.5 — — mA DSE = 0, VOH >= —

current Standard VDD_HV_A/B - 0.7V
Plus GPIO and
RESET IO 5,6

IOH_50_M 5.0V output high 4.0 — — mA DSE = 0, VOH >= —

current for Medium VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_50_F 5.0V output high 6.0 — — mA DSE = 0, VOH >= —

current for Fast VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_50_SP 5.0V output high 5.0 — — mA DSE = 1, VOH >= —

current for Standard VDD_HV_A/B - 0.7V
Plus GPIO and
RESET IO 5,6

IOH_50_M 5.0V output high 8.0 — — mA DSE = 1, VOH >= —

current for Medium VDD_HV_A/B - 0.7V
GPIO 5,6

IOH_50_F 5.0V GPIO output 12.0 — — mA DSE = 1, VOH >= —

high current for Fast VDD_HV_A/B - 0.7V
GPIO 5,6

IOL_50_S 5.0V output 1.6 — — mA VOL <= 0.7V —

low current for
Standard GPIO 5,6

IOL_50_SP 5.0V output low 2.5 — — mA DSE =0, VOL <= 0.7V —
current for Standard
Plus GPIO and
RESET IO 5,6

IOL_50_M 5.0V output low 4.0 — — mA DSE =0, VOL <= 0.7V —
current for Medium
GPIO 5,6

Table continues on the next page...

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NXP Semiconductors
I/O parameters

Table 25. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

IOL_50_F 5.0V output low 6.0 — — mA DSE =0, VOL <= 0.7V —
current for Fast
GPIO 5,6

IOL_50_SP 5.0V output low 5.0 — — mA DSE =1, VOL <= 0.7V —
current for Standard
Plus GPIO and
RESET IO 5,6

IOL_50_M 5.0V output low 8.0 — — mA DSE =1, VOL <= 0.7V —
current for medium
GPIO 5,6

IOL_50_F 5.0V output low 12.0 — — mA DSE =1, VOL <= 0.7V —
current for Fast
GPIO 5,6

FMAX_50_S 5.0V maximum — — 10 MHz 3.6V - 5.5V CL (max) = —

frequency for 25pF
Standard GPIO 5,7

FMAX_50_SP 5.0V maximum — — 25 MHz 3.6V - 5.5V CL (max) = —

frequency for 25pF
Standard Plus
GPIO 5,7

FMAX_50_M 5.0V maximum — — 25 MHz 3.6V - 5.5V CL (max) = —

frequency for 25pF
Medium GPIO 5,7

FMAX_50_F 5.0V maximum — — 25 MHz 3.6V - 5.5V CL (max) = —

frequency for Fast 25pF
GPIO 5,7

IOHT Output high current — — 100 mA — —

total for all ports 8

1. Maximum length of RESET pulse will be filtered by an internal filter on this pin.
2. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.
3. A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage
flowing out the pin with the pin at ground.
4. Hysteresis spec does not apply to fast pad
5. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for
system level simulations, as discrete values for I/O transition times are not representative of the I/O pad behavior when
connected to an actual transmission line load.
6. I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating
Conditions of this document.
7. I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.
A lumped 8pF load is assumed in addition to a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/inch..
For best signal integrity, the series resistance in the transmission line should be matched closely to the selected output
resistance (ROUT_*) of the I/O pad.
8. To determine total switching current on any I/O supply, current values per output pin should not be incrementally summed.
I/O interfaces on the device are asynchronous to each other, so not all switching occurs at the same instant. Actual use
case must be considered.

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NXP Semiconductors
I/O parameters

MCUsee note 1 PCB External

device
5 in.
(4 layer FR4)
CPCB = ~3.3 pF/inch * 5 inch

RDSON
RPCB = RDSON

RDSON CL = 8 pF

Notes:
1. See IBIS models for further details.

Figure 34. Reference Load Diagram

7.3 5.0V (4.5V - 5.5V) GPIO Output AC Specification

Table 26. 5.0V (4.5V - 5.5V) GPIO Output AC Specification

Symbol Description Min Typ Max Unit Condition Spec

Number

TR_TF_50_S 5.0V Standard GPIO 5 — 21 ns CL (max) = 25pF —

rise/fall time 1,2,3

TR_TF_50_S 5.0V Standard GPIO 8.5 — 31 ns CL (max) = 50pF —

rise/fall time 1,2,3,4

TR_TF_50_SP 5.0V Standard 3 — 13.2 ns DSE=0 CL (max) = —

Plus GPIO rise/fall 25pF
time 1,2,3

TR_TF_50_SP 5.0V Standard 1 — 7.1 ns DSE=1 CL (max) = —

Plus GPIO rise/fall 25pF
time 1,2,3

TR_TF_50_SP 5.0V Standard 6.4 — 18.8 ns DSE=0 CL (max) = —

Plus GPIO rise/fall 50pF
time 1,2,3,4

TR_TF_50_SP 5.0V Standard 3.4 — 11 ns DSE=1 CL (max) —

Plus GPIO rise/fall =50pF
time 1,2,3,4

TR_TF_50_M 5.0V Medium GPIO 1.8 — 8.2 ns DSE=0, SRE=0 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_50_M 5.0V Medium GPIO 2.5 — 9.8 ns DSE=0, SRE=1 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_50_M 5.0V Medium GPIO 0.7 — 4.5 ns DSE=1, SRE=0 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_50_M 5.0V Medium GPIO 1.8 — 7.2 ns DSE=1, SRE=1 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_50_M 5.0V Medium GPIO 3.95 — 13.2 ns DSE=0, SRE=0 CL —

rise/fall time 1,2,3,4 (max) = 50pF

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NXP Semiconductors
I/O parameters

Table 26. 5.0V (4.5V - 5.5V) GPIO Output AC Specification (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

TR_TF_50_M 5.0V Medium GPIO 4.3 — 13.8 ns DSE=0, SRE=1 CL —

rise/fall time 1,2,3,4 (max) = 50pF

TR_TF_50_M 5.0V Medium GPIO 1.6 — 7.1 ns DSE=1, SRE=0 CL —

rise/fall time 1,2,3,4 (max) = 50pF

TR_TF_50_M 5.0V Medium GPIO 2.7 — 9.6 ns DSE=1, SRE=1 CL —

rise/fall time 1,2,3,4 (max) = 50pF

TR_TF_50_F 5.0V Fast GPIO rise/ 0.4 — 3.15 ns DSE=0, SRE=0 CL —

fall time 1,2,3 (max) = 25pF

TR_TF_50_F 5.0V Fast GPIO rise/ 1.5 — 6.7 ns DSE=0, SRE=1 CL —

fall time 1,2,3 (max) = 25pF

TR_TF_50_F 5.0V Fast GPIO rise/ 0.3 — 2.02 ns DSE=1, SRE=0 CL —

fall time 1,2,3 (max) = 25pF

TR_TF_50_F 5.0V Fast GPIO rise/ 0.9 — 4.85 ns DSE=1, SRE=1 CL —

fall time 1,2,3 (max) = 25pF

TR_TF_50_F 5.0V Fast GPIO rise/ 1.0 — 5.8 ns DSE=0, SRE=0 CL —

fall time 1,2,3,4 (max) = 50pF

TR_TF_50_F 5.0V Fast GPIO rise/ 1.9 — 8.5 ns DSE=0, SRE=1 CL —

fall time 1,2,3,4 (max) = 50pF

TR_TF_50_F 5.0V Fast GPIO rise/ 0.9 — 3.0 ns DSE=1, SRE=0 CL —

fall time 1,2,3,4 (max) = 50pF

TR_TF_50_F 5.0V Fast GPIO rise/ 1.3 — 6.1 ns DSE=1, SRE=1 CL —

fall time 1,2,3,4 (max) = 50pF

1. I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.
A lumped 8pF load (typical) is assumed at the end of a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/
inch. For best signal integrity, the series resistance in the transmission line should be matched closely to the selected
output resistance (ROUT_*) of the I/O pad.
2. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for
system level simulations, as discrete values for I/O transition times are not representative of the I/O pad behavior when
connected to an actual transmission line load.
3. GPIO rise/fall time specifications are derived from simulation model for the defined operating points (between 20% and
80% of VDD_HV_A/B level). Actual application rise/fall time should be extracted from IBIS model simulations with the
microcontroller models and application PCB.
4. Output timing valid for maximum external load C L = 50pF (includes PCB trace, package trace, and external device input
load).

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NXP Semiconductors
I/O parameters

MCUsee note 1 PCB External

device
5 in.
(4 layer FR4)
CPCB = ~1.5 pF/inch * 5 inch = ~7.5 pF

RDSON
RPCB = RDSON

RDSON CL = 8 pF

Notes:
1. See IBIS models for further details.

Figure 35. Reference Load Diagram

7.4 3.3V (2.97V - 3.63V) GPIO Output AC Specification

Table 27. 3.3V (2.97V - 3.63V) GPIO Output AC Specification

Symbol Description Min Typ Max Unit Condition Spec

Number

TR_TF_33_S 3.3V Standard GPIO 5 — 28 ns CL (max) = 25pF —

rise/fall time 1,2,3

TR_TF_33_S 3.3V Standard GPIO 9.5 — 43 ns CL (max) = 50pF —

rise/fall time 1,2,3

TR_TF_33_SP 3.3V Standard 4 — 17.5 ns DSE=0 CL (max) = —

Plus GPIO rise/fall 25pF
time 1,2,3

TR_TF_33_SP 3.3V Standard 1.9 — 10 ns DSE=1 CL (max) = —

Plus GPIO rise/fall 25pF
time 1,2,3

TR_TF_33_SP 3.3V Standard 7.5 — 27 ns DSE=0 CL (max) = —

Plus GPIO rise/fall 50pF
time 1,2,3,4

TR_TF_33_SP 3.3V Standard 3.5 — 15 ns DSE=1 CL (max) = —

Plus GPIO rise/fall 50pF
time 1,2,3,4

TR_TF_33_M 3.3V Medium GPIO 2.2 — 12.3 ns DSE=0, SRE=0 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_33_M 3.3V Medium GPIO 3.0 — 14 ns DSE=0, SRE=1 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_33_M 3.3V Medium 0.8 — 6.6 ns DSE=1, SRE=0 CL —

GPIO rise/fall (max) = 25pF
time 1,2,3

TR_TF_33_M 3.3V Medium GPIO 2.4 — 10.5 ns DSE=1, SRE=1 CL —

rise/fall time 1,2,3 (max) = 25pF

TR_TF_33_M 3.3V Medium GPIO 4.5 — 17.3 ns DSE=0, SRE=0 CL —

rise/fall time 1,2,3,4 (max) = 50pF

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NXP Semiconductors
I/O parameters

Table 27. 3.3V (2.97V - 3.63V) GPIO Output AC Specification (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

TR_TF_33_M 3.3V Medium GPIO 5 — 19.8 ns DSE=0, SRE=1 CL —

rise/fall time 1,2,3,4 (max) = 50pF

TR_TF_33_M 3.3V Medium GPIO 2.2 — 10 ns DSE=1, SRE=0 CL —

rise/fall time 1,2,3,4 (max) = 50pF

TR_TF_33_M 3.3V Medium GPIO 3.6 — 13.9 ns DSE=1, SRE=1 CL —

rise/fall time 1,2,3,4 (max) = 50pF

TR_TF_33_F 3.3V Fast GPIO rise/ 0.5 — 4.9 ns DSE=0, SRE=0 CL —

fall time 1,2,3 (max) = 25pF

TR_TF_33_F 3.3V Fast GPIO rise/ 2.1 — 10 ns DSE=0, SRE=1 CL —

fall time 1,2,3 (max) = 25pF

TR_TF_33_F 3.3V Fast GPIO rise/ 0.4 — 2.2 ns DSE=1, SRE=0 CL —

fall time 1,2,3 (max) = 25pF

TR_TF_33_F 3.3V Fast GPIO rise/ 1.2 — 7.1 ns DSE=1, SRE=1 CL —

fall time 1,2,3 (max) = 25pF

TR_TF_33_F 3.3V Fast GPIO rise/ 1.1 — 8 ns DSE=0, SRE=0 CL —

fall time 1,2,3,4 (max) = 50pF

TR_TF_33_F 3.3V Fast GPIO rise/ 2.6 — 12.1 ns DSE=0, SRE=1 CL —

fall time 1,2,3,4 (max) = 50pF

TR_TF_33_F 3.3V Fast GPIO rise/ 0.8 — 4.2 ns DSE=1, SRE=0 CL —

fall time 1,2,3,4 (max) = 50pF

TR_TF_33_F 3.3V Fast GPIO rise/ 1.5 — 8.6 ns DSE=1, SRE=1 CL —

fall time 1,2,3,4 (max) = 50pF

1. I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.
A lumped 8pF load (typical) is assumed at the end of a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/
inch. For signals with frequency greater than 63MHz, a maximum 2 inch PCB trace is assumed. For best signal integrity,
the series resistance in the transmission line should be matched closely to the selected output resistance (ROUT_*) of the
I/O pad.
2. GPIO rise/fall time specifications are derived from simulation model for the defined operating points (between 20% and
80% of VDD_HV_A/B level). Actual application rise/fall time should be extracted from IBIS model simulations with the
microcontroller models and application PCB.
3. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for
system level simulations, as discrete values for I/O transition times are not representative of the I/O pad behavior when
connected to an actual transmission line load.
4. Output timing valid for maximum external load C L = 50pF (includes PCB trace, package trace, and external device input
load).

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NXP Semiconductors
Glitch Filter

MCUsee note 1 PCB External

device
5 in.
(4 layer FR4)
CPCB = ~3.3 pF/inch * 5 inch

RDSON
RPCB = RDSON

RDSON CL = 8 pF

Notes:
1. See IBIS models for further details.

Figure 36. Reference Load Diagram

8 Glitch Filter
The glitch filter parameters in the following table apply to the filters of WKPU pins and TRGMUX inputs 60-63.

Table 28. Glitch Filter

Symbol Description Min Typ Max Unit Condition Spec

Number

TFILT Glitch filter max — — 20 ns — —

filtered pulse
width 1,2,3

TUNFILT Glitch filter min 400 — — ns — —

unfiltered pulse
width 2,3,4

1. Pulses shorter than defined by the maximum value are guaranteed to be filtered (not passed).
2. An input signal pulse is defined by the duration between the input signal's crossing of a Vil/Vih threshold voltage level, and
the next crossing of the opposite level.
3. Pulses in between the max filtered and min unfiltered may or may not be passed through.
4. Pulses larger than defined by the minimum value are guaranteed to not be filtered (passed).

9 Flash memory specification

9.1 Flash memory program and erase specifications

Table 29. Flash memory program and erase specifications

Symbol Characteristic1 Typ2 Factory Field Update Unit

Programming3,4

Initial Max Initial Max, Typical Lifetime Max6

Full Temp End of
Life5

20°C ≤TA -40°C ≤TJ -40°C ≤TJ ≤ 1,000 ≤ 100,000

≤30°C ≤150°C ≤150°C cycles cycles

tdwpgm Doubleword (64 bits) program time 102 122 129 111 150 µs

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NXP Semiconductors
Flash memory specification

Table 29. Flash memory program and erase specifications (continued)

Symbol Characteristic1 Typ2 Factory Field Update Unit

Programming3,4

Initial Max Initial Max, Typical Lifetime Max6

Full Temp End of
Life5

20°C ≤TA -40°C ≤TJ -40°C ≤TJ ≤ 1,000 ≤ 100,000

≤30°C ≤150°C ≤150°C cycles cycles

tppgm Page (256 bits) program time 142 171 180 157 200 µs

tqppgm Quad-page (1024 bits) 314 377 396 341 450 µs

program time

t8kpgm 8 KB Sector program time 20 24 26 22 30 ms

t8kers 8 KB Sector erase time 4.8 8.5 10.6 6.5 30 ms

t256kbers 256KB Block erase time 22.8 27.4 28.8 24.4 40 — ms

t512kbers 512KB Block erase time 25.4 30.5 32.1 27.9 45 — ms

t1mbers 1MB Block erase time 30.6 36.8 38.7 33.6 50 — ms

t2mbers 2MB Block erase time 41.1 49.3 51.8 45.2 60 — ms

1. Program times are actual hardware programming times and do not include software overhead. Sector program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 25 cycles, nominal voltage.
4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: -40°C ≤TJ ≤150°C, full spec voltage.

9.2 Flash memory Array Integrity and Margin Read specifications

Table 30. Flash memory Array Integrity and Margin Read specifications

Symbol Characteristic Min Typical Max1 2 Units3

tai256kseq Array Integrity time and Margin — — 8192 x Tperiod x Nread —

Read time for sequential sequence
(plus 40uS adder required if User
on 256KB block.
Margin Read)

tai512kseq Array Integrity time and Margin — — 16384 x Tperiod x Nread —

Read time for sequential sequence
(plus 40uS adder required if User
on 512KB block.
Margin Read)

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NXP Semiconductors
Flash memory specification

Table 30. Flash memory Array Integrity and Margin Read specifications (continued)

Symbol Characteristic Min Typical Max1 2 Units3

tai1mseq Array Integrity time and Margin — — 32768 x Tperiod x Nread —

Read time for sequential sequence
(plus 40uS adder required if User
on 1MB block.
Margin Read)

tai2mseq Array Integrity time and Margin — — 65536 x Tperiod x Nread —

Read time for sequential sequence
(plus 40uS adder required if User
on 2MB block.
Margin Read)

tai256kprop Array Integrity time for proprietary — — 106496 —

sequence on 256KB block. x Tperiod x Nread

tai512kprop Array Integrity time for proprietary — — 229376 —

sequence on 512KB block.
x Tperiod x Nread

tai1mprop Array Integrity time for proprietary — — 491520 —

sequence on 1MB block. x Tperiod x Nread

tai2mprop Array Integrity time for proprietary — — 1048576 —

sequence on 2MB block. x Tperiod x Nread

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including single read, dual read, quad read contribution. Thus for a
read setup that requires 6 clocks to read Nread would equal 6.
2. Array Integrity times are actual hardware execution times and do not include software overhead or system code execution
overhead.
3. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.

9.3 Flash memory module life specifications

Table 31. Flash memory module life specifications

Symbol Characteristic Conditions Min Typical Units

Array P/E Number of program/erase cycles per block — 100,000 — P/E

cycles for 256 KB and 512 KB blocks using cycles
Sector Erase.

Number of program/erase cycles per block for — 1,000 — P/E

1 MB and 2 MB blocks using Sector Erase. cycles

Number of program/erase cycles per block — 25 — P/E

using Block Erase1 cycles

Data Minimum data retention. Blocks with 0 - 1,000 20 — Years

retention P/E cycles.

Blocks with 100,000 10 — Years

P/E cycles.

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NXP Semiconductors
Flash memory specification

1. Program and erase supported for factory conditions. Nominal supply values and operation at 25°C.

9.3.1 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure.
The spec window represents qualified limits.

Minimum Data Retention Life (Years) 25

20

15

10

0
1 10 100 1000 10000 100000 1000000
P/E Cycles (Sector Erases)

Figure 37. Data retention vs program/erase cycles

9.4 Flash memory AC timing specifications

Table 32. Flash memory AC timing specifications

Symbol Characteristic Min Typical Max Units

tdone Time from 0 to 1 transition on the MCR[EHV] bit — — 5 ns

initiating a program/erase until the MCR[DONE]
bit is cleared.

tdones Time from 1 to 0 transition on the MCR[EHV] bit 5 plus four — 22 plus four µs
aborting a program/erase until the MCR[DONE] system clock system clock
bit is set to a 1. periods periods1

tdrcv Time to recover once exiting low power mode. 14 plus seven 17.5 plus 21 plus seven µs
system clock seven system system clock
periods2 clock periods periods

taistart Time from 0 to 1 transition of UT0[AIE] initiating a — — 5 ns

Margin Read or Array Integrity until the UT0[AID]
bit is cleared. This time also applies to the
resuming from a suspend or breakpoint by
clearing UT0[AISUS] or clearing UT0[NAIBP]

taistop Time from 1 to 0 transition of UT0[AIE] initiating — — 50 ns

an Array Integrity abort until the UT0[AID] bit is system clock
set. This time also applies to the UT0[AISUS] to periods

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NXP Semiconductors
Flash memory specification

Table 32. Flash memory AC timing specifications (continued)

Symbol Characteristic Min Typical Max Units

UT0[AID] setting in the event of a Array Integrity

suspend request.

tmrstop Time from 1 to 0 transition of UT0[AIE] initiating — — 26 µs

a Margin Read abort until the UT0[AID] bit is
plus fifteen
set. This time also applies to the UT0[AISUS] to
system clock
UT0[AID] setting in the event of a Margin Read
periods
suspend request.

1. For Block Erase, Tdones times may be 3x max spec.

2. In extreme cases (1 block configurations) Tdrcv min may be faster (12uS plus seven system clocks)

9.5 Flash memory read timing parameters

Table 33. Flash Read Wait State Settings (S32K344, S32K324, S32K314, S32K342, S32K322, S32K341, S32K312,
S32K311, S2K310 and S32K389(PFC1))

Flash Frequency RWSC setting

250 KHz < Freq ≤ 66 MHz 1

66 MHz < Freq ≤ 100 MHz 2

100 MHz < Freq ≤ 133 MHz 3

133 MHz < Freq ≤ 167 MHz 4

167 MHz < Freq ≤ 200 MHz 5

200 MHz < Freq ≤ 233 MHz 6

233 MHz < Freq ≤ 250 MHz 7

Table 34. Flash Read Wait State Settings (S32K358, S32K348, S32K338, S32K328, S32K388 and S32K389(PFC0))

Flash Frequency RWSC setting

250 KHz < Freq ≤ 60 MHz 1

60 MHz < Freq ≤ 90 MHz 2

90 MHz < Freq ≤ 120 MHz 3

120 MHz < Freq ≤ 150 MHz 4

150 MHz < Freq ≤ 180 MHz 5

180 MHz < Freq ≤ 210 MHz 6

210 MHz < Freq ≤ 240 MHz 7

240 MHz < Freq ≤ 250 MHz 8

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10 Analog modules

10.1 SAR_ADC
All below specs are applicable only when one ADC instance is in operation and averaging is used or multiple ADC instances are
operational at the same time but sampling different channels. Best performance can be achieved if only one ADC is operational
at a time sampling one channel

Table 35. SAR_ADC

Symbol Description Min Typ Max Unit Condition Spec

Number

VDD_HV_A ADC Supply 2.97 — 5.5 V — —

Voltage 1

DVREFL VSS / VREFL -100 — 100 mV — —

Voltage Difference 2

VAD_INPUT ADC Input Voltage 3 VREFL — VREFH V — —

fAD_CK ADC Clock 10 — 80 MHz — —

Frequency
(S32K344,
S32K324, S32K314,
S32K342, S32K341,
S32K322)

fAD_CK ADC Clock 10 — 120 MHz — —

Frequency
(S32K312,
S32K311, S32K310,
S32K358, S32K348,
S32K338, S32K328,
S32K388, S32K389)

tSAMPLE ADC Input Sampling 275 — — ns — —

Time

tCONV ADC Total 1 — — us 12-bit result —

Conversion Time

tCONV ADC Total 0.9 — — us 10-bit result —

Conversion Time

CAD_INPUT ADC Input — — 13.8 pF ADC component —

Capacitance plus pad capacitance
(~2pF)

RAD_INPUT ADC Input — — 4.6 KΩ ADC + mux+SOC —

Resistance routing

RS Source Impedance, — 20 — Ω — —
precision channels

RS Source Impedance, — 20 — Ω — —
standard channels

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Table 35. SAR_ADC (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

TUE ADC Total — +/-4 +/-6 LSB without adjacent pin —

Unadjusted Error 4,5 current injection

TUE ADC Total — +/-4 +/-8 LSB with up to +/-3mA —

Unadjusted Error 5 of current injection on
adjacent pins

IAD_REF Current — — 200 uA Per ADC for dedicated —

Consumption on or shared reference
ADC Reference pin, pins
VREFH.

IDDA Current — 2.1 — mA Current consumption —

Consumption on per ADC module, ADC
ADC Supply, enabled and converting
VDD_HV_A

CS Sampling 6.4 7.36 8.32 pF all channels —

Capacitance (gain=0) (gain=0) (gain=0)
9.72 11.12 12.52
pF(gain= pF(gain= (gain=ma
max) max) x)

RAD Sampling Switch 80 170 520 Ohm all channels —

Impedance

CP1 Pin capacitance 1.42 — 5.30 pF all channels —

CP1 Pin capacitance 1.42 — 4.38 pF Precision channels —

CP1 Pin capacitance 1.61 — 5.30 pF Standard channels —

CP2 Analog Bus 0.32 — 4.18 pF all channels —

Capacitance

CP2 Analog Bus 0.32 — 1.42 pF Precision channels —

Capacitance

CP2 Analog Bus 0.497 — 4.18 pF Standard channels —

Capacitance

RSW1 Channel selection 65.9 — 1410 Ohm all channels —

Switch impedance

RSW1 Channel selection 65.9 — 712 Ohm Precision channels —

Switch impedance

RSW1 Channel selection 65.9 — 1410 Ohm Standard channels —

Switch impedance

1. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference supply design for
SAR_ADC.
2. VSS and VREFL should be shorted on PCB. 100mV difference between VSS and VREFL is for transient only (not for DC).
3. This is ADC Input range for ADC accuracy guaranteed in this input range only. For SoC Pin capability, see Operation Condition Section.
4. Spec valid if potential difference between VDD_HV_A and VREFH should follow VDD_HV_A +0.1V >=VREFH >= VDD_HV_A -1.5V
5. TUE spec for precision and standard channels is based on 12-bit level resolution.

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EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

VDD_HV_A
Channel
Selection Sampling
Source Filter Current Limiter

RS RF RL RSW1 RAD

VA CF CP1 CP2 CS

RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions: CP1, CP2)
CS Sampling Capacitance

Figure 38. SAR_ADC Input Circuit

10.2 Supply Diagnosis

The table below gives the specification for the on die supply diagnosis.

Table 36. Supply Diagnosis

Symbol Description Min Typ Max Unit Condition Spec

Number

AN_ACC Offset to internally -5 0 5 % — —

monitored supply at
ADC input 1,2,3

AN_T_on Switching time from — 2.5 12 ns — —

closed (OFF) to
conducting (ON) 1

AN_TADCSA Required ADC 1.2 — — µs — —

sampling time 2

1. These specs will have degraded performance when used in extended supply voltage operation range, i.e. normal supply
voltage range specification is exceeded.
2. Required ADC sampling time specified by parameter AN_TADCSA needs to be used at the ADC conversion to guarantee
the specified accuracy. A smaller sampling time leads to a less accurate result.
3. If V15 > VDD_HV_A +100mV then the V15 measurement via anamux may be imprecise.

10.3 Low Power Comparator (LPCMP)

Table 37. Low Power Comparator (LPCMP)

Symbol Description Min Typ Max Unit Condition Spec

Number

idda(IDHSS) vdda Supply — 240 — uA — —

Current, High Speed
Mode 1,2

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Table 37. Low Power Comparator (LPCMP) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

idda(IDLSS) vdda Supply — 17 — uA — —

Current, Low Speed
Mode 1,2

idda(IDHSS) vdda Supply — 10 — uA — —

Current, high speed
mode, DAC only 2

idda_lkg vdda Supply — 2 — nA vdda=5.5V, T=25C —

Current, module
disabled 2

TDHSB Propagation Delay, — — 200 ns — —

High Speed Mode 3

TDLSB Propagation Delay, — — 2 us — —

Low Speed mode 3

TDHSS Propagation Delay, — — 400 ns — —

High Speed Mode 4

TDLSS Propagation Delay, — — 5 us — —

Low Speed mode 4

TIDHS Initialization Delay, — — 3 us — —

High Speed Mode 5

TIDLS Initialization Delay, — — 30 us — —

Low Speed mode 5

VAIO Analog Input Offset -25 +/-1 25 mV — —

Voltage, High Speed
Mode

VAIO Analog Input Offset -40 + /- 5 40 mV — —

Voltage, Low Speed
mode

VAHYST0 Analog Comparator — 0 — mV HYSTCTR[1:0]= 2'b00 —

Hysteresis, High
Speed Mode

VAHYST1 Analog Comparator — 14 41 mV HYSTCTR[1:0]= 2'b01 —

Hysteresis, High
Speed Mode

VAHYST2 Analog Comparator — 27 76 mV HYSTCTR[1:0]= 2'b10 —

Hysteresis, High
Speed Mode

VAHYST3 Analog Comparator — 40 111 mV HYSTCTR[1:0]= 2'b11 —

Hysteresis, High
Speed Mode

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Table 37. Low Power Comparator (LPCMP) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

VAHYST0 Analog Comparator — 0 — mV HYSTCTR[1:0]= 2'b00 —

Hysteresis, Low
Speed mode

VAHYST1 Analog Comparator — 8 60 mV HYSTCTR[1:0]= 2'b01 —

Hysteresis, Low
Speed mode

VAHYST2 Analog Comparator — 15 113 mV HYSTCTR[1:0]= 2'b10 —

Hysteresis, Low
Speed mode

VAHYST3 Analog Comparator — 23 165 mV HYSTCTR[1:0]= 2'b11 —

Hysteresis, Low
Speed mode

INL DAC integral -1 — 1 LSB vrefh_cmp = vdda, —

linearity 2,6,7 vrefl_cmp = vss

INL DAC integral -1.5 — 1.5 LSB vrefh_cmp < vdda —

linearity 2,6,7

DNL DAC differential -1 — 1 LSB vrefh_cmp = vdda, —

linearity 2,6 vrefl_cmp = vss

DNL DAC differential -1.5 — 1.5 LSB vrefh_cmp < vdda —

linearity 2,6

tDDAC DAC — — 30 us — —
Initialization time

VAIN Analog input voltage 0 — VDDA V — —

1. Difference at input > 200mV

2. vdda is comparator HV supply and internally shorted to VDD_HV_A pin. vss is comparator ground
3. Applied +/- (100 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point
4. Applied +/- (30 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point
5. Applied ± (100 mV + VAHYST0/1/2/3 ).
6. 1 LSB = (vrefh_cmp - vrefl_cmp) /256. vrefh_cmp and vrefl_cmp are comparator reference high and low
7. Calculation method used: Linear Regression Least Square Method

For Comparator IN signals adjacent to VDD_HV_A/VDD_HV_B/VSS or XTAL/EXTAL or switching pins cross coupling may
happen and hence hysteresis settings can be used to obtain the desired Comparator performance. Additionally an external
capacitor to ground (1nF) should be used to filter noise on input signal. Also source drive should not be weak (Signal with <50K
pull up/down is recommended).
For devices where the VDD_HV_B domain is present, LPCMP0 channels must only be selected/enabled when VDD_HV_A >=
VDD_HV_B. These channels must be disabled when VDD_HV_A goes below VDD_HV_B.

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90

Hysteresis
(mV)
60

30

0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VAIN (V)
25 Junction Temp (°C)
3.3 VDD_HV_A (V)
HYSTCTR setting
00 01 10 11

Figure 39. Typical Hysteresis vs VAIN (VDD_HV_A = 3.3 V, High Speed Mode)

60

Hysteresis
(mV)

40

20

0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VAIN (V)
25 Junction Temp (°C)
3.3 VDD_HV_A (V)
HYSTCTR setting
00 01 10 11

Figure 40. Typical Hysteresis vs VAIN (VDD_HV_A = 3.3 V, Low Speed Mode)

90

Hysteresis
(mV)
60

30

0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VAIN (V)
25 Junction Temp (°C)
5 VDD_HV_A (V)
HYSTCTR setting
00 01 10 11

Figure 41. Typical Hysteresis vs VAIN (VDD_HV_A = 5 V, High Speed Mode).png

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60

Hysteresis
(mV)

40

20

0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VAIN (V)
25 Junction Temp (°C)
5 VDD_HV_A (V)
HYSTCTR setting
00 01 10 11

Figure 42. Typical Hysteresis vs VAIN (VDD_HV_A = 5 V, Low Speed Mode).png

10.4 Temperature Sensor

The table below gives the specification for the MCU on-die temperature sensor.

Table 38. Temperature Sensor

Symbol Description Min Typ Max Unit Condition Spec

Number

TS_TJ Junction -40 — 150 °C — —

temperature
monitoring range

TS_IV25 ON state current — 400 — µA ETS_EN=1 —

consumption on V25

TS_ACC1 Temperature output -5 0 +5 °C 100 °C < Tj <= 150 °C —

error at circuit output
(Voltage) 1,2,3

TS_ACC2 Temperature output -10 0 +10 °C -40 °C <= Tj <=100 °C —

error at circuit output
(Voltage) 1,2,3

TS_TSTART Circuit start up time — 4 30 µs — —

TS_TADCSA Required ADC 1.2 — — µs — —

sampling time 1

1. Required ADC sampling time specified by parameter TS_TADCSA needs to be used at the ADC conversion to guarantee
the specified accuracy. A smaller sampling time leads to a less accurate result.
2. Note: The temperature sensor measures the junction temperature Tj at the location where it is placed on die. The local Tj
is modulated by current and previous active state of the circuit elements on die.
3. The error caused by ADC conversion and provided temperature calculation formula is not included.

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Clocking modules

11 Clocking modules

11.1 FIRC
Table 39. FIRC

Symbol Description Min Typ Max Unit Condition Spec

Number

fFIRC FIRC nominal — 48 — MHz — —

Frequency

FACC FIRC Frequency -5 — 5 % — —

deviation across
process, voltage,
and temperature
after trimming

TSTART Startup Time 1 — 10 25 us — —

1. Startup time is for reference only.

11.2 SIRC
Table 40. SIRC

Symbol Description Min Typ Max Unit Condition Spec

Number

fSIRC SIRC nominal — 32 — KHz — —

Frequency

fSIRC_ACC SIRC Frequency -10 — 10 % — —

deviation across
process, voltage,
and temperature
after trimming

TSIRC_start SIRC Startup Time 1 — — 3 ms — —

TSIRC_DC SIRC duty cycle 30 — 70 % — —

1. Startup time is for information only.

11.3 PLL
FPLL_DS, FPLL_FM and all fractional mode jitter specifications are not applicable to Auxiliary PLL on S32K328, S32K338,
S32K348, S32K358, S32K388 and S32K389 devices.
Jitter values specified in this table are applicable for FXOSC reference clock input only.

Table 41. PLL

Symbol Description Min Typ Max Unit Condition Spec

Number

FPLL_in PLL input frequency 8 — 40 MHz This is the frequency —

after the Reference
Divider within the PLL

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Table 41. PLL (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

FPLL_out PLL output 25 — 480 MHz — —

frequency
(PLL_PHIn_CLK)

FPLL_vcoRange VCO Frequency 640 — 1280 MHz — —

range

FPLL_DS Modulation Depth -0.5 — -3 % — —

(down spread)

FPLL_FM Modulation — — 32 KHz — —

frequency

TPLL_start PLL lock time — — 1 ms — —

JPLL_cyc PLL period jitter (pk- — — 237 ps FPLL_out = 240MHz, —

pk) 1,2,3 Integer Mode

JPLL_cyc PLL period jitter (pk- — — 487 ps FPLL_out = 240MHz, —

pk) 1,2,3 Fractional Mode

JPLL_acc PLL accumulated — — 840 ps FPLL_out = 240MHz, —

jitter (pk-pk) 1,2,3 Integer Mode

JPLL_acc PLL accumulated — — 1680 ps FPLL_out = 240MHz, —

jitter (pk-pk) 1,2,3 Fractional Mode

JPLL_cyc PLL period jitter (pk- — — 295 ps FPLL_out = 160MHz, —

pk) 1,2,3 Integer Mode

JPLL_cyc PLL period jitter (pk- — — 670 ps FPLL_out = 160MHz, —

pk) 1,2,3 Fractional Mode

JPLL_acc PLL accumulated — — 840 ps FPLL_out = 160MHz, —

jitter (pk-pk) 1,2,3 Integer Mode

JPLL_acc PLL accumulated — — 1680 ps FPLL_out = 160MHz, —

jitter (pk-pk) 1,2,3 Fractional Mode

JPLL_cyc PLL period jitter (pk- — — 353 ps FPLL_out = 120MHz, —

pk) 1,2,3 Integer Mode

JPLL_cyc PLL period jitter (pk- — — 853 ps FPLL_out = 120MHz, —

pk) 1,2,3 Fractional Mode

JPLL_acc PLL accumulated — — 840 ps FPLL_out = 120MHz, —

jitter (pk-pk) 1,2,3 Integer Mode

JPLL_acc PLL accumulated — — 1680 ps FPLL_out = 120MHz, —

jitter (pk-pk) 1,2,3 Fractional Mode

1. For SSCG, jitter due to systematic modulation needs to be added as per applied modulation. Accumulated jitter
specification is not valid with SSCG
2. Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma .
3. Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement.

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11.4 FXOSC
Table 42. FXOSC

Symbol Description Min Typ Max Unit Condition Spec

Number

FREQ_BYPASS Input clock — — 50 MHz — —

frequency in bypass
mode 1

TRF_BYPASS Input clock rise/fall — — 5 ns — —

time in bypass
mode 1

CLKIN_DUTY_ Input clock duty 47.5 — 52.5 % — —

BYPASS cycle in bypass
mode 1

FXOSC_CLK output clock 8 — 40 MHz — —

frequency in crystal
mode

TFXOSC Fxosc start up — — 2 ms — —

time (ALC enabled) 2

IFXOSC Oscillator Analog — — 1 mA using 8, 16 or 40 MHz —

circuit supply crystal
current, V25 supply
(ALC enable)

IFXOSC Oscillator Analog — — 2.7 mA using 8, 16 or 40 MHz —

circuit supply crystal
current, V25 supply
(ALC disabled)

EXTAL_SWING_ Peak-to-peak 0.3 — 1.4 V — —

PP voltage swing on
EXTAL pin in crystal
oscillator mode (ALC
enabled)

EXTAL_SWING_ Peak-to-peak 1.2 — 2.75 V — —

PP voltage swing on
EXTAL pin in crystal
oscillator mode (ALC
disabled) 3

CLKIN_VIL_ Input clock low level 0 — vref-1 V vref=0.5*VDD_HV_A —

EXTAL_BYPASS in bypass mode 4

CLKIN_VIH_ Input clock high level vref+1 — VDD_HV V vref=0.5*VDD_HV_A —

EXTAL_BYPASS in bypass mode 4 _A

VSB Self Bias Voltage 350 — 850 mV — —

GM Amplifier 9.7 — 18.5 mA/V GM_SEL[3:0] = —

Transconductance 4`b1111

1. For bypass mode applications, the EXTAL pin should be driven low when FXOSC is in off/disabled state.
2. The startup time specification is valid only when the recommended crystal and load capacitors are used. For higher load
capacitances, the actual startup time might be higher.

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3. The recommended gm setting to ensure extal swing < 2.75V at 8MHz in ALC-disabled mode is gm=4'b0010.
Recommended gm settings in ALC-disabled mode for all other supported frequencies and crystals remain the same.
4. For bypass mode applications, the EXTAL pin should be driven symmetrical around Vref =0.5* VDD_HV_A

To ensure stable oscillations, FXOSC incorporates the feedback resistance internally.

In single ended bypass mode, the XTAL pin can be left unconnected.
Drive level is a crystal specification and if crystal load capacitance is increased beyond the recommended value, it may violate
the crystal drive level rating. In such cases, contact NXP sales representative for selecting the correct crystal.

Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:
gm_crit = 4 * (ESR + RS) * (2πF)2 * (C0 + CL)2

where:
• gmXOSC is the transconductance of the internal oscillator circuit
• ESR is the equivalent series resistance of the external crystal
• RS is the series resistance connected between XTAL pin and external crystal for current limitation
• F is the external crystal oscillation frequency
• C0 is the shunt capacitance of the external crystal
• CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
• Cs is stray or parasitic capacitance on the pin due to any PCB traces
• C1, C2 external load capacitances on EXTAL and XTAL pins
See manufacture datasheet for external crystal component values

Figure 43. Oscillation build-up equation

NOTE
To improve the FXOSC & PLL jitter performance in S32K328, S32K338, S32K348, S32K358 the functionality of
the pins (namely - PTG0,PTG3,PTF11,PTF19,PTF30, PMOS_CTRL in BGA289 package) cannot be
toggling edge aligned.

NOTE
To improve the FXOSC jitter & duty cycle performance in S32K310, S32K311, S32K312, S32K322, S32K341
S32K342, S32K314,S32K324 and S32K344, the functionality of the pin next to the Oscillator (namely, PTE14 in
172-HDQFP and PTE3 in 100-HDQFP package) must be limited to static GPIO operation.

NOTE
To improve the FXOSC & PLL jitter performance in S32K388, the functionality of the pins (namely - PTG0, PTG2,
PTG3, PTF30, PTE12, PTA29, PMOS_CTRL in BGA289 package) cannot be toggling edge-aligned.

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Figure 44. Block diagram

11.5 SXOSC
Table 43. SXOSC

Symbol Description Min Typ Max Unit Condition Spec

Number

Fsxosc Oscillator Crystal — 32.768 — KHz IP in crystal mode —

Frequency 1

Tstart SXOSC startup time — — 2 s start up time is —

dependent upon board
and crystal model.

ISXOSC Oscillator Analog — 2.1 10 uA — —

circuit supply current

gm_sxocs NMOS Amplifier 3 — 40 u A/V — —

Transconductance

1. Supports single frequency

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Communication interfaces

12 Communication interfaces

12.1 LPSPI
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many
of the transfer attributes are programmable. The following table provides timing characteristics for classic LPSPI timing modes.
1. All timing is shown with respect to 50% VDD_HV_A/B thresholds.
2. All measurements are with maximum output load of 30pF (except 50pF support on K3x8 and S32K389 with Fast/Medium/
Standard-Plus IOs), input transition of 1 ns and pad configured DSE = 1, SRC = 0.
See I/O parameters for GPIO electrical specifications.

Table 44. LPSPI

Symbol Description Min Typ Max Unit Condition Spec

Number

fperiph Peripheral Frequenc — — 40 MHz Master —

y 1,2,3

fperiph Peripheral Frequenc — — 40 MHz Slave —

y 1,2,3

fperiph Peripheral Frequenc — — 80 MHz Master Loopback —

y 2,3,4

fop Operating frequency — — 15 MHz Slave 1

fop Operating frequency — — 15 MHz Master 1

fop Operating — — 10 MHz Slave_10Mbps 1

frequency 5

fop Operating — — 10 MHz Master_10Mbps 1

frequency 5

fop Operating — — 20 MHz Master Loopback 1

frequency 4,6

tSPSCK SPSCK period 66 — — ns Slave 2

tSPSCK SPSCK period 66 — — ns Master 2

tSPSCK SPSCK period 4 50 — — ns Master Loopback 2

tSPSCK SPSCK period 100 — — ns Master_10Mbps 2

tSPSCK SPSCK period 100 — — ns Slave_10Mbps 2

tLEAD Enable lead time tSPCK/2 — — ns Slave 3

(PCS to SPSCK
delay) 7

tLEAD Enable lead time 30 — — ns Master 3

(PCS to SPSCK
delay) 7

tLEAD Enable lead time 30 — — ns Master Loopback 3

(PCS to SPSCK
delay) 4,7

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Table 44. LPSPI (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tLAG Enable lag time tSPCK/2 — — ns Slave 4

(After SPSCK
delay) 8

tLAG Enable lag time 30 — — ns Master 4

(After SPSCK
delay) 8

tLAG Enable lag time 30 — — ns Master Loopback 4

(After SPSCK
delay) 4,8

tWSPCK Clock (SPSCK) time tSPSCK/ — tSPSCK/ ns Slave 5

(SPSCK duty 2-3 2+3
cycle) 9

tWSPCK Clock (SPSCK) time tSPSCK/ — tSPSCK/ ns Master 5

(SPSCK duty 2-3 2+3
cycle) 9

tWSPCK Clock (SPSCK) time tSPSCK/ — tSPSCK/ ns Master Loopback 5

(SPSCK duty 2-3 2+3
cycle) 4,9

tSU Data setup 6 — — ns Slave 6

time(inputs)

tSU Data setup 25 — — ns Master 6

time(inputs)

tSU Data setup 5 — — ns Slave_10Mbps 6

time(inputs)

tSU Data setup 36 — — ns Master_10Mbps 6

time(inputs)

tSU Data setup 6 — — ns Master_Loopback 6

time(inputs) 4

tHI Data hold 3 — — ns Slave 7

time(inputs)

tHI Data hold 0 — — ns Master 7

time(inputs)

tHI Data hold 4 — — ns Slave_10Mbps 7

time(inputs)

tHI Data hold 0 — — ns Master_10Mbps 7

time(inputs)

tHI Data hold 3 — — ns Master Loopback 7

time(inputs) 4

tA MISO valid time after — — 50 ns Slave 8

SS assertion

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Table 44. LPSPI (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tDIS Slave MISO (SOUT) — — 50 ns Slave 9

disable time

tV Data valid (after — — 26 ns Slave 10

SPSCK edge) 10

tV Data valid (after — — 14 ns Master 10

SPSCK edge) 10

tV Data valid (after — — 36 ns Slave_10Mbps 10

SPSCK edge) 10

tV Data valid (after — — 21 ns Master_10Mbps, for 10

SPSCK edge) 10 all S32K3xx variants
except S32K3x8

tV Data valid (after — — 24 ns Master_10Mbps, for 10

SPSCK edge) 10 S32K3x8

tV Data valid (after — — 8 ns Master Loopback, 10

SPSCK edge) 4,10 applies to S32K388
LPSPI2 and LPSPI5
@20MHz

tV Data valid (after — — 8 ns Master Loopback, 10

SPSCK edge) 4,10 applies to S32K389
LPSPI1, LPSPI2,
LPSPI3, LPSPI4 and
LPSPI5 @20MHz

tV Data valid (after — — 17.5 ns Master Loopback, 10

SPSCK edge) 4,10 applies to all devices
LPSPI0 @20 MHz

tHO Data hold time 3 — — ns Slave 11

(outputs) 10

tHO Data hold time -8 — — ns Master 11

(outputs) 10

tHO Data hold time 3 — — ns Slave_10Mbps 11

(outputs) 10

tHO Data hold time -15 — — ns Master_10Mbps, for 11

(outputs) 10 all S32K3xx variants
except S32K3x8

tHO Data hold time -18 — — ns Master_10Mbps, for 11

(outputs) 10 S32K3x8

tHO Data hold time -4.5 — — ns Master Looopback, 11

(outputs) 4,10 applies to S32K389
LPSPI1, LPSPI2,
LPSPI3, LPSPI4 and
LPSPI5 @20MHz

Table continues on the next page...

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Table 44. LPSPI (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tHO Data hold time -4.5 — — ns Master Looopback, 11

(outputs) 4,10 applies to S32K388
LPSPI2 and LPSPI5
@20MHz

tHO Data hold time -2 — — ns Master Loopback, 11

(outputs) 4,10 applies to all devices
LPSPI0 @20 MHz

tRI/FI Rise/Fall time — — 1 ns Slave —

input 11

tRI/FI Rise/Fall time — — 1 ns Master —

input 11

tRI/FI Rise/Fall time — — 1 ns Master Loopback —

input 4,11

1. For LPSPI0 instance, max. peripheral frequency is equal to AIPS_PLAT_CLK.

2. tperiph = 1/fperiph
3. fperiph = LPSPI peripheral clock
4. Master Loopback mode: In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting
LPSPI_CFGR1[SAMPLE] bit as 1.
5. These specifications apply to the SPI operation, as master or slave, at up to 10 Mbps for the combinations not indicated
in the table below. Unless otherwise noted, all other ‘master’ and ‘slave’ specifications are also applicable in the 10Mbps
configurations. See table "LPSPI 20 MHz and 15 MHz Combinations.
6. LPSPI0 support up to 20MHz on fast pin.
7. Minimum configuration value for CCR[PCSSCK] field is 3(0x00000011).
8. Minimum configuration value for CCR[SCKPCS] field is 3(0x00000011).
9. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
10. Output rise/fall time is determined by the output load and GPIO pad drive strength setting. See the GPIO specifications for
detail.
11. The input rise/fall time specification applies to both clock and data, and is required to guarantee related timing parameters.

SS
(INPUT)
2 4
3
SPSCK
(CPOL = 0)
(INPUT)
5 5
SPSCK
(CPOL = 1)
(INPUT)
10 11 9
MISO
SLAVE MSB OUT BIT 6 ... 1 SLAVE LSB OUT
(OUTPUT)
8 6 7
MOSI
MSB IN BIT 6 ... 1 LSB IN
(INPUT)

Figure 45. LPSPI Slave Mode Timing (CPHA=1)

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SS
(INPUT)
2 12 4
3 13
SPSCK
(CPOL = 0)
(INPUT)
5 5 12 13
SPSCK
(CPOL = 1) 9
(INPUT)
8
10 11 11
MISO
SLAVE MSB BIT 6 ... 1 SLAVE LSB OUT
(OUTPUT)
6 7
MOSI
MSB IN BIT 6 ... 1 LSB IN
(INPUT)

Figure 46. LPSPI Slave Mode Timing (CPHA=0)

SS1
(OUTPUT)
2 4
3
SPSCK
(CPOL = 0)
(OUTPUT)
5 5
SPSCK
(CPOL = 1)
(OUTPUT)
6 7
MISO
MSB IN2 BIT 6 ... 1 LSB IN
(INPUT)
10 11
MOSI
MSB OUT2 BIT 6 ... 1 LSB OUT
(OUTPUT)

Figure 47. LPSPI Master Mode Timing (CPHA=0)

SS1
(OUTPUT)
2 4
3
SPSCK
(CPOL = 0)
(OUTPUT)
5 5
SPSCK
(CPOL = 1)
(OUTPUT)
6 7
MISO
MSB IN2 BIT 6 ... 1 LSB IN
(INPUT)
10 11
MOSI
PORT DATA MASTER MSB OUT BIT 6 ... 1 MASTER LSB OUT PORT DATA
(OUTPUT)

Figure 48. LPSPI Master Mode Timing (CPHA=1)

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12.2 LPSPI0 20 MHz and 15 MHz Combinations

NOTE
15 and 20 Mbps is supported on LPSPI0 only.

All measurements are with maximum output load of 25pF (except 30pF support on K358 with Standard-Plus IOs, and 50pF
support on K388 with Standard-Plus IOs). S32K31x devices support only 15 MHz modes and all other devices support both 15
and 20 MHz combinations.

Table 45. LPSPI0 20 MHz and 15 MHz Combinations

PORT SPI Signal 20Mbps (In loopback 15 Mbps

mode only)

PTB1 LPSPI0_SOUT LPSPI0_SOUT

PTB0 LPSPI0_PCS0 LPSPI0_PCS0

PTC9 LPSPI0_SIN LPSPI0_SIN

PTC8 LPSPI0_SCK LPSPI0_SCK

PTD6 LPSPI0_PCS0 LPSPI0_PCS0

PTD5 LPSPI0_PCS1 LPSPI0_PCS1

PTD12 LPSPI0_SOUT LPSPI0_SOUT

PTD11 LPSPI0_SCK LPSPI0_SCK

PTD10 LPSPI0_SIN LPSPI0_SIN

NOTE
Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.

12.3 LPSPI2 and LPSPI5 20MHz combination for S32K388 and S32K389
NOTE
LPSPI running at 20MHz speed is possible only on specific pads as per table below.

All measurements are with maximum output load of 25pF.

Table 46. LPSPI2 and LPSPI5 20MHz combination for S32K388 and S32K389

LPSPI Instance Signal Type PIN LPSPI Signal

LPSPI2 Master Loopback PCS PTF7 LPSPI2_PCS0

SCK PTA11 LPSPI2_SCK

SOUT PTF4 LPSPI2_SOUT

SIN PTE24 LPSPI2_SIN

LPSPI5 Master Loopback PCS PTG23 LPSPI5_PCS0

SCK PTD31 LPSPI5_SCK

SOUT PTG25 LPSPI5_SOUT

SIN PTD28 LPSPI5_SIN

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Table 47. LPSPI5 and LPSPI0 20MHz combination for S32K388 and S32K389

LPSPI Instance Signal Type PIN LPSPI Signal

LPSPI5 Master Loopback PCS PTD17 LPSPI5_PCS0

SCK PTD14 LPSPI5_SCK

SOUT(MOSI) PTE9 LPSPI5_SOUT

SIN(MISO) PTD13 LPSPI5_SIN

LPSPI0 Master Loopback PCS PTD6 LPSPI0_PCS0

SCK PTD11 LPSPI0_SCK

SOUT(MOSI) PTD12 LPSPI0_SOUT

SIN(MISO) PTD10 LPSPI0_SIN

Table 48. LPSPI1, LPSPI3 and LPSPI4 for S32K389

LPSPI Instance Signal Type PIN LPSPI Signal

LPSPI1 Master Loopback PCS PTI16 LPSPI1_PCS0

SCK PTI14 LPSPI1_SCK

SOUT PTI18 LPSPI1_SOUT

SIN PTI20 LPSPI1_SIN

LPSPI3 Master Loopback PCS PTJ12 LPSPI3_PCS0

SCK PTJ10 LPSPI3_SCK

SOUT PTJ14 LPSPI3_SOUT

SIN PTJ16 LPSPI3_SIN

LPSPI4 Master Loopback PCS PTJ29 LPSPI4_PCS0

SCK PTK0 LPSPI4_SCK

SIN PTJ23 LPSPI4_SIN

SOUT PTJ26 LPSPI4_SOUT

12.4 Communication between two S32K388 devices

S32K388 devices supports fast data sending between two of them. Interface uses is four data lines at frequency of 6.6MHz in one
direction and four data lines at frequency of 6.6MHz in opposite direction. Configuration of LPSPI interface is 4x data lines half
duplex mode. For purpose of this communication LPSPI2, LPSPI5 and set of PINs was designed. Below figure shows diagram of
connection between two S32K388 devices. Left device will use LPSPI2 in Master 4x data line half duplex mode to send data to
LPSPI2 in Slave 4x dataline half duplex mode on second device. Similarly LPSPI5, but for in opposite direction than LPSPI2 do.

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PCS

LPSPI 2
LPSPI 2
SCK

Master mode

Slave mode
D0
D1

K388 Right
D2
K388 Left D3

LPSPI 5 PCS

LPSPI 5
SCK

Master mode
Slave mode
D0
D1
D2
D3

Figure 49. Connection between two S32K388 devices

Table 49. Pins and signals assignment for this communication.

K388 Left K388 Right

LPSPI instance Signal PIN LPSPI signal LPSPI instance Signal PIN LPSPI signal
type type

PCS PTF7 LPSPI2_PCS0 PCS PTF7 LPSPI2_PCS0

SCK PTA11 LPSPI2_SCK SCK PTA11 LPSPI2_SCK

Master mode

Slave mode

D0 PTF4 LPSPI2_SOUT D0 PTF4 LPSPI2_SOUT

LPSPI2
LPSPI2

D1 PTE24 LPSPI2_SIN D1 PTE24 LPSPI2_SIN

D2 PTH0 LPSPI2_PCS2 D2 PTH0 LPSPI2_PCS2

D3 PTH1 LPSPI2_PCS3 D3 PTH1 LPSPI2_PCS3

PCS PTG23 LPSPI5_PCS0 PCS PTG28 LPSPI5_PCS0

SCK PTD31 LPSPI5_SCK SCK PTG31 LPSPI5_SCK

Master mode
Slave mode

D0 PTG25 LPSPI5_SOUT D0 PTG30 LPSPI5_SOUT

LPSPI5

LPSPI5

D1 PTD28 LPSPI5_SIN D1 PTG29 LPSPI5_SIN

D2 PTG24 LPSPI5_PCS2 D2 PTG13 LPSPI5_PCS2

D3 PTD30 LPSPI5_PCS3 D3 PTG8 LPSPI5_PCS3

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12.4.1 Timing specification for S32K388 to S32K388 communication

Below table lists the timing parameters for this communication. This parameters is valid only on set of pins preselected for this
device to device communication. All timing is shown with respect to 50% VDD_HV_A/B thresholds. All measurements are with
maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew setting (DSE = 1'b1).

Table 50. Timing specification for S32K388 to S32K388 communication

Symbol Description Min Typ Max Unit Condition Spec

Number

fcom Communication — — 6.6 MHz — —

frequency

tWSPCK Clock (SPSCK) high 69 — 79 ns — —

or low time (SPSCK
duty cycle)

tSU Data setup time 34 — — ns Master mode 6

tSU Data setup time 5 — — ns Slave mode 6

tV Data valid (after — — 21 ns Master mode 10

SPSCK edge)

tV Data valid (after — — 34 ns Slave mode 10

SPSCK edge)

tHO Input hold time 0 — — ns Master mode input 7

tHO Input hold time 4 — — ns slave mode input 7

tHO Output hold time 3 — — ns Slave mode output 11

tHO Output hold time -15 — — ns Master mode output 11

tLEAD Enable lead time 30 — — ns Master mode 3

(PCS to SPSCK
delay)

tA Slave access time — — 50 ns — —

tDIS Slave MISO (SOUT) — — 50 ns — —

disable time

tLAG Enable lag time 30 — — ns — —

(After SPSCK delay)

12.5 I2C
See I/O parameters for I2C specification.
"For supported baud rate see section 'Chip-specific LPI2C information' of the Reference Manual."

12.6 FlexCAN characteristics

See I/O parameters for FlexCAN specification.
"For supported baud rate, see section 'Protocol timing' of the Reference Manual."

12.7 SAI electrical specifications

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12.7.1 SAI Electrical Characteristics, Slave Mode

The following table describes the SAI electrical characteristics. Measurements are with maximum output load of 30pF,
input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Table 51. SAI Electrical Characteristics, Slave Mode

Symbol Description Min Typ Max Unit Condition Spec

Number

S13 SAI_BCLK cycle 80 — — ns — —

time (input)

S14 SAI_BCLK pulse 45 — 55 % — —

width high/low
(input) 1

S15 SAI_RXD input 8 — — ns — —

setup before
SAI_BCLK

S16 SAI_RXD input hold 2 — — ns — —

after SAI_BCLK

S17 SAI_BCLK to — — 28 ns — —
SAI_TXD output
valid

S18 SAI_BCLK to 0 — — ns — —
SAI_TXD output
invalid

S19 SAI_FS input setup 8 — — ns — —

before SAI_BCLK

S20 SAI_FS input hold 2 — — ns — —

after SAI_BCLK

S21 SAI_BCLK to — — 28 ns — —
SAI_FS output valid

S22 SAI_BCLK to 0 — — ns — —
SAI_FS output
invalid

1. The slave mode parameters (S15 - S22) assume 50% duty cycle on SAI_BCLK input. Any change in SAI_BCLK duty cycle
input must be taken care during the board design or by the master timing.

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S13
S14
SAI_BCLK (input) S14
S21
S22
SAI_FS (output)

S19
S20
SAI_FS (input)
S17
S17 S18
S18
SAI_TXD

S15 S16

SAI_RXD

Figure 50. SAI slave mode

12.7.2 SAI Electrical Characteristics, Master Mode

The following table describes the SAI electrical characteristics. Measurements are with maximum output load of 30pF,
input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b 0. I/O operating voltage ranges from 2.97 V to 3.63 V.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Table 52. SAI Electrical Characteristics, Master Mode

Symbol Description Min Typ Max Unit Condition Spec

Number

S1 SAI_MCLK cycle 40 — — ns — —
time

S2 SAI_MCLK pulse 45 — 55 % — —
width high/low

S3 SAI_BCLK cycle 80 — — ns — —
time

S4 SAI_BCLK pulse 45 — 55 % — —
width high/low

S5 SAI_RXD input 28 — — ns — —
setup before
SAI_BCLK

S6 SAI_RXD input hold 0 — — ns — —

after SAI_BCLK

S7 SAI_BCLK to — — 8 ns — —
SAI_TXD output
valid

S8 SAI_BCLK to -2 — — ns — —
SAI_TXD output
invalid

S9 SAI_FS input setup 28 — — ns — —

before SAI_BCLK

Table continues on the next page...

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Table 52. SAI Electrical Characteristics, Master Mode (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

S10 SAI_FS input hold 0 — — ns — —

after SAI_BCLK

S11 SAI_BCLK to — — 8 ns — —
SAI_FS output valid

S12 SAI_BCLK to -2 — — ns — —
SAI_FS output
invalid

Figure 51. SAI master mode

12.8 Ethernet characteristics

12.8.1 Ethernet MII (10/100 Mbps)

The following timing specs are defined at the device I/O pin and must be translated appropriately to arrive at timing specs/
constraints for the physical interface. Measurements are with maximum output load of 25pF, input transition of 1ns and pad
configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Table 53. Ethernet MII (10/100 Mbps)

Symbol Description Min Typ Max Unit Condition Spec

Number

— RXCLK frequency — 2.5/25 — MHz 10/100 Mbps —

MII1 RXCLK pulse width 35 — 65 %RXCLK — —

high period

Table continues on the next page...

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Table 53. Ethernet MII (10/100 Mbps) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

MII2 RXCLK pulse width 35 — 65 %RXCLK — —

low period

MII3 RXD[3:0], RXDV, 5 — — ns 10/100 Mbps —

RXER to RXCLK
setup

MII4 RXCLK to RXD[3:0], 5 — — ns 10/100 Mbps —

RXDV, RXER hold

tCYC_TX TXCLK frequency — 2.5 / 25 — MHz 10/100 Mbps —

MII5 TXCLK pulse width 35 — 65 %TXCLK — —

high period

MII6 TXCLK pulse 35 — 65 %TXCLK — —

width low period

MII7 TXCLK to TXD[3:0], 2 — — ns — —

TXEN, TXER invalid

MII8 TXCLK to TXD[3:0], — — 25 ns — —

TXEN, TXER valid

Figure 52. MII receive diagram

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Figure 53. MII transmit diagram

12.8.2 Ethernet MII (200 Mbps)

The following timing specs are defined at the device I/O pin and must be translated appropriately to arrive at timing specs/
constraints for the physical interface. Measurements are with maximum output load of 25pF, input transition of 1ns and pad
configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Table 54. Ethernet MII (200 Mbps)

Symbol Description Min Typ Max Unit Condition Spec

Number

— RXCLK frequency — — 50 MHz — —

MII1 RXCLK pulse width 35 — 65 % — —

high RXCLK
period

MII2 RXCLK pulse width 35 — 65 % — —

low RXCLK
period

MII3 RXD[3:0], RXDV, 4 — — ns — —

RXER to RXCLK
setup time

MII4 RXCLK to RXD[3:0], 2 — — ns — —

RXDV, RXER hold
time

— TXCLK frequency — — 50 MHz — —

Table continues on the next page...

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Table 54. Ethernet MII (200 Mbps) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

MII5 TXCLK pulse width 35 — 65 % — —

high TXCLK
period

MII6 TXCLK pulse width 35 — 65 % — —

low TXCLK
period

MII7 TXCLK to TXD[3:0], 2 — — ns — —

TXDV, TXER invalid

MII8 TXCLK to TXD[3:0], — — 15 ns — —

TXDV, TXER valid

Figure 54. MII receive diagram

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Figure 55. MII transmit diagram

12.8.3 Ethernet RMII (10/100 Mbps)

The following timing specs are defined at the device I/O pin and must be translated appropriately to arrive at timing specs/
constraints for the physical interface. Measurements are with maximum output load of 25pF, input transition of 1ns and pad
configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Table 55. Ethernet RMII (10/100 Mbps)

Symbol Description Min Typ Max Unit Condition Spec

Number

— RMII input — — 50 MHz 10/100 Mbps —

clock frequency
(RMII_CLK)

RMII1,RMII5 RMII_CLK pulse 35 — 65 %RMII_C — —

width high LK period

RMII2,RMII6 RMII_CLK pulse 35 — 65 %RMII_C — —

width low LK period

RMII3 RXD[1:0], CRS_DV, 4 — — ns — —

RXER to RMII_CLK
setup

RMII4 RMII_CLK to 2 — — ns — —
RXD[1:0], CRS_DV,
RXER hold

Table continues on the next page...

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Table 55. Ethernet RMII (10/100 Mbps) (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

RMII8 RMII_CLK to — — 15 ns — —
TXD[1:0], TXEN
data valid

RMII7 RMII_CLK to 2 — — ns — —
TXD[1:0], TXEN
data invalid

Figure 56. RMII receive diagram

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Figure 57. RMII transmit diagram

12.8.4 Ethernet RGMII

The following timing specs are defined at the device I/O pin and must be translated appropriately to arrive at timing specs/
constraints for the physical interface. Measurements are with maximum output load of 13.5pF, input transition of 1ns and pad
configured with DSE = 1'b1 and SRE = 1'b0.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Table 56. Ethernet RGMII

Symbol Description Min Typ Max Unit Condition Spec

Number

Tcyc Clock cycle 7.2 — 8.8 ns SRC = 0 —

duration 1,2

TskewT Data to clock -500 — 500 ps SRC=0 —

output skew (at
transmitter) 2

TskewRi Data to clock input 1 — 2.6 ns SRC=0 —

skew (at receiver) 2

TskewRo Data to clock output -650 — 650 ps SRC=0 —

skew (at receiver) 2

Duty_G Clock duty cycle for 45 — 55 % SRC=0 —

Gigabit 2

Duty_T Clock duty cycle for 40 — 60 % SRC=0 —

10/100T 2

Tr Output rise time 3 — — 1 ns SRC=0 —

Tf Output fall time 3 — — 1 ns SRC=0 —

1. For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.

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2. RGMII timing specifications is valid for 3.3V nominal I/O pad supply voltage.
3. Output timing valid for maximum external load CL = 13.5 pF (includes PCB trace, package trace (around 2pF) and flash
input load).

RXC (at transmitter)

TskewT
RXD[8:5][3:0] RXD[8:5]
RXD[7:4][3:0] RXD[3:0]
RXD[7:4]

RXD[4] RXD[9]
RX_CTL
RXDV RXERR
TskewR

RXC (at receiver)

Figure 58. RGMII Receive Timing

TXC (at transmitter)

TskewT
TXD[8:5][3:0] TXD[8:5]
TXD[7:4][3:0] TXD[3:0]
TXD[7:4]

TXD[4] TXD[9]
TX_CTL
TXEN TXERR
TskewR

TXC (at receiver)

Figure 59. RGMII Transmit Timing

12.8.5 MDIO timing specifications

The following table describes the MDIO electrical characteristics. Measurements are with maximum output load of 25 pF, input
transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1 and SRE = 1’b0). I/O operating voltage ranges from
2.97 V to 3.63 V. MDIO pin must have external Pull-up.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Table 57. MDIO timing specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

— MDC clock — — 2.5 MHz — —

frequency

MDC1 MDC pulse width 40 — 60 %MDC — MDC1

high period

MDC2 MDC pulse width low 40 — 60 %MDC — MDC2

period

MDC5 MDC falling edge — — 25 ns — MDC5

to MDIO output
valid(maximum
propagation delay)

Table continues on the next page...

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Table 57. MDIO timing specifications (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

MDC6 MDC falling edge -10 — — ns — MDC6

to MDIO output
invalid(minimum
propagation delay)

MDC3 MDIO (input) to 25 — — ns Applies to S32K3x4, MDC3

MDC rising edge S32K342, S32K341,
setup time S32K322, S32K328,
S32K338, S32K348,
S32K358 and all GPIO
pads of S32K388
except GPIO[113]

MDC3 MDIO (input) to 29.5 — — ns Applies to GPIO[113] MDC3

MDC rising edge pad of S32K388
setup time

MDC4 MDIO (input) to 0 — — ns — MDC4

MDC rising edge
hold time

MDC1 MDC2

MDC (output)

MDC6

MDIO (output)

MDC5

MDIO (input)

MDC3 MDC4

Figure 60. MII/RMII serial management channel timing

12.9 QuadSPI

12.9.1 QuadSPI Quad 3.3V SDR 120MHz

The following table applies to S32K344, S32K324, S32K314, S32K342, S32K341, S32K322, S32K328, S32K338, S32K348,
and S32K358.
The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input
transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI
trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have
pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance
of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain
upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device
Reference Manual for register and bit descriptions.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux

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Program register value QuadSPI_FLSHCR[TCSS] = 4`h3.

Program register value QuadSPI_FLSHCR[TCSH] = 4`h3.
Program register value QuadSPI_DLLCRA[SLV_FINE_OFFSET] to 4'b0001.
Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock
transitions measured at mid-supply.

Table 58. QuadSPI Quad 3.3V SDR 120MHz

Symbol Description Min Typ Max Unit Condition Spec

Number

fSCK SCK clock — — 120 MHz Pad Loopback —

frequency 1

fSCK SCK clock — — 60 MHz Internal Loopback —

frequency 1

tSCK SCK clock period 1/fSCK — — ns Pad Loopback —

tSCK SCK clock period 1/fSCK — — ns Internal Loopback —

tSDC SCK duty cycle 2 45 — 55 % Internal Loopback —

tSDC SCK duty cycle 2 45 — 55 % Pad Loopback —

tIS Data input setup 1.75 — — ns Pad Loopback —

time

tIS Data input setup 9 — — ns Internal Loopback —

time

tIH Data input hold time 1 — — ns Pad Loopback —

tIH Data input hold time 1 — — ns Internal Loopback —

tOV Data output valid — — 1.75 ns Pad Loopback —

time

tOV Data output valid — — 1.75 ns Internal Loopback —

time

tIV Data output invalid -1.5 — — ns Pad Loopback —

time

tIV Data output invalid -1.5 — — ns Internal Loopback —

time

tCSSCK CS to SCK time 5 — — ns Pad Loopback —

tCSSCK CS to SCK time 5 — — ns Internal Loopback —

tSCKCS SCK to CS time 3 — — ns Pad Loopback —

tSCKCS SCK to CS time 3 — — ns Internal Loopback —

1. This frequency specification is valid only if output valid time of external flash is ≤ 5.5ns, and if output valid time of
external flash is more than 5.5ns but ≤ 6.5ns, then maximum fSCK is 104MHz.
2. For S32K342 100HDQFP, tSDC spec would be 44%-56% when ENET and SAI active along with QuadSPI at 120MHZ

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Figure 61. QuadSPI input timing (SDR mode)

Figure 62. QuadSPI output timing (SDR mode)

12.9.2 QuadSPI Octal 3.3V DDR 100MHz

The following table applies to S32K328, S32K338, S32K348, S32K358.
The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input
transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI
trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have
pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance
of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain
upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device
Reference Manual for register and bit descriptions.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.
Set FLSHCR[TCSS]=2 and FLSHCR[TCSH]=5.
Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock
transitions measured at mid-supply.

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Table 59. QuadSPI Octal 3.3V DDR 100MHz

Symbol Description Min Typ Max Unit Condition Spec

Number

fSCK_DQS SCK / DQS — — 100 MHz — —

frequency 1

tSDC SCK duty cycle 45 — 55 % — —

tCL_SCK_DQS SCK / DQS low 4.500 — — ns — —

time 1

tCH_SCK_DQS SCK / DQS high 4.500 — — ns — —

time 1

tOD_DATA Data output delay 1.016 — 3.484 ns — —

(w.r.t. SCK)

tOD_CS CS output delay 3.016 - n/ — -0.016 + ns — —

(w.r.t. SCK) 2 fSCK m/fSCK

tDVW Input data valid 3.284 — — ns — —

window 1

tISU_DQS Input setup time -0.816 — — ns — —

(w.r.t. DQS) 1

tIH_DQS Input hold time (w.r.t. 3.684 — — ns — —

DQS) 1

1. Input timing assumes maximum input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the
Flash.
2. Where m=TCSS and n=TCSH-1.

12.9.3 QuadSPI Quad 3.3V SDR 103.33MHz

The following table applies only to S32K388 and S32K389.
The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input
transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI
trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have
pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance
of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain
upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device
Reference Manual for register and bit descriptions.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.
Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock
transitions measured at mid-supply.

Table 60. QuadSPI Quad 3.3V SDR 103.33MHz

Symbol Description Min Typ Max Unit Condition Spec

Number

fSCK SCK clock frequency — — 103.33 MHz — —

tCL_SCK SCK clock low time 1 4.327 — — ns — —

Table continues on the next page...

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Table 60. QuadSPI Quad 3.3V SDR 103.33MHz (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tCH_SCK SCK clock high 4.327 — — ns — —

time 1

tOD_DATA Data output delay -2.330 — 2.880 ns — —

(w.r.t. SCK)

tOD_CS CS output delay 3.391 - n/ — 5.901 + ns — —

(w.r.t. SCK) 2 fSCK m/fSCK

tDVW Input data valid 5.5 — — ns — —

window 1

tISU_SCK Input setup time 2.152 — — ns — —

(w.r.t. SCK) 1

tIH_SCK Input hold time (w.r.t. 2.0 — — ns — —

SCK) 1

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).

2. Where m=TCSS and n=TCSH-1.

12.9.4 QuadSPI Octal 3.3V DDR 120MHz

The following table applies to S32K328, S32K338, S32K348, S32K358.
The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input
transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI
trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have
pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance
of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain
upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device
Reference Manual for register and bit descriptions.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.
Set FLSHCR[TCSS]=2 and FLSHCR[TCSH]=5.
Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock
transitions measured at mid-supply

Table 61. QuadSPI Octal 3.3V DDR 120MHz

Symbol Description Min Typ Max Unit Condition Spec

Number

fSCK_DQS SCK / DQS — — 120 MHz DLL enabled —

frequency 1

fSCK_DQS SCK / DQS — — 120 MHz DLL mode enabled —

frequency 1

tSCK SCK clock period 1/ — — ns External DQS —

fSCK_D
QS

Table continues on the next page...

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Table 61. QuadSPI Octal 3.3V DDR 120MHz (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tSDC SCK / DQS duty 45 — 55 % External DQS —

cycle

tCL_SCK_DQS SCK / DQS low 3.75 — — ns — —

time 1

tCH_SCK_DQS SCK / DQS high 3.75 — — ns — —

time 1

tOD_DATA Data output delay 0.816 — 2.934 ns — —

(w.r.t. SCK)

tOD_CS CS output delay 3.016 — -0.766 ns — —

(w.r.t. SCK)

tDVW Input data valid 2.518 — — ns — —

window 1

tISU_DQS Input setup time -0.616 — — ns — —

(w.r.t. DQS) 1

tIH_DQS Input hold time (w.r.t. 3.134 — — ns — —

DQS) 1

1. Input timing assumes an input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the Flash.

12.9.5 QuadSPI Quad 3.3V SDR 125MHz

The following table applies only to S32K388 and S32K389.
The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input
transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI
trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have
pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance
of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain
upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device
Reference Manual for register and bit descriptions.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.
Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock
transitions measured at mid-supply.

Table 62. QuadSPI Quad 3.3V SDR 125MHz

Symbol Description Min Typ Max Unit Condition Spec

Number

fSCK SCK clock — — 125 MHz — —

frequency 1

tCL_SCK SCK clock low time 1 3.6 — — ns — —

tCH_SCK SCK clock high 3.6 — — ns — —

time 1

Table continues on the next page...

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Table 62. QuadSPI Quad 3.3V SDR 125MHz (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tOD_DATA Data output delay -1.294 — 1.844 ns — —

(w.r.t. SCK)

tOD_CS CS output delay 3.391 - n/ — 3.829 + ns — —

(w.r.t. SCK) 2 fSCK m/fSCK

tDVW Input data valid 4.724 — — ns — —

window 1

tISU_SCK Input setup time 1.580 — — ns — —

(w.r.t. SCK) 1

tIH_SCK Input hold time (w.r.t. 1.5 — — ns — —

SCK) 1

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).

2. Where m=TCSS and n=TCSH-1.

12.10 uSDHC

12.10.1 uSDHC SDR electrical specifications

The following table describes the uSDHC electrical characteristics. Measurements are with maximum output load of
25pF, input transition of 1ns(20%/80%) and pad configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from
2.97 V to 3.63 V.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.
Data transitions measured at 25%/62.5% at 3.3V for the write path. Data transitions measured at mid-supply for the read path.
Clock transitions measured at mid-supply.

Table 63. uSDHC SDR electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

fpp Clock frequency (low — — 400 kHz — SD1

speed) 1

fpp Clock frequency — — 50 MHz Medium/Fast Pad SD1

(eMMC4.4/4.41
SDR, SD3.0
SDR) 1,2

fpp Clock frequency — — 25 MHz Standard plus/Medium SD1

(eMMC4.4/4.41 pad
SDR, SD3.0
SDR) 1,3

fOD Clock frequency 100 — 400 kHz — SD1

(identification
mode) 1

tWL Clock low time 6 — — ns Medium/Fast pad SD2

Table continues on the next page...

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Table 63. uSDHC SDR electrical specifications (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

tWL Clock low time 12 — — ns Standard plus/Medium SD2

pad

tWH Clock high time 6 — — ns Medium/Fast pad SD3

tWH Clock high time 12 — — ns Standard plus/Medium SD3

pad

tTLH Clock rise time 1,4 — — 4 ns Medium/Fast pad SD4

tTLH Clock rise time 1,4 — — 8 ns Standard plus/Medium SD4

pad

tTHL Clock fall time 1,4 — — 4 ns Medium/Fast pad SD5

tTHL Clock fall time 1,4 — — 8 ns Standard plus/Medium SD5

pad

tOD SDHC output delay -5.6 — 2.6 ns fpp= 50 MHz, SDHC_ SD6
(output valid) 1 CLK to SDHC_DAT

tOD SDHC output delay -5.6 — 10.64 ns fpp= 25 MHz, 400 KHz, SD6
(output valid) 1 SDHC_CLK to SDHC_
CMD / SDHC_DAT

tOD SDHC output delay -5.6 — 3.1 ns fpp= 50 MHz, SDHC_ SD6
(output valid) 1 CLK to SDHC_CMD

tISU SDHC Input setup 6.3 — — ns fpp= 25 MHz, 400 KHz, —

time SDHC_CMD / SDHC_
DAT to SDHC_CLK

tISU SDHC Input setup 4.8 — — ns fpp= 50 MHz, SDHC_ SD7

time CMD / SDHC_DAT to
SDHC_CLK

tIH SDHC Input hold 2 — — ns SDHC_CLK to SDHC_ SD8

time CMD / SDHC_DAT

1. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash
input load).
2. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed
mode, clock frequency can be any value between 0–50 MHz.
3. In normal (full) speed mode for MMC card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
4. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay
specifications. SDHC_CLK output transition time is dependent on output load and GPIO pad drive strength. See the GPIO
pad specifications for detail.

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Communication interfaces

SD4
SD2
SD5 SD1

SDx_CLK

SD3
SD6

Output from uSDHC to card

SDx_DATA[7:0]

SD7 SD8

Input from card to uSDHC

SDx_DATA[7:0]

Figure 63. SD/eMMC4.3 High Speed Mode Interface Timing

12.10.2 uSDHC DDR electrical specifications

The following table describes the uSDHC electrical characteristics. Measurements are with maximum output load of
25pF, input transition of 1ns(20%/80%) and pad configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from
2.97 V to 3.63 V.
Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.
Data transitions measured at 25%/62.5% at 3.3V for the write path. Data transitions measured at mid-supply for the read path.
Clock transitions measured at mid-supply.

Table 64. uSDHC DDR electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

fpp Clock frequency — — 50 MHz Medium/Fast pad SD1

(eMMC4.4/4.41
DDR) 1

tWL Clock low time 6 — — ns Medium/Fast pad —

tWH Clock high time 6 — — ns Medium/Fast pad —

tTLH Clock rise time 1,2 — — 4 ns Medium/Fast pad —

tTHL Clock fall time 1,2 — — 4 ns Medium/Fast pad —

tOD SDHC output delay 2.7 — 6.53 ns SDHC_CLK to SDHC_ SD2

(output valid) 1 DAT

tOD SDHC output delay -5.6 — 2.6 ns SDHC_CLK to SDHC_ SD6

(output valid) 1 CMD (See
SDR
figure)

tISU SDHC Input setup 1.6 — — ns SDHC_DAT to SDHC_ SD3

time CLK

tISU SDHC Input setup 4.8 — — ns SDHC_CMD to SDHC_ SD7

time CLK (See

Table continues on the next page...

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Debug modules

Table 64. uSDHC DDR electrical specifications (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

SDR
figure)

tIH SDHC Input hold 1.5 — — ns SDHC_CLK to SDHC_ SD4

time DAT

tIH SDHC Input hold 1.5 — — ns SDHC_CLK to SDHC_ SD8

time CMD (See
SDR
figure)

1. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash
input load).
2. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay
specifications. SDHC_CLK output transition time is dependent on output load and GPIO pad drive strength. See the GPIO
pad specifications for detail.

SD1

SDx_CLK

SD2
SD2

Output from eSDHCv3 to card .......

SDx_DATA[7:0]

SD3
SD4

Input from card to eSDHCv3 .......

SDx_DATA[7:0]

Figure 64. SD/eMMC4.4/4.41 DDR50 Mode Interface Timing

12.11 LPUART specifications

See I/O parameters for LPUART specifications.

13 Debug modules

13.1 Debug trace timing specifications

The following table describes the Debug trace electrical characteristics. Measurements are with maximum output load of 25pF,
input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0.
See I/O parameters for GPIO electrical specifications.

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Debug modules

Table 65. Debug trace timing specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

fTRACE Trace clock — — 120 MHz Applies to all —

frequency (trace on K3xx variants except
Fast pads) S32K388 and S32K389

fTRACE Trace clock — — 125 MHz Applies to S32K388 —

frequency (trace on and S32K389
Fast pads)

fTRACE Trace clock — — 25 MHz — —

frequency (trace on
StandardPlus pads)

tDVW Data output valid 1.2 — — ns — —

window

tDIV Data output invalid 0.3 — — ns — —

Figure 65. Trace CLKOUT specifications

13.2 SWD electrical specifications

The following table describes the SWD electrical characteristics. Measurements are with maximum output load of 30pF, input
transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0.
See I/O parameters for GPIO electrical specifications.

Table 66. SWD electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

S1 SWD_CLK — — 33 MHz — S1
frequency

S2 SWD_CLK cycle 1 / S1 — — ns — S2
period

S3 SWD_CLK pulse 40 — 60 % — S3
width

Table continues on the next page...

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Debug modules

Table 66. SWD electrical specifications (continued)

Symbol Description Min Typ Max Unit Condition Spec

Number

S4 SWD_CLK rise and — — 1 ns — S4

fall times

S9 SWD_DIO input 5 — — ns — S9
data setup time to
SWD_CLK rise

S10 SWD_DIO input 5 — — ns — S10

data hold time
after SWD_CLK
rising edge

S11 SWD_CLK high to — — 22 ns — S11

SWD_DIO output
data valid

S12 SWD_CLK high to — — 22 ns — S12

SWD_DIO output
data hi-Z

S13 SWD_CLK high to 0 — — ns — S13

SWD_DIO output
data invalid

S2
S3 S3

SWD_CLK (input)

S4 S4

Figure 66. SWD Input Clock Timing

SWD_CLK

S9 S10

SWD_DIO Input data valid

S11

S13

SWD_DIO Output data valid

S12

SWD_DIO

Figure 67. SWD Output Data Timing

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Debug modules

13.3 JTAG electrical specifications

The following table describes the JTAG electrical characteristics. These specifications apply to JTAG and boundary scan.
Measurements are with maximum output load of 30pF, input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0.
See I/O parameters for GPIO electrical specifications.

Table 67. JTAG electrical specifications

Symbol Description Min Typ Max Unit Condition Spec

Number

tJCYC TCK cycle time 1,2 30 — — ns — 1

tJDC TCK clock pulse 40 — 60 % — 2

width

tTCKRISE TCK rise/fall times — — 1 ns — 3

(40%-70%)

tTMSS, tTDIS TMS, TDI data setup 5 — — ns — 4

time

tTMSH, tTDIH TMS, TDI data hold 5 — — ns — 5

time

tTDOV TCK low to TDO — — 22 ns — 6

data valid 3

tTDOI TCK low to TDO 0 — — ns — 7

data invalid

tTDOHZ TCK low to TDO — — 22 ns — 8

high impedance

tBSDV TCK falling edge to — — 600 ns — 11

output valid 4

tBSDVZ TCK falling edge to — — 600 ns — 12

output valid out of
high impedance

tBSDHZ TCK falling edge — — 600 ns — 13

to output high
impedance

tBSDST Boundary scan input 15 — — ns — 14

valid to TCK rising
edge

tBSDHT TCK rising edge to 15 — — ns — 15

boundary scan input
invalid

1. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Refer to pad specification for allowed transition frequency
2. Cycle time is 30ns assuming full cycle timing. Cycle time is 60ns assuming half cycle timing.
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

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Debug modules

TCK
2

3 2

1 3

Figure 68. JTAG TCK Input Timing

TCK

TMS, TDI

7 8

TDO

Figure 69. JTAG Test Access Port Timing

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Thermal Attributes

TCK

11 13

Output
signals

12

Output
signals

14
15

Input
signals

Figure 70. Boundary Scan Timing

14 Thermal Attributes

14.1 Description
The tables in the following sections describe the thermal characteristics of the device.

NOTE
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting
side (board) temperature, ambient temperature, air flow, power dissipation or other components on the board, and
board thermal resistance.

14.2 Thermal characteristics

Thermal Design and Characteristics
• Junction temperature of the device does not solely depend on package thermal resistance but is also a function of chip
power dissipation, PCB attributes, environmental conditions (ambient temperature & air flow) and cumulative effects of
other heat generating ICs on the PCB.
• The appropriate thermal design must be carried out on package so that it can safely dissipate the necessary amount of
power needed for it to function properly without exceeding the maximum junction temperature. This may involve adding a
cooling solution on the package, creating thermal enhancements on the PCB and improving environmental conditions.
• The customer is encouraged to use the package model to perform design and risk assessment through simulations.
Package models in FloTHERM or Icepak formats can be obtained under NDA from the sales team.

Thermal Ratings
• The table below is the package thermal ratings for LQFP, HDQFP & MAPBGA package variants. These numbers are
derived through simulations based on standardized tests as described in the footnotes.

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Thermal Attributes

• Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a
standardized specified environment. It is not meant to predict the performance of a package in an application-specific
environment :

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NXP Semiconductors
Table 68. Thermal characteristics

Rating Conditions Symbol Package Device Unit

S32K311 S32K312 S32K342 S32K344 S32K358 S32K388 S32K389

S32K310 S32K341 S32K314 S32K348
S32K322 S32K324 S32K328
S32K338

Thermal resistance, Junction Four-layer RϴJA 48-LQFP 45 NA NA NA NA NA NA °C/W

to Ambient (Natural board (2s2p)2
100-HDQFP 35.3 38 33.8 NA NA NA NA °C/W
Convection)1
172-HDQFP NA 30.5 29.6 28.9 NA NA NA °C/W

257-MAPBGA NA NA NA 26.8 NA NA NA °C/W

S32K3xx Data Sheet, Rev. 10, 07/2024

172 HDQFP_EP NA NA NA NA 15.6 NA NA °C/W

Preliminary Information for S32K389

289-MAPBGA NA NA NA NA 20.9 20.4 NA °C/W

437-BGA NA NA NA NA NA NA TBD °C/W

Thermal characterization Natural ΨJT 48-LQFP 2 NA NA NA NA NA NA °C/W

parameter, Junction-to-Top of Convection
100-HDQFP 0.66 0.8 0.5 NA NA NA NA °C/W
package1
172-HDQFP NA 0.5 0.5 0.4 NA NA NA °C/W

257-MAPBGA NA NA NA 0.3 NA NA NA °C/W

172 HDQFP_EP NA NA NA NA 0.3 NA NA °C/W

289-MAPBGA NA NA NA NA 0.4 0.4 NA °C/W

437-BGA NA NA NA NA NA NA TBD °C/W

1. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal performance
comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific
environment
2. Thermal test board meets JEDEC specification for this package (JESD51-9).

Thermal Attributes
131 / 152
NXP Semiconductors
Dimensions

15 Dimensions

15.1 Obtaining package dimensions

Package dimensions are provided in the package drawings. To find a package drawing, go to nxp.com and perform a keyword
search for the drawing’s document number:

Package option Document Number

48-pin LQFP 98ASH00962A

257-ball MAPBGA 98ASA01483D

172-pin HDQFP 98ASA01107D

100-pin HDQFP 98ASA01570D

172-pin HDQFP_EP 98ASA01667D

289-ball MAPBGA 98ASA01216D

437-BGA TBD

16 Revision history
The following table lists the changes in this document.

Rev 10, July 2024

• Updated front matter, from "Upto 128K of flexible program" to "Upto 256KB of flexible program"
• In "Absolute Max Ratings" updated footnote from "…. the voltage in the respective I/O power domain (VDD_HV_A or
VDD_HV_B) would increase …." to "…voltage in the respective I/O power domain (VDD_HV_A or VDD_HV_B) would
increase and may cause damage to the MCU. It is recommended to.."
• In "S32K328" and "S32K348" block diagrams, updated the instances of FlexCAN to 8.
• Updated Part number nomenclature diagram.
• In "Power mode transition operating behavious", removed Fast Recovery from description of "tMODE_STDBYEXIT" for
S32K388 and S32K389.
• Updated table. "HSE Firmware memory verification time examples".
• In "289BGA package decoupling cap pinout digram(S32K388)", added CBULK capacitor, to H8.
• In section "V15 regulator(SMPS option)", updated the footnote from "Only needed..." to "Highly Recommended..."
• Added CBULK_SMPS in fig "SMPS circuit"
• In "V11 regulator (NMOS ballast transistor control) electrical specifications", updated the Typ value of V11 to 1.14V.
• In Supply current added values for S32K388.
• In table. Run mode configuration options, updated footnote from EMAC to EMAC/GMAC
• In GPIO DC electrical specifications, updated spec "VHSYS_33" and added footnote " Hysteresis spec does not apply to
fast pad"
• In PLL, for spec "FPLL_out" updated the Max value to 480 MHz.

Table continues on the next page...

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 132 / 152
NXP Semiconductors
Revision history

Rev 10, July 2024

• In section "FXOSC":
— Updated the Max value of CLKIN_VIL_EXTAL_BYPASS and Min value of CLKIN_VIH_EXTAL_BYPASS and
added new footnote "For bypass mode application, the EXTAL..."
— Added new note "To improve the FXOSC & PLL jitter performance in S32K388, the functionality of the pins
(namely -PTG0, PTG2, PTG3, PTF30, PTE12, PTA2..." specifically for S32K388.
• In LPSPI :
— Added new spec "tV" and "tHO" specifically for S32K389
— Updated the desciption of tA to "MISO valid time after SS assertion" and its reference in figure.
• Added new table ""LPSPI1, LPSPI3 and LPSPI4 for S32K389.
• In uSDHC SDR and DDR electrical specifications sections, updated the footnote "Öutput timing valid for maximum
external load CL= 25pF(includes PCB trace.…)"
• In section "V15 regulator (SMPS option) electrical specifications", added devices S32K388 and S32K389.
• In "FXOSC", added information "In single ended bypass mode, the XTAL pin can be left unconnected".
• Added CBULK capacitors for SMPS figures in Decoupling capacitor figures.
• In Table. "Thermal characteristics", added values for S32K388.
• Updated the attached Part Number sheet.
• Added information "See I/O parameters for GPIO electrical specifications" in LPSPI, JTAG, SWD and Debug Trace
timing Specifications.

Rev 10_DraftA, March 2024

• Updated front matter as below :

— Added package : 437BGA
— Program flash memory to 12MB
— SRAM with ECC to 2304 KB
— HMI upto 320 GPIO Pins
— FlexCAN modules to 12
• Added block diagram for S32K389
• Added information for S32K389 device throught the data sheet.

Rev 9.1, March 2024

• In table "LPSPI5 and LPSPI0 20MHz combination for S32K388", updated the instances of LPSPI2 to LPSPI5.
• In "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)", updated conditions for "FMAX_33_F" mentioning it
for specific devices.

S32K3xx Data Sheet, Rev. 10, 07/2024

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NXP Semiconductors
Revision history

Rev 9, January 2024

• In "features", updated "Up to 512 KB SRAM with ECC, includes 192 KB" to "Up to 1152 KB SRAM with ECC, includes
384 KB".
• Updated "feature comparison".
• Updated the DMIPS values in the Table of Features to align with the footnotes.
• In Absolute Max Ratings :
— Updated footnote "When the input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B)..." and
referred to S32K3xx hardware design guidelines instead of AN.
— Updated footnotes "Absolute max ratings must be..." and "When the input pad voltage levels.."
— Added new footnote "If a positive injection current is present..." to spec "I_INJSUM_DC_ABS".
— Added "S32K388" in statement "The VDD_DCDC supply voltage is only present in certain devices.."
— Updated condition for V15 and V11 spec.
• In Voltage and current operating requirements :
— Updated footnote "When input pad voltage levels are close to VDD_HV_A..."
— Added new footnotes "Keeping the input voltage between" and "If a positive injection current is present..."
— Added "S32K388" in statement "The VDD_DCDC supply voltage is only present in certain devices.."
— Updated condition for V15 and V11 spec.
• In "Power mode transition operating behaviour", added values for S32K3x8 devices.
• In "Supply Monitoring", added footnote "The HVD_V15 monitor is provided to indicate if the V15 rail is far above the standard
V15 operating range...".
• In Recommneded Decoupling capacitors diagrams and SMPS Circuit updated "VDD_HV_SMPS" to "VDD_DCDC".
• In Table. "V15 regulator (SMPS option) electrical specifications" added symbol "L_SMPS" for External coil inductance and
"D_SMPS" for External Schottky diode average forward current.
• Added IBCTL label in "Ballast circuit" figure.
• In "V11 regulator (NMOS ballast transistor control) electrical specifications" added new spec "VTH_NMOS" for 5.0 V supply
and updated Max value to "1.5" for VTH spec for 3.3 V supply.
• In "Supply currents" section , added values for "S32K358, S32K348, S32K338, S32K328".
• In RUN mode supply currents (peripherals disabled) for S32K3x8, deleted values from "
Min. Config. [Clock Option A+] Triple Core @240 MHz " for S32K358, S32K348, S32K338, S32K328 variants.
• In GPIO DC electrical specifications:-
— Updated footnote "I/O timing specifications are valid for the un-terminated 50ohm..." and figure related to it with correct
load details.
— Updated the conditions for FMAX specs.
• In "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)", added spec "FMAX_33_F" with max frequency
125 MHz.
• In GPIO Output AC electrical specifications, updated spec values and added new footnotes and figure.
• In "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)" and "GPIO DC electrical specifications, 5.0V (4.5V -
5.5V)", updated the max and min values of ILKG parameters.

Table continues on the next page...

S32K3xx Data Sheet, Rev. 10, 07/2024

Data Sheet: Technical Data Preliminary Information for S32K389 134 / 152
NXP Semiconductors
Revision history

Rev 9, January 2024

• Updated table "FIRC" mentioning FACC +/-5% for all K3xx devices.
• Updating figure title to "S32K310: ASIL B Single Core 512 KB General Purpose MCU".
• In "FXOSC":
— Added note "To improve the FXOSC & PLL jitter performance..."
— Updated the footnote "To improve the FXOSC jitter & duty cycle performance.."
• In "PLL", updated min value for "FPLL_out" from 48 to 25 MHz.
• In LPSPI, updated the output loads.
• In "LPSPI2 and LPSPI5 20MHz combination for S32K388", added new table "LPSPI2 and LPSPI0 20MHz combination
for S32K388".
• In "LPSPI"
— Updating min values of tLEAD/tLAG to ""tSPCK/2" for LPSPI Slave mode.
— For "tWPSCK", removed "high or low" from description.
— Updated information "All measurements are with maximum output load of 30pf.." at the top of the table.
— Removed Rise/Fall time output specs.
— Added footnotes "Output rise/fall time is determined by the output load and GPIO pad drive strength setting..." and
"The input rise/fall time specification applies to both clock and data..."
— Added "tV" and "tHO" spec with condition "Master Loopback, S32K388 LPSPI2 and LPSPI5 @20MHz"
— For "tV" with max value "17.5" ns, updated condition to ""Master Loopback, applies to all devices LPSPI0 @20 MHz"
— For "tHO" with min value "-2" ns, updated condition to ""Master Loopback, applies to all devices LPSPI0 @20 MHz"
— Updated LPSPI timing diagrams with 50/50 levels.
• In "LPSPI" and "Timing specification for S32K388 to S32K388", updated information from "All timing is shown
with respect to 20% VDD_HV_A/B and 80% VDD_HV_A/B thresholds" to "All timing is shown with respect to 50%
VDD_HV_A/B thresholds."
• Added information "Valid pin combinations to be referred from K3xx*_Use sheet in IOmux." in all SAI, uSHDC, QSPI and
Ethernet modes.
• Added information "Data transitions measured at 30%/70% supply for the write path. Data transitions measured at
mid-supply for the read path. Clock transitions measured at mid-supply." in all QSPI modes.
• Changed footer to "Preliminary Information for S32K388"
• Updated Preliminary Information for S32K388 throughout the data sheet.
• In "HSE Firmware memory verification time examples" table, there are some TBC's. Those will be updated in the next
revision as new measurements showed different timings. There is no major performance degradation to be expected.
• Added information in section "LPSPI 20 MHz and 15MHz combinations", and removed S32K344 PAD TYPE column from
Table. "LPSPI 20 MHz and 15MHz combinations".
• Added new section "LPSPI2 and LPSPI5 20MHz combination for S32K388".
• In "Timing specification for S32K388 to S32K388", updated maximum output load from 30pF to 50pF.
• In "Ethernet RGMII", updated footnote to "Output timing valid for maximum external load CL = 13.5 pF (includes PCB trace,
package trace (around 2pF) and flash input load)...."

Table continues on the next page...

S32K3xx Data Sheet, Rev. 10, 07/2024

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NXP Semiconductors
Revision history

Rev 9, January 2024

• In "QuadSPI Octal 3.3V DDR 120MHz", for spec "fSCK_DQS", updated condition from "DLL and Auto-Learning mode
enabled" to "DLL enabled"
• In section "uSDHC SDR electrical specifications":
— Updated description for "fpp" spec.
— Updated condition for "tOD" with description "SDHC Output delay(Output valid)"
— Added 2 rows of spec "tOD" with value "-5.6" and description ""fpp= 25 MHz, 400 KHz,..." and "fpp= 50 MHz, SDHC_
CLK to SDHC_CMD".
— Updated min value for spec "tIH" to 2 ns.
— Removed footnote " In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7V to 3.6V."
• In '"uSDHC" modes :
— Added information "Data transitions measured at 25%/62.5% at 3.3V for the write path. Data transitions measured at
mid-supply for the read path. Clock transitions measured at mid-supply."
— Removed footnote "Input timing assumes an input signal slew rate of 3ns (20%/80%)" from "uSDHC SDR electrical
specifications" and "uSDHC DDR electrical specifications" table. Added input transition of 1ns (20%/80%) information
to top of the table.
• In section "uSDHC DDR electrical specifications", removed spec "fpp" with description "Clock frequency (SD3.0 DDR)".
• In uSDHC SDR and uSDHC DDR electrical specifications updated footnote to "Output timing valid for maximum external
load CL = 25 pF..."

Rev 8.1, November 2023

• Updated "supply currents" for "S32K344, S32K324, S32K314, S32K342, S32K322, S32K341 and S32K312".

Rev 8, Jun 2023

• Moved S32K311 and S32K310 to support list from preliminary and added S32K322 to supported list.
• Updated frequency to 320 MHz for S32K388 mentioned in features and updated S32K388 block diagram.
• In section "Thermal operating characteristics" added ambient temperature seperately for both V- and M-grade parts.
• Deleted power management figures. See reference manual for these figures.
• Decoupling capacitors are updated with new formats.
• In section "V15 regulator (SMPS option) electrical specifications" updated the SMPS circuit figure.
• In section "V11 regulator (NMOS ballast transistor control) electrical specifications" updated V11 output from 1.14 to
1.155 V.
• In section "Supply currents" added current numbers for S32K311 and S32K310 and added support for 320MHz for
S32K388.
• In section "Supply currents" merged VDD_HV_A for S32K3x8, S32K34x, S32K32x and S32K314 and mentioned the
max current.
• Added table title to table in section "Cyclic wake-up current".
• In section "Low Power Comparator (LPCMP)",

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NXP Semiconductors
Revision history

Rev 8, Jun 2023

— for symbol tDDAC updated description from "DAC Initialization and switching settling time" to "DAC Initialization
time".
— updated footnote attached to TDHSS and TDLSS from "Applied +/- (30 mV + 2 x VAHYST0/1/2/3 + max. of VAIO)
around switch point" to "Applied +/- (30 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point"
• In section "Temperature Sensor" clarified that its an MCU on-die temperature sensor.
• In section "FIRC" updated FACC for S32K311 and S32K310 for different temperature ranges.
• In section "PLL", added sentence "Jitter values specified in this table are applicable for FXOSC reference clock input
only".
• In section "Fast External Oscillator (FXOSC)", added IFXOSC for ALC disabled.
• In section "Slow Crystal Oscillator (SXOSC)" updated ISXOSC max from 4 to 10 uA.
• In section " LPSPI" updated symbols of Data hold time (inputs) to tHI.
• Updated heading of Ethernet MII and RMII to mention support of 10 and 100 Mbps.
• In "uSDHC SDR electrical specifications" updated conditions for the supported pads.
• In "uSDHC DDR electrical specifications" updated conditions for the supported pads and deleted 25 MHz specifications.
• Updated RϴJA for 172HDQFP_EP to 15.6 °C/W.

Rev 7, Apr 2023

• Updated caution in overview and updated feature comparison.

• In "S32K3xx chip's feature comparison" section clarified via footnote that S32K388 supports QuadSPI SDR modes only.
• Updated S32K312 and S32K388 block diagram.
• QFP package references updated to HDQFP.
• In section "Absolute maximum ratings" added footnote to VDD_DCDC as "Voltage at VDD_DCDC cannot be higher than
VDD_HV_A".
• In section "Voltage and current operating requirements" added footnote to V15 as "Min and Max values are applicable
only for non-SMPS mode where V15 is sourced externally".
• Updated descriptions and condition in following sections:
— Boot time, HSE firmware not installed
— Boot time, HSE firmware installed
— HSE firmware memory verification time examples
• In section "Recommended Decoupling Capacitors" updated variants for COUT V11.
• In section "V15 regulator (SMPS option) electrical specifications" added CBULK_SMPS.
• In section "V15 regulator (BJT option, NPN ballast transistor control) electrical specifications" added V15 input.
• In section "SAR ADC" updated paragraph "All below specs are applicable...". and added footnote to TUE as "Spec valid
if potential difference between VDD_HV_A.." and figure updated to show VDD_HV_A instead of VREFH.
• In LPCMP section changed ACMP0 to LPCMP0.
• In PLL added paragraph to mention Auxiliary PLL applicability and footnote updated to mention "Accumulated jitter
specification is not valid with SSCG".
• In PLL added CLKIN_VIL_EXTAL_BYPASS and CLKIN_VIH_EXTAL_BYPASS specifications.

S32K3xx Data Sheet, Rev. 10, 07/2024

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NXP Semiconductors
Revision history

Rev 7, Apr 2023

• Added section "Communication between two S32K388 devices".

• In section "Ethernet MII (100 Mbps)" updated specification for 10 and 100 Mbps.
• In section "Ethernet RGMII" added paragraph "The following timing specs are defined at the device".
• In section "MDIO timing specifications" updated MDC3 for GPIO[113]pad of S32K388.
• Added following QuadSPI modes for S32K388:
— QuadSPI Quad 3.3V SDR 103.33MHz
— QuadSPI Quad 3.3V SDR 125MHz
• In QuadSPI modes, mentioned the applicability to the devices in K3 family.
• In "Debug trace timing specifications" section added row for 125 MHz for S32K388.
• Updated "Thermal characteristics" to add information on Thermal design and characteristics.

Rev 6, Nov 2022

• Added S32K388 decoupling capacitor diagrams.

• In section "Power mode transition operating behavior" tMODE_STDBYEXIT time is added as 80 us.
• In "V15 regulator (SMPS option) electrical specifications" section changed V15 output supply from 1.51V to 1.5V.
• In "5.0V (4.5V - 5.5V) GPIO Output AC Specification"
— TR_TF_50_F with condition DSE=1, SRE=0, Capacitance=25pF changed from 0.9 to 1.9 ns.
— TR_TF_50_F with condition DSE=0, SRE=0, Capacitance=50pF changed from 5.3 to 6.0 ns.
— TR_TF_50_F with condition DSE=0, SRE=1, Capacitance=50pF changed from 7.7 to 9.0 ns.
— TR_TF_50_F with condition DSE=1, SRE=1, Capacitance=50pF changed from 5.1 to 6.5 ns.
• In "3.3V (2.97V - 3.63V) GPIO Output AC Specification"
— TR_TF_33_F with condition DSE=0, SRE=0, Capacitance=25pF changed from 4 to 4.5 ns.
— TR_TF_33_F with condition DSE=1, SRE=0, Capacitance=25pF changed from 2 to 2.5 ns.
— TR_TF_33_F with condition DSE=0, SRE=0, Capacitance=50pF changed from 7 to 8 ns.
• In section "Fast External Oscillator (FXOSC)" added EXTAL_SWING_PP and VSB specs and related footnote.

Rev 5.2, Oct 2022

• Added S32K310 and S32K388 where applicable.

• Updated "overview".
• In "features":
— Updated M7 support upto 300 MHz.
— Updated Ethernet instance from one to two.
— Added Support to AES accelerator(for K388 only)
— Removed I3C instances.
• Added S32K310 and S32K388 block diagram and updated others to remove I3C.

S32K3xx Data Sheet, Rev. 10, 07/2024

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NXP Semiconductors
Revision history

Rev 5.2, Oct 2022

• Updated "Feature comparison".

• Updated "Ordering information".
• In "Absolute maximum ratings":
— Added symbol "V15" as "Voltage sensing input" for S32K388 and changed max value to 2.75V for S32K358.
— Added symbol "V11" for S32K388.
• In "Voltage and current operating requirements":
— Added symbol "V15" as "Voltage sensing input" for S32K388 and updated conditions for V15 and V15_extended.
Also added a footnote to V15_extended as You must ensure that the junction temperature"...".
— Added symbol "V11" for S32K388.
— Updated link to download hardware design guidelines document.
• In section "Thermal operating characteristics" added sentence as "For S32K388, applications running at 125°C
Tamb.....".
• Added S32K388 power management diagram and added other variants to diagrams as applicable.
• In section "Power mode transition operating behavior, added condition for tMODE_STDBYEXIT_FAST as "FIRC ON
@48MHz in Standby mode".
• In section "Supply monitoring" added sentence as "Certain monitors are present on certain...".
• In section "Recommended Decoupling Capacitors" added COUT_V11 for S32K388 and updated decoupling capacitor
diagrams.
• Section "SMPS regulator electrical specifications" changed to "V15 regulator (SMPS option) electrical specifications" and
following changes done:
— Added paragraphs at the begining of table as:
◦ "Some devices (S32K358, S32K348, S32K338, and S32K328)...."
◦ "The table below describes the electrical parameters for the components needed to implement an SMPS...."
◦ Updated existing to include inductor "The chip hardware design guidelines document lists the
recommended...".
◦ Added figure, removed redundant sentence "The table below describes the electrical parameters.." and
updated part numbers.
— Added "External Schottky diode average forward current" as 2A.
— Added "External P-channel MOSFET threshold voltage" as 2V.
• Section "NPN Ballast Transistor Control Specification" renamed to "V15 regulator (BJT option, NPN ballast transistor
control) electrical specifications" and updated the following:
— added paragraph "Some devices (S32K358, S32K348, S32K338, S32K328, S32K344, S32K324, S32K314,
S32K342, S32K322, S32K341) support ...."
— Updated ballast circuit figure.
• Added section "V11 regulator (NMOS ballast transistor control) electrical specifications".
• In section "Supply currents":
— added template for S32K388.
— added values for S32K342.

S32K3xx Data Sheet, Rev. 10, 07/2024

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NXP Semiconductors
Revision history

Rev 5.2, Oct 2022

— added S32K310 along with S32K311.

• GMAC term is added along with EMAC in "Operating mode" section.
• Updated GPIO specs to clarify leakage specifications.
• In SAR ADC section, removed TBD from RS max specification.
• In section "SXOSC", Oscillator Analog circuit supply current max updated to 4 uA.
• In section "LPSPI", updated tV and tHO for S32K358 and a note is added as "15 and 20 Mbps is supported on LPSPI0
only.".
• In section "uSDHC SDR electrical specifications" relaxed tISU for 25 MHz and 400 KHz from 4.8 to 6.3 ns.
• Deleted I3C specifications
• Updated "Thermal characteristics"
• Added 48-pin LQFP package drawing number in "Obtaining package dimensions" section.
• Editorial updates.

Rev 4, April 2022

• Removed S32K312 from preliminary list from the title of the document and "Overview".
• In features on first page added MAPBGA289 to the package list and updated GPIO pins upto 235.
• Removed "NDA required" term from all block diagrams.
• In "Ordering information", added HDQFP-EP package suffix.
• In section "Absolute maximum ratings", and "Voltage and current operating requirements", added S32K341 variant to
the sentence "The VDD_HV_B and V15 voltage supply domains are only present....".
• In section “Voltage and current operation requirement”, the footnote attached to supply ramp rate is updated as “ The
MCU Supply ramp applicable to the MCU input/external supplies...".
• Updated capacitor symbol to non-polarity in following figures at V25 and V11:
— Power management system - S32K344, S32K324, S32K341, S32K314, S32K342, and S32K322.
— Power management system - S32K312, S32K311
• In "Power management system - S32K358" figure, updated connections to optional circuit with dashed lines for
PGATE_CTRL and VSS_DCDC.
• In section “SMPS regulator electrical specifications”, added a sentence “The chip hardware design guidelines
documents lists the recommended part numbers of PMOS & Schottky diode."
• In table "SMPS regulator electrical specifications" :
— The typ. value of "External coil inductance" changed from 5 to 4.7uH.
— Added “Schottky diode reverse voltage” with Min value 5.0 V.
— Added “Schottky diode forward current” with Min value 1.0 A.
• In section "SMPS regulator electrical specifications" changed "COUT_V15" to "COUT_V15_SMPS" to match it with
corresponding figure.
• In section "Recommended Decoupling Capacitors" changed "COUT_V15" to "COUT_V15_NPN" to match it with
corresponding figure.
• In section "Recommended Decoupling Capacitors", following footnotes updated:

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NXP Semiconductors
Revision history

Rev 4, April 2022

— Footnote attached to CDEC "Optionally, 1 nF capacitors can be added...".

— Footnote attached to CBULK "For devices where the VDD_HV_B domain is present, if the VDD_HV_B...".
— Added footnote to CBULK "These capacitors must be placed close to the source."
• In section "Recommended Decoupling Capacitors", updated and added decoupling capacitors diagrams.
• In section "NPN Ballast Transistor Control Specification" added specification for VDD_HV_NPN.
• Updated "Ballast circuit" figure under section " NPN Ballast Transistor Control Specification".
• Current IDD specs are updated for S32K12 for following :
— Table “STANDBY mode supply currents”
— Table “Low speed RUN mode supply currents”
— Table “RUN mode supply currents (peripherals disabled)”
— Table “Example RUN mode configuration supply current”
• In section “supply current”, Removed table “Recommended current limits in board design” and related sentence “The
power supplies for the voltage ...."
• In section “Power management”, added section ”Cyclic wake-up current” and removed table "Low-power, cyclic
operation mode" from supply currents.
• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)",with symbol "ILKG_33_S", the condition has
been changed from PTC0 to PTD0.
• In section "5.0V (4.5V - 5.5V) GPIO Output AC Specification":
— for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Min changed from "2.8" to "1.9".
— for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Max changed from "10.2" to "7.7".
— for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Min changed from "1.9" to "1.3".
— for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Max changed from "6.7" to "5.1".
— for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Min changed from "2.0" to "1.0".
— for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Max changed from "7.4" to "5.3".
— for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Min changed from "0.9" to "0.3".
— for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Max changed from "3.0" to "0.9".
— for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Min changed from "1.3" to "0.9".
— for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Max changed from "5.1" to "4.1".
— for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Min changed from "1.6" to "0.9".
— for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Max changed from "3.6" to "3.0".
— for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Min changed from "1.0" to "0.4".
— for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Max changed from "5.3" to "3.1".
— for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Min changed from "1.9" to "1.5".
— for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Max changed from "7.7" to "6.1".
• In section “SAR ADC“, the footnote attached to “ADC Total Unadjusted Error” is updated as “TUE spec for precision and
standard channels is based on 12-bit level resolution”.

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Revision history

Rev 4, April 2022

• In section "Supply Diagnosis", for Symbol "AN_ACC" and "AN_T_on" footnote added "These specs will have degraded
performan..."
• In section "Fast External Oscillator (FXOSC)", for Symbol "TFXOSC" description changed from "Fxosc start up time" to
"Fxosc start up time (ALC enabled)".
• In section "Fast External Oscillator (FXOSC)", removed the crystal part numbers and related information which includes
following sentences, "In crystal mode NX5032GA crystal .....", " In crystal mode NX8045GB crystal …" and updated
sentence "To ensure stable oscillations, FXOSC incorporates the feedback resistance internally.".
• In section "LPSPI", updated the sentence updated maximum output load of 50pF to 30pF.
• In section "LPSPI", footnote attached to "fperiph" is udated to mention clock name instead of frequency. "For LPSPI0
instance, max. peripheral...".
• In section "I3C Push-Pull Timing Parameters for SDR Mode", Symbol "tV" and tHI are deleted.
• Added section "Ethernet RGMII".
• In all QuadSPI modes updated trace length from 3 inches to 2 inches.
• Added "QuadSPI Octal 3.3V DDR 100MHz" mode.
• Deleted "QuadSPI Quad 3.3V DDR 80MHz" mode.
• In section "QuadSPI Octal 3.3V DDR 120MHz" :
— For symbol “tOD_DATA”, Max. value changed from “2.567” to “ 2.934”.
— For symbol “tOD_CS”, Min value has been changed from “3.015” to “3.016” and Max. value changed from “-1.33”
to “-0.766”.
— For symbol “tDVW”, Min value has been changed from “2.314” to “2.518”.
— For symbol “tIH_DQS”, Min value has been changed from “2.767” to “3.134”.
• uSDHC specifications are updated thoroughly.
• In "Thermal characteristics":
— Updated table header to include all variants.
— For S32K312 100-HDQFP updated RϴJA from 34.8 to 38 °C/W and RϴJT from 0.6 to 0.8 °C/W.
— For S32K3x4, 257MAPBGA updated RϴJA from 27 to 26.8 °C/W.
• Updated Legal information.

Rev 3, Oct 2021

• Datasheet classification is updated to "Technical data" for S32K344.

• In section "Supply currents" added values for 85C (typ and max) and updated 105 (max) and 125 (max) values for
S32K344.
• In front page features, added HDQFP172 with Exposed pad (EP) option and information on I3C.
• In section "Overview", added a note "S32K3x1, S32K3x2 and S32K3x8 specific information ....".
• In "Feature comparision" section added footnote to add information about HDQFP172 with Exposed pad (EP) package
for S32K3x8 devices.
• VDD_HV_SMPS is changed to VDD_DCDC throughout.
• In section "Absolute maximum ratings", footnote attached to "I_INJSUM_DC_ABS" is exteded to add information "See
application note AN4731 for...".

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Revision history

Rev 3, Oct 2021

• Figure "Power management system - S32K344, S32K324, S32K341, S32K314, S32K342, and S32K322." is updated to
add COUT_V15 capacitor.
• Figure "Power management system - S32K358" is updated to add COUT_V15 capacitor and optional circuit explained in
the notes.
• In section "SMPS regulator electrical specifications", COUT_V15 is added to "External bypass capacitor".
• Figure "Package decoupling capacitor pinout diagram" is updated to show HDQFP172-EP package.
• Table title "Current limit requirements for board design" is changed to "Recommended current limits in board design" and
added a note as "The power supplies for the voltage rails must be...".
• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)":
— for ILKG_33_S updated condition to update pins which has Analog Function Count=2/3
— for ILKG_33_M updated condition to update pins which has Analog Function Count=1
— added ILKG_33_M with condition "PTE8 and PTD6"
— udpdated ILKG_33, -120 nA (min) and 120 nA (max).
— updated condition of IOH_*, IOL_* to add < and > symbols.
— added IOHT specification.
— Updated sentence "I/O current specifications are...". and removed "RMS current values are given....".
• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)":
— for ILKG_50_S updated condition to update pins which has Analog Function Count=2/3
— for ILKG_50_M updated condition to update pins which has Analog Function Count=1
— added ILKG_50_M with condition "PTE8 and PTD6"
— udpdated ILKG_50, -150 nA (min) and 150 nA (max).
— updated condition of IOH_*, IOL_* to add < and > symbols.
— added IOHT specification.
— Updated sentence "I/O current specifications are...". and removed "RMS current values are given....".
• In section "5.0V (4.5V - 5.5V) GPIO Output AC Specification":
— for Symbol "TR_TF_50_S" with condition "Capacitance=25pF" Min changed from "TBD" to "5"
— for Symbol "TR_TF_50_S" with condition "Capacitance=25pF" Max changed from "TBD" to "21"
— for Symbol "TR_TF_50_S" with condition "Capacitance=50pF" Min changed from "TBD" to "10"
— for Symbol "TR_TF_50_S" with condition "Capacitance=50pF" Max changed from "TBD" to "31"
— for Symbol "TR_TF_50_SP" with condition "DSE=0, Capacitance=25pF" Min changed from "5" to "3.5"
— for Symbol "TR_TF_50_SP" with condition "DSE=1, Capacitance=25pF" Min changed from "2.4" to "1.2"
— for Symbol "TR_TF_50_SP" with condition "DSE=0, Capacitance=50pF" Min changed from "8.9" to "7.1"
— for Symbol "TR_TF_50_SP" with condition "DSE=1, Capacitance=50pF" Min changed from "4.1" to "3.4"
— for Symbol "TR_TF_50_M" with condition "DSE=0, SRE=0, Capacitance=25pF" Min changed from "2.5" to "1.8"
— for Symbol "TR_TF_50_M" with condition "DSE=0, SRE=1, Capacitance=25pF" Min changed from "3" to "2.5"
— for Symbol "TR_TF_50_M" with condition "DSE=1, SRE=0, Capacitance=25pF" Min changed from "1" to "0.8"

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Revision history

Rev 3, Oct 2021

— for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Max changed from "4.3" to "5.3"
— for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Max changed from "1.6" to "3.0"
• In section "3.3V (2.97V - 3.63V) GPIO Output AC Specification":
— for Symbol "TR_TF_33_S" with condition "Capacitance=25pF" Min changed from "TBD" to "6.5"
— for Symbol "TR_TF_33_S" with condition "Capacitance=25pF" Max changed from "TBD" to "28"
— for Symbol "TR_TF_33_S" with condition "Capacitance=50pF" Min changed from "TBD" to "11"
— for Symbol "TR_TF_33_S" with condition "Capacitance=50pF" Max changed from "TBD" to "43"
— for Symbol "TR_TF_33_SP" with condition "DSE=0, Capacitance=25pF" Min changed from "5" to "4"
— for Symbol "TR_TF_33_SP" with condition "DSE=1, Capacitance=25pF" Min changed from "2.4" to "2.0"
— for Symbol "TR_TF_33_M" with condition "DSE=0, SRE=0, Capacitance=25pF" Min changed from "3.2" to "2.2"
— for Symbol "TR_TF_33_M" with condition "DSE=0, SRE=1, Capacitance=25pF" Min changed from "3.8" to "3.0"
— for Symbol "TR_TF_33_M" with condition "DSE=1, SRE=0, Capacitance=25pF" Min changed from "1" to "0.8"
— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Min changed from "1.1" to "0.5"
— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Max changed from "7.0" to "4"
— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Min changed from "2.6" to "2.1"
— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Max changed from "11.0" to "9"
— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Min changed from "0.8" to "0.4"
— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Max changed from "3.4" to "2"
— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Min changed from "1.5" to "1.2"
— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Max changed from "7.8" to "6.4"
— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Min changed from "2.5" to "1.1"
— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Max changed from "10.8" to "7"
— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Min changed from "3.6" to "2.6"
— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Max changed from "15.0" to "11"
— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Min changed from "1.5" to "0.8"
— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Max changed from "5.5" to "4.2"
— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Min changed from "2.2" to "1.5"
— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Max changed from "10.0" to "7.8"
• In section "SAR ADC", added paragraph "All below specs are applicable when only one ADC instance is in operation .....
to determine the most appropriate settings for AVGS." and removed footnote from RS specification.
• In section "SAR ADC", added specifications for CP1, CP2 and RSW1 corresponding to all channels, shared channels
and precision channels. Also added the related figure.
• In section "PLL", removed some non-applicable footnotes.
• In section "LPSPI", added information before the table The Low Power Serial Peripheral Interface (LPSPI) provides a
synchronous serial bus with master....".
• In section "LPSPI0 20 MHz and 15 MHz Combinations", added note as "Trace length should not exceed 11 inches for
SCK pad when used in Master loopback mode."

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Revision history

Rev 3, Oct 2021

• Added "I3C" specifications.

• In section "Ethernet MII (100 Mbps)", for "RXCLK frequency" typ value moved to max.
• In section "Ethernet RMII", added paragraph "The following timing specs are defined at the device I/O pin and must
be .....I/O operating voltage ranges from 2.97 V to 3.63 V."
• In section "QuadSPI Quad 3.3V SDR 120MHz", for Symbol "tSDC" footnote added "For S32K342 100MQFP, tSDC spec
would be ..."
• In section "QuadSPI Quad 3.3V SDR 120MHz" added sentence "Program register value
QuadSPI_DLLCRA[SLV_FINE_OFFSET] to 4'b0001.".
• In section "QuadSPI Octal 3.3V DDR 120MHz", Symbol "tSCK" min is calrified, condition updated to External DQS and
"tSCK" with condition Internal Loopback is deleted.
• In section "QuadSPI Octal 3.3V DDR 120MHz", Symbol "tSDC" condition updated to External DQS and "tSDC" with
condition Internal Loopback is deleted..
• In section "QuadSPI Octal 3.3V DDR 120MHz", specifications tISU_PCS, tIH_PCS, tCK2CKmin and tCK2CKmax are
deleted.

Rev 2, Aug 2021

• Added section "Overview".

• In block diagrams:
— S32K311/S32K312/S32K314 removed "Scalable ARM M7 core in Lock step" and added "Single ARM M7 core".
— S32K322/S32K324 removed "Scalable ARM M7 core in Lock step" and added "Two independent ARM M7 cores".
• In "Absolute maximum ratings" and "Voltage and current operating requirements":
— Some general footnotes are moved to top of table
— VDD_HV_SMPS added footnotes
• In "Voltage and current operating requirements" for VREFH extended footnote "VREFH should always be equal to...".
• Updated title - Power management system - S32K344, S32K324, S32K341, S32K314, S32K342, and S32K322.
• In figure "Power management system - S32K358" updated double bond to triple bond.
• In section "Recommended Decoupling Capacitors" added COUT_V11 with typ as 1 uF.
• Added section "Power mode transition operating behaviors" and its subsections:
— Power mode transition operating behaviour
— Boot time, HSE firmware not installed
— Boot time, HSE firmware installed
— HSE firmware memory verification time examples
• Moved information from "Supply monitoring" to "Supply diagnosos" and attached it to "AN_ACC". The information is "If
V15 > VDD_HV_A +100mV then..."
• Updated figure "Package decoupling capacitor pinout diagram" to add 289 MapBGA
• In section "Glitch Filter", added sentence ".... WKPU pins and TRGMUX inputs 60-63.".
• Section "Flash memory program and erase specifications" updated thoroughly.
• In section "Flash memory module life specifications" removed footnotes 1 and 2.

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Revision history

Rev 2, Aug 2021

• In section "Data retention vs program/erase cycles" added sentence before related to figure "The spec window
represents qualified limits.".
• In section "Flash memory AC timing specifications":
— Updated register naming representation
— Added footnote to tdrcv min as " In extreme cases (1 block configurations)...".
— Max updated to "50 system clock periods" for taistop
• Ins ection "Flash memory read timing parameters" mantioned part numbers for each table as applicable.
• >In section "SAR ADC", for Symbol "fAD_CK" added new spec and max updated to 120.
• In section "FIRC", Symbol "IFIRC" is deleted.
• In section "SIRC", Symbol "Ivdda" with condition "On state" is deleted.
• In section "PLL", clarification added in condition column for jitter specifications.
• In section "Fast External Oscillator (FXOSC)", for Symbol "FREQ_BYPASS", "TRF_BYPASS" and
"CLKIN_DUTY_BYPASS" footnote added "For bypass mode applications, the EXTAL ...".
• In section "Fast External Oscillator (FXOSC)", for Symbol "TFXOSC" footnote added "The startup time specification is
valid ...".
• In section "Fast External Oscillator (FXOSC)", Symbol "IFXOSC" specs are merged into one and description and
condition updated.
• In section "Fast External Oscillator (FXOSC)", added paragraph "Drive level is a crystal specification and ....".
• In section "LPSPI", Symbol "tSPSCK" with condition "Slave_10Mbps" is added.
• In section "LPSPI", Symbol "tSPSCK" with condition "Master_10Mbps" is added.
• Updated title to mention LPSPI0 of "LPSPI0 20 MHz and 15 MHz Combinations", and updated header "20Mbps" to
"20Mbps (In loopback mode only)".
• In "I3C" section, added two sentences.
• Updated "QuadSPI" sections.
• Editorial updates.

Rev 2 Draft B, Mar 2021

• Updated "block diagrams" and "Feature comparison"

• Updated "Ordering information" to add 289 pagkage and removed one.
• In section "Absolute maximum ratings", Symbol "VDD_HV_SMPS" is added.
• In section "Absolute maximum ratings", for Symbol "I_INJPAD_DC_ABS" and "I_INJSUM_DC_ABS" footnote updated
"When input pad voltage levels are close ...".
• In section "Voltage and current operating requirements", Symbol "IINJSUM_DC_OP" and "IINJPAD_DC_OP" condition is
updated
• In section "Voltage and current operating requirements", Symbol "VDD_HV_SMPS" is added.
• In section "Voltage and current operating requirements", for Symbol "I_INJPAD_DC_ABS" and "I_INJSUM_DC_ABS"
footnote updated "When input pad voltage levels are close ...".
• In section "Power management":

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Revision history

Rev 2 Draft B, Mar 2021

— "Power management system - S32K344, S32K324, S32K314" figure updated.

— "Power management system - S32K312, S32K311" figure updated.
— "Power management system - S32K358" figure added.
• In section "Supply Monitoring", Symbol "HVD_V15" is added.
• In section "Supply Monitoring", for "LVD_VDD_HV_A", symbol and description updated.
• Added section "SMPS regulator electrical specifications"
• In section "NPN Ballast Transistor Control Specification", fig with title "Ballast circuit" is changed.
• In section "Supply currents" and "operating mode" tables are updated.
• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)", fig with title "Reference Load Diagram" is
changed.
• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)", footnote updated "A positive value is
leakage flowing into...".
• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)", Symbol "ILKG_50_S_PTE13" with condition "PMC
VRC_CTRL pin" is added.
• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)", footnote updated "A positive value is leakage flowing
into...".
• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)", fig with title "Reference Load Diagram" is changed.
• In section "Flash memory specification", added specs for 512KB and 2MB specifications.
• In table "Flash memory AC timing specifications", taistop max updated.
• Updated "Flash Read Wait State Settings"
• In section "Low Power Comparator (LPCMP)", updated IDLSS typ to 17uA.
• In section "Low Power Comparator (LPCMP)", updated INL and DNL.
• In section "Low Power Comparator (LPCMP)", updated paragraph "For devices where the VDD_HV_B domain is
present..."
• In "Low Power Comparator (LPCMP)" added hysterisis plots.
• In section "PLL", symbol "FPLL_out" description updated to add (PLL_PHIn_CLK)
• In section "PLL", "IPLL_V25" deleted.
• In section "PLL", updated jitter specifications.
• In section "FXOSC", updated paragraph "To improve the FXOSC jitter and duty cycle performance...".
• In section "SXOSC", updated description of "ISXOSC" to Oscillator Analog circuit supply current.
• In section "I2C", added paragraph "For supported baud rate ....."
• Added section "I3C".
• In section "FlexCAN characteristics", added paragraph "For supported baud rate ....."
• Added QuadSPI DDR electrical specifications for Octal and Quad.
• Added uSDHC specifications.
• Updated "Thermal characteristics" and "Obtaining package dimensions"

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Revision history

Rev 2 Draft A, Nov 2020

• Updated features to show maximum memory support up to 8 MB.

• Added information for S32K341.
• Updated "Block diagrams".
• Updated "Feature comparision"
• Updated "Thermal characterstics" to add data for S32K312 and S32K342.
• Added document number for 172-pin HDQFP package in section "Obtaining package dimensions"

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Notice: All referenced brands, product names, service names, and
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Export control — This document as well as the item(s) described herein may be
subject to export control regulations. Export might require a prior authorization NXP — wordmark and logo are trademarks of NXP B.V.
from competent authorities.

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NXP Semiconductors
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CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali,
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Bluetooth — the Bluetooth wordmark and logos are registered trademarks

owned by Bluetooth SIG, Inc. and any use of such marks by NXP
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eIQ — is a trademark of NXP B.V.

I2C-bus — logo is a trademark of NXP B.V.

NXP SECURE CONNECTIONS FOR A SMARTER WORLD — is a trademark

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SafeAssure — is a trademark of NXP B.V.

SafeAssure — logo is a trademark of NXP B.V.

SuperFlash — This product uses SuperFlash® technology. SuperFlash® is a

registered trademark of Silicon Storage Technology, Inc.

Synopsys & Designware — are registered trademarks of Synopsys, Inc.

Synopsys — Portions Copyright © 2018-2022 Synopsys, Inc. Used with

permission. All rights reserved.

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Please be aware that important notices concerning this document and the product(s) described
herein, have been included in section 'Legal information'.

© NXP B.V. 2024. All rights reserved.

For more information, please visit: https://www.nxp.com

Date of release: 07/2024

Document identifier: S32K3XX