Department of ECE

23EC2106R
PROCESSORS AND CONTROLLERS
CO - 4 & Part – 1

PIC & ARM MICROCONTROLLER

 ARM PROCESSORS
• ARM stands for “Advanced RISC Machine”
• First RISC microprocessor for commercial use
• Market-leader for low-power and cost-sensitive embedded
applications
 ARM PROCESSORS: History
• Developed at Acorn Computers Limited, of Cambridge,
England , between 1983 and 1985
• Problems with CISC:
• Slower memory parts
• Clock cycles per instruction
 ARM PROCESSORS: Applications
Applications of ARM Processors:
• Handheld devices
• High end applications involving complex computation
• Robotics
• Automation system
• Consumer electronics
 ARM PROCESSORS
➢ Fundamental characteristics of ARM:
• Load/store architecture
• An orthogonal instruction set.
• Mostly single-cycle execution.
• Enhanced power-saving design.
• 64 and 32-bit execution states for scalable high performance.
• Hardware virtualization support.

➢ Features of ARM:
• High performance, low power, small in size (ideal for embedded sys)
• Large Register File, Small instruction set, Load-Store instructions
• Fixed length instructions, Conditional execution of instructions
• High code density, most instructions executable in single cycle
• 32-bit in-line barrel shifter, built-in circuit for hardware debugging
• DSP enhanced instructions, Jazelle (Java byte code extn. 3rd state)
 ARM PROCESSORS
➢ ARM Nomenclature:
A R M {x}{ y}{ z} T D M I E J F S (Example: ARM7-TDMI-S)

ARM Advanced RISC Machine

x Series
y MMU ( No. of Memory Management units present)
z Cache Memory ( in terms of KB)
T Thumb instructions Support
D Debugger ( Debugging via JTAG interface)
M Multiplier
I In-Circuit Emulator (ICE) macrocell
E Enhanced Instructions for DSP related applications
J Jazelle instructions support for JAVA Codes execution
F Floating-point unit
S Synthesizable version

Eg. ARM7TDMI, ARM926EJ-S, ARM1136J(F)-S

 ARM PROCESSORS: RISC vs CISC
RISC: Reduced Instruction Set Computer CISC: Complex Instruction Set Computer
Architecture Architecture
Complex instruction may take one or more
Simple instruction taking one cycle.
clock cycles.
Large register file Few registers to store data.
Fewer instructions to access memory. More instructions to access memory
Few addressing modes. More addressing modes
Instruction Decoder is simple. Hardwired logic The instruction decoder is complex. A decoder
is used for the decoder. using ROM which consists microcode.
Supports pipelining. Does not support pipelining.
Fixed instruction size. Variable instruction size.
Core takes less chip area so more space for
More chip area is taken by core CPU.
cache, MMU.
Complexity in software. Compiler design is Complexity in Hardware. Emphasis is on
difficult hardware
Higher clock rates. So faster. Lower clock rates. So, comparatively slower.
Cache memory is absent or unified cache is
Cache memory is present.
present
 ARM PROCESSORS
➢ ARM & RISC Design Philosophy
RISC Processors:
• It is a design philosophy aimed at delivering simple but powerful instruction
set that executes within a single cycle at high clock speed.

• CISC and RISC differ in complexities of their instruction sets where CISC is
more complex than RISC.

• The smaller instruction set allows a designer to implement a hardwired

control unit which runs at a higher clock rate than its equivalent micro
sequenced control unit.
 ARM PROCESSORS
➢ RISC Philosophy: Four major rules
1. Instructions:Less no of instruction classes to provide simple operations
that can execute in a single cycle, each instruction is a fixed length to
allow the pipeline to fetch future instructions before decoding the
current instruction. (Unlike CISC)

2. Pipelines:The processing of instructions is broken down into smaller

units that can be executed in parallel by pipelines, instructions can be
decoded in one pipeline stage.

3. Registers:RISC machines have a large general-purpose register set & any

register can contain either data or an address.

4. Load-Store Architecture: Processor operates on data held in registers.

Separate load and store instructions: transfer data between the register
bank and external memory. Because memory accesses are costly.
 ARM PROCESSORS: Pipelining
➢ Pipeline Organization
• Increases speed – most instructions executed in single cycle
• Increased efficiency – Parallel Execution
• Versions:
– 3-stage Pipelining (ARM7TDMI and earlier)

– 5-stage Pipelining (ARMS, ARM9TDMI)

– 6-stage Pipelining (ARM10TDMI)

 ARM PROCESSORS: Pipelining
➢ 3-stage Pipelining Organization
• 3-stages of pipelining: Fetch – Decode – Execute
• Fetch: the instruction is fetched from memory.
• Decode: the fetched instruction is decoded.
• Execute: as per the decoded data, the operation is executed.

• Three-cycle latency, one instruction per cycle throughput.

• Advantages: Reduced Complexity, Lower Power Consumption, Reduced Latency.
i
n
s
t i Fetch Decode Execute
r
u i+1 Fetch Decode Execute
c
ti i+2 Fetch Decode Execute
o
n t t+1 t+2 t+3 t+4 cycle
 ARM PROCESSORS: Pipelining
➢ 5-stage Pipelining Organization
• 5-stages of pipelining: Fetch–Decode–Execute–Memory (LS1)–Memory (LS2)
• Fetch: the instruction is fetched from memory.
• Decode: the fetched instruction is decoded.
• Execute: as per the decoded data, the operation is executed.
• Memory (LS1): (Load) check any registers needed the data.
• Memory (LS2): (Store) store the result of the operation in to memory.

• Reduces work per cycle => allows higher clock frequency.

• Separates data and instruction memory => reduction of CPI (average number
of clock Cycles Per Instruction).
• Advantages: Increased Instruction Throughput, Better Resource Utilization,
Scalability, Lower Power Consumption, Reduced Latency.
 ARM PROCESSORS: Pipelining
➢ 5-stage Pipelining Organization

➢ Stages:
Fetch

Decode

Execute

Memory: LS1

Memory: LS2
 ARM PROCESSORS: Pipelining
➢ 6-stage Pipelining Organization
• 6-stages of pipelining: Fetch–Issue–Decode–Execute–Memory (LS1)–Memory (LS2)
• Fetch: the instruction is fetched from memory.
• Issue: check if the fetched instruction is ready to be decoded.
• Decode: the fetched instruction is decoded.
• Execute: as per the decoded data, the operation is executed.
• Memory (LS1): (Load) check any registers needed the data.
• Memory (LS2): (Store) store the result of the operation in to memory.

• Reduces work per cycle => allows even higher clock frequency than 5-stages
• Reduction of CPI (average number of clock Cycles Per Instruction)
 ARM PROCESSORS: Pipelining
➢ 6-stage Pipelining Organization

➢ Stages:
Fetch

Issue

Decode

Execute

Memory: LS1

Memory: LS2
 ARM PROCESSORS: Pipelining
➢ Pipeline Organization

3-stage Pipelining

5-stage Pipelining

6-stage Pipelining
 ARM7 PROCESSORS
➢ Fundamental characteristics of ARM7:
• All ARM instructions are 32-bit long & stored word aligned.
• ARM processor like all RISC processors is a Load Store architecture, Von-
Neuman Architecture (same program + data memory).
• ARM has two special instructions types for transferring data in & data out
of processor.
– Load Instruction = Copy data from memory to registers in the core.
(Registers in the processor core <----Memory)
– Store Instruction = Copy data from registers to memory
(Registers in processor core ----> Memory)
• There are no data processing instructions that are directly manipulate
data in memory (Hence Data processing is carried out only in registers).
• ARM core is a 32-bit bit processor most instructions treat the registers ad
holding signed or unsigned 32-bit value.
• Data Types: Word – 32-bit, Halfword – 16-bit, Byte – 8-bit
 ARM7 PROCESSORS
➢ Features of ARM7:
• ARM7 is a 32-bit processor.
• 3 stage Pipeline (Fetch, Decode, Execute)
• Operating frequency: 80 MHz
• Power Consumption: 0.06 mW/MHz.
• MIPS is 0.97
• Available in Von-Neumann Architecture.
• Supports both 16- & 32-bit instruction set.
 ARM ARCHITECTURE
• Typical RISC architecture:
• Large uniform register file
• Simple addressing modes
• Uniform and fixed-length instruction fields
• Load/store architecture (loading the registers from memory &
storing the register contents into memory)

• Enhancements:
• Each instruction controls the ALU and shifter
• Auto-increment and auto-decrement addressing modes
• Multiple Load/Store
• Conditional execution
 ARM ARCHITECTURE

 Current low-end ARM core for applications like digital

mobile phones
 TDMI
 T: Thumb, 16-bit instruction set
 D: on-chip Debug support, enabling the processor to halt in
response to a debug request
 M: enhanced Multiplier, yield a full 64-bit result, high performance
 I: Embedded in-circuit emulator (ICE) hardware

 Von Neumann architecture

 3-stage pipeline
ARM ARCHITECTURE
 ARM ARCHITECTURE
➢ Data Flow Model / ARM Core Architecture:

• When an instruction is decoded

inside the ARM core and how a
particular instruction is executed by
interacting with the internal registers
file and then send result out of the
registers.
 ARM PROCESSORS
➢ Data Sizes and Instruction Sets:
• The ARM is a 32-bit architecture.

• When used in relation to the ARM:

– Byte means 8 bits
– Half word means 16 bits (two bytes)
– Word means 32 bits (four bytes)

• Most ARM’s implement two instruction sets

– 32-bit ARM Instruction Set
– 16-bit Thumb Instruction Set

• Jazelle cores can also execute Java byte code

 ARM PROCESSORS

➢ Question Bank:
• ARM- features/fundamentals.
• ARM & RISC DESIGN PHILOSOPHY
• RISC VS CISC
• PIPELINE
• ARM – DATA FLOW MODEL
• Describe about ARM Processors & mention the Popular ARM Architectures in detail?
THANK YOU

N L PRASAD