Introduction to ARM Microcontrollers:

ARM (Acorn RISC Machine) microcontrollers are a family of embedded processors designed by
ARM Holdings. These processors are widely used in various electronic devices due to their
energy efficiency, performance, and versatility. ARM architecture has become a standard in the
microcontroller industry and is prevalent in applications ranging from consumer electronics to
industrial systems.

Features
​ Reduced Instruction Set Computing (RISC) Architecture:
● Description: ARM follows the RISC design philosophy, emphasizing a small and
efficient set of instructions.
● Advantages: This approach simplifies the instruction pipeline, leading to faster
execution, reduced power consumption, and a more streamlined architecture.
​ Scalability:
● Description: ARM architecture offers a scalable range of processors, from simple
8-bit and 16-bit microcontrollers to powerful 32-bit and 64-bit processors.
● Advantages: Developers can choose a processor that aligns with the complexity
and performance requirements of their specific applications.
​ Energy Efficiency:
● Description: ARM processors are known for their energy-efficient design, making
them suitable for battery-powered devices and applications with strict power
constraints.
● Advantages: Low power consumption enhances battery life and reduces heat
generation, critical factors for mobile devices and IoT applications.
​ Unified Architecture:
● Description: ARM provides a unified architecture, ensuring software
compatibility across different ARM-based processors.
● Advantages: Developers can reuse code and applications across various ARM
platforms, promoting consistency and ease of development.
​ Versatility:
 ● Description: ARM processors are used in a wide range of applications, including
mobile devices, consumer electronics, automotive systems, industrial automation,
and more.
● Advantages: The versatility of ARM architecture allows it to address diverse
market segments, and its adaptability supports a variety of peripherals and
features tailored to different applications.
​ Security Features:
● Description: Some ARM processors include built-in security features such as
TrustZone technology for creating secure and non-secure execution environments.
● Advantages: These features enhance the security of devices, protecting sensitive
data and enabling secure execution of applications.
​ Connectivity Options:
● Description: ARM-based microcontrollers often include various connectivity
options, such as USB, Ethernet, Wi-Fi, and Bluetooth.
● Advantages: This enables ARM processors to seamlessly integrate into connected
devices, IoT systems, and networked environments.
​ Real-time Operating System (RTOS) Support:
● Description: ARM architecture is well-supported by real-time operating systems,
facilitating the development of real-time and embedded applications.
● Advantages: RTOS support is crucial for applications with strict timing
requirements, such as automotive control systems and industrial automation.

Memory organization of ARM

1. Address Space:
a. ARM processors typically have a 32-bit or 64-bit address space, depending on the
architecture version. This provides a vast range of memory addresses that can be
accessed by the processor.
2. Memory Types:
a. ARM systems commonly have different types of memory, including RAM
(Random Access Memory) for data and stack, ROM (Read-Only Memory) for
 storing firmware and code that doesn't change, and various types of non-volatile
memory.
3. Little Endian:
a. ARM processors use a little-endian byte order, meaning the least significant byte
is stored at the lowest memory address. This is important to consider when
working with multi-byte data types.
9 84 58 74 28 99 05 26
2000 - 26
2001 - 05
2002 - 99
4. Memory Regions:
a. The memory space is typically divided into several regions, such as code, data,
stack, and peripherals. Each region serves a specific purpose and has specific
characteristics.
5. Code Memory:
a. The code memory region holds the program instructions. It is often implemented
using Flash memory or other non-volatile memory technologies. The CPU fetches
instructions from this region during program execution.
6. Data Memory:
a. The data memory region stores variables and data used by the program. It
includes both RAM (volatile) and ROM (non-volatile) data sections. Data
memory is further divided into sections such as the heap and the stack.
7. Stack:
a. The stack is a region in RAM used for managing function calls, local variables,
and storing return addresses. The stack grows and shrinks dynamically as
functions are called and return.
8. Heap:
a. The heap is an area in RAM used for dynamic memory allocation, typically
managed by functions like malloc and free. It is crucial for applications that need
to allocate memory at runtime.
9. Peripheral Memory:
 a. ARM-based systems often have memory-mapped peripherals, where the
addresses in the memory space correspond to the registers of various hardware
components, such as timers, GPIO (General Purpose Input/Output) ports, and
communication interfaces.
10. Virtual Memory:
a. Some ARM processors support virtual memory, allowing processes to have their
own isolated address space. This facilitates memory protection and enhances
security.

Advantages of ARM Processor :

● They are cheaper as compared to other processors.
● It consumes less power.
● Better battery life than other processors.
● It works faster because it performs one operation at a time.
● Users choose ARM processors because of availability and applications support.

Disadvantages of ARM Processor :

● You can not run windows on it very soon because it is not binary compatible with
x86.
● The speeds and memory bandwidths are limited in such cases because of ARM
processor’s clock frequencies.
● Debugging is difficult because of scheduling of instructions.
● The performance of these processors totally depend on execution so if programmer
does not execute it properly then it can take a long time to work properly.

Instruction Pipeline
The instruction pipeline in ARM architecture refers to the sequential stages that an instruction
passes through during its execution. The pipeline is designed to improve the overall throughput
and performance of the processor by allowing multiple instructions to be processed
simultaneously.
 Instruction Fetch (IF) Stage:
● In this stage, the processor fetches the next instruction from memory. The
program counter (PC) is used to determine the address of the instruction to be
fetched.
​ Instruction Decode (ID) Stage:
● The fetched instruction is decoded in this stage. The processor determines the
operation to be performed and identifies the operands. It may also calculate the
branch target address for branch instructions.
​ Execute (EX) Stage:
● The actual execution of arithmetic and logic operations takes place in this stage.
For memory access instructions, the effective address is calculated. Branch
instructions may also be resolved, and the next instruction address is determined.
​ Memory Access (MEM) Stage:
● If the instruction involves a memory access, such as a load or store operation, it is
performed in this stage. The effective address calculated in the execute stage is
used to access memory.
​ Write Back (WB) Stage:
● The result of the executed instruction is written back to the register file in this
stage. For instructions that don't produce a result (e.g., branch instructions), this
stage may be a no-operation.
1. Data Path:

● The data path is a critical component in the ARM microcontroller responsible for the
movement and manipulation of data within the processor. It includes key elements such
as:
● Registers: Storage locations for data, operands, and intermediate results.
● ALU (Arithmetic Logic Unit): Performs arithmetic and logic operations on data.
● Barrel Shifter: Facilitates shifting and rotating of the second operand by a
specified number of bits.
● Address Register and Incrementer: Manages addresses, holding either the
Program Counter (PC) address or operand address.

2. Decoder:

● The decoder is a component that interprets machine code instructions and generates
control signals to coordinate the operation of various elements in the microcontroller.
 ● Instruction Decoder: Translates machine code instructions into control signals that
guide the execution of the instruction.
● Control Signals: Signals that govern the actions of the data path components,
ALU, and other functional units.

3. Two Read Ports to Register Banks (A-Bus and B-Bus):

● ARM microcontrollers often feature multiple registers, and the A-Bus and B-Bus
represent two pathways for reading data from these register banks.
● Register Banks: Collections of registers that store operands and intermediate
values.
● A-Bus and B-Bus: Paths through which data is read from registers, facilitating
parallel data access.

4. One Write Port from ALU:

● After performing arithmetic or logic operations, the ALU generates a result that needs to
be stored back in the registers. This is accomplished through a write port.
● Write Port: Pathway through which the ALU writes the result back to the register
banks.

5. Barrel Shifter:

● The barrel shifter is a specialized component that allows for efficient shifting and rotating
of binary values.
● Shift/Rotation: The ability to move bits left or right, or perform circular rotations.
● Dynamic Shift Amount: The number of bits to shift can be determined
dynamically.

6. ALU (Arithmetic Logic Unit):

● The ALU is a fundamental unit that performs arithmetic and logic operations on data.
● Arithmetic Operations: Addition, subtraction, multiplication, and division.
● Logic Operations: AND, OR, XOR, and other bitwise operations.
● Result: The outcome of the ALU operation is often stored in a register.

7. Address Register and Address Incrementer:

● These components are crucial for managing addresses during the execution of
instructions.
● Address Register: Holds either the Program Counter (PC) address or operand
address.
 ● Address Incrementer: Increments the address value as needed during program
execution.

8. Data Register:

● The data register is used to hold data that is read from or written to memory.
● Read/Write Data: Holds the data being transferred between the processor and
memory.

9. Instruction Decoder:

● The instruction decoder interprets machine code instructions, generating control signals
to coordinate the actions of the data path and functional units.
● Control Signals: Signals that direct the flow of data and operations within the
microcontroller based on the executed instruction.

Addressing Modes of PIC microcontroller

​ Immediate Addressing Mode:

● Explanation: In immediate addressing mode, the operand is specified directly in
the instruction.
● Example: MOV R0, #5
● Explanation of Example: This instruction moves the immediate value 5 into
register R0.
​ Register Addressing Mode:
● Explanation: In register addressing mode, the operand is the content of a register.
● Example: ADD R1, R2, R3
● Explanation of Example: This instruction adds the contents of registers R2 and R3
and stores the result in register R1.
​ Register Indirect Addressing Mode:
● Explanation: The operand's address is stored in a register, and the actual data is
fetched from that memory location.
● Example: LDR R4, [R5]
● Explanation of Example: This instruction loads the data from the memory
location pointed to by the content of register R5 into register R4.
 ​ Indexed Addressing Mode:
● Explanation: The effective address is determined by adding a constant offset to
the contents of a register.
● Example: LDR R6, [R7, #8]
● Explanation of Example: This instruction stores the content of register R6 into the
memory location obtained by adding 8 to the content of register R7.
​ Base-Register Addressing Mode:
● Explanation: The effective address is determined by adding a constant offset to
the contents of a base register.
● Example: LDR R8, [SP, #12]
● Explanation of Example: This instruction loads the data from the memory
location obtained by adding 12 to the content of the Stack Pointer (SP) into
register R8.
​ Autoincrement/ Autodecrement Addressing Mode:
● Explanation: The register value is used as an address, and after the operation, the
register is automatically incremented or decremented.
● Example: LDMIA R9!, {R10, R11}
● Explanation of Example: This instruction loads the contents of memory locations
pointed to by the content of register R9 into registers R10 and R11, and then
increments the content of R9.
● Eg R9 = 5000 = 37
■ O/P R10 = 37, R11 = 37 and R9 = 5001

Programming Model of PIC

The programmer's model of ARM (Acorn RISC Machine) refers to the architectural features and
components that software developers interact with when writing programs for ARM-based
systems.

​ Registers:
 ● General-Purpose Registers (GPRs): ARM architecture typically has a set of 16 or
32 general-purpose registers (R0-R15). These registers are used for general data
manipulation, arithmetic, and logical operations.
● Program Counter (PC): The PC holds the address of the next instruction to be
fetched.
● Stack Pointer (SP): The SP points to the top of the stack, used for managing
subroutine calls, local variables, and return addresses.
● Link Register (LR): The LR stores the return address when a subroutine is called.
● Status Registers (CPSR and, on ARMv7-A and later, SPSR): The CPSR (Current
Program Status Register) contains flags indicating the current processor status,
including the condition codes, interrupt status, and execution mode.
​ Instruction Set:
● ARM processors have a rich instruction set supporting a variety of operations,
including arithmetic, logical, data movement, branch and control, and SIMD
(Single Instruction, Multiple Data) instructions.
● Thumb and Thumb-2 instructions provide a compressed form of the instruction
set, enhancing code density for embedded systems.
​ Modes of Operation:
● ARM processors can operate in different modes, each with its specific set of
privileges and resources. Common modes include User mode, Supervisor mode
(used by the operating system), IRQ (Interrupt Request) mode, and FIQ (Fast
Interrupt Request) mode.
● The mode is determined by the CPSR's mode bits, and the processor can switch
between modes based on events like interrupts or exceptions.
​ Exception Handling:
● ARM architecture supports exception handling for events such as interrupts,
resets, and undefined instructions.
● Exception vectors point to specific addresses where the processor jumps when an
exception occurs.
​ Pipeline and Execution Stages:
 ● ARM processors typically have an instruction pipeline with stages like Fetch,
Decode, Execute, Memory Access, and Write Back.
● Out-of-order execution, pipelining, and other architectural features contribute to
performance improvements.
​ Thumb and Thumb-2 Modes:
● ARM processors can operate in Thumb mode, using a 16-bit instruction encoding
for improved code density in memory-constrained environments.
● Thumb-2 mode extends Thumb, providing a mix of 16-bit and 32-bit instructions
for better performance without sacrificing code size.