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Mem2reg S

The report details the timing analysis of a specific path group in a digital circuit, focusing on the maximum delay and transition times. It highlights the data arrival and required times, indicating a slack of -0.1, which signifies a timing violation. The analysis includes various components and their respective delays, fanouts, and capacitances, ultimately revealing issues in meeting timing constraints.

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chia wei liu
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14 views3 pages

Mem2reg S

The report details the timing analysis of a specific path group in a digital circuit, focusing on the maximum delay and transition times. It highlights the data arrival and required times, indicating a slack of -0.1, which signifies a timing violation. The analysis includes various components and their respective delays, fanouts, and capacitances, ultimately revealing issues in meeting timing constraints.

Uploaded by

chia wei liu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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****************************************

Report : timing
-path full
-delay max_fall
-nets
-max_paths 1
-transition_time
Path Group: mem2reg
Path Type: max

Point
Fanout Cap Trans Incr Path

-----------------------------------------------------------------------------------
----------------------------------------------------------------------------
clock clk_cpu (rise edge)
0.0 0.0
clock network delay (propagated)
0.5 0.5
iram_blk_ixy_ram_xy_xram0/u_mem/CLKB
(mem_ts45nkkb2p22sassl512sa11p4_4096x16_cm8_bk8_cdtrue_bwe1_byes_rno)
0.0 0.0 0.5 r
iram_blk_ixy_ram_xy_xram0/u_mem/QB[10]
(mem_ts45nkkb2p22sassl512sa11p4_4096x16_cm8_bk8_cdtrue_bwe1_byes_rno) <-
0.0 0.7 c 1.3 f
iram_blk_ixy_ram_xy_xram0/QB[10] (net)
1 0.0 0.0 1.3 f
iram_blk_ixy_ram_xy_xram0/QB[10]
(mem_ts45nkkb2p22sassl512sa11p4_4096x16_cm8_bk8_cdtrue_bwe1_byes_rno_wrapper_0) <-
0.0 1.3 f
i_rams_xy_x1_rdata_a[10] (net)
0.0 0.0 1.3 f
icpu_coast_ixy_top/rams_xy_x1_rdata_a[10] (xy_top) <-
0.0 1.3 f
icpu_coast_ixy_top/rams_xy_x1_rdata_a[10] (net)
0.0 0.0 1.3 f
icpu_coast_ixy_top/icc_route_opt666/A (STL_INV_6) <-
0.0 0.0 @ 1.3 f
icpu_coast_ixy_top/icc_route_opt666/X (STL_INV_6) <-
0.0 0.0 @ 1.3 r
icpu_coast_ixy_top/n8124 (net)
1 0.0 0.0 1.3 r
icpu_coast_ixy_top/icc_route_opt665/A (STL_INV_10) <-
0.0 0.0 @ 1.3 r
icpu_coast_ixy_top/icc_route_opt665/X (STL_INV_10) <-
0.0 0.0 @ 1.3 f
icpu_coast_ixy_top/n4631 (net)
1 0.0 0.0 1.3 f
icpu_coast_ixy_top/icc_place370/A (STL_INV_16) <-
0.0 0.0 @ 1.3 f
icpu_coast_ixy_top/icc_place370/X (STL_INV_16) <-
0.0 0.0 @ 1.3 r
icpu_coast_ixy_top/n1742 (net)
1 0.0 0.0 1.3 r
icpu_coast_ixy_top/icc_place246/A (STL_INV_16) <-
0.0 0.0 @ 1.3 r
icpu_coast_ixy_top/icc_place246/X (STL_INV_16) <-
0.0 0.0 @ 1.3 f
icpu_coast_ixy_top/n11539 (net)
1 0.0 0.0 1.3 f
icpu_coast_ixy_top/icc_place4268/A (STL_INV_16) <-
0.0 0.0 @ 1.3 f
icpu_coast_ixy_top/icc_place4268/X (STL_INV_16) <-
0.0 0.0 @ 1.4 r
icpu_coast_ixy_top/n12600 (net)
1 0.0 0.0 1.4 r
icpu_coast_ixy_top/icc_place4287/A (STL_INV_16) <-
0.0 0.0 @ 1.4 r
icpu_coast_ixy_top/icc_place4287/X (STL_INV_16) <-
0.0 0.0 @ 1.4 f
icpu_coast_ixy_top/n12599 (net)
1 0.0 0.0 1.4 f
icpu_coast_ixy_top/icc_place221/A (STL_INV_16) <-
0.0 0.0 @ 1.4 f
icpu_coast_ixy_top/icc_place221/X (STL_INV_16) <-
0.0 0.0 @ 1.4 r
icpu_coast_ixy_top/n11538 (net)
1 0.0 0.0 1.4 r
icpu_coast_ixy_top/icc_place161/A (STL_INV_16) <-
0.0 0.0 @ 1.4 r
icpu_coast_ixy_top/icc_place161/X (STL_INV_16) <-
0.0 0.0 @ 1.4 f
icpu_coast_ixy_top/n8276 (net)
6 0.1 0.0 1.4 f
icpu_coast_ixy_top/U_pfu_0/mau_x1_data_a[10] (xy_pfu_0) <-
0.0 1.4 f
icpu_coast_ixy_top/U_pfu_0/mau_x1_data_a[10] (net)
0.1 0.0 1.4 f
icpu_coast_ixy_top/U_pfu_0/icc_clock396/B1 (STL_AO22_6) <-
0.0 0.0 @ 1.4 f
icpu_coast_ixy_top/U_pfu_0/icc_clock396/X (STL_AO22_6) <-
0.0 0.0 @ 1.5 f
icpu_coast_ixy_top/U_pfu_0/n1564 (net)
1 0.0 0.0 1.5 f
icpu_coast_ixy_top/U_pfu_0/icc_clock392/A (STL_INV_8) <-
0.0 0.0 @ 1.5 f
icpu_coast_ixy_top/U_pfu_0/icc_clock392/X (STL_INV_8) <-
0.0 0.0 @ 1.5 r
icpu_coast_ixy_top/U_pfu_0/n2958 (net)
1 0.0 0.0 1.5 r
icpu_coast_ixy_top/U_pfu_0/U1828/A1 (STL_ND2_T_8) <-
0.0 0.0 @ 1.5 r
icpu_coast_ixy_top/U_pfu_0/U1828/X (STL_ND2_T_8) <-
0.0 0.0 @ 1.5 f
icpu_coast_ixy_top/U_pfu_0/sel_data_a[10] (net)
1 0.0 0.0 1.5 f
icpu_coast_ixy_top/U_pfu_0/buff_data_0_r_reg_10_/D (STL_FSDPRBQO_4)
0.0 0.0 @ 1.5 f
data arrival time
1.5

clock clk_cpu (rise edge)


1.0 1.0
clock network delay (propagated)
0.5 1.5
clock reconvergence pessimism
0.0 1.5
inter-clock uncertainty
-0.1 1.4
icpu_coast_ixy_top/U_pfu_0/buff_data_0_r_reg_10_/CK (STL_FSDPRBQO_4)
0.0 1.4 r
library setup time
0.0 1.4
data required time
1.4

-----------------------------------------------------------------------------------
----------------------------------------------------------------------------
data required time
1.4
data arrival time
-1.5

-----------------------------------------------------------------------------------
----------------------------------------------------------------------------
slack (VIOLATED)
-0.1

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