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Published in IET Power Electronics
Received on 21st February 2013
Revised on 23rd August 2013
Accepted on 21st September 2013
doi: 10.1049/iet-pel.2013.0277

ISSN 1755-4535

Reconfiguration of semi-cascaded multilevel inverter

to improve systems performance parameters
Mohamad Reza Banaei, Mohammad Reza Jannati Oskuee, Hossein Khounjahan
Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran
E-mail: m.banaei@azaruniv.edu

Abstract: In this study, a new topology of semi-cascaded multilevel inverter is proposed which is a proper alternative to be used
in medium voltage applications. This structure consists of series connected sub-multilevel inverters blocks. The proposed
topology is based on the connections of several cell units in an appropriate scheme with the help of six power switches.
Compared to the traditional cascaded multilevel inverter, in suggested topology the number of switches, inverter cost and
installation area are reduced significantly. Also, in comparison with semi-cascaded multilevel inverter, the proposed inverter
works with lower total peak inverse voltage. The proposed inverter is able to be used as an asymmetrical inverter. To verify
the operation and good performance of the proposed inverter the simulation and experimental results are obtained.

1 Introduction Therefore, in practical implementation, reducing the number

of switches and relevant gate driver circuits are important.
Multilevel inverters are becoming popular for different A new topology of symmetrical and asymmetrical
applications since the initial prototype of multilevel inverter multilevel inverter is proposed in this paper, which is
was introduced by Nabae et al. [1]. In recent years, commonly suited for high number of steps associated with
multilevel inverters have been used for many a low number of power switches and relevant gate driver
implementations such as microgrid systems [2, 3], circuits. By considering the same number and value of DC
distributed generation [4, 5], power systems [6], sources in suggested inverter in [11] and proposed topology
adjustable-speed drives and static reactive power in this paper and also by supposing that one bidirectional
compensation [7, 8]. In recent years, different multilevel switch includes two unidirectional switches, the number of
inverter configurations have been developed and also switches in suggested inverter in [11] is much more than
several subtopologies and hybrid topologies have been that of proposed in this paper. The given simulation and
introduced [9–12]. The common configurations of experimental results confirm the validity of the proposed
multilevel inverters are cascaded inverter [13], diode inverter. The rest of this paper is organised as follows:
clamped inverter [14] and flying capacitor inverter [15]. Section 2 illustrates the proposed inverter configuration and
Each of the mentioned topologies above uses a different defines the methods to improve the inverters capability to
mechanism for providing the stepped voltage. be used as symmetrical and asymmetrical inverter. In
Semiconductor switches, diodes, capacitors and separated Section 3, the simulation and experimental results are
DC voltage sources are used in mentioned topologies [16]. detailed.
The performance of multilevel inverters is depending on the
modulation strategy. Since multilevel has been introduced, 2 Proposed topology
several switching methods are proposed which can be used
for various multilevel inverters to increase efficiency and In all popular multilevel inverter configurations, the required
improve the inverters output waveform [17–19]. number of components depends on the output voltage level. It
Advantages of multilevel inverters compared to two-level means that if the number of levels in output voltage increases,
inverter configuration are good waveform quality, low the number of components will be increased. The switches
electromagnetic compatibility, low switching losses, and related gate drive circuits are the main components in
high-voltage capability, lower voltage ratings of devices and structure of multilevel converters. With an increasing in the
low-speed ratings of switches [20–22]. Despite the components, the inverter circuit size and cost increase and
mentioned advantages, multilevel topologies have some the control scheme gets complicated. Fig. 1 defines the
disadvantages over the two-level inverters. The main proposed topology for asymmetric multilevel inverter.
disadvantage is the great number of power semiconductor The proposed topology is inspired of connection of several
switches needed. This problem increases circuit intricacy, cells in a proper way with the help of six switches which
which necessitates intricate control scheme that add to the provide different paths to generate the output waveform
expense and reduces the reliability of the inverter [10]. with all steps and with both positive and negative polarity

1106 IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1106–1112

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0277
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Fig. 1 Asymmetric proposed inverter

in output waveform. Each cell consists of two switches and In the proposed structure the currents of all switches are equal
one DC source. It also is needed to note that in the with the rated current of the load.
proposed topology V1 = Vdc. A provided output phase To provide a large number of output levels without
voltage is synthesised by individual voltages of DC sources increasing the number of DC sources, the proposed inverter
of each cell. Providing the value of every DC source in the can be utilised as an asymmetrical inverter which is a
output is obtainable with the proposed inverter. So, the substantial ability of the proposed. In the following, two
maximum voltage will be obtained in the output which is different methods to determine the value of DC voltage
the sum of the amplitude of DC sources. Equation (1) sources which are synthesised in the proposed topology are
represents the maximum output voltage (Vo,max) of specified. It is noted that by the given methods, every
proposed topology number of voltage step can be provided in output.

n
Vo, max = Vi (1) 2.1 First method
i=1
For symmetric inverter the magnitude of all DC voltage
sources value is equal to Vdc. When the symmetrical
where n is the number of DC sources. Every switch introduces
topology is considered, the switches related to one DC
an undesired voltage drop which is known as the power loss
source (e.g. V1) can be omitted. Fig. 2 shows the
on a power switch, and it takes while the switch is changed to
symmetrical proposed inverter. In the symmetric state, two
on state from off state and vice versa and also when
switches are eliminated from the proposed structure shown
conducting. As the above description, the power loss results
in Fig. 1.
from two main factors: conduction losses and switching
In the symmetric proposed inverter, the available
losses. In the asymmetric proposed topology, to provide
maximum voltage and the number of voltage levels (m) are
every voltage in the output, always (n + 2) switches must
given in the following expression
conduct. To calculate the maximum output voltage, the on
state voltage drop of a switch is assumed to be Vd, so (2)
evaluates the maximum output voltage when the power Vo, max = n × Vdc (4)
losses of all switches are mentioned
m = 2n + 1 (5)


n
Vo, max = Vi − (n + 2)Vd ; where n is the number of DC sources.
i=1

for asymmetric topology 2.2 Second method

(2)


n
Vo, max = Vi − (n + 1)Vd ; In asymmetric proposed multilevel inverter, DC voltage
i=1 sources of various cells are non-equal. Asymmetric inverter
provides an increased number of steps in output waveform
for symmetric topology for the same cells number than its symmetric counterpart.
In asymmetric scheme, the DC voltages of separated cells
One important problem in multilevel inverters is the voltage of Fig. 1 are chosen according to a geometric progression
ratings of switches. The total peak inverse voltage (PIV) of with a factor of p
switches is calculated by the following equation

Vi = pi−1 Vdc , where p = 2 and i = 1, 2 . . . n (6)
PIV = PIVSwitchj (3)
j=1 For n-DC sources, the maximum voltage and the number of

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Fig. 2 Prototype of symmetric proposed inverter

voltage steps are Table 2 Comparison of power component requirements for

conventional cascade inverter
1 − pn
Vo, max = V (7) Parameters First method Second method
1 − p dc
no. of DC sources n n
1 − pn no. of switches 4n 4n
m=2 +1 (8)
1−p no. of output levels 2n + 1 2
1 − pn
+1
1−p
1 − pn
maximum voltage nVdc V
Table 1 compares the power devices requirements of 1 − p dc
proposed multilevel inverter for both illustrated methods. 1 − pn
PIVpu 4n 4
1−p
2.3 Comparison between proposed inverter and no. of on state switches 2n 2n
conventional cascaded and semi-cascaded
multilevel inverters

This paper aims to propose a novel multilevel inverter which inverter can be employed only as a symmetric inverter. For
has the substantial improvements compared to the traditional the proposed, cascaded inverter and semi-cascaded inverters
cascaded multilevel inverters structure. The proposed inverter the number of elements is integer. Thus, if an integer
circuit requires lower power devices than the traditional number has not been result, the nearest integer number is
cascaded inverter. This sufficiency reduces the expense and certainly the appropriate solution.
facilitates the implementation which is the main property As the detailed in Tables 1 and 2, it obtains that to realise
must be noted in new designs. Tables 2 and 3 collate the the same level in output the required switches is lower for
component requirements of conventional cascaded inverter proposed inverter. Another essential parameter which it
and semi-cascaded multilevel inverter and its novel, plays a consequential role on overall inverter expense is the
respectively, according to the methods defined in Section voltage and current ratings of the power switches. It is
3. Semi-cascaded multilevel inverters, proposed in [23, 24],
can be used in both symmetrical and asymmetrical ones.
The novel semi-cascaded multilevel inverter, proposed in Table 3 Comparison of power component requirements for
[24], with reduction of two switches form semi-cascaded semi-cascade inverter structures

Parameters First method Second method

For novel For semi-cascaded
Table 1 Comparison of power component requirements for semi-cascaded inverter proposed
proposed multilevel inverter inverter in [23]
proposed in [24]
Parameters First method Second method
no. of DC sources n n
no. of DC sources n n no. of switches 2n + 2 2n + 4
no. of switches 2n + 2 2n + 4
1 − pn
1 − pn no. of output levels 2n + 1 2 +1
no. of output levels 2n + 1 m=2 +1 1−p
1−p
1−p n 1 − pn
maximum voltage nVdc V maximum voltage nVdc V
1 − p dc 1 − p dc
1 − pn 1 − pn
PIVpu 6n − 4 6 − 2p n−1 PIVpu 6n − 2 6
1−p 1−p
no. of on state switches n+1 n+1 no. of on state switches n+1 n+2

1108 IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1106–1112

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0277
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Fig. 3 Circuit diagram of nine-level multilevel inverter

apparent that the ratings of switches are applied in medium has the great importance which is the main parameter of
voltage applications are almost the same in value. So, the voltage reduction. With described in Tables 1 and 2, the
number of required power switches is more important than proposed topology has lower number of on state switches.
the rating of power semiconductor switches in medium The total power loss which is dependent on the on state
voltage applications. As clarified before the proposed switches is mentioned as a significant parameter to compare
inverter is appropriate for medium voltage applications. So, conventional cascaded and proposed inverter. The
for the advantages detailed for the proposed inverter and commonly two kinds of losses which are studied in
because of the nature of applications where the proposed inverters are conduction losses and switching losses.
inverter will be utilised, a bit increase in total PIV of Conduction losses are the result of the equivalent resistance
overall system with compared to traditional cascaded and the on state voltage drop of the switches. The switching
inverter can be neglected. As detailed before the number of losses are because of non-ideal operation of switches. The
on state switches which cause an undesired voltage drop number of on state switches for both traditional cascaded

Fig. 4 Output voltage and load current of the proposed symmetric nine-level inverter and harmonic spectra for output voltage
a Voltage and current waveform
b Harmonic content of the proposed nine-level inverter

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Table 4 Switching states of a symmetric nine-level proposed
inverter

Output voltage S1S2 S3 S4H1 H2 H3 H4 H5 H6

4Vdc (1010010101)
3Vdc (1010011100)
2Vdc (1001011100)
Vdc (0101011100)
0 (0101111000)
−Vdc (0101100011)
−2Vdc (1001100011)
−3Vdc (1001100011)
−4Vdc (1001101010)
Fig. 6 Visible hardware of the implemented of proposed nine-level
inverter

multilevel inverter and proposed inverter have been shown in

Tables 1 and 2. As compared to traditional multilevel inverter, 3 Simulation and experimental results
proposed inverter has less on state voltage drop and
conduction losses, because less number of switches is 3.1 Simulation results
turned on at any given time. The proposed inverter requires
reduced number of switches so the suggested topology To substantiate the good performance of the proposed
needs fewer related gate drive circuits. Each switch requires multilevel inverter, the simulation studies are carried out for
one gate driver. Therefore less components results a the two different methods illustrated before. The first case
reduction on the required installation area and causes that points to symmetrical multilevel inverter and the second
the cost of the inverter obtains lower. Also, proposed shows operation of asymmetrical topology. The simulation
inverter is compared with mentioned semi-cascaded inverter has done by MATLAB/Simulink software. The prototype of
structures, and it results that the proposed inverter works symmetric proposed configuration consists of four DC
with lower total PIV of system when the same output level sources and ten switches which produces a staircase
is obtained. waveform with the maximum 60 V. A series R–L with

Fig. 5 Output voltage and load current of the proposed asymmetric 31-level inverter and harmonic spectra for output voltage
a Voltage and current waveform
b Harmonic content of the proposed 31-level inverter

1110 IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1106–1112

& The Institution of Engineering and Technology 2014 doi: 10.1049/iet-pel.2013.0277
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Fig. 7 Experimental results of implemented nine-level inverter

a Output voltage (no load) (10 V/div)
b Output voltage and load resistant voltage (current), 2 × 10 V/div

magnitudes 20 Ω and 20 mH, respectively, are considered as Fig. 7 validates the practicability of proposed symmetric
load parameters (Fig. 3). multilevel inverter which can generate all voltage steps for
Fig. 4 illustrates the voltage, current waveform and the a test case nine-level symmetric inverter. For a test case,
harmonic content of symmetric inverter. nine-level symmetric inverter THD value is measured 13%
Table 4 defines the switching principle of symmetric a bit more than the simulation resulting.
nine-level proposed inverter.
In Fig. 4, the nine-level inverter with the equal DC sources 4 Conclusion
with the magnitude of 15 V is mentioned.
Fig. 5 shows the voltage, current waveform and the In this paper, a new topology is proposed for multilevel
harmonic content of asymmetric inverter. The 31-level inverter which can be used as a symmetric and asymmetric
proposed inverter with non-equal DC sources, ( p = 2), inverter. The proposed multilevel inverter uses reduced
where V1 = 4 V is considered in Fig. 5. number of devices. The proposed topology needs smaller
amount of switches and gate driver circuits. To implement
the inverter circuit, lower number of required devices results
3.2 Experimental results
the substantial reduction on total cost and make the control
A prototype of the proposed topology is implemented scheme easier. Two procedures have been presented for
according to one shown in Fig. 3. determination of the magnitudes of the DC voltage sources,
A single phase prototype of symmetric nine-level proposed too. A prototype of the proposed symmetric topology has
inverter is implemented (Fig. 6). The hardware of inverter been implemented and the experimental result corresponds
includes ten IRFP 460 MOSFETs driven by TLP very well with the simulation.
250Optocouplers. The value of DC voltage is 20 V, and
series resistive–inductive (R − L) load is 27 Ω–164.5 mH. 5 References
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1112 IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1106–1112

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