application UC1706
INFO UC2706
available
UC3706
Dual Output Driver
FEATURES DESCRIPTION
• Dual, 1.5A Totem Pole Outputs The UC1706 family of output drivers are made with a high-speed
Schottky process to interface between low-level control functions and
• 40nsec Rise and Fall into 1000pF
high-power switching devices - particularly power MOSFET's. These de-
• Parallel or Push-Pull Operation vices implement three generalized functions as outlined below.
• Single-Ended to Push-Pull Conversion First: They accept a single-ended, low-current digital input of either polar-
ity and process it to activate a pair of high-current, totem pole outputs
• High-Speed, Power MOSFET which can source or sink up to 1.5A each.
Compatible
Second: They provide an optional single-ended to push-pull conversion
• Low Cross-Conduction Current Spike through the use of an internal flip-flop driven by double-pulse-
• Analog, Latched Shutdown suppression logic. With the flip-flop disabled, the outputs work in parallel
for 3.0A capability.
• Internal Deadband Inhibit Circuit
Third: Protection functions are also included for pulse-by-pulse current
• Low Quiescent Current limiting, automatic deadband control, and thermal shutdown.
• 5 to 40V Operation These devices are available in a two-watt plastic “bat-wing” DIP for op-
eration over a 0°C to 70°C temperature range and, with reduced power,
• Thermal Shutdown Protection
in a hermetically sealed cerdip for -55°C to +125°C operation. Also avail-
• 16-Pin Dual-In-Line Package able in surface mount Q and L packages.
• 20-Pin Surface Mount Package TRUTH TABLE
INV N.I OUT OUT = INV and N.I.
H H L OUT = INV or N.I.
L H H
H L L
L L L
BLOCK DIAGRAM
SLUS200A - OCTOBER 1998 - REVISED APRIL 2001
UC1706
UC2706
UC3706
ABSOLUTE MAXIMUM RATINGS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N--Pkg . . . . . . . . . . . . . . . J--Pkg
Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . 40V . . . . . . . . . . . . . . . . . . 40V
Collector Supply Voltage, VC . . . . . . . . . . . . . . . . . . 40V . . . . . . . . . . . . . . . . . . 40V
Output Current (Each Output, Source or Sink)
Steady--State . . . . . . . . . . . . . . . . . . . . . . . . . . ±500mA. . . . . . . . . . . . . . . ±500mA
Peak Transient . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5A. . . . . . . . . . . . . . . . . ±1.0A
Capacitive Discharge Energy . . . . . . . . . . . . . . . 20µJ . . . . . . . . . . . . . . . . . . . 15µJ
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V . . . . . . . . . . . . . . . . . 5.5V
Analog Stop Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . VIN . . . . . . . . . . . . . . . . . . . . VIN
Power Dissipation at TA = 25°C (See Note) . . . . . . . 2W . . . . . . . . . . . . . . . . . . 1W
Power Dissipation at T (Leads/Case) = 25°C . . . . . . 5W . . . . . . . . . . . . . . . . . . . 2
(See Note)
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . --55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . --65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . . . 300°C
Note: All voltages are with respect to the four ground pins which must be connected
together. All currents are positive into, negative out of the specified trerminal. Consult
Packaging sections of the Databook for thermal limitations and considerations of package.
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (TOP VIEW) PLCC-20, LCC-20 (TOP VIEW)
J or N Package, DW Package Q, L Packages
N/C
B INHIBIT 1 16 A INHIBIT B INHIBIT A INHIBIT
INV INPUT INHIBIT REF
INV. INPUT 2 15 INHIBIT REF
3 2 1 20 19
N.I. INPUT 3 14 VIN N.I.INPUT 4 18 VIN
GROUND 5 17 GROUND
GROUND 4 13 GROUND
N/C 6 16 N/C
GROUND 5 12 GROUND GROUND 7 15 GROUND
A OUTPUT 6 11 B OUTPUT A OUTPUT 8 14 B OUTPUT
9 10 11 12 13
FLIP/FLOP 7 10 STOP NON-INV. FLIP/FLOP STOP INV.
VC STOP NON-INV.
VC 8 9 STOP INV.
N/C
Note: All four ground pins must be connected to a common
ground.
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for
the UC1706, –25°C to +85°C for the UC2706 and 0°C to +70°C for the UC3706; VIN = VC = 20V. TA = TJ.
PARAMETERS TEST CONDITIONS MIN TYP MAX UNITS
VIN Supply Current VIN = 40V 8 10 mA
VC Supply Current VC = 40V, Outputs Low 4 5 mA
VC Leakage Current VIN = 0, VC = 30V, No Load .05 0.1 mA
Digital Input Low Level 0.8 V
Digital Input High Level 2.2 V
Input Current VI = 0 –0.6 –1.0 mA
Input Leakage VI = 5V .05 0.1 mA
2
UC1706
UC2706
UC3706
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for
the UC1706, –25°C to +85°C for the UC2706 and 0°C to +70°C for the UC3706; VIN = VC = 20V. TA = TJ.
PARAMETERS TEST CONDITIONS MIN TYP MAX UNITS
Output High Sat., VC-VO IO = -50mA 2.0 V
Output Low Sat., VO IO = 50mA 0.4 V
IO = 500mA 2.5 V
Inhibit Threshold VREF = 0.5V 0.4 0.6 V
VREF = 3.5V 3.3 3.7 V
Inhibit Input Current VREF = 0 –10 –20 µA
Analog Threshold VCM = 0 to 15V, for the UC2706 and UC3706 100 130 160 mV
VCM = 0 to 15V, for the UC1706 80 130 160 mV
Input Bias Current VCM = 0 –10 –20 µA
Thermal Shutdown 155 °C
TYPICAL SWITCHING CHARACTERISTICS: VIN = VC = 20V, TA = 25°C. Delays measured to 10% output change.
PARAMETERS TEST CONDITIONS OUTPUT CL = UNITS
From Inv. Input to Output: open 1.0 2.2 nF
Rise Time Delay 110 130 140 ns
10% to 90% Rise 20 40 60 ns
Fall Time Delay 80 90 110 ns
90% to 10% Fall 25 30 50 ns
From N. I. Input to Output:
Rise Time Delay 120 130 140 ns
10% to 90% Rise 20 40 60 ns
Fall Time Delay 100 120 130 ns
90% to 10% Fall 25 30 50 ns
VC Cross-Conduction Current Spike Duration Output Rise 25 ns
Output Fall 0 ns
Inhibit Delay Inhibit Ref. = 1V, Inhibit Inv. = 0.5 to 1.5V 250 ns
Analog Shutdown Delay Stop Non-Inv. = 0V, Stop Inv. = 0 to 0.5V 180 ns
CIRCUIT DESCRIPTION
Outputs Digital Inputs
The totem-pole outputs have been designed to minimize With both an inverting and non-inverting input available,
cross-conduction current spikes while maximizing fast, either active-high or active-low signals may be accepted.
high-current rise and fall times. Current limiting can be These are true TTL compatible inputs—the threshold is
done externally either at the outputs or at the common approximately 1.2V with no hysteresis; and external pull-
VC pin. The output diodes included have slow recovery up resistors are not required.
and should be shunted with high-speed external diodes
Inhibit Circuit
when driving high-frequency inductive loads.
Although it may have other uses, this circuit is included to
Flip/Flop eliminate the need for deadband control when driving
Grounding pin 7 activates the internal flip-flop to alter- relatively slow bipolar power transistors. A diode from
nate the two outputs. With pin 7 open, the two outputs each inhibit input to the opposite power switch collector
operate simultaneously and can be paralleled for higher will keep one output from turning-on until the other has
current operation. Since the flip-flop is triggered by the turned-off. The threshold is determined by the voltage on
digital input, an off-time of at last 200nsec must be pro- pin 15 which can be set from 0.5 to 3.5V. When this cir-
vided to allow the flip/flop to change states. Note that the cuit is not used, ground pin 15 and leave 1 and 16 open.
circuit logic is configured such that the “OFF” state is de-
fined as the outputs low.
3
UC1706
UC2706
CIRCUIT DESCRIPTION (cont.) UC3706
Analog Shutdown use with a 7 to 40V supply; however, with some slight re-
This circuit is included to get a latched shutdown as close sponse time degradation, it can also be driven from 5V.
to the outputs as possible, from a time standpoint. With When VIN is low, the entire circuit is disabled and no cur-
an internal 130mV threshold, this comparator has a rent is drawn from VC. When combined with a UC1840
common-mode range from ground to (VIN – 3V). When PWM, the Driver Bias switch can be used to supply VIN to
not used, both inputs should be grounded. The time re- the UC1706. VIN switching should be fast as if VC is
quired for this circuit to latch is inversely proportional to high, undefined operation of the outputs may occur with
the amount of overdrive but reaches a minimum of VIN less than 5V.
180nsec. As with the flip-flop, an input off-time of at least Thermal Considerations
200nsec is required to reset the latch between pulses. Should the chip temperature reach approximately 155°C,
Supply Voltage a parallel, non--inverting input is activated driving both
With an internal 5V regulator, this circuit is optimized for outputs to the low state.
APPLICATIONS
D1, D2; UC3611 Schottky Diodes D1, D2; UC3611 Schottky Diodes
Power MOSFET Drive Circuit Power MOSFET Drive Circuit Using Negative Bias Voltage and
Level Shifting to Ground Referenced PWMs
D1, D2: UC3611 Schottky Diodes
Transformer Coupled MOSFET Drive Circuit Charge Pump Circuits
4
UC1706
UC2706
APPLICATIONS (cont'd) UC3706
D1, D2: UC3611 Schottky Diodes D1, D2: UC3611 Schottky Diodes
Power Bipolar Drive Circuit Transformer Coupled Push-Pull MOSFET Drive Circuit
UC3706 Converts Single Output PWMs to High Current Push-Pull Configuration
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
5
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
5962-89611012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 89611012A
5962-8961101EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8961101EA Samples
& Green
UC1706J ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 UC1706J Samples
& Green
UC1706J883B ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 UC1706J/883B Samples
& Green
UC1706L ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 UC1706L Samples
& Green
UC2706DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2706DW Samples
UC2706J ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -40 to 85 UC2706J Samples
& Green
UC2706N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 UC2706N Samples
UC3706DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3706DW Samples
UC3706DWTR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3706DW Samples
UC3706N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UC3706N Samples
UC3706NG4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UC3706N Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2024
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1706, UC2706, UC2706M, UC3706 :
• Catalog : UC3706, UC2706
• Military : UC2706M, UC1706
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Dec-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS
K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC3706DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Dec-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC3706DWTR SOIC DW 16 2000 356.0 356.0 35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Dec-2023
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-89611012A FK LCCC 20 55 506.98 12.06 2030 NA
UC1706L FK LCCC 20 55 506.98 12.06 2030 NA
UC2706DW DW SOIC 16 40 507 12.83 5080 6.6
UC2706N N PDIP 16 25 506 13.97 11230 4.32
UC3706DW DW SOIC 16 40 507 12.83 5080 6.6
UC3706N N PDIP 16 25 506 13.97 11230 4.32
UC3706NG4 N PDIP 16 25 506 13.97 11230 4.32
Pack Materials-Page 3
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