DR.
BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE
Winter Examination – 2022
Course: B. Tech. Branch : E&TC Semester :V
Subject Code & Name: [BTETPE504C] Digital System Design
Max Marks: 60 Date:08/02/2023 Duration: 3 Hours
Instructions to the Students:
1. All the questions are compulsory.
2. The level of question/expected answer as per OBE or the Course Outcome (CO) on
which the question is based is mentioned in ( ) in front of the question.
3. Use of non-programmable scientific calculators is allowed.
4. Assume suitable data wherever necessary and mention it clearly.
(Level/CO) Marks
Q. 1 Solve Any Two of the following. 12
A) Explain Structural modeling with an example. CO1 6
B) Explain the following Data objects in VHDL with Syntax. CO1 6
i. signals
ii. variables
iii. constants
iv. files
C) What are the sequential statements in VHDL and explain any four. CO2 6
Q.2 Solve Any Two of the following. 12
A) Write the difference between Data flow, Behavioral, and Structural CO2 6
modeling in VHDL.
B) What is the purpose of test bench in VHDL? Design Half-adder and CO2 6
write the test bench code.
C) State the difference between Procedures and Functions in VHDL. CO2 6
Q. 3 Solve Any Two of the following. 12
A) Design full-adder and write VHDL code using behavioral modeling. CO1 6
B) Design half subtractor and write VHDL code using dataflow modeling. CO1 6
C) Design 3: 8 decoders (Binary to Octal) and write VHDL code using CO1 6
structural modeling.
Q.4 Solve Any Two of the following. 12
A) Convert the following Mealy machine to the Moore machine. CO2 6
B) Reduce the following State diagram and prepare a State table for the CO2 6
reduced State diagram
C) State the difference between Mealy and Moore machine and convert the CO2 6
given Moore machine to Mealy machine.
Q. 5 Solve Any Two of the following. 12
A) Design 4-bit SISO Shift resister and write VHDL code. CO2 6
B) For the following asynchronous sequential circuits draw maps, CO2 6
transition table and state table.
C) Explain Metastability and Synchronizers. CO2 6
*** End ***
DR. BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE
Winter Examination – 2022
Course: B. Tech. Branch : Electronics Engineering Semester :V
Subject Code & Name: [BTEXOE505A] Digital System Design
Max Marks: 60 Date:14/02/2023 Duration: 3 Hours
Instructions to the Students:
1. All the questions are compulsory.
2. The level of question/expected answer as per OBE or the Course Outcome (CO) on
which the question is based is mentioned in ( ) in front of the question.
3. Use of non-programmable scientific calculators is allowed.
4. Assume suitable data wherever necessary and mention it clearly.
(CO) Marks
Q. 1 Solve Any Two of the following. 12
A) Explain any four data objects in VHDL with syntax. CO1 6
B) Explain Design flow for Digital System Design using VHDL. CO1 6
C) Explain the following sequential statements with Syntax: CO2 6
if statement
next
exit
return
loop
case
Q.2 Solve Any Two of the following. 12
A) What is test bench in VHDL and write test bench code for 4:1 MUX. CO2 6
B) Explain attributes in VHDL with example. CO2 6
C) Write a short note on configuration. CO2 6
Q. 3 Solve Any Two of the following. 12
A) Design Octal to Binary Encoder and write VHDL code. CO1 6
B) Design full subtractor and write VHDL code using dataflow modeling. CO1 6
C) Design 8 to 1 Multiplexer and write its VHDL code. CO1 6
Q.4 Solve Any Two of the following. 12
A) What is a state assignment in Finite State Machine? Draw the state CO2 6
diagram from the following state table.
Present Input x=0 Input x=1
state Next state Output Next state Output
q1 q1 0 q2 0
q2 q2 1 q3 0
q3 q2 0 q3 1
B) Reduce the following State diagram and prepare a State table for the CO2 6
reduced State diagram
C) Convert Mealy machine to Moore machine from the following diagram. CO2 6
Q. 5 Solve Any Two of the following. 12
A) Write a short note on place & route process. CO2 6
B) Write a short note on ROM. CO2 6
C) Write a short note on Programmable Logic Array (PLA). CO2 6
*** End ***
DR. BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE
Supplementary Summer-2023
Course: B. Tech. Branch :Electronics Engineering Semester : V
Subject Code & Name: Digital System Design (BTEXOE505A)
Max Marks: 60 Date:19/08/2023 Duration: 3 Hr.
Instructions to the Students:
1. All the questions are compulsory.
2. The level of question/expected answer as per OBE or the Course Outcome (CO) on
which the question is based is mentioned in ( ) in front of the question.
3. Use of non-programmable scientific calculators is allowed.
4. Assume suitable data wherever necessary and mention it clearly.
(Level/CO) Marks
Q. 1 Solve/Answer Any Two of the following. 12
A) What is VHDL? And what are its key features for hardware description? CO1 6
B) Compare CO1,CO2 6
i)concurrent and sequential statements in VHDL
ii) Data objects and signal drivers in VHDL,
C) Design an 8-to-1 multiplexer using combinational logic and write its VHDL code. CO1,CO2 6
Q.2 Solve/Answer Any Two of the following. 12
A) Explain Read-Only Memory (ROM), Programmable Logic Array (PLA), and CO3 6
Programmable Array Logic (PAL) devices
B) Design a 4-bit adder circuit using basic logic gates (AND, OR, XOR, etc.) and CO1,CO2 6
write VHDL code.
C) Design 4-bit SISO shift register and write VHDL code CO3 6
Q. 3 Solve/Answer Any Two of the following. 12
A) Explain the various data types in VHDL. CO4 6
B) Explain different modeling styles of VHDL with suitable examples CO1 6
C) Write a VHDL entity and Architecture for the following function. CO2,CO4 6
F(x) = (a + b) (c + d). Also draw the relevant logic diagram.
Q.4 Solve/Answer Any Two of the following. 12
A) Explain about Simulation and Synthesis processes in VHDL. CO4 6
B) Write a VHDL program for a 2 bit Magnitude Comparator using Data Flow model. CO2,CO3 6
C) What is VHDL ? And Explain the following with syntax in VHDL CO4 6
File, signal , Variable
Q. 5 Solve/Answer Any Two of the following. 12
A) Briefly explain the architecture of a Complex Programmable Logic Device CO4 6
B) Define FSM. Also Differentiate between Mealy and Moore machines in terms of CO3 6
their output generation and transition behavior
C) Design 3:8 decoder and write VHDL code using structural modeling CO1,CO2 6
*** End ***
