Course: VLSI design (EECE3051)
Unit-III: MOSFET Physical operation & V-I Characteristics
Y.V.Appa Rao
Assistant Professor
Department of EECE.
GITAM Institute of Technology (GIT)
Visakhapatnam – 530045
Email: vyempada@gitam.edu
Objectives
• To understand the essentials of various Integrated
Circuit (IC) Technologies, like NMOS, CMOS and
BiCMOS
• To familiarize with the role of MOS VLSI Technology
• To gain knowledge on the fabrication processes for
NMOS, CMOS and BiCMOS technologies
• To understand qualitatively the pros and cons of various
IC technologies (Power and delay performance metrics)
• To familiarize with the concepts of enhancement mode
MOSFET and depletion mode MOSFET
MOS Technology
• MOSFETs due to their excellent scalability are crucial for the
high-performance ICs
• The basic building block of TB memory chips, GHz
microprocessors, analog, and RF circuits
• Favorable due to their lower power dissipation
• MOSFETs are fundamentally potential-barrier controlled
devices,
o Potential barrier (Source-Channel) height is controlled by the
application of Gate voltage - Field Effect Transistor (FET)
Classification of MOSFETs
❑ Based on the charge induced in the channel (Inversion)
▪ N-channel MOSFET (NMOSFET)
▪ P-channel MOSFET (PMOSFET)
❖ CMOS Technology explores characteristics of both NMOS and PMOS
❑ Based on the characteristics of the channel
▪ Enhancement mode MOSFET (Induced channel)
▪ Depletion mode MOSFET (Implanted channel)
Different ways of representing a MOSFET
Physical structure
▪ Source and Drain diffusions are heavily doped, while the substrate is lightly
doped; They are of inverted type
▪ Source/Drain–Body PN junctions remain reverse biased
▪ MOSFET is a symmetrical structure
Enhancement mode MOSFET
❖Also known as Normally-off MOSFETs
❖The channel is induced by applying a gate voltage, which is larger
than the threshold voltage
❖ The induced channel (or inversion layer) consists of electrons for N-
channel MOSFETs, whereas for P-channel it consists of holes
❖The substrate (or body) usually Silicon, is lightly doped (Active
substrate) (Body terminal)
❖The poly-Si gate insulated from the substrate by a thin (Gate oxide)
layer of Silicon dioxide(Sio2)-hundreds of Angstrom (A0)
Physical structure of MOSFET
Enhancement mode MOSFET
MOS Device Structure (NMOS)
❑ Vertical dimensions:
▪ Oxide thickness
▪ Junction depth
❑ Lateral dimensions:
• Channel length (L)
• Channel width (W)
3-Dimentional View8
MOS Device Structure (NMOS)
2-Dimensional View
9
MOS Device Structure (PMOS)
2-Dimensional
10 View
CMOS Device Structure (N-well CMOS)
11
CMOS = NMOS + PMOS
Summary-Qualitative understanding
• Potential barrier-controlled devices: Source/Channel potential barrier
controlled by the gate
• Majority charge carrier-based device (or Unipolar device)
• Low power and Low voltage applications
• Enhancement and Depletion modes (Based on the channel conductivity)
• W.r.t gate control: Accumulation, Depletion, Inversion operating modes
• Operation: Source/Drain-body PN junctions are reverse biased
• Doping concentrations: Source/Drain diffusions are heavily doped, while
the body is lightly doped
Summary-Qualitative understanding
• CMOS fabrication process: N-Well CMOS, P-Well CMOS, Dual well
CMOS
• CMOS process: Oxide isolation (STI) and PN junction isolation
• Operation: Surface inversion takes place when the applied gate
voltage is larger than the threshold voltage
Physical operation of the
MOSFET
ENHANCEMENT MODE MOSFET
MOS Physical Operation (NMOS)
▪ Normally in a MOSFET,
the Source/Body and
Drain/Body PN junctions
are reverse biased
▪ Due to reverse bias, the
depletion region width
increases
▪ In thermal equilibrium the
built-in potential (or field)
is significant, causing zero
bias depletion width to be
considered
▪ As the substrate is lightly
doped, the depletion
With out Applying any Bias region extends more into
(EQUILLIBRIUM) the substrate
15
MOS Physical Operation (NMOS) Induced channel: When the
applied gate voltage is larger
than the threshold voltage, the
charge is induced at the MOS
surface, in this case it is n-
channel (or inversion layer of
electrons)
✓ The inversion charge is
supported by the depletion
charge (Depletion region)
✓ The total charge in the
substrate, Inversion layer
charge and depletion charge,
With VDS = 0 and VGS > Vtn is balanced by the charge on
16
the gate
MOS Physical Operation (NMOS) Smaller VDS :
▪ The channel is uniformly
concentrated from source
to drain (thin sheet of
charge)
▪ The force experienced by
charge carriers in the
channel is lesser, causing
them to move towards
the drain with a velocity
(drift) (due to VDS)
▪ As the source is
grounded, the channel
With VDS > 0 and VGS > Vtn potential increases from
17
0 to VDS
MOS Physical Operation (LINEAR REGION)
VDS vs ID Characteristics
Deep triode (Linear)
Region (VDS << (VGS-Vtn))
18 Voltage controlled resistor
MOS Physical Operation (Effect of VDS on the channel-
Lateral Electric field) As VDS increases:
▪ channel becomes
non-uniform
▪ Near the source end
the channel is
uniform, while at the
drain end the
channel thickness
decreases leading
to pinch-off
▪ pinch-off: VDS is
larger than the
overdrive voltage
With large VDS and VGS > Vtn 19 (VGS-Vtn)
MOS Physical Operation ( Pinch-off mode or
Saturation) ➢Uniform channel
thickness in deep
triode operation
➢Channel gets pinched
off with increasing
VDS
➢Lateral Electric field
(along the channel
due to VDS) causes
charge carriers in the
channel to move
towards the drain
Variation in channel resistivity (thickness) with VDS : Channel gets
pinched- off for larger drain voltage (VDS > (VGS-Vtn))
20
MOS Physical Operation (Linear & Saturation
regions)
VDS-ID
Characteristics
(given VGS)
21
MOS Physical Operation (contd.)
VDS vs IDS Characteristics
With Variable VGS
22
MOS Physical Operation (Summary)
Cutoff Region Triode Region
and
Saturation Region
and
Conditions for Different Operating Regions
vOV : Overdrive voltage = (VGS-Vtn)
23
Deriving MOS V-I Characteristics
Assumptions:
✓Long channel MOSFET
✓ Uniform doping
✓Gradual channel
approximation (GCA) :
The Electric field (or
potential gradient)
varies gradually along
the channel, compared
Channel shape in Deep Triode Region to the vertical direction
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MOS V-I Characteristics
Charge per Unit
Length
Electric Field per Unit
Length
Electron Drift
25
Velocity
MOS V-I Characteristics
Drain Current = Charge * Velocity
Drain to Source Conductance
26
MOS V-I Characteristics
Drain to Source Resistance
Drain Current in
Deep Triode Region
Aspect ratio
Process transconductance 27 Transconductance
MOS V-I Characteristics
28
Channel shape in Triode Region
MOS V-I Characteristics
29
MOS V-I Characteristics
Channel shape @ edge of Triode Region
30
MOS V-I Characteristics
31
MOS V-I Characteristics
Cutoff Region Triode Region
and
Saturation Region
and
32
MOS V-I Characteristics
MOSFET Large Signal Model
33
MOS V-I Characteristics
Channel Length Modulation
34
MOS V-I Characteristics
35
MOS V-I Characteristics
MOSFET Model with Channel Length Modulation
36
MOS V-I Characteristics
Output Resistance of MOSFET
37
MOS V-I Characteristics
38
MOS V-I Characteristics
Cutoff Region Triode (or Linear)Region
and
Saturation Region
and
39
MOSFET Circuit Symbols (NMOS)
Body terminal also acts like gate
40
MOSFET Circuit Symbols (PMOS)
41
MOS V-I Characteristics (PMOS)
42
MOS V-I Characteristics (PMOS)
43
MOS V-I Characteristics (PMOS)
Cutoff Region Triode Region
and
Saturation Region
and
44
MOS V-I Characteristics (Channel length modulation)
45
Applications of MOSFET
MOSFET as a switch
MOSFET as a Switch
47
MOS Small-Signal Models
48
MOS Small-Signal Models
49
