31 July 2023 1445 محرم14
ً َو َما أُوتِيت ُ ْم مِ نَ ْالع ِْل ِم إِ اَّل قَل
ِيل
Ain Shams University – Faculty of Engineering – ECE Dept. – Integrated Circuits Lab.
Dr. Hesham Omran
Analog IC Design – Cadence Tools
Lab 03
Cascode Amplifier
Intended Learning Objectives
In this lab you will:
• Learn how to generate and use the Sizing Assistant (SA) to size the transistors.
• Design and simulate a cascode amplifier.
• Design a bias circuit for the cascode amplifier.
• Investigate the gain, the bandwidth, and the GBW of a cascode amplifier.
NOTE: The values and charts reported below assume the provided 180 nm educational device model
and 1.8 V supply. Other models/technologies can be used by applying reasonable adjustments to the
values.
Part 1: Device Sizing Using SA
1) From the square law, we have
2𝐼𝐷 2
𝑔𝑚 = → 𝑉𝑜𝑣 =
𝑉𝑜𝑣 𝑔𝑚 /𝐼𝐷
2
For a real MOSFET, if we compute 𝑉𝑜𝑣 and 𝑔 they will not be equal. Let’s define a new parameter
𝑚 /𝐼𝐷
called V-star (𝑉 ∗ ) which is calculated from actual simulation data using the formula
2 2𝐼𝐷
𝑉∗ = ↔ 𝑔𝑚 = ∗
𝑔𝑚 /𝐼𝐷 𝑉
∗
The lower the 𝑉 the higher the 𝑔𝑚 , but the larger the area and the lower the speed. An often used
sweet-spot that provides good compromise between different trade-offs is 𝑉 ∗ = 200𝑚𝑉.
2) Although the 𝑉 ∗ is a nice parameter that is inspired by the square-law, it does not have an intuitive
or a physical meaning (it is not an actual voltage in the circuit). We actually defined 𝑉 ∗ in order to be
able to define a relation between the 𝑔𝑚 and 𝐼𝐷 . Thus, the real parameter that we should care about
is the 𝑔𝑚 over 𝐼𝐷 ratio (𝑔𝑚 /𝐼𝐷 ).
If the square-law is valid
2𝐼𝐷 𝑔𝑚 2
𝑔𝑚 = → =
𝑉𝑜𝑣 𝐼𝐷 𝑉𝑜𝑣
Using 𝑉 ∗
𝑔𝑚 2
= ∗
𝐼𝐷 𝑉
A small 𝑔𝑚 /𝐼𝐷 means large 𝑉𝑜𝑣 (biasing in strong inversion) and a large 𝑔𝑚 /𝐼𝐷 means small 𝑉𝑜𝑣
(biasing in weak inversion).
3) There are many good things about using the 𝑔𝑚 /𝐼𝐷 as a design knob:
a. The 𝑔𝑚 /𝐼𝐷 gives a direct relation between the most important MOSFET parameter (gm) and
the most valuable resource (ID). For example, a 𝑔𝑚 /𝐼𝐷 = 10 𝑆/𝐴 means you get 10 𝜇𝑆 of
𝑔𝑚 for every 1 𝜇𝐴 of bias current.
b. The 𝑔𝑚 /𝐼𝐷 is a normalized knob: it has a limited search range (typically from 5 to 25 S/A)
independent of the technology or the device type.
c. The 𝑔𝑚 /𝐼𝐷 is intuitive because it tells you directly about the inversion level (bias point) and
consequently all related trade-offs. For example, 𝑔𝑚 /𝐼𝐷 = 5 𝑆/𝐴 means strong inversion
(SI), 𝑔𝑚 /𝐼𝐷 = 15 𝑆/𝐴 means moderate inversion (MI), and 𝑔𝑚 /𝐼𝐷 = 25 𝑆/𝐴 means weak
inversion (WI).
d. The 𝑔𝑚 /𝐼𝐷 is an orthogonal knob: If we define the 𝑔𝑚 /𝐼𝐷 then we define the inversion level
(bias point). If you change 𝐼𝐷 or 𝐿 while keeping 𝑔𝑚 /𝐼𝐷 fixed, then the inversion level (bias
point) is kept fixed. The 𝑊 is treated as an output variable instead of being treated as an
e. The higher the 𝑔𝑚 /𝐼𝐷 (the lower the 𝑉 ∗) the higher the efficiency, but the larger the area
and the lower the speed. An often used sweet-spot that provides good compromise
between different trade-offs is 𝑔𝑚 /𝐼𝐷 = 10 𝑆/𝐴 (𝑉 ∗ = 200𝑚𝑉).
4) We want to design a common source (CS) amplifier that has ideal current source load with the
following parameters.
Parameter Value
𝑨𝒗 = 𝒈𝒎 𝒓𝒐 1 50
𝒈𝒎 /𝐼𝐷 10 𝑆/𝐴
Supply (𝑽𝑫𝑫) 1.8 𝑉
Quiescent (DC) output voltage 𝑉𝐷𝐷 /2 = 0.9 𝑉
Current consumption 20 𝜇𝐴
5) Since the square-law is not accurate, we cannot use it to calculate the sizing. Instead, we will use the
Sizing Assistant which is a powerful analog calculator that uses LUTs that are pre-generated from the
simulations. The sizing from SA is shown below. We will use the same sizing (𝐿 and 𝑊) to build a
cascode amplifier.
1
A relatively small L is necessary for Part 3 to make sure that Cgd is not negligible compared to Cgs.
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PART 2: Cascode for Gain
1. OP Analysis
1) Create a new schematic. Construct the circuit shown below. Use 𝐼𝐵 = 20𝜇𝐴. Use 𝐿 and 𝑊 as
selected in Part 1 for M0, M1, M2, and M4. Use the same 𝑊 for M3 but it will have different 𝐿 as will
be shown later. Use 𝐶𝐿 = 1𝑝𝐹.
2) We need to set the quiescent (DC) output voltage of the amplifiers to bias the transistors in
saturation. However, the output node is a high impedance node; thus, it is difficult to control its DC
voltage. As a workaround in simulation, we use a feedback loop and switches (analogLib >
sp1tswitch) with different settings in DC/AC to change the circuit connections in DC/AC simulations.
At DC, the transistor is diode connected and 𝑉𝐺𝑆 is set by the current source. At AC, the diode
connection is removed, and the input signal source is applied.
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3) For the cascode amplifier, we will choose 𝑉𝐵 to set 𝑉𝐷𝑆1 = 𝑉𝐷𝑆2 = 0.45 𝑉 as will be shown shortly.
4) To calculate 𝑉𝐵 we need to find 𝑉𝐺𝑆2 because 𝑉𝐵 = 𝑉𝐺𝑆2 + 𝑉𝐷𝑆1. Note that M2 experiences body
effect, so its 𝑉𝐺𝑆 will be higher than M0 and M1.
5) M3 and M4 are used to generate the cascode bias voltage. Note that M4 is always in saturation and
M3 is always in triode (why?). We need to find the 𝐿 of M3, so we set a sweep for M3 as shown
below.
6) Double click 𝑉𝐺𝑆 in the results table and find L that gives the required 𝑉𝐺𝑆 = 𝑉𝐵 = 𝑉𝐺𝑆2 + 𝑉𝐷𝑆1 .
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7) A dc shift (V1 and V3) is used to set the quiescent (DC) output voltage “roughly” to the required
value. Setting the output voltage to exactly 0.9 𝑉 is neither practical nor necessary. 𝑉𝐺𝑆0 and 𝑉𝐺𝑆1
can be retrieved from SA. Note that 𝑉𝐷𝑆0 = 0.9 𝑉 but 𝑉𝐷𝑆1 = 0.45 𝑉 so their 𝑉𝐺𝑆 will be slightly
different. This can be ignored as 𝑉𝐺𝑆 is always affected by 𝑉𝑇𝐻 variations.
8) Simulate the DC OP point of the above CS and cascode amplifiers. Report a snapshot showing info
balloons of the following parameters for M0 to M4 in addition to DC node voltages clearly
annotated.
ID
VGS
VDS
VTH
VDSAT
GM
GDS
GMB
CDB
CGD
CGS
CSB
Region
NOTE: “vdsat” is the minimum drain-source voltage required to bias the transistor in saturation. It
is equal to 𝑽𝒐𝒗 for a square-law device. It is also referred to as “vdss” (drain-source saturation
voltage) in some models. It is considered an ambiguous parameter because the transition from
triode to saturation is gradual, not abrupt.
9) Check that all transistors operate in saturation. Does any transistor operate in triode? Why?
10) Do all transistors have the same vth? Why?
11) What is the relation (≪, <, =, >, ≫) between gm and gds?
NOTE: use ≫ or ≪ if the difference is 10 times or more (one order of magnitude).
12) What is the relation (≪, <, =, >, ≫) between gm and gmb?
13) What is the relation (≪, <, =, >, ≫) between cgs and cgd?
14) What is the relation (≪, <, =, >, ≫) between csb and cdb?
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2. AC Analysis
1) Perform AC analysis (1Hz:10GHz, logarithmic, 10points/decade) to simulate gain and bandwidth.
2) Use calculator to create expressions for circuit parameters (DC gain, BW, GBW, and UGF) and export
them to adexl.
NOTE: Use the following expressions in the calculator and send them to adexl to quickly calculate
circuit parameters.
3) Report the Bode plot (magnitude) of CS and cascode appended on the same plot.
4) Using small signal parameters from OP simulation or SA, perform hand analysis to calculate DC gain,
BW, and GBW of both circuits.
5) Report a table comparing the DC gain, BW, UGF, and GBW of both circuits from simulation and hand
analysis.
6) Comment on the results.
PART 3 [Optional]: Cascode for BW
1. OP Analysis
1) Create a new schematic. Copy the old schematic instances to the new one. Make the following
modifications:
o Remove the feedback connection used to set the DC output voltage. The DC output voltage
is going to be set by the voltage drop on the resistance.
o Replace the current source with a resistor load 𝑅𝐷 .
o Create a diode connected transistor (M5) that is used to generate the DC bias input voltage
of the two amplifiers. This voltage is connected to the amplifier in DC only. In AC analysis,
the AC input source is connected.
o Set 𝐶𝐿 = 1𝑓𝐹 and the signal source resistance 𝑅𝑠𝑖𝑔 = 10𝑀Ω. This will make the dominant
pole the input pole instead of the output pole.
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2) Calculate 𝑅𝐷 analytically such that the voltage drop on it is ≈ 𝑉𝐷𝐷 /2 (the current remains roughly
the same as in Part 2 because we are using the VGS generated by M5). Note that the DC voltage of
the output node is set by the resistance (𝑅𝐷 ); thus, we don’t need a feedback loop as in the previous
case.
3) Simulate the DC OP point of the new CS and cascode amplifiers. Add info balloons and report a
snapshot showing the following parameters for M1, M2 and M3 in addition to DC node voltages
clearly annotated.
ID
VGS
VDS
VTH
VDSAT
GM
GDS
GMB
CDB
CGD
CGS
CSB
Region
4) Check that all transistors operate in saturation.
2. AC Analysis
1) Perform AC analysis (1Hz:10GHz, logarithmic, 10points/decade) to simulate gain and bandwidth.
2) Use calculator to create expressions for circuit parameters (DC gain, BW, GBW, and UGF) and export
them to adexl as in Part 2.
3) Report the Bode plot (magnitude) of CS and cascode appended on the same plot.
4) Using small signal parameters from OP simulation or SA, perform hand analysis to calculate DC gain,
BW, and GBW of both circuits.
5) Report a table comparing the DC gain, BW, UGF, and GBW of both circuits from simulation and hand
analysis. Comment on the results.
Lab Summary
In Part 1 you learned:
• How to find transistor sizing using the Sizing Assistant (SA).
• How to design common-source and cascode amplifiers.
In Part 2 you learned:
• How to do ac and DC simulations of a cascode amplifier with current-source load.
• How the gain of a cascode amplifier with current-source load changes with frequency.
• How to simulate the gain, the bandwidth and the GBW of a cascode amplifier with current-source
load.
In Part 3 you learned:
• How to do ac and DC simulations of a cascode amplifier with resistive load.
• How the gain of a cascode amplifier with resistive load changes with frequency.
• How to simulate the gain, the bandwidth and the GBW of a cascode amplifier with resistive load.
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Acknowledgements
Thanks to all who contributed to these labs. Special thanks to Dr. Sameh A. Ibrahim for reviewing
and editing the labs. If you find any errors or have suggestions concerning these labs, contact
Hesham.omran@eng.asu.edu.eg.
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