Chapter

Digital Voltmeters 5
INTRODUCTION 5.1
Digital voltmeters (DVMs) are measuring instruments that convert analog voltage
signals into a digital or numeric readout. This digital readout can be displayed on
the front panel and also used as an electrical digital output signal.
Any DVM is capable of measuring analog dc voltages. However, with
appropriate signal conditioners preceding the input of the DVM, quantities
such as ac voltages, ohms, dc and ac current, temperature, and pressure can be
measured. The common element in all these signal conditioners is the dc voltage,
which is proportional to the level of the unknown quantity being measured. This
dc output is then measured by the DVM.
DVMs have various features such as speed, automation operation and program-
ability. There are several varieties of DVM which differ in the following ways:
1. Number of digits
2. Number of measurements
3. Accuracy
4. Speed of reading
5. Digital output of several types.
The DVM displays ac and dc voltages as discrete numbers, rather than as a
pointer on a continuous scale as in an analog voltmeter. A numerical readout is
advantageous because it reduces human error, eliminates parallax error, increases
reading speed and often provides output in digital form suitable for further
processing and recording. With the development of IC modules, the size, power
requirements and cost of DVMs have been reduced, so that DVMs compete with
analog voltmeters in portability and size. Their outstanding qualities are their
operating and performance characteristics, as detailed below.
1. Input range from + 1.000 V to + 1000 V with automatic range selection
and overload indication
2. Absolute accuracy as high as ±0.005% of the reading
3. Resolution 1 part in million (1 mV reading can be read or measured on
1 V range)
4. Input resistance typically 10 MW, input capacitance 40 pF
5. Calibration internally from stabilised reference sources, independent of
measuring circuit
 Digital Voltmeters 129

6. Output in BCD form, for print output and further digital processing.
Optional features may include additional circuitry to measure current,
ohms and voltage ratio.

RAMP TECHNIQUE 5.2

The operating principle is to measure the time that a linear ramp takes to change
the input level to the ground level, or vice-versa. This time period is measured
with an electronic time-interval counter and the count is displayed as a number of
digits on an indicating tube or display. The operating principle and block diagram
of a ramp type DVM are shown in Figs 5.1 and 5.2.
Start of Ramp
+ 12 V
1st Coincidence Volt
oltage
age to
be measured
2nd Coincidence

Time
Volt
oltage
age
0 Ramp

- 12 V

Count Time Interval

t
Gate

Clock Pulses

Fig. 5.1 Voltage to time conversion

The ramp may be positive or negative; in this case a negative ramp has been
selected.
At the start of the measurement a ramp voltage is initiated (counter is reset
to 0 and sampled rate multivibrator gives a pulse which initiates the ramp
generator). The ramp voltage is continuously compared with the voltage that is
being measured. At the instant these two voltage become equal, a coincidence
circuit generates a pulse which opens a gate, i.e. the input comparator generates
a start pulse. The ramp continues until the second comparator circuit senses that
the ramp has reached zero value. The ground comparator compares the ramp
with ground. When the ramp voltage equals zero or reaches ground potential, the
ground comparator generates a stop pulse. The output pulse from this comparator
closes the gate. The time duration of the gate opening is proportional to the input
voltage value.
In the time interval between the start and stop pulses, the gate opens and the
oscillator circuit drives the counter. The magnitude of the count indicates the
130 Electronic Instrumentation

magnitude of the input voltage, which is displayed by the readout. Therefore,

the voltage is converted into time and the time count represents the magnitude
of the voltage. The sample rate multivibrator determines the rate of cycle of
measurement. A typical value is 5 measuring cycles per second, with an accuracy
of ± 0.005% of the reading. The sample rate circuit provides an initiating pulse
for the ramp generator to start its next ramp voltage. At the same time a reset
pulse is generated, which resets the counter to the zero state.
Any DVM has a fundamental cycle sequence which involves sampling,
displaying and reset sequences.
Test Input
Ranging Comparator
dc and
i/p Attenuator Start
Pulse

Oscillator Gate Counter

Stop Read
Ramp Pulse out
Generator
GND
Comparator
Sampled
Rate
M/V

Fig. 5.2 Block diagram of ramp type DVM

Advantages and Disadvantages The ramp technique circuit is easy to design and
its cost is low. Also, the output pulse can be transmitted over long feeder lines.
However, the single ramp requires excellent characteristics regarding linearity
of the ramp and time measurement. Large errors are possible when noise is
superimposed on the input signal. Input filters are usually required with this type
of converter.

DUAL SLOPE INTEGRATING TYPE DVM

(VOLTAGE TO TIME CONVERSION) 5.3
In ramp techniques, superimposed noise can cause large errors. In the dual ramp
technique, noise is averaged out by the positive and negative ramps using the
process of integration.

Principle of Dual Slope Type DVM As illustrated in Fig. 5.3, the input voltage
‘ei’ is integrated, with the slope of the integrator output proportional to the test
input voltage. After a fixed time, equal to t1, the input voltage is disconnected and
the integrator input is connected to a negative voltage –er. The integrator output
will have a negative slope which is constant and proportional to the magnitude
of the input voltage. The block diagram is given in Fig. 5.4.
 Digital Voltmeters 131

Slope Constant Slope

Proportional to ei Proportional to -er

Time
t1 t2
t2¢
t2¢¢

Fig. 5.3 Basic principle of dual slope type DVM

C
Comparator
(Zero detector)
Si R eo
ei ¶
- er
Sr eo

t1 t2 1 1
0 t 1 + t2 0
Gate Gate
Open Close
Counter
& Displays
Switch F/F 0000 Gate
Drive

Oscillator

Fig. 5.4 Block diagram of a dual slope type DVM

At the start a pulse resets the counter and the F/F output to logic level ‘0’. Si
is closed and Sr is open. The capacitor begins to charge. As soon as the integrator
output exceeds zero, the comparator output voltage changes state, which opens
the gate so that the oscillator clock pulses are fed to the counter. (When the ramp
voltage starts, the comparator goes to state 1, the gate opens and clock pulse
drives the counter.) When the counter reaches maximum count, i.e. the counter
is made to run for a time ‘t1’ in this case 9999, on the next clock pulse all digits
go to 0000 and the counter activates the F/F to logic level ‘1’. This activates
the switch drive, ei is disconnected and –er is connected to the integrator. The
integrator output will have a negative slope which is constant, i.e. integrator
output now decreases linearly to 0 volts. Comparator output state changes again
and locks the gate. The discharge time t2 is now proportional to the input voltage.
The counter indicates the count during time t2. When the negative slope of the
integrator reaches zero, the comparator switches to state 0 and the gate closes,
132 Electronic Instrumentation

i.e. the capacitor C is now discharged with a constant slope. As soon as the
comparator input (zero detector) finds that eo is zero, the counter is stopped. The
pulses counted by the counter thus have a direct relation with the input voltage.
During charging
t
1 e t
eo = - Ú
RC 0
ei dt = - i 1
RC
(5.1)
During discharging
t2
1 er t2
eo =
RC Ú - er dt = - R C (5.2)
0
Subtracting Eqs 5.2 from 5.1 we have
- er t2 Ê - ei t1 ˆ
eo - eo = -Á
RC Ë R C ˜¯
- er t2 Ê - ei t1 ˆ
0= -Á
RC Ë R C ˜¯
er t2 ei t1
fi =
RC RC
t2
\ ei = er (5.3)
t1
If the oscillator period equals T and the digital counter indicates n1 and n2
counts respectively,
n2 T n
ei = er i.e. ei = 2 er
\ n1 T n1
er
Now, n1 and er are constants. Let K1 = . Then ei = K1 n2 (5.4)
n1
From Eq. 5.3 it is evident that the accuracy of the measured voltage is
independent of the integrator time constant. The times t1 and t2 are measured by
the count of the clock given by the numbers n1 and n2 respectively. The clock
oscillator period equals T and if n1 and er are constants, then Eq. 5.4 indicates
that the accuracy of the method is also independent of the oscillator frequency.
The dual slope technique has excellent noise rejection because noise and
superimposed ac are averaged out in the process of integration. The speed and
accuracy are readily varied according to specific requirements; also an accuracy
of ± 0.05% in 100 ms is available.

INTEGRATING TYPE DVM (VOLTAGE TO FREQUENCY

CONVERSION) 5.4
The principle of operation of an integrating type DVM is illustrated in Fig. 5.5.
 Digital Voltmeters 133

A constant input voltage is integrated Slope 2

eo Slope 1 Slope 3
and the slope of the output ramp is er
proportional to the input voltage. When
the output reaches a certain value, it
is discharged to 0 and another cycle
begins. The frequency of the output Time
waveform is propor-tional to the input
voltage. The block diagram is illustrated Fig. 5.5 Voltage to frequency conversion
in Fig. 5.6.
C

R1 eo Comparator
ei
Ú Digital
Freq.
Meter
er
R2

Pulse
Generator

Fig. 5.6 Block diagram of an integrating type DVM

The input voltage produces a charging current, ei/R1, that charges the capacitor
‘C’ to the reference voltage er. When er is reached, the comparator changes state,
so as to trigger the precision pulse generator. The pulse generator produces
a pulse of precision charge content that rapidly discharges the capacitor. The
rate of charging and discharging produces a signal frequency that is directly
proportional to ei.

Waveforms er
at
Output of
the Integrator
Time
t1 t2 (Along X-axis)

At Pulse
Output of the
Pulse Generator
Fig. 5.7

The voltage-frequency conversion can be considered to be a dual slope

method, as shown in Fig. 5.7.
Referring to Eq. 5.3 we have
e t
ei = r 2
t1
134 Electronic Instrumentation

But in this case er and t2 are constants.

Let K2 = er t2
Ê 1ˆ
\ ei = K 2 Á ˜ = K 2 ( f 0 )
Ë t1 ¯
The output frequency is proportional to the input voltage ei. This DVM has
the disadvantage that it requires excellent characteristics in linearity of the ramp.
The ac noise and supply noise are averaged out.

Example 5.1 An integrator contains a 100 kW and 1 mF capacitor. If the

voltage applied to the integrator input is 1 V, what voltage will be present at
the output of the integrator after 1 s.

Solution Using the equation

ei ¥ t1 1¥1s 1
eo = = = = 10 V
RC 100 k ¥ 1 mF 0.1

Example 5.2 Now if a reference voltage is applied to the integrator of the

above example at time t1 is 5 V in amplitude, what is the time interval of t2?

Solution Using the equation

ei ¥ t1 er ¥ t2
=
RC RC
ei 1¥1
Therefore, t2 = ¥ t1 ; t2 = = 0.2 s
er 5

Example 5.3 An integrator consists of a 100 kW and 2 mF capacitor. If the

applied voltage is 2V, what will be the output of the integrator after 2 seconds?

Solution Given, R = 100 kW , C = 2 mF, e1 = 2 V and t1 = 2 s

Using the equation,
e1 ¥ t1 2V ¥ 2s 4 4 ¥ 103 4000
e0 = = = = = = 20 V
R ¥ C 100 k ¥ 2 mF 200 ¥ 103 ¥ 10 -6 200 200

Example 5.4 Now if a reference voltage of 10 V is applied to the integrator

of the above example (Ex 5.3) at time t1, what is the time interval of t2?

Solution Given reference voltage 10 V.

e1 ¥ t1 e2 ¥ t2
=
R¥C R¥C