MP2499M

36V, 3A Max, High-Efficiency,

Synchronous, Step-Down Converter
with Output Line Drop Compensation

DESCRIPTION FEATURES
The MP2499M is a synchronous, rectified, step-  Wide 5V to 36V Continuous Operating Input
down, switch-mode converter with built-in Range
power MOSFETs. The MP2499M offers a very  85mΩ/55mΩ Low RDS(ON) Internal Power
compact solution that achieves a maximum of MOSFETs
3A of continuous output current with built-in,  High-Efficiency Synchronous Mode
output, line drop compensation. Operation
The MP2499M has synchronous mode  Default 270kHz Switching Frequency
operation for high efficiency over the output  Synchronizes to a 200kHz to 2.4MHz
current load range. Current-mode operation External Clock
provides fast transient response and eases loop  Internal Soft Start
stabilization.  Output Line Drop Compensation
 Accurate Continuous Output Current Limit
Full protection features include over-current
with External Resistor
protection (OCP) and thermal shutdown.
 Over-Current Protection (OCP) and Hiccup
The MP2499M requires a minimal number of  Thermal Shutdown
readily available, standard, external  Output Adjustable from 0.8V
components and is available in a space-saving  Available in a QFN-13 (2.5mmx3mm)
QFN-13 (2.5mmx3mm) package. Package
APPLICATIONS
 USB Dedicated Charging Ports (DCP)
 Automotive Cigarette Lighter Adapters
 USB Chargers
 USB PD Applications
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.

TYPICAL APPLICATION

R4
VIN 12V 20Ω
IN BST
C1
C4 L1
22μF
0.1μF 11μH
EN/SYNC MP2499M
SW
EN/SYNC +
C2 C2A
R1 100μF 1μF
VCC 82.5kΩ
FB VOUT
C3 5V/2.4A
0.1μF R2
AGND 15.4kΩ

PGND ISENSE
R3
40mΩ

MP2499M Rev 1.0 www.MonolithicPower.com 1

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

ORDERING INFORMATION
Part Number* Package Top Marking
MP2499MGQB QFN-13 (2.5mmx3mm) See Below
* For Tape & Reel, add suffix –Z (e.g. MP2499MGQB–Z)

TOP MARKING

ART: Product code of MP2499MGQB

Y: Year code
WW: Week code
LLL: Lot number

PACKAGE REFERENCE
TOP VIEW
PGND PGND PGND BST

13 12 11 10

9 SW
IN 1
8 AGND
IN 2
7 VCC

3 4 5 6

NC ISENSE EN/ FB
SYNC

QFN-13 (2.5mmx3mm)

MP2499M Rev 1.0 www.MonolithicPower.com 2

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) θJA θJC

VIN ................................................... -0.3V to 40V QFN-13 (2.5mmx3mm) .......... 60 ....... 13 ... °C/W
VSW .................................... -0.3V (-5V for <10ns)
NOTES:
to 41V (43V for <10ns) 1) Absolute maximum ratings are rated under room temperature
VBST ...................................................... VSW + 6V unless otherwise noted. Exceeding these ratings may
All other pins ................................ -0.3V to 6V (2) damage the device.
2) For details on EN/SYNC’s ABS max rating, please refer to the
Continuous power dissipation (TA = +25°C) (3) Enable/SYNC Control section on page 12.
3) The maximum allowable power dissipation is a function of the
QFN-13 (2.5mmx3mm) ............................ 2.08W maximum junction temperature TJ (MAX), the junction-to-
Junction temperature ................................150°C ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
Lead temperature .....................................260°C any ambient temperature is calculated by PD (MAX) = (TJ
Storage temperature .................. -65°C to 150°C (MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
Recommended Operating Conditions the regulator to go into thermal shutdown. Internal thermal
Continuous supply voltage (VIN) .......... 5V to 36V shutdown circuitry protects the device from permanent
damage.
Output voltage (VOUT) ............. 0.8V to DMAX x VIN 4) Measured on JESD51-7, 4-layer PCB.
Operating junction temp. (TJ). .. -40°C to +125°C

MP2499M Rev 1.0 www.MonolithicPower.com 3

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C (5), unless otherwise noted. Typical values are at TJ = +25°C.
Parameter Symbol Condition Min Typ Max Units
Supply current (shutdown) ISHDN VEN = 0V 10 μA
Supply current (quiescent) IQ VEN = 2V, VFB = 1V 0.7 0.9 mA
HS switch on resistance RON_HS VBST-SW = 5V 85 150 mΩ
LS switch on resistance RON_LS VCC = 5V 55 105 mΩ
Switch leakage ILKG_SW VEN = 0V, VSW = 12V 1 μA
Current limit ILIMIT Under 40% duty cycle 4 6 8 A
Oscillator frequency fSW VFB = 750mV 200 270 340 kHz
VFB < 240mV, and OC
Foldback frequency fFB 70 kHz
(VCOMP is high)
Maximum duty cycle (6) DMAX VFB = 750mV, 250kHz 97 %
(6)
Minimum on time tON_MIN 70 ns
Sync frequency range fSYNC 0.2 2.4 MHz
ISENSE reference voltage VISENSE 94 118 142 mV
Line drop compensation IO = 2.4A, RSENSE = 40mΩ,
ISINK 4 6 8 μA
current TJ = 25°C
TJ = 25°C 780 792 804
Feedback voltage VFB mV
TJ = -40°C to 85°C 776 792 808
Feedback current IFB VFB = 820mV 10 100 nA
EN/SYNC rising threshold VEN_RISING 1.15 1.4 1.65 V
EN/SYNC falling threshold VEN_FALLING 1.05 1.25 1.45 V
EN/SYNC threshold hysteresis VEN_HYS 150 mV
VIN under-voltage lockout
INUVRISING 4.2 4.5 4.8 V
threshold rising
VIN under-voltage lockout
INUVFALLING 4 4.3 4.6 V
threshold-falling
VIN under-voltage lockout
INUVHYS 200 mV
threshold hysteresis
VCC regulator VCC ICC = 0mA 4.6 4.9 5.2 V
VCC load regulation ICC = 5mA 1.5 4 %
Soft-start period tSS VOUT from 10% to 90% 1.6 ms
(6)
Thermal shutdown 170 °C
Thermal hysteresis (6) 30 °C
NOTES:
5) Not tested in production. Guaranteed by over-temperature correlation.
6) Guaranteed by design and engineering sample characterization.

MP2499M Rev 1.0 www.MonolithicPower.com 4

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 12V, VOUT = 5V, L = 11µH, TA = +25°C, unless otherwise noted.

MP2499M Rev 1.0 www.MonolithicPower.com 5

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 12V, VOUT = 5V, L = 11µH, TA = +25°C, unless otherwise noted.

MP2499M Rev 1.0 www.MonolithicPower.com 6

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 12V, VOUT = 5V, L = 11µH, TA = +25°C, unless otherwise noted.

MP2499M Rev 1.0 www.MonolithicPower.com 7

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 12V, VOUT = 5V, L = 11µH, TA = +25°C, unless otherwise noted.

MP2499M Rev 1.0 www.MonolithicPower.com 8

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

PIN FUNCTIONS
Package
Name Description
Pin #
Supply voltage. The MP2499M operates from a 5V to 36V input rail. A capacitor
1, 2 IN
(C1) is required to decouple the input rail. Connect IN using a wide PCB trace.
3 NC No connection. Do not connect.
Output current sense. Connect a resistor from ISENSE close to AGND to sense
4 ISENSE
the output current and set the continuous output current limit threshold.
Enable/synchronize. Drive EN/SYNC high to enable the MP2499M; drive
5 EN/SYNC EN/SYNC low to disable the MP2499M. EN/SYNC cannot be floated. Apply an
external clock to EN/SYNC to change the switching frequency.
Feedback. Connect FB to the tap of an external resistor divider from the output to
GND to set the output voltage. The frequency foldback comparator lowers the
6 FB
oscillator frequency when the FB voltage is below 240mV to prevent current limit
runaway during a short-circuit fault condition.
Bias supply. Decouple VCC with a 0.1μF to 0.22μF capacitor. Select a capacitor
7 VCC
that does not exceed 0.22μF.
8 AGND Analog ground.
9 SW Switch output. Connect SW using a wide PCB trace.
Bootstrap. A capacitor is required connected between SW and BST to form a
10 BST floating supply across the high-side switch driver. A 20Ω resistor placed between
the SW and BST capacitor is strongly recommended to reduce SW voltage spikes.
System ground. PGND is the reference ground of the regulated output voltage.
11, 12, 13 PGND PGND required requires special care during PCB layout. For best results, connect
PGND with copper traces and vias.

MP2499M Rev 1.0 www.MonolithicPower.com 9

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

BLOCK DIAGRAM

Figure 1: Functional Block Diagram

MP2499M Rev 1.0 www.MonolithicPower.com 10

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

OPERATION For example, with 12V connected to VIN,

RPULLUP ≥ (12V - 6.5V) ÷ 150µA = 36.7kΩ.
The MP2499M is a high-frequency,
synchronous, rectified, step-down, switch-mode Connecting EN/SYNC to a voltage source
converter with built-in power MOSFETs. The directly without a pull-up resistor requires
MP2499M offers a very compact solution to limiting the voltage amplitude to ≤6V to prevent
achieve 3A max of continuous output current damage to the Zener diode.
with built-in output line drop compensation.
The MP2499M operates in a fixed-frequency,
peak-current-control mode to regulate the
output voltage. An internal clock initiates a
PWM cycle. The integrated high-side power
MOSFET (HS-FET) turns on and remains on Figure 2: 6.5V Type Zener Diode
until its current reaches the value set by the Connect an external clock with a range of
error amplifier (EA) COMP voltage (VCOMP). 200kHz to 2.4MHz to synchronize the internal
When the power switch is off, it remains off until clock rising edge to the external clock rising
the next clock cycle begins. If the current in the edge. The pulse width of the external clock
power MOSFET does not reach the current signal should be less than 3μs.
value set by COMP within 97% of one PWM
period, the power MOSFET is forced off. Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
Internal Regulator
from operating at an insufficient supply voltage.
The 5V internal regulator powers most of the The MP2499M UVLO comparator monitors the
internal circuitries. This regulator takes the VIN output voltage of the internal regulator (VCC).
input and operates in the full VIN range. When The UVLO rising threshold is about 4.5V, while
VIN exceeds 5.0V, the output of the regulator is its falling threshold is 4.3V.
in full regulation. When VIN falls below 5.0V, the
output of the regulator decreases following VIN. Internal Soft Start (SS)
A 0.1µF decoupling ceramic capacitor is Soft start (SS) prevents the converter output
needed at VCC. voltage from overshooting during start-up.
When the chip starts up, the internal circuitry
Error Amplifier (EA)
generates a soft-start voltage that ramps up
The error amplifier (EA) compares the FB from 0V to 1.2V. When SS is lower than REF,
voltage against the internal 0.8V reference SS overrides REF so the error amplifier uses
(REF) and outputs a COMP voltage. This SS as the reference. When SS exceeds REF,
COMP voltage controls the power MOSFET the error amplifier uses REF as the reference.
current. The optimized internal compensation The SS time is set to 1.6ms internally.
network minimizes the external component
count and simplifies the control loop design. Output Line Drop Compensation
The MP2499M is capable of compensating for
Enable/SYNC Control
an output voltage drop, such as high
EN/SYNC is a digital control pin that turns the impedance caused by a long trace, to maintain
regulator on and off. Drive EN/SYNC high to a fairly constant load-side voltage.
turn on the regulator; drive EN/SYNC low to
turn off the regulator. EN/SYNC cannot be The MP2499M uses the sensed load current
floated. through the external sensing resistor (RSENSE) to
sink a current (ISINK) at FB. Calculate ISINK with
EN/SYNC is clamped internally using a 6.5V Equation (1):
series Zener diode (see Figure 2). Connect the
EN/SYNC input through a pull-up resistor to any ILOAD  RSENSE
ISINK  (1)
voltage connected to IN. The pull-up resistor 16.5k
limits the EN/SYNC input current below 150µA.

MP2499M Rev 1.0 www.MonolithicPower.com 11

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

This current flows through the feedback resistor the output is dead-shorted to ground. The
(R1) and generates the compensation voltage average short-circuit current is reduced greatly
(VCOMP) (see Figure 3). to alleviate thermal issues and protect the
regulator. The MP2499M exits hiccup mode
L once the over-current condition is removed.
SW +
The MP2499M also has a continuous output

USB
VCOMP
MP2499M R1
+
current limit. A current sensing resistor senses
Co -
FB
the load current to protect the output from over-
GND Rsense current. If output over-current is detected
R2 (ISENSE voltage exceeds 118mV), and the
output voltage drops until FB is 30% below the
reference, the MP2499M enters hiccup mode.
Figure 3: Output Line Drop Compensation The MP2499M enters hiccup mode when the
soft start finishes, over-current occurs (internal
Calculate VCOMP with Equation (2): cycle-by-cycle inductor peak current limit or
 R1  external sensed continuous output current limit),
VCOMP  ILOAD  RSENSE   1 (2) and FB falls below the UV threshold.
 16.5k 
Thermal Shutdown
The line drop compensation voltage amplitude
Thermal shutdown prevents the chip from
increases linearly as the load current increases.
operating at exceedingly high temperatures.
Setting a different R1 value can produce
When the silicon die temperature exceeds
different voltages to compensate for the cable
170°C, the entire chip shuts down. When the
drop voltage (see Figure 4). When the load
temperature drops below its lower threshold
current is 2.4A, R1 is 82.5kΩ, RSENSE is 40mΩ,
(typically 140°C), the chip is enabled again.
and the compensation voltage is 384mV.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. A dedicated
internal regulator charges and regulates the
bootstrap capacitor voltage to ~5V (see Figure
5). When the voltage between the BST and SW
nodes drops below regulation, a PMOS pass
transistor connected from VIN to BST turns on.
The charging current path is from VIN to BST to
SW. The external circuit should provide enough
voltage headroom to facilitate charging. As long
as VIN is significantly higher than SW, the
bootstrap capacitor remains charged.

Figure 4: Output Line Drop Compensation at When the HS-FET is on, VIN ≈ VSW, so the
Different R1 Values bootstrap capacitor cannot charge. When the
low-side MOSFET (LS-FET) is on, VIN - VSW
Over-Current Protection (OCP) and Hiccup reaches its maximum for fast charging. When
The MP2499M uses a cycle-by-cycle over- there is no inductor current, VSW = VOUT, so the
current limit when the inductor current peak difference between VIN and VOUT can charge the
value exceeds the current limit threshold. If the bootstrap capacitor. The floating driver has its
output voltage drops until FB is below the own UVLO protection with a rising threshold of
under-voltage (UV) threshold (typically 30% 2.2V and hysteresis of 150mV. A 20Ω resistor
below the reference), the MP2499M enters placed between the SW and BST capacitor is
hiccup mode to restart the part periodically. strongly recommended to reduce SW voltage
This protection mode is especially useful when spikes.

MP2499M Rev 1.0 www.MonolithicPower.com 12

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

Figure 5: Internal Bootstrap Charging Circuit

Start-Up and Shutdown
If both VIN and EN/SYNC exceed their thresholds
respectively, the chip starts up. The reference
block starts first, generating stable reference
voltages and currents, and then the internal
regulator is enabled. The regulator provides a
stable supply for the remaining circuitries.
Three events can shut down the chip: EN/SYNC
low, VIN low, and thermal shutdown. In the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. The EA
VCOMP and the internal supply rail are then pulled
down. The floating driver is not subject to this
shutdown command.

MP2499M Rev 1.0 www.MonolithicPower.com 13

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

APPLICATION INFORMATION Choose a different RSENSE to set a different

continuous output current limit. For RSENSE =
Setting the Output Voltage
40mΩ, the current limit is 2.95A.
The external resistor divider sets the output
voltage (see Figure 6). The feedback resistor Setting the Line Drop Compensation
(R1) sets the feedback loop bandwidth with the The MP2499M is able to generate a
internal compensation capacitor. Choose R1 to compensation voltage (VCOMP) to compensate
be around 82.5kΩ. R2 can then be calculated for the line drop at the output (see Figure 3).
with Equation (2):
VCOMP can be calculated with Equation (6):
R1
R2  (2)  R1 
VOUT VCOMP  ILOAD  RSENSE   1 (6)
1  16.5k 
0.792V
When the load current is 2.4A, R1 is 82.5kΩ,
RSENSE is 40mΩ, and VCOMP is 384mV.
Setting VIN UVLO
The MP2499M has an internal, fixed, under-
voltage lockout (UVLO) threshold. The rising
Figure 6: Feedback Network threshold is 4.5V while the falling threshold is
Selecting the Inductor about 4.3V. For applications requiring a higher
UVLO point, an external resistor divider
For most applications, use a 10µH to 20µH
between EN/SYNC and IN can be used to
inductor with a DC current rating at least 25%
achieve a higher equivalent UVLO threshold
percent higher than the maximum load current.
(see Figure 7).
For the highest efficiency, an inductor with a
small DC resistance is recommended. For most
VIN IN
designs, the inductance value can be derived
from Equation (3): R6
VOUT  (VIN  VOUT ) IEN
L1  (3) EN
VIN  IL  fOSC
R7
Where ∆IL is the inductor ripple current.
Choose the inductor ripple current to be
approximately 40% of the maximum load Figure 7: Adjustable UVLO using EN/SYNC
current. The maximum inductor peak current Divider
can be calculated with Equation (4): The UVLO threshold can be calculated with
IL Equation (7) and Equation (8):
IL(MAX )  ILOAD  (4)
2  R6 
INUVRISING   1    VEN _ RISING  IEN  R6
Setting the Continuous Output Current Limit  R7  (7)
The MP2499M has a programmable continuous
 R6 
output current limit which is set by an external INUVFALLING   1    VEN _ FALLING  IEN  R6
resistor (RSENSE). The current limit can be  R7  (8)
calculated with Equation (5):
Where VEN_RISING = 1.4V, VEN_FALLING = 1.25V,
V and IEN = 7μA.
ICC _ LIMIT  ISENSE
RSENSE When choosing R6, ensure that it is large
(5)
enough to limit the current flow into EN/SYNC
Where VISENSE = 118mV. below 150μA.

MP2499M Rev 1.0 www.MonolithicPower.com 14

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

Selecting the Input Capacitor Where L1 is the inductor value and RESR is the
The input current to the step-down converter is equivalent series resistance (ESR) value of the
discontinuous and therefore requires a output capacitor.
capacitor to supply AC current to the step-down For ceramic capacitors, the capacitance
converter while maintaining the DC input dominates the impedance at the switching
voltage. Use low ESR capacitors for the best frequency, and the capacitance causes the
performance. Ceramic capacitors with X5R or majority of the output voltage ripple. For
X7R dielectrics are recommended for best simplification, the output voltage ripple can be
results because of their low ESR and small estimated with Equation (13):
temperature coefficients. For CLA applications,
a 100μF electrolytic capacitor and two 10μF VOUT  V  (13)
ΔVOUT    1  OUT 
ceramic capacitors are recommended. 8  fS2  L1  C2  VIN 

Since C1 absorbs the input switching current, it For tantalum or electrolytic capacitors, the ESR
requires an adequate ripple current rating. The dominates the impedance at the switching
RMS current in the input capacitor can be frequency. For simplification, the output ripple
estimated with Equation (9): can be approximated with Equation (14):

IC1  ILOAD 
VOUT  VOUT 
 1
VOUT  V  (14)
(9) ΔVOUT   1  OUT   RESR
VIN  VIN  fS  L1  VIN 
The worst-case condition occurs at VIN = 2VOUT, The characteristics of the output capacitor
shown in Equation (10): affect the stability of the regulation system. The
ILOAD MP2499M can be optimized for a wide range of
IC1  (10) capacitance and ESR values.
2
For simplification, choose an input capacitor BST Resistor and External BST Diode
with an RMS current rating greater than half of A 20Ω resistor in series with the BST capacitor
the maximum load current. is recommended to reduce SW voltage spikes.
The input capacitor can be electrolytic, tantalum, A higher resistance is better for SW spike
or ceramic. When using electrolytic or tantalum reduction, but compromises efficiency.
capacitors, add a small, high-quality ceramic An external BST diode can enhance the
capacitor (e.g.: 1μF) as close to the IC as efficiency of the regulator when the duty cycle is
possible. When using ceramic capacitors, high (>65%). A power supply between 2.5V and
ensure that they have enough capacitance to 5V can be used to power the external bootstrap
provide sufficient charge to prevent excessive diode. VCC or VOUT is recommended for this
voltage ripple at the input. The input voltage power supply in the circuit (see Figure 8).
ripple caused by the capacitance can be
estimated with Equation (11):
ILOAD V  V  (11)
VIN   OUT   1  OUT 
fS  C1 VIN  VIN 

Selecting the Output Capacitor

The output capacitor (C2) maintains the DC
output voltage. Use ceramic, tantalum, or low-
ESR electrolytic capacitors. For best results,
use low ESR capacitors to keep the output Figure 8: Optional External Bootstrap Diode to
voltage ripple low. The output voltage ripple can Enhance Efficiency
be estimated with Equation (12): The recommended external BST diode is
VOUT  VOUT   1  IN4148, and the recommended BST capacitor
VOUT   1    RESR  
(12) value is 0.1µF to 1μF.
fS  L1  VIN   8  fS  C2 

MP2499M Rev 1.0 www.MonolithicPower.com 15

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

PCB Layout Guidelines (7)

Efficient PCB layout, especially of the input
capacitor and VCC capacitor placement, is Vo
critical for stable operation. For best results, GND
VIN
refer to Figure 9 and follow the guidelines below.
1. Place the ceramic input capacitors as close
to IN and PGND as possible. Top Layer

2. Keep the connection of the input capacitor

and IN as short and wide as possible.
3. Place the VCC capacitor as close to VCC VIN
sw
and AGND as possible.
GND
4. Make the trace length of the VCC pin to the
VCC capacitor anode to the VCC capacitor Bottom Layer
cathode to the chip’s AGND pin as short as Figure 9: Recommended PCB Layout
possible.
5. Use a large ground plane to connect to
PGND directly.
6. Add vias near PGND if the bottom layer is a
ground plane.
7. Route SW and BST away from sensitive
analog areas such as FB.
8. Place the feedback resistor close to the chip
to ensure that the trace connecting to FB is
as short as possible.
NOTE:
7) The recommended layout is based on the Typical
Application Circuit page 17.

MP2499M Rev 1.0 www.MonolithicPower.com 16

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

TYPICAL APPLICATION CIRCUIT

VIN L2 R4
6.5V-36V 0 20Ω
1,2 10
IN BST
C1C C1B + C1A C1 R6 C4 L1
NS 100μF 10μF 10μF 300kΩ 0.1μF 11μH VOUT 5V/2.4A
MP2499M 9
5 SW
EN/SYNC C5 +
C2A C2 D- U
Optional filter for
39pF R7 100μF 1μF
improving EMI 7 R5 D+ S
VCC 10Ω
0Ω B
C3 FB 6
0.1μF R1
8 R2
AGND 82.5kΩ
15.4kΩ

NC ISENSE 4
PGND
11-13 3
R3
40mΩ

Figure 10: CLA Typical Application Circuit

MP2499M Rev 1.0 www.MonolithicPower.com 17

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
 MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER
PACKAGE OUTLINE DRAWING FOR 13L FCQFN (2.5X3.0MM) -2
MF-PO-D-0257 revision 0.0
PACKAGE INFORMATION
QFN-13 (2.5mmx3mm)

PIN 1 ID
MARKING
PIN 1 ID
0.15X45º TYP

PIN 1 ID
INDEX AREA

TOP VIEW BOTTOM VIEW

SIDE VIEW

0.15X45º
NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
3) JEDEC REFERENCE IS MO-220.
4) DRAWING IS NOT TO SCALE.

RECOMMENDED LAND PATTERN

NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.

MP2499M Rev 1.0 www.MonolithicPower.com 18

5/1/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.