Chapter 3
Branch, Call,
and Time Delay
Loop
DECFSZ fileReg, d
• Decrement fileReg and skip next instruction if 0.
• Loop repeating a sequence of instructions or an
operation a certain number of times.
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Figure 3-1. Flowchart for the
DECFSZ Instruction
BNZ Branch if not zero
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Maximum Number of Times for
loop
Loop Inside a Loop Nested Loop
Other Conditional Jumps
BZ Branch if Z = 1
BNC Branch If No Carry (CY = 0)
Short Jumps
• All conditional jumps are short jumps.
• Meaning that the address of the target must be within
256 bytes of the contents of the PC.
• 2-byte instructions.
• Target address = (2nd byte of instructions2)+PC
• The 2nd byte can be a value from -127 to +128
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Unconditional Branch Instruction
GOTO
• Long jump can go any memory locations in the 2M
address space of the PIC18.
• A 4-byte instruction.
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Unconditional Branch Instruction
BRA (Branch)
• A 2-byte instruction.
• The first 5 bits are the opcode.
• The rest lower 11 bits are the relative address of the
target address
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• GOTO to itself using $ sign.
• HERE GOTO HERE
GOTO $
• OVER BRA OVER
BRA $
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CALL Instructions and Stack
• A 4-byte instruction.
• Long call.
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Simplified view of a PIC
microcontroller
22
Figure 3-7. PIC Stack 31 × 21
• A 5-bit stack pointer (SP) with initial value 0.
• Last-In-First-Out (LIFO)
RCALL (Relative Call)
• A 2-byte instruction.
• Only 11 bits of the 2 bytes are used for the address.
• The target address of RCALL must be within a 2K
range.
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Delay Calculation
• Two factors that affect the accuracy of the delay:
– The crystal frequency
– The PIC design
• An instruction in one cycle
– Use Harvard architecture
– Use RISK features
– Use piplining
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Figure 3-9. Pipeline vs. Non-
pipeline
• Instruction cycles (machine cycles) In PIC18, one
instruction cycle consists of four oscillator periods.
• Brach penalty CPU flushes out the instruction queue.
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Pipeline Activity