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 MODULE-1
1.1. FUNCTIONAL BLOCKS OF A COMPUTER SYSTEM

Computer Architecture refers to those attributes of a system visible to a programmer. Computer

Organizaion refers to the operational units and their interconnections that realize the architectural
will have a
specifications. As an example, it is an architectural design issue whether a computer
multiply instruction. It is an organizational issue whether that instruction will be implemented by
a

special multiply unit or by the method of repeated addition by using the add unit of the system.

The model of a computer can be described by four basic units in high level abstraction. These
basic units are:

Central Processor Unit

Input Unit
Output Unit
Memory Unit

Menor

1. Central Processor Unit [CPU]: Central processorunit consists of two basic blocks
.The program control unit has a set of registers and control circuit to generate
control signals.
.The execution unit or data processing unit contains a set of registers for
storing data and an Arithmetic and Logic Unit (ALU) for execution of
arithmetic and logical operations.
In addition, CPU may have some additional registers for temporary storage of
data.

2. Input Unit: With the help of input unit data from outside can be supplied to the
computer. Program or data is read into main storage from input device or secondary
storage under the control of CPU input instruction.
Example of input devices: Keyboard, Mouse, Hard disk, Floppy disk, CD-ROM drive
etc
3. Output Unit: With the help of output unit computer results can be provided to the
user or it can be stored in storage device permanently for future use. Output data from
main storage go to output device under the control of CPU output instructions.
Example of output devices: Printer, Monitor, Plotter, Hard Disk, Floppy Disk etc.

Page 4 of 106
 4. Memory Unit: Memory unit is used to store the data and program. CPU can work
with the information stored in memory unit. This memory unit is termed as primary
memory or main memory module. These are basically semiconductor memories.
There are two types of semiconductor memories
Volatile Memory : RAM (Random Access Memory).

Non-Volatile Memory: ROM (Read only Memory), PROM(Programmay.ooM

EPROM (Erasable PROM), EEPROM
5.
(Electrically Erasable PROM).
Secondary Memory: There is another kind of storage device, apart from primary or
main memory, which is known as secondary memory. Secondary memories are non-
volatile memory and it is used for
permanent storage of data and program.
Example of secondary memories
Hard Disk, Floppy Disk,
Magnetic Tape- these are magnetic devices
CD-ROM1- is optical device
Thumb Drive (or Pen Drive) is semiconductor memory

1.2. INSTRUCTION SET ARCHITECTURE

This is an abstraction the interface between the hardware and the low-level
on

deals with_the software. It

functional behaviour of a computer system as viewed by a programmer.
Computer organization deals with structural relationships thar are not Visible by a
programmer. Instruction set architecture is the attribute of a computing system, as seen by the
assembly language programmer or compiler.
ISA is determined by
ata
Data Storage.
Memory Addressing Modes.
Operations in the Instruction Set.
Instruction Formats.
Encoding the Instruction Set.
Compiler's View.
The Instruction Set Architecture (ISA) is the part of the processor that is visible to the
programmer or compiler writer. The ISA serves as the boundary between =software and
hardware. We will briefly describe the instruction sets found in many of the microprocessors
used today. The ISA of a processor can be described using 5 categories:

Operand Storage in the CPU

2. Where are the operands kept other than in memory?
Number of explicit named operands
How many operands are named in a typical instruction?
9perand location

1.2.1. CPU ARCHITECTURE TYPES (ACCUMULATOR, REGISTER, STACK,

MEMORY/ REGISTER)
In general, most processors or computers are organized in one of 3 ways
1. Single register (Accumulator) organization
Basic Computer is a good example
Accumulator is the only general purpose register

Page 5 of 106
 2. Stack organization
All operations are done using the hardware stack
For example, an OR instruction will
pop the two top elements from the stack,
do a logical OR on them, and
push result on the stack
the
3. General register organization
. Used by most modern computer processors
Any the registers can be used as the source or destination for
of
computer
operations
1.2.2. ACCUMULATOR TYPE OF ORGANIZATION
In case of accumulator type of
organizations, one operand is in memory and other is in
accumulator.
The instructions we can run with accumulator are:

AC-ACADR AND with DR

AC-AC +DR Add with DR
AC-DR Transfer from DR
AC(0-7)+- INPR Transfer from INPR
AC-AC Complement
AC-shr AC, AC(15) - E Shift right
ACshlAC, AC(0) +E Shift left
AC-0 Clear
ACAC+1 Increment
Circuit required:

Adder and
FromDR logic
circuit
AC 1
From INPR | To bus

LD INR CLR Clock

Control
Gates

1.2.3. STACK ORGANIZATION

Stack:

Page 6 of 106
 nested interrupt services
Very useful feature for nested subroutines,
Also efficient for arithmetic expression evaluation
Storage which can be accessed in LIFO
Pointer: SP
Only PUSHand POP operations are applicable
Stack type of organization is of two types
1. REGISTER STACK ORGANIZATION

Address

Flags 63
FULL EMPTY

Stack pointer 4
SP 3
6 bits

DR

Push, Pop operation

Initially, SP = 0, EMPTY 1, FULL = 0

**********

PUSH POP
SPSP +1 DR-MISP]
MISP]-DR SPSP-1
If(SP= 0) then (FULL-1) If(SP = 0) then (EMPTY+1)
EMPTY0 FULL-0

2. MEMORY STACK ORGANIZATION

Memory with Program, Data, and Stack Segments

A portion of memory is used as a stack with a processor register as a stack pointer

PUSH: SPSP 1 M
SP] DR

Page 7 of 106
 POP: DRM [SP]
SPSP+1
Note: Most computers do not provide hardware to check stack overflow (full stack) or
underflow (empty stack) must be done in software

1000
PC Programn
instrucudns)

Data
AR
(OperandS
SP 3000

3997
3998
3999
4000
4001

Stack grows
In this direction

1.2.4. REGISTER TYPE OF ORGANIZATION

In this we take the help of various registers, say Ri to R8 for transfer and manipulation of data.

Page 8 of 106
 REGISTER BASED CPU
DETAILED DATA PATH OF
A TYPICAL
Input
Clock

R
R2
R3
R4
R5

Load

C7 linegELS1 MUX MUX }SELS2

Decoder
3x8
81 $2
SELD
OPR ALU

Output/Result

very time consuming and thus a costlytechnique),

To avoid memory access directly (as it is
it proves to be more efficient and time saving
prefer the register organization
as
we

organization.

and a decoder decide which registers to

In this we are using 7 registers. The two multiplexers of
a destination for the storage
be used as operands source and what register to be used as
result.

the 1st operand register which depends on

the values of
SELSI (Selector for
MUX 1 decides
source 1). Similarly, for MUX 2, SELs2 works as input for 2nd operand decision.

reach ALU. OPR denotes the type of operation to

These two inputs through Slbus and $2 bus Then the result is
or operation is performed on ALU.
be performed and the computation
which decides which is
either stored back in one of the 7 registersS With the help of decoder
SELD.
the resultant register with the help of
TO 5 STAGE)
1.2.5. FETCH-DECODE-EXECUTE CYCLE (TYPICALLY 3

Page 9 of 106
 Begin

Fetch Next
Instruction

Decode
Instruction

Execute
nstruction

1. Fetch Cycle
2. Decode Cycle
3. Execute Cycle
Working of Instruction feteh Execute Cycle
1. Fetch an instruction from memory.
2. Fetch any data required by the instruction from memory.
3. Execute the instruction (process the data).
4. Store results in memory.
5. go back to step (1)
1. Fetch Cycle: The fetch cycle begins with retrieving the address stored in the Program
Counter (PC). The address stored in the PC is some valid address in the memory
instruction to be executed. (In case this address does not exist we would
holding the
end up causing an interrupt or exception).
The Central processing unit completes this step by fetching the instruction stored at

this address from the memory and transferring this instruction to a special register -

Instruction Register (IR) to hold the instruction to be executed. The program counter
is incremented to point to the next address from which the new instruction is to be

fetched.
instruction that was
2 Decode Cycle: The decode cycle is used for interpreting the
fetched in the Fetch Cycle. The operands are retrieved from the addresses if the need

be.
3. Execute Cycle: This cycle as the name suggests, simply executes the instruction that
was fetched and decoded.

1.3. RTL INTERPRETATION OF INSTRUCTIONS

is
The symbolic notation used to describe the micro-operation transfers amongst registers

Page 10 of 106
called Registertransfer language.
The term register transfer means the availability of hardware logic circuits that can perform a
stated micro-operation and traDsfer the result of the operation to the same or another register.

The word language is borrowed from programmers who apply this term to programming
a given
languages.This programming language is a procedurefor writing symbols to specity
Computational process.
Following are some commonly used registers:
the
Accumulator: This is the most common register, used to store data taken out from

memory.
General Purpose Registers: This is used to store data intermediate results during program
execution. It can be accessed via assembly programming.
Users do not access these registers. These registers are
for
Special Purpose Registers:
Computer system,
holds the address for memory unit.
MAR: Memory Address Register are those registers that

MBR: Memory Buffer Register stores instruction

and data received from the memory and
sent from the memory.
instruction to be executed.
PC: Program Counter points to the next
executed
R:Instruction Register holds the instruction to be
Register Transfer
register to another is designated in symbolic form by
means
Information transferred from one

of replacement operator.

R2-R1

register R1 into R2.

It denotes the transfer ofthe data from
control condition. This can be
Normally we want the transfer tó occur only predetermined
in
then (R2-R1)
shown by following if-then statement: if (P=1)

Here P is a control signal generated in the control section.

Block Diagrams of Registers

6 5 4 3 210
Register R Showing Individual Bits

8 7

RI PCH) PCL)

Numbering of Bits Divided Into Two Parts

Page 11 of 106
Register Transfer Language Instructions

Register Transfer R2- R1

Simultaneous Transfer R2 R1, R1 R2
Conditional Transfer (Control Function)P: R2-R1
orIf (P =1) Then R2R1
Conditional, Simultaneous Transfer T: R2-R1, Rl - R2
Basic Symbols for Register Transfer Speuitl an MCR
Suau bYaukels 4ddus for
Symbol Description Examples
Letters (and Denotes a MAR, R2
numerals) register
Parentheses () Denotes a part R2(0-7), R2(L)
of a register
Arrow Denotes Transfer R2 R1
of information
Comma Separates 2 R2 -R1, RI-RI1
microoperations
Colon l:Conou tional P:A,tR
Register Transfer and Hardware
operotien if P1
Every statement in Register Transfer Language implies the existence of hardware that
implements the micro operation.

The statement P: R2-Rl implies the existence of the

necessary circuitry to implement
the transfer as well as the mechanism to set and clear the control variable P.
 Instruction Set
Since the 8085 is an 8-bit device it can have up to 28 (256)
instructions.
However, the 8085 only uses 246 combinations that represent a
total of 74 instructions
Most of the instructions have more than oneformat.

These instructions can begrouped into five different groups:

Data Transfer Operations

Arithmetic Operations
Logic Operations
Branch Operations
Machine Control Operations

Instruction Set.....cont...
(A) Data Transferoperation
These operations simply COPY the data from the source to the
destination. A
***

>They transfer:
Data between registers.
Data Byte to a register or memorylocation.
Data betweena memory locationand a register.
Databetweenan l/ODeviceandtheaccumulator.
Thedata in the sourceis not changed.
Data transfer instructions neveraffect the flag bits.
eg LDA, STA,MOV, LDAX, STAX, MVI, LXI etc.
DA oad Actumulatok
L

S TA -Shr Accumulaton
L AX laad a cCumulaker indud
STAX- S t o a CCumulskoi in ouet
MVI MO Immu oliolt
XI -Load ngiin fa mmeolialt

LI H 400oH
Exmpl MoV M, *

MVI H, olata
MVI A, 0S
MV1 M, dlala
 Instruction Set....cont...
(B) Arithmetic Operation
These instruction perform addition, subtraction and compareoperations
These operations are always performed with accumulator as one of the
operands.
The status of the resultcan be verified by the contents of the flag register.
Addition: Any 8-bit number, or the contents of a register or the contents of a
memory location can be added to the contents of the accumulator and
sum is stored in the accumulator. The instruction DAD is an exception; it adds the
16-bit data directly inregister pairs. Ex ADD, ADI
Subtraction Any 8bit number, or the contents of a registér, or the contents
of a memory location can be subtracted from the contents of the accumulator
and the results stored in the accumulator, Subtraction is done by 2s
compliment method and set carry tlag toindicate borrow.SUB.SBI
Increment/Decrement The 8-bit contents of a register or a memory
location can be incremented or decrement by 1 Similarly, the 16-bit contents
a register pair (such as BC) can
be incremented or decrement by 1. INR,DCR. of
www

6 PR BC E H
InstructionSet.. (Cont..)
(C) Logical Operation .
.
*
.
. ..
..

Perform 8-bit basic logical operations with: the content of the

accumulator
Logicalinstructionsalso modify the flagbits
Op-codes for logical instructions include ANA, ANI, ORA, ORI, XRA, ( x AA R
XRI, CMA, CMC, RAL, RLC, RAR, RRC, CMP, CPI etc. xAA M)
c
P1Cempa mne dia ith H accmulaken Seend by dala
AND, OR Exclusive-ORAny 8-bit number, or the contents of register. or
memory location can be 1ogically AND, Or or of a Mpda a

Exclusive-OR with
accumulator The results are stored in the accumülatOr the contents of the
.

Rotate- Each bit in the accumulator can be

shifted either left or right to the next
position. CMA Cemp wmu acummulako cMC- omb mle ca
MPCompanu k e1 memoru 1 actumulokoi
Compare Any 8-bit number, or the contents of a register, or a
compared for equality greater than, or less memory location can be
than, with the contents of the accumulator.
Complement- The contents of the accumulator can be
w complemented.
ANA 0gical AND qstn an mimony with h A CCwmulalm.
ANI- Logrtal AND immedua t i t h ths accwmulako
loc a OR HAs ty am meme with ha acc Umulao
&RA
Ex cluwsiR OR eg Au imou th +ha accumulalor
XRA
 Instruction Set... Cont..
(D) Branch Operation
These instructions are used to transfer the program control:
l o jump from one memory location to any other memory location within a
program
From one program toanotherprogram called as a subroutine.
Alters the sequence of program execution either conditionally or
unconditionally
Unconditional branchinstructions Tansfertheprogram to the specified label or
address JMP unconditionally i.e without satisfying anycondition.
UnconditionalProgram control instructionsare and Aart
An

used o call a p e du
Call&RET 4ddus o the tauk
o Hhe mam
Rd e u em thu pro adwre
Conditional branchinstructions Transfertheprogramtothe specified label or
address when certain conditionissatisfied
JNCJCNZLPIM PE PO
CNC,CC CNZ CZ, CP CM.CPE, CPO pas/thve
RNC RC RNZ, RZ,RP,RM, RPE, RPO
wwN

InstructionSet... '.*
Cont..
.

(E) Machine Control Operation

These instructions include special instructions such as I/0 data
transfer perform machine related operation
HLT- To halt the CPU
NOP To perform nooperation
SIM Toset the masking of hardware interrupts and serial
output data
>RIM- Toread the status of interrupt mask and serial input
data
EI Enable Interrupt
DI Disable Interrupt
JNC wred o jump C a flaa(Y=) | e cal i Cawup
JNC wtd 3u 1m0 Cau
Fo floq Ccyz0) CNC- Coll if n o ca
a

JNZ wmd h jum i1 3u 4log=o CN-Cak if 3eio fog o

T-Call it o lag=
JPE- Rd o up i Panity un PF - ) CPE CaR if en Pauy
3Po d ko
jut i pa ood PF = cpo-Call ifdd Pait
 RAL- Apod actumulakor loft through cassu
RLC Aotali aucumulakn ljf
RRC Rotas accumulabor ughs
RAR- Rv ta accumular ight hiaough Cauy
Bit shiffed fo
RLALC Exomp 10lolo|o Cy - 0
ady a n t D2
Cy
ololo]o beuem Do. Cak
modfhad
Io1ololo y=° Hog cy a
Ccgnod biH Dg.
9 beomis the
RAL
lo lelo lo, cY20 Canuy bit and
T S C'ay bif
sitfrd mo Do.

I0loool; cy 20
3 RRC Exomb lo 16ooooo Bit Dg Deuenas
; C720P
Do Ca a flag
,St | 00 o0 00
- C =1
Cy mooi fj2d
q Ccaolg o A

bit Do
4) RAR EXampk l;(y=b
looo oool;
Bit Do becenes
he C a y þit

C20 and Cay bit

1oloooo0 shifld into
- Cary fla
Cy modi fled
ccorold
bif Do

'
 Parts Of Instruction Format
The parts of the instruction format are:

1. Addressing Mode

The data is
represented in the instruction format with the help of addressing mode
The addressing mode is the first part of the instruction format
The data can either be stored in the
memory of a computer or it can be located in the
register of the CPU

2. Operation Code( OPCODE)

The operation code gives instructions to the processor to perform the specific Operation
The operation code is the second
part of the instruction format

3. OPERAND

I t is the part of the instruction format that

specifies the data or the address of the data
Depending upon the processor of the computer the instruction format contains zero to
three operands
 A large number of instructions typically from 100 to 250 instructions.
Some instructions that perform specialized tasks and are used infrequently.
A large variety of addressing modes- typically from 5 to 20 different modes.
Variable length instruction formats.
Instructions that manipulate operands in memory.
Example
For performing an ADD operation, CISC will execute a single ADD command which
will execute all the
required load and store operations.
RISC will execute each operation for loading data from memory, adding values and
storing data back to memory using different low-level instructions.

Format Of Instruction
The set of instructions that manages the operation codes is called the format of instruction. The
design of bits in instruction is supported by the format of instruction. The length of instruction is
generally preserved in multiples of character, which is 8bits. The instruction format determines
the behaviour and complexity of instruction. Dependling upon the number of addresses, the
format of instruction is of variable length.

Types of instruction format include:

Zero(0) Address Instruction format

One(1) Address Instruction format
Two(2) Address Instruction format
Three(3) Address Instruction format

Types Of Instruction Format

Types of instruction formats are:

1. Zero(0) Address Instruction format

The instruction format in which there is no address field is called zero address instruction

.In zero address instruction format, stacks are used

I n zero order instruction format, there is no operand

2. One(1) Address Instruction format

The instruction format in which the instruction uses only one address field is called the
one address instruction format
I n this type of instruction format, one operand is in the accumulator and the other is in the
memory location
It has only one operand
 I t has two special instructions LOAD and STORE

3. Two(2) Address Instruction format

The instruction format in which the instruction uses only two address fields is called the
two address instruction format
This type of instruction format is the most
commonly used instruction format
A s in one addressinstruction format, the result is stored in the accumulator only, but in
two addresses instruction format the result can be stored in different locations
This type of instruction format has two operands
It requires shorter assembly language instructions

4. Three(3) Address Instruction format

The instruction format in which the instruction uses the three address fields is called the
three address instruction format
It has three operands
It requires shorter assembly language instructions
It requires more bits

Example Of format Of Instruction

1.Zero Address Instruction examples
Assembly language instruction PUSH A, PUSH B etc.
Stack transfer operation-TOS A, TOS - B etc
2. One Address Instruction examples
Assembly language instruction-LOAD C, ADD B, STORE T etc
Operation Register instruction AC M[T) AC -MIC] etc.

3. Two Address Instruction examples

Assembly language instruction MOV R1, A; ADD R1, B etc.
Operation Registerinstruction - R1 MIA], R2-M[C] etc.

4 Three AddressInstructionexarmples
Assembly language instruction-ADD R1, A, B etc.

Operation Register instruction - R1 < M[A] + M[B] etc.