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Pcie Bus

The document provides an overview of PCIe (Peripheral Component Interconnect Express), detailing its structure and functionality, including the three layers of the PCIe protocol: Transaction Layer, Data Link Layer, and Physical Layer. It includes a block diagram and descriptions of various modules related to PCIe verification, such as modules for transaction handling, memory and IO operations, and data link layer processing. Each module is designed to manage specific tasks related to packet transactions and communication between devices.

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Bharath
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29 views4 pages

Pcie Bus

The document provides an overview of PCIe (Peripheral Component Interconnect Express), detailing its structure and functionality, including the three layers of the PCIe protocol: Transaction Layer, Data Link Layer, and Physical Layer. It includes a block diagram and descriptions of various modules related to PCIe verification, such as modules for transaction handling, memory and IO operations, and data link layer processing. Each module is designed to manage specific tasks related to packet transactions and communication between devices.

Uploaded by

Bharath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
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PCIe Bus DOCUMENT

This Document will provide you for the information and


reference document of PCIe Verification and block diagram of TL
and DLLP single packet transaction.

INTRODUCTION
PCIe – Peripheral Component Interconnect Express.
It is a serial expansion bus standard for connecting a computer to
one or more devices. It has Lanes for communication.It achieves
reliable data transfers using a 3 layer pcie protocol.
1.Transaction Layer 2.Data Link Layer 3.Physical Layer

Block Diagram
List of files and Description

File Name: Module main


This module is used to connect all the sub-modules that include
transaction layer and data link layer for transmit and receive devices,
switch, IO and memory devices. It also includes the stimulus to
Provide the required inputs to the main module and observe the
output signals for PCI transactions.

File Name: Module TL TX A


This module performs the functionality of the transaction layer of
the transmitting device by computing the fields of TLP such as
transaction type, transaction length, first byte enable, last byte enable,
etc. Once the TLP is formed it is passed on to the data link layer of
that device.

File Name: Module RX BUFFER B


This module performs the functionality of the receive buffer by
storing and managing the link packets sent to the receiving device.

File Name: Module Memory


This module computes the address and number of bytes for
memory read/write transactions. For memory read transactions data is
read from the specified memory address and a completion packet is
formed. For posted memory write transactions data in TLP is written to
the specified address in memory.
File Name: Module IO
This module computes the address and number of bytes for IO
read/write transactions. For IO read transactions data is read//II from
the specified IO address and completion packet is formed. For IO
write transactions data in TLP is written to the specified IO address
and corresponding completion packet is formed.

File Name: Module DLL TX A


This module gets TLPs from the transaction layer of the
transmitting device; calculates sequence number for the TLP,
generates LCRC and stores the packets in the replay buffer. These
packets are transmitted after checking the Flow Control Credit of the
receiving device. The packets are purged from the replay buffer on
receiving ACK DLLP or retransmitted on receiving NAK DLLP from the
receiving device.

File Name: Module DLL Rx A


This module purges or replays the TLPS in replay buffer of the
transmitting device based on ACK/NAK DLLP sent by the receiving
device to the corresponding transmitting device.

File Name: Module SWITCH


This module checks for the transaction type of every packet and
forwards it appropriately to memory or IO device and sends ACK/NAK
DLLP to the device that transmitted the packet to the switch.
Variables:

Form_new_packet // To create a new packet


In_desired_address // Address (32 bit address)
In_byte_length // Length of the data
In_trans_type // Transaction Type
In_data_in // Data

Ack_nak_dllp // DLLP for Ack/Nak


New_dllp // New DLLP

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