IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.

6, JUNE 2011 1673

Methods of Reducing Audible Noise Caused by

Magnetic Components in Variable-Frequency-
Controlled Switch-Mode Converters
Laszlo Huber, Member, IEEE, and Milan M. Jovanović, Fellow, IEEE

Abstract—Methods and a circuit implementation of audible as well as the optimal selection of semiconductor components,
noise reduction (ANR) in switch-mode converters with variable design optimization of magnetics, and implementation of power
switching frequency are presented. The audible noise caused by management techniques. While in the past the major research
magnetic components is reduced by controlling the switching fre-
quency so that it remains above the audible range as the load de- effort was on finding new architectures and topologies with im-
creases. This is accomplished by decreasing the peak value of the proved performance [6]–[10], the major efficiency gains were
main switch current pulses in discrete steps until the peak value enabled by the advances in semiconductor devices and by better
of the main switch current pulses is decreased to a level that is understanding of magnetics design [11]–[13]. In fact, except for
sufficiently low not to produce unacceptable audible noise. At very minor refinements, the architectures and topologies employed
light loads and at no load, the ANR circuit can be disabled in or-
der to meet various worldwide standards that limit the maximum in today’s high-performance power supplies are essentially the
input power. The performance of the proposed circuit was exper- same as those used in the past.
imentally verified in a 90-W single-stage power-factor-correction As the silicon-based devices approach their theoretical per-
flyback adapter. formance limit, their ability to improve the performance of the
Index Terms—Audible noise, continuous feedback control next generation of power supplies is diminished. The emerging
(CFC), peak current programming, switching frequency monitor- SiC and GaN technologies will certainly bring about future sig-
ing, switch-mode converters, variable switching frequency (VSF). nificant incremental efficiency improvements [14]–[16]. Never-
theless, the major improvements of the power supply efficiency
I. INTRODUCTION in the future are expected to be achieved by power management.
While power management, which is being enabled by the recent
ROMPTED by environmental concerns and economic rea-
P sons caused by the continuous and aggressive growth of
the Internet infrastructure and a relatively low-energy efficiency
developments of digital infrastructure for power-supply appli-
cations, is shown indispensable in flattening efficiency curve
across the entire load range, it is even more essential in maxi-
of its power delivery system, the power supply industry today
mizing the efficiency at very light and no load conditions.
faces a very challenging task of making power conversion prod-
Generally, to meet the efficiency requirements at light loads
ucts that exhibit a high efficiency in the entire load range. These
and at no load, the switching frequency needs to be reduced.
tough efficiency targets have already been defined in a number
This can be achieved by employing cycle skipping, also called
of voluntary and mandatory specifications issued by a number
burst mode of operation, or by employing a variable switch-
of worldwide agencies, most notable by the US Energy Star [1]
ing frequency (VSF) control, i.e., by continuously decreasing
and its European Community’s counterpart [2].
the switching frequency as the load decreases. The burst mode
Generally, the optimization of efficiency across the entire load
of operation is typically employed in power supplies with a
range reduces to finding the right balance between switching and
constant switching frequency control. However, reducing the
conduction losses because the full load efficiency is predomi-
switching frequency or operating in the burst mode may cause
nantly determined by conduction losses of semiconductor and
audible noise if the switching frequency or the burst frequency
magnetic components, whereas light load efficiencies for the
falls in the audible range (20 Hz–20 kHz).
most part are determined by switching losses of semiconduc-
The main sources of the audible noise in switched-mode
tors and core losses of magnetic components [3]–[5]. This itera-
power supplies are cooling fans and magnetic components
tive optimization process involves selection of the most suitable
such as transformers, input filter inductors, and power-factor-
power supply architectures and power conversion topologies,
correction (PFC) chokes. In today’s power supplies that employ
fan speed control, the fan noise caused by the air turbulence
generated by the fins is dominant at heavy and medium loads,
Manuscript received July 6, 2010; revised September 23, 2010; accepted i.e., at loads above approximately 20–40% of the full load. As
October 6, 2010. Date of current version July 22, 2011. Recommended for pub- a result, the noise generated by magnetic components is not a
lication by Associate Editor S. Y. Hui.
The authors are with Delta Products Corporation, Power Electronics Labo- concern at these loads. However, at lighter loads, with a reduced
ratory, Research Triangle Park, NC 27709 USA (e-mail: lhuber@deltartp.com; fan speed, the noise generated by magnetic components may
milan@deltartp.com). become a design issue.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. Magnetic-component’s audible noise can be separated in two
Digital Object Identifier 10.1109/TPEL.2010.2089700 parts depending on different excitation mechanisms as described

0885-8993/$26.00 © 2011 IEEE

1674 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

in [17]. The first and most dominant part of the noise is caused by
magnetization of the core, generally assumed to arise from mag-
netostriction, where the core dimensions change when subjected
to an applied magnetic field. The second part of the magnetic
component noise is caused by electromagnetic forces created by
the magnetic field of the currents in the component’s windings.
Generally, magnetostriction can cause a mechanical interaction
between the core and the windings that leads to vibrations. These
mechanical vibrations are closely related to the magnetic flux
swing.
While audible noise caused by mechanical vibrations of
magnetic components is a problem in any power supply,
it is especially undesirable in external ac–dc power sup-
plies (adapters/chargers) for portable electronics because these
adapters do not have a cooling fan and are usually placed close
to the user. In the absence of any audible noise agency specifica-
tions, many companies have defined their own internal specifica-
tions. According to the majority of these internal specifications, Fig. 1. Block diagram of a switch-mode power supply with VSF and with
CFC.
if the audible noise of an adapter is above 25 dB(A)/20.0 μPa
measured at a distance of 5 cm, appropriate measures should be
taken to reduce the audible noise. as described in [21]. It should be noted that [21] is aimed at
Methods for reducing the magnetic-components-related au- the problem of reducing the audible noise in power converters
dible noise in switch-mode converters can be divided into me- with VSF, where the switching frequency decreases as the load
chanical and electrical methods. The mechanical approaches are increases and where the switching frequency can drop below the
based on techniques that prevent or damp vibrations by mechan- upper threshold of the audible range when exceptional operating
ical means such as varnishing, gluing, and potting. While these circumstances exist such as over power, short circuit, start up,
methods are successful in some applications, generally, they are or turning OFF the converter.
undesirable since they involve extra manufacturing steps and, In this paper, methods and a circuit implementation for re-
therefore, increase the cost. Electrical methods of controlling ducing audible noise caused by magnetic components in switch-
audible noise are preferred since they are more successful and mode converters with VSF and with continuous feedback con-
cost effective. trol (CFC), where the switching frequency decreases as the load
The literature on audible noise reduction methods in switch- decreases, are described. Generally, the described audible noise
mode converters caused by magnetic components is very scarce reduction solutions are intended primarily for switch-mode con-
[18]–[21]. More importantly, the available literature does not verters that do not have cooling fans and where the only noise
offer any experimental evaluation of the effectiveness of the sources are magnetic components. Specifically, the most appro-
proposed audible noise reduction techniques. priate application of the presented work is for external ac/dc
Generally, in [18]–[20], methods for reducing the audible converters for portable electronics equipment such as notebook
noise in burst mode of operation are proposed. Specifically, adapters/chargers that can be placed in close proximity to the
in [18] and [20], shaping the envelope of the switch current user.
pulses is proposed to reduce the audible noise in burst mode of
operation. In [19], the audible noise problem is solved by pre-
setting the switching frequency values above the audible range II. AUDIBLE NOISE REDUCTION METHODS
and by decreasing the switch current limit as the load decreases The block diagram of a switch-mode power supply with VSF
until the lowest current limit has been reached, which is low and with CFC is shown in Fig. 1. The VSF control is achieved
enough such that the flux density in the core of the transformer by the voltage-controlled oscillator (VCO), controlled by the
does not produce unacceptable audible noise. Moreover, in [19], feedback voltage VFB at the output of the error amplifier (EA).
constant switching frequency power converters with ON/OFF According to the control method in Fig. 1, as the load decreases,
feedback control and with a relatively complex cycle skipping the feedback voltage decreases, and consequently, the switching
algorithm are considered. frequency decreases, as illustrated in Fig. 2. For simplicity, in
In power supplies with VSF, the audible noise can be com- Fig. 2, a linear relationship between the switching frequency
pletely eliminated by preventing the switching frequency to and load current is assumed, which is a good approximation
drop below the upper threshold of the audible range. This can for a converter operating in discontinuous conduction mode. A
be achieved directly by limiting the maximum switching period duty cycle is initiated by the VCO and is terminated when the
or by limiting the maximum off time; or indirectly, by monitor- current-sense (CS) voltage VCS reaches the reference voltage
ing the switching frequency to detect when has the switching level VCS,Ref , as shown in Fig. 1. The principle of operation is
frequency dropped close to the upper threshold of the audible illustrated in Fig. 3 on the example of the flyback converter. If
range and, then, instantly increasing the switching frequency, the peak value of the switch current pulses IPeak is constant, the
HUBER AND JOVANOVIĆ: METHODS OF REDUCING AUDIBLE NOISE CAUSED BY MAGNETIC COMPONENTS 1675

Fig. 2. Relationship between the switching frequency and load current of a

converter operating in discontinuous conduction mode.

switching frequency linearly changes with the load current so

that when the switching frequency decreases twice, the average
switch current also decreases twice, which means that the load
current decreases twice.
In Fig. 2, the switching frequency enters the audible range at
load current ILoad1 . The minimum switching frequency, fswM in ,
is obtained at no load, which is typically above the lower thresh-
old of the audible range, fAudibleL . If the peak value of the switch
current pulses is not sufficiently low, the corresponding mag-
netic flux swing in the core of the transformer will produce
unacceptable audible noise.
In this paper, the audible noise is reduced by controlling the
switching frequency so that it remains above the audible range
as the load decreases by decreasing the peak value of the main
switch current pulses in discrete steps, as illustrated in Fig. 4, un-
til the peak value of the main switch current pulses is decreased
to a level that is sufficiently low so that the corresponding mag-
netic flux swing in the core of the transformer does not produce
unacceptable audible noise.
To detect when the switching frequency has dropped close
to the upper threshold of the audible range, the switching fre- Fig. 3. Principle of operation corresponding to Fig. 2 on the example of the
flyback converter.
quency has to be monitored. The switching frequency can be
directly monitored or indirectly monitored by monitoring either
the feedback voltage or the load current.
After detecting that the switching frequency has dropped
close to the upper threshold of the audible range, the peak value
of the main switch current pulses is decreased in a discrete
step. Consequently, the switching frequency increases (Δfsw in
Fig. 4) in order to provide the same power to the load. Three
methods can be used to decrease the peak value of the main
switch current pulses. First, by decreasing the reference value
of the current-sense voltage VCS,Ref ; second, by adding a dc
bias to the current-sense voltage VCS ; and, third, by increasing
the value of the current-sense resistor RCS .
To prevent the oscillation of the switching frequency when the
peak value of the main switch current pulses changes between
two consecutive discrete values, a hysteresis can be added to the
control of the switching frequency, as illustrated in Fig. 5.
It should be noted that the switching frequency control by
employing three discrete peak values of the main switch current Fig. 4. Basic method of ANR.
1676 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

Fig. 5. ANR method with hysteresis.

Fig. 7. Simplified block diagram of the ANR circuit.

As mentioned earlier, the switching frequency can also be indi-

Fig. 6. ANR method where ANR is disabled at very light loads and no load. rectly monitored by monitoring the feedback voltage or the load
current. In that case, the input of the ANR block is connected to
the output of the EA or to the output of the load current sensing
pulses as shown in Figs. 4 and 5 is an illustrative example and
circuit, respectively. It is also shown in Fig. 7 that the output of
that the number of the discrete peak values of the main switch
the ANR circuit, i.e., the output of the peak current program-
current pulses can be selected from a minimum value of 2 to a
ming block, can modify either current-sense reference voltage
finite large number.
VCS,Ref , current-sense voltage VCS , or current-sense resistor
At very light loads and at no load, an increased switching fre-
RCS .
quency will result in increased switching losses. Consequently,
meeting standard requirements that limit the maximum input
III. IMPLEMENTATION
power at very light loads and at no load can be an issue. If
necessary, at very light loads and at no load, the audible noise The implementation of the ANR circuit is based on the
reduction circuit can be disabled and the switching frequency method shown in Fig. 6. The ANR circuit is implemented by
decreased to its original value as illustrated in Fig. 6 at ILoad = directly monitoring the switching frequency and by adding a dc
ILoad3 . In fact, in Fig. 6, the switching frequency is decreased bias to the current-sense voltage in order to decrease the peak
by increasing the peak value of the main switch current pulses value of the main switch current pulses. For simplicity, only two
to the original peak value IPeak1 . It should be noted that at very discrete peak values of the main switch current pulses are em-
light loads and at no load, the original switching frequency is, ployed to control the switching frequency. The simplified circuit
typically, close to the lower threshold of the audible range and, diagram of the ANR circuit is presented in Fig. 8. Key wave-
therefore, a larger peak value of the main switch current pulses forms that illustrate the operation of the circuit are presented in
and, consequently, a larger magnetic flux swing in the core of Figs. 9 and 10.
the transformer will not produce unacceptable audible noise, The control of the switching frequency at the upper threshold
which is the result of the nonlinear sensitivity of the human ear of the audible range around load current ILoad = ILoad1 shown in
to the audible frequencies [23]. Fig. 6 is implemented in Block H in Fig. 8, whereas the control
A simplified block diagram of the audible noise reduction of the switching frequency inside the audible range at very light
(ANR) circuit is shown in Fig. 7, where the switching frequency loads around ILoad = ILoad3 shown in Fig. 6 is implemented in
is directly monitored by monitoring the switch driving signal. Block L in Fig. 8.
HUBER AND JOVANOVIĆ: METHODS OF REDUCING AUDIBLE NOISE CAUSED BY MAGNETIC COMPONENTS 1677

Fig. 8. Simplified circuit diagram of the ANR circuit.

Fig. 10. Key waveforms that illustrate the operation of the circuit in Fig. 8 at
very light load IL o a d = IL o a d 3 shown in Fig. 6, where the switching frequency
decreases to threshold level fsw T h L 1 inside the audible range.

capacitors are discharged by briefly turning ON the respective

Fig. 9. Key waveforms that illustrate the operation of the circuit in Fig. 8 at ramp switches SWH 1 and SWL 1 in parallel with the ramp ca-
load current IL o a d = IL o a d 1 shown in Fig. 6, where the switching frequency pacitors. The control signal for the ramp switches is obtained
decreases close to the upper threshold of the audible range. by differentiating the gate drive signal of the main switch.
The detection of the switching frequency at the upper thresh-
old of the audible range is achieved by comparing ramp volt-
The switching frequency, i.e., the switching period, is moni- age vRam pH to the reference voltage VCom pH Ref at the inputs
tored by converting time to voltage. The ramp voltages, vRam pH of comparator COMPH , whereas the detection of the switch-
and vRam pL , are generated by charging the respective ramp ing frequency inside the audible range at very light loads is
capacitors CH and CL with a constant current, IH and IL , re- achieved by comparing ramp voltage vRam pL to the reference
spectively. At the beginning of a switching period, the ramp voltage VCom pL Ref at the inputs of comparator COMPL . To
1678 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

control the switching frequency according to the method shown sequently, the output voltage of comparator COMPH and D in-
in Fig. 6, each reference voltage has two discrete levels. It should put of D flip-flop FFH become HIGH. At the beginning of the
be noted that the ramp voltages are clamped by Zener diodes next switching cycle, [T1 , T2 ], at the positive edge of the gate
ZDH and ZDL to a level slightly higher than the voltage of the drive signal, the data at D input of D flip-flops are transferred to
respective reference voltage sources VRefH and VRefL . Q output of the flip-flops, resulting in QFFH = 1 and QFFL =
The output voltage of a comparator becomes HIGH if the 0. Consequently, the output of AND gate AND1 becomes HIGH
switching frequency is equal to or smaller than the relevant and the peak value of the main switch current pulses decreases
reference frequency, i.e., if the switching period is equal to or from IPeak1 to IPeak2 . It should be noted in Fig 9 that the gate
greater than the relevant reference period. The information about drive pulse width in switching cycle [T0 , T1 ] is larger than the
the switching frequency obtained in the current switching cycle gate drive pulse width in the succeeding switching cycles. To
is used in the next switching cycle to control the peak value of keep the output voltage of the power converter constant, the
the main switch current pulses. In fact, the voltage level at the feedback voltage increases, resulting in an increased switching
output of a comparator is stored in the corresponding D flip- frequency.
flop at the positive edge of the gate drive signal. It should be When output Q of D flip-flop FFH becomes HIGH, the refer-
noted that the output voltage of a comparator can easily meet the ence voltage of comparator COMPH decreases from HIGH to
setup-time requirement of a positive-edge triggered D flip-flop LOW level, VCom pH Ref = VRefH ·RH2 /(RH1 + RH2 ). As long as
due to the delay time of the comparator. Initially, all D flip-flops the switching frequency is lower than fswThH2 , i.e., the switching
are reset through the direct reset pins. period is larger than TswThH2 , ramp voltage vRam pH will always
The peak current programming block is implemented by cross the LOW reference voltage level of comparator COMPH ,
adding a dc bias to the current-sense voltage in order to de- and therefore, output Q of D flip-flop FFH will remain HIGH,
crease the peak value of the main switch current pulses. When keeping the output of AND gate AND1 HIGH.
the output of AND gate AND1 is LOW, switch SW1 is open and The waveforms in Fig. 10 illustrate the operation of the circuit
the current-sense voltage vCS is equal to the voltage across the in Fig. 8 at very light load ILoad = ILoad3 shown in Fig. 6, where
current-sense resistor. It should be noted in Fig. 8 that resis- the switching frequency decreases to threshold level fswThL1 in-
tor R1 and capacitor C1 make a conventional low-pass filter at side the audible range and, consequently, the peak value of
the current-sense input of the control circuit. When the output the switch current pulses increases from IPeak2 to IPeak1 , re-
of AND gate AND1 is HIGH, switch SW1 is closed and the sulting in a further decreased switching frequency as shown in
current-sense voltage vCS is determined as follows: Fig. 6.
Before instant t=T0 , the output voltage of D flip-flops FFH
R2 R1 and FFL is HIGH and LOW, respectively. Therefore, the output
vCS = · RCS iQ + · VCC (1)
R1 + R2 R1 + R2 of AND gate AND1 is HIGH and IPeak = IPeak2 . The reference
where iQ is the main switch current. Equation (1) can be rewrit- voltage of both comparators, VCom pH Ref and VCom pL Ref , is
ten as follows: LOW. During switching cycle [T0 , T1 ], the switching frequency
  decreases below threshold frequency fswThL1 , i.e., the switch-
R2 R1 ing period increases above threshold period TswThL1 , and ramp
vCS = · RCS iQ + · VCC
R1 + R2 R2 voltage vRam pL crosses the reference voltage level of compara-
(2) tor COMPL . Consequently, the output voltage of comparator
R1
≈ RCS iQ + · VCC COMPL and D input of D flip-flop FFL become HIGH. At the
R2
beginning of the next switching cycle, [T1 , T2 ], at the positive
because R2  R1 . The second term in (2) represents the dc bias edge of the gate drive signal, the HIGH logic level at D input
of the current-sense voltage. of D flip-flop FFL is transferred to its Q output, resulting in
The waveforms in Fig. 9 illustrate the operation of the circuit QFFL = 1. Consequently, the output of AND gate AND1 be-
in Fig. 8 at ILoad = ILoad1 shown in Fig. 6, where the switching comes LOW and the peak value of the main switch current
frequency decreases close to the upper threshold of the audible pulses increases from IPeak2 to IPeak1 . It should be noted
range and, consequently, the peak value of the main switch in Fig 10 that the gate drive pulse width in switching cycle
current pulses decreases from IPeak1 to IPeak2 , resulting in an [T0 , T1 ] is smaller than the gate drive pulse width in the succeed-
increased switching frequency, Δfsw in Fig. 6. ing switching cycles. To keep the output voltage of the power
Before instant t = T0 , the output voltage of both D flip-flops, converter constant, the feedback voltage decreases, resulting in
FFH and FFL , is LOW, and therefore, the output of AND gate a further decreased switching frequency.
AND1 is LOW and IPeak = IPeak1 . The reference voltage of When output Q of D flip-flop FFL becomes HIGH, the ref-
comparator COMPH has HIGH value, VCom pH Ref = VRefH , erence voltage of comparator COMPL increases from LOW to
whereas the reference voltage of comparator COMPL has LOW HIGH level, VRefL . As long as the switching frequency is lower
value, VCom pL Ref = VRefL ·RL 2 /(RL 1 + RL 2 ). During switch- than fswThL2 , i.e., the switching period is larger than TswThL2 ,
ing cycle [T0 , T1 ], the switching frequency decreases below ramp voltage vRam pL will always cross the HIGH reference
threshold frequency fswThH1 , i.e., the switching period increases voltage level of comparator COMPL and, therefore, output Q of
above threshold period TswThH1 , and ramp voltage vRam pH D flip-flop FFL will remain HIGH, keeping the output of AND
crosses the reference voltage level of comparator COMPH . Con- gate AND1 LOW.
HUBER AND JOVANOVIĆ: METHODS OF REDUCING AUDIBLE NOISE CAUSED BY MAGNETIC COMPONENTS 1679

Fig. 11. Worst case “A”-weighted FFT spectrum measurements obtained at 110-Vrm s line voltage (a) without and (b) with ANR circuit.

IV. EXPERIMENTAL RESULTS TABLE I

WORST CASE AUDIBLE NOISE MEASURMENTS
The ANR circuit in Fig. 8 was applied in a 90-W single-
stage PFC flyback adapter with VSF [22]. The audible noise
is measured as the “A” weighted sound pressure level (SPL)
relative to 20 μPa, which is the lower threshold of the human
perception of sound [23], i.e.,

p
LpA [dB(A)] = 20 log + LwA [dB] (3)
20 μPa

where p is the measured sound pressure in μPa before weighting

and LwA is the transfer function of the “A” weighting network
follows:
employed to compensate the characteristic of the human ear,
which is differently sensitive to different frequencies. In fact, the  

transfer function of the “A” weighting network is approximately LpA,tot [dB(A)] = 10 log 10 L p A , k /10
(4)
equal to the inverted equal loudness level contour of the human k
ear at a lower SPL.
The measured SPL after “A” weighting is converted into the where LpA,k is the “A” weighted SPL of the kth 1/3-octave band.
frequency domain by using fast Fourier transform (FFT), as The audible noise limits for power supplies can be specified
shown in Fig. 11. by the 1/3-octave-band SPL limits or by the total SPL limit. The
To obtain the total SPL, a frequency analysis is performed by audible noise measurement methods are specified in [24]. The
dividing the audible range into 1/3-octave bands [24]. This fre- audible noise was measured by using the PULSE 3560C system
quency analysis is called constant-percentage-bandwidth anal- from Bruel and Kjaer (B&K). The B&K 4190 microphone was
ysis because the ratio of the upper and lower limits of each band used. The measurement was performed in a 45 cm × 45 cm ×
is constant and the bandwidth is a constant percentage of the 65 cm anechoic chamber.
band center frequency. In each 1/3-octave band, based on the Audible noise measurement results are presented in Table I.
FFT spectrum, the rms value of the “A” weighted sound pres- It can be seen from Table I that the worst case audible noise at
sure is determined and plotted as a function of the band center 110-Vrm s line voltage is significantly reduced from 29.0 dB(A)
frequency, as shown in Fig. 12. The total SPL is obtained as to 20.2 dB(A). The corresponding “A”-weighted FFT-spectrum
1680 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011

Fig. 12. Worst case “A”-weighted 1/3-octave frequency spectrum measurements obtained at 110-Vrm s line voltage (a) without and (b) with ANR circuit.

and 1/3-octave-spectrum measurements are shown in Figs. 11 disabled and the switching frequency decreased to its original
and 12, respectively. value.
The experimental ANR circuit is implemented by directly
monitoring the switching frequency and by adding a dc bias to
V. SUMMARY the current-sense voltage in order to decrease the peak value of
the main switch current pulses. The experimental ANR circuit
Methods and a circuit implementation for reducing audible
was applied to a 90-W single-stage PFC flyback adapter. Worst
noise caused by magnetic components in switch-mode convert-
case audible noise measurements are provided.
ers with VSF and with CFC, where the switching frequency de-
creases as the load decreases, are presented. The audible noise
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[10] W. Langeslag, R. Pagano, K. Schetters, A. Strijker, and A. Zoest, “VLSI
design and application of a high-voltage-compatible SoC-ASIC in bipolar Laszlo Huber (M’86) was born in Novi Sad,
CMOS/DMOS technology for ac/dc rectifiers,” IEEE Trans. Ind. Elec- Yugoslavia, in 1953. He received the Dipl. Eng. de-
tron., vol. 54, no. 5, pp. 2626–2641, Oct. 2007. gree from the University of Novi Sad, Novi Sad, the
[11] Z. Liang, B. Lu, J. D. Wyk, and F. C. Lee, “Integrated CoolMOS FET/SiC- M.S. degree from the University of Niš, Niš, Yu-
diode module for high performance power switching,” IEEE Trans. Power goslavia, and the Ph.D. degree from the University of
Electron., vol. 20, no. 3, pp. 679–686, May 2005. Novi Sad in 1977, 1983, and 1992, respectively, all
[12] L. Lorenz, “Power semiconductor devices and smart power IC’s – The in electrical engineering.
enabling technology for future high efficient power conversion systems,” From 1977 to 1992, he was an Instructor at the In-
in Proc. IEEE Int. Power Electron. Motion Control Conf. (IPEMC), May stitute for Power and Electronics, University of Novi
2009, pp. 193–201. Sad. In 1992, he joined the Virginia Power Electron-
[13] C. Yan, F. Li, J. Zeng, T. Liu, and J. Ying, “A novel transformer structure ics Center at Virginia Tech, Blacksburg, as a Visiting
for high power high frequency converter,” in Proc. IEEE Power Electron. Professor. From 1993 to 1994, he was a Research Scientist at the Virginia Power
Specialists Conf. (PESC), Jun. 2007, pp. 214–218. Electronics Center. Since 1994, he has been a Senior Member of the R&D Staff
[14] Lj. D. Stevanović, K. S. Matocha, P. A. Losee, J. S. Glaser, J. J. Nasadoski, at the Power Electronics Laboratory, Delta Products Corporation, Research Tri-
and S. D. Arthur, “Recent advances in Silicon Carbide MOSFET power angle Park, NC, the Advanced R&D unit of Delta Electronics, Inc., Taiwan,
devices,” in Proc. IEEE Appl. Power Electron. Conf. (APEC), Feb. 2010, one of the world’s largest manufacturers of power supplies. He has published
pp. 401–407. more than 80 technical papers and holds four U.S. patents. His research inter-
[15] M. A. Khan, G. Simin, S. G. Pytel, A. Monti, E. Santi, and J. L. Hudgins, ests include the analysis, simulation, and design of high-frequency, high-power
“New developments in Gallium Nitride and the impact on power electron- density, single-phase and three-phase power processors; modeling, simulation,
ics,” in Proc. IEEE Power Electron. Specialists Conf. (PESC), Jun. 2005, evaluation, and application of high-power semiconductor devices; and model-
pp. 15–26. ing, simulation, analysis, and design of analog and digital electronics circuits.
[16] N. Ikeda, Y. Niiyama, H. Kambayashi, Y. Sato, T. Nomura, S. Kato, Dr. Huber is the recipient of the IEEE Power Electronics Society Transactions
and S. Yoshida, “GaN power transistors on Si substrates for switching Prize Paper Award for the best paper published in 2009 and of the Yugoslav
applications,” Proc. IEEE, vol. 98, no. 7, pp. 1151–1161, Jul. 2010. Conference on Electronics, Telecommunication, Automation, and Nuclear Tech-
[17] B. Weisner, H. Pfutzner, and J. Anger, “Relevance of magnetostriction and nique Best Paper Award in 1990.
forces for the generation of audible noise of transformer cores,” IEEE
Trans. Magn., vol. 36, no. 5, pp. 3759–3777, Sep. 2000.
[18] F. L’ Hermite “Method and apparatus for reducing audible acoustical noise
in power supply transformer by shaping the waveform of a primary side
inductor current,” U.S. Patent 6 477 066, Nov. 5, 2002.
[19] B. Balakrishnan, A. B. Djenguerian, and K. Wong. “Method and apparatus
Milan M. Jovanović (S’85–M’88–SM’89–F’01)
for reducing audio noise in switching regulator,” U.S. Patent 6 525 514,
was born in Belgrade, Serbia. He received the Dipl.
Feb. 15, 2003.
Ing. degree in electrical engineering from the Univer-
[20] J. W. Hall and C. Basso “Low audible noise power supply method and sity of Belgrade, Belgrade.
controller therefore,” U.S. Patent Application 0 171 179, Aug. 3, 2006.
He is currently the Chief Technology Officer of the
[21] W. H. M. Langeslag and J. W. Strijker, “Noise reduction in a power con-
Power Systems Business Group of Delta Electronics,
verter,” U.S. Patent 7 202 609, Apr. 10, 2007.
Inc., Taiwan, one of the world’s largest manufacturers
[22] L. Huber, M. M. Jovanović, and C. C. Chang. “AC/DC flyback converter,” of power supplies, and the Vice President for R&D of
U.S. Patent 6 950 319, Sep. 27, 2005.
Delta Products Corporation, Research Triangle Park,
[23] M. Norton and D. Karczub, Fundamentals of Noise and Vibration analysis
NC.
for Engineers. Cambridge, U.K.: Cambridge Univ. Press, 2003.