RTL8370MB

LAYER 2 MANAGED 8+2-PORT 10/100/1000

SWITCH CONTROLLER

DRAFT DATASHEET
(CONFIDENTIAL: Development Partners Only)

Rev. 0.2
Aug 11, 2015
Track ID:

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
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USING THIS DOCUMENT

This document is intended for the hardware and software engineer‟s general information on the Realtek
RTL8370MB IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.

REVISION HISTORY
Revision Release Date Summary
0.1 2015-05-26 First release.
0.2 2015-08-11 Revise some description and error.
Add chapter 10.5.2 SPI FLASH Interface Timing Characteristics,10.5.13~10.5.16
SGMII/1000Base-X/100FX Interface Timing Characteristics

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Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
2. FEATURES ......................................................................................................................................................................... 3
3. BLOCK DIAGRAM ........................................................................................................................................................... 5
4. SYSTEM APPLICATION ................................................................................................................................................. 6
4.1. 8-PORT 1000BASE-T+2-PORT 1000BASE-X/100BASE-FX SWITCH ............................................................................ 6
4.2. 8-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII............................................................................................... 7
4.3. 8-PORT 1000BASE-T ROUTER WITH DUAL SGMII ...................................................................................................... 8
5. PIN ASSIGNMENTS ......................................................................................................................................................... 9
5.1. PACKAGE IDENTIFICATION ........................................................................................................................................... 9
5.2. PIN ASSIGNMENT TABLE ............................................................................................................................................ 10
6. PIN DESCRIPTIONS ...................................................................................................................................................... 13
6.1. MEDIA DEPENDENT INTERFACE PINS ......................................................................................................................... 13
6.2. RGMII INTERFACE PINS ............................................................................................................................................ 14
6.3. MII/TMII INTERFACE PINS ........................................................................................................................................ 15
6.4. RMII INTERFACE PINS ............................................................................................................................................... 17
6.5. SERDES INTERFACE PINS ........................................................................................................................................... 18
6.6. PARALLEL LED PINS ................................................................................................................................................. 18
6.7. SERIAL MODE LED PINS............................................................................................................................................ 20
6.8. SPI FLASH INTERFACE PINS ..................................................................................................................................... 20
6.9. UART INTERFACE PINS ............................................................................................................................................. 20
6.10. CPU INTERFACE PINS ................................................................................................................................................ 21
6.11. GPIO INTERFACE PINS ............................................................................................................................................... 21
6.12. CONFIGURATION STRAPPING PINS ............................................................................................................................. 22
6.13. MISCELLANEOUS PINS ............................................................................................................................................... 24
6.14. TEST PINS .................................................................................................................................................................. 25
6.15. POWER AND GND PINS .............................................................................................................................................. 26
7. PHYSICAL LAYER FUNCTIONAL OVERVIEW...................................................................................................... 27
7.1. MDI INTERFACE ........................................................................................................................................................ 27
7.2. 1000BASE-T TRANSMIT FUNCTION ........................................................................................................................... 27
7.3. 1000BASE-T RECEIVE FUNCTION .............................................................................................................................. 27
7.4. 100BASE-TX TRANSMIT FUNCTION........................................................................................................................... 27
7.5. 100BASE-TX RECEIVE FUNCTION ............................................................................................................................. 27
7.6. 10BASE-T TRANSMIT FUNCTION ............................................................................................................................... 28
7.7. 10BASE-T RECEIVE FUNCTION .................................................................................................................................. 28
7.8. AUTO-NEGOTIATION FOR UTP .................................................................................................................................. 28
7.9. CROSSOVER DETECTION AND AUTO CORRECTION ..................................................................................................... 28
7.10. POLARITY CORRECTION ............................................................................................................................................. 28
8. GENERAL FUNCTION DESCRIPTION ...................................................................................................................... 30
8.1. RESET ........................................................................................................................................................................ 30
8.1.1. Hardware Reset .................................................................................................................................................... 30
8.1.2. Software Reset ...................................................................................................................................................... 30
8.2. IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................ 30
8.3. HALF DUPLEX FLOW CONTROL ................................................................................................................................. 31
8.3.1. Back-Pressure Mode ............................................................................................................................................ 31
8.4. SEARCH AND LEARNING ............................................................................................................................................ 31
8.5. SVL AND IVL/SVL ................................................................................................................................................... 32
8.6. ILLEGAL FRAME FILTERING ....................................................................................................................................... 32

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8.7. IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL ............................................................................. 32
8.8. BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL ..................................................................................... 33
8.9. PORT SECURITY FUNCTION ........................................................................................................................................ 33
8.10. MIB COUNTERS ......................................................................................................................................................... 33
8.11. PORT MIRRORING ...................................................................................................................................................... 33
8.12. VLAN FUNCTION ...................................................................................................................................................... 33
8.12.1. Port-Based VLAN ............................................................................................................................................ 34
8.12.2. IEEE 802.1Q Tag-Based VLAN ....................................................................................................................... 34
8.12.3. Protocol-Based VLAN ..................................................................................................................................... 35
8.12.4. Port VID .......................................................................................................................................................... 35
8.13. QOS FUNCTION .......................................................................................................................................................... 35
8.13.1. Input Bandwidth Control ................................................................................................................................. 36
8.13.2. Priority Assignment ......................................................................................................................................... 36
8.13.3. Priority Queue Scheduling............................................................................................................................... 36
8.13.4. IEEE 802.1p/Q and DSCP Remarking ............................................................................................................ 37
8.13.5. ACL-Based Priority ......................................................................................................................................... 37
8.14. IGMP & MLD SNOOPING FUNCTION......................................................................................................................... 37
8.15. IEEE 802.1X FUNCTION ............................................................................................................................................. 37
8.15.1. Port-Based Access Control .............................................................................................................................. 37
8.15.2. Authorized Port-Based Access Control ........................................................................................................... 38
8.15.3. Port-Based Access Control Direction .............................................................................................................. 38
8.15.4. MAC-Based Access Control............................................................................................................................. 38
8.15.5. MAC-Based Access Control Direction ............................................................................................................ 38
8.15.6. Optional Unauthorized Behavior..................................................................................................................... 38
8.15.7. Guest VLAN ..................................................................................................................................................... 38
8.16. IIEEE 802.1D FUNCTION ........................................................................................................................................... 38
8.17. EMBEDDED 8051 ........................................................................................................................................................ 39
8.18. REALTEK CABLE TEST (RTCT) ................................................................................................................................. 39
8.19. LED INDICATOR ........................................................................................................................................................ 39
8.19.1. Parallel LED Mode.......................................................................................................................................... 40
8.19.2. Serial LED Mode ............................................................................................................................................. 41
8.20. GREEN ETHERNET ...................................................................................................................................................... 44
8.20.1. Link-On and Cable Length Power Saving ....................................................................................................... 44
8.20.2. Link-Down Power Saving ................................................................................................................................ 44
8.21. IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ............................................................................... 44
8.22. INTERRUPT PIN FOR EXTERNAL CPU ......................................................................................................................... 45
9. INTERFACE DESCRIPTIONS ...................................................................................................................................... 46
9.1. I2C MASTER FOR EEPROM AUTO-LOAD ................................................................................................................... 46
9.2. I2C-LIKE SLAVE INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8370MB ............................................................ 47
9.3. SLAVE MII MANAGEMENT SMI INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8370MB .................................... 48
9.4. SLAVE SPI INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8370MB..................................................................... 48
9.5. SPI FLASH INTERFACE ............................................................................................................................................. 49
9.6. EXTENSION GMAC1 & GMAC2 RGMII/MII/TMII/RMII INTERFACE ..................................................................... 49
9.6.1. Extension GMAC1 and GMAC2 RGMII Mode..................................................................................................... 50
9.6.2. Extension GMAC1 and GMAC2 Full Duplex MII MAC/PHY Mode Interface .................................................... 53
9.6.3. Extension GMAC1 and GMAC2 Full Duplex TMII MAC/PHY Mode Interface .................................................. 57
9.6.4. Extension GMAC1 and GMAC2 RMII MAC/PHY Mode Interface ...................................................................... 61
9.7. EXTENSION GMAC1 & GMAC2 SGMII/1000BASE-X/100BASE-FX INTERFACE..................................................... 65
9.7.1. Extension GMAC1 and GMAC2 SGMII Interface ................................................................................................ 65
9.7.2. Extension GMAC1 and GMAC2 1000Base-X/100Base-FX Interface .................................................................. 66
10. ELECTRICAL CHARACTERISTICS .......................................................................................................................... 67
10.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 67
10.2. RECOMMENDED OPERATING RANGE.......................................................................................................................... 67
10.3. THERMAL CHARACTERISTICS .................................................................................................................................... 67
10.3.1. TQFP-176-EPAD ............................................................................................................................................ 67
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10.4. DC CHARACTERISTICS ............................................................................................................................................... 69
10.5. AC CHARACTERISTICS ............................................................................................................................................... 71
10.5.1. I2C Master for EEPROM Auto-load Interface Timing Characteristics ........................................................... 71
10.5.2. SPI FLASH Interface Timing Characteristics ................................................................................................. 72
10.5.3. I2C-Like Slave Mode for External CPU Access Interface Timing Characteristics .......................................... 73
10.5.4. Slave MII Management SMI for External CPU Access Interface Timing Characteristics .............................. 73
10.5.5. Slave SPI for External CPU Access Interface Timing Characteristics ............................................................ 75
10.5.6. RGMII Timing Characteristics ........................................................................................................................ 76
10.5.7. MII MAC Mode Timing ................................................................................................................................... 78
10.5.8. MII PHY Mode Timing .................................................................................................................................... 79
10.5.9. TMII MAC Mode Timing ................................................................................................................................. 80
10.5.10. TMII PHY Mode Timing .................................................................................................................................. 81
10.5.11. RMII MAC Mode Timing ................................................................................................................................. 82
10.5.12. RMII PHY Mode Timing .................................................................................................................................. 83
10.5.13. SGMII Differential Transmitter Characteristics.............................................................................................. 84
10.5.14. SGMII Differential Receiver Characteristics .................................................................................................. 85
10.5.15. 1000Base-X/100Base-FX Differential Transmitter Characteristics ................................................................ 86
10.5.16. 1000Base-X/100Base-FX Differential Receiver Characteristics ..................................................................... 87
10.6. POWER AND RESET CHARACTERISTICS ...................................................................................................................... 88
11. MECHANICAL DIMENSIONS...................................................................................................................................... 89
12. ORDERING INFORMATION ........................................................................................................................................ 90

List of Tables
TABLE 1. PIN ASSIGNMENT TABLE ............................................................................................................................................... 10
TABLE 2. MEDIA DEPENDENT INTERFACE PINS............................................................................................................................. 13
TABLE 3. RGMII INTERFACE PINS ................................................................................................................................................ 14
TABLE 4. MII/TMII INTERFACE PINS ............................................................................................................................................ 15
TABLE 5. RMII INTERFACE PINS ................................................................................................................................................... 17
TABLE 6. SERDES INTERFACE PINS ............................................................................................................................................... 18
TABLE 7. PARALLEL LED PINS ..................................................................................................................................................... 18
TABLE 8. SERIAL MODE LED PINS ............................................................................................................................................... 20
TABLE 9. SPI FLASH INTERFACE PINS ......................................................................................................................................... 20
TABLE 10. UART INTERFACE PINS ............................................................................................................................................... 20
TABLE 11. CPU INTERFACE PINS .................................................................................................................................................. 21
TABLE 12. GPIO INTERFACE PINS ................................................................................................................................................ 21
TABLE 13. CONFIGURATION STRAPPING PINS ............................................................................................................................... 22
TABLE 14. CONFIGURATION STRAPPING PINS CONFIGURE NOTE .................................................................................................. 24
TABLE 15. MISCELLANEOUS PINS ................................................................................................................................................. 24
TABLE 16. TEST PINS .................................................................................................................................................................... 25
TABLE 17. POWER AND GND PINS ................................................................................................................................................ 26
TABLE 18. MEDIA DEPENDENT INTERFACE PIN MAPPING ............................................................................................................ 28
TABLE 19. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE ......................................................................................... 32
TABLE 20. LED DEFINITIONS........................................................................................................................................................ 39
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TABLE 21. RTL8231 SHIFT REGISTER MODE STRAPPING PINS CONFIGURATION ......................................................................... 43
TABLE 22. SLAVE MII MANAGEMENT SMI ACCESS FORMAT....................................................................................................... 48
TABLE 23. RTL8370MB GENERAL PURPOSE INTERFACES PIN DEFINITIONS ................................................................................ 50
TABLE 24. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................. 67
TABLE 25. RECOMMENDED OPERATING RANGE ........................................................................................................................... 67
TABLE 26. ASSEMBLY DESCRIPTION ............................................................................................................................................. 67
TABLE 27. MATERIAL PROPERTIES ............................................................................................................................................... 68
TABLE 28. SIMULATION CONDITIONS ........................................................................................................................................... 68
TABLE 29. THERMAL PERFORMANCE OF E-PAD TQFP-176 ON PCB UNDER STILL AIR CONVECTION ......................................... 69
TABLE 30. THERMAL PERFORMANCE OF E-PAD TQFP-176 ON PCB UNDER FORCED CONVECTION ............................................ 69
TABLE 31. DC CHARACTERISTICS................................................................................................................................................. 69
TABLE 32. MASTER I2C FOR EEPROM AUTO-LOAD TIMING CHARACTERISTICS ......................................................................... 72
TABLE 33. SPI FLASH AC TIMING .............................................................................................................................................. 72
TABLE 34. SLAVE I2C-LIKE FOR EXTERNAL CPU ACCESS INTERFACE TIMING CHARACTERISTICS.............................................. 73
TABLE 35. SLAVE SMI (MDC/MDIO) TIMING CHARACTERISTICS AND REQUIREMENTS ............................................................. 74
TABLE 36. SLAVE SPI FOR EXTERNAL CPU ACCESS INTERFACE TIMING CHARACTERISTICS AND REQUIREMENTS ..................... 75
TABLE 37. RGMII TIMING CHARACTERISTICS .............................................................................................................................. 77
TABLE 38. MII MAC MODE TIMING ............................................................................................................................................. 78
TABLE 39. MII PHY MODE TIMING CHARACTERISTICS ................................................................................................................ 79
TABLE 40. TMII MAC MODE TIMING .......................................................................................................................................... 80
TABLE 41. TMII PHY MODE TIMING CHARACTERISTICS ............................................................................................................. 81
TABLE 42. RMII MAC MODE TIMING CHARACTERISTICS ............................................................................................................ 82
TABLE 43. RMII PHY MODE TIMING CHARACTERISTICS ............................................................................................................. 83
TABLE 44. SGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS............................................................................................ 84
TABLE 45. SGMII DIFFERENTIAL RECEIVER CHARACTERISTICS .................................................................................................. 85
TABLE 46. 1000BASE-X/100BASE-FX DIFFERENTIAL TRANSMITTER CHARACTERISTICS ............................................................ 86
TABLE 47. 1000BASE-X/100BASE-FX DIFFERENTIAL RECEIVER CHARACTERISTICS ................................................................... 87
TABLE 48. POWER AND RESET CHARACTERISTICS ........................................................................................................................ 88
TABLE 49. ORDERING INFORMATION ............................................................................................................................................ 90

List of Figures
FIGURE 1 BLOCK DIAGRAM OF RTL8370MB ................................................................................................................................. 5
FIGURE 2 8-PORT 1000BASE-T+2-PORT 1000BASE-X/100BASE-FX SWITCH ................................................................................ 6
FIGURE 3 8-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII .................................................................................................. 7
FIGURE 4 8-PORT 1000BASE-T ROUTER WITH DUAL SGMII .......................................................................................................... 8
FIGURE 5. PIN ASSIGNMENTS .......................................................................................................................................................... 9
FIGURE 6. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION .................................................................................................... 29
FIGURE 7. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART ................................................................................... 35
FIGURE 8. RTL8370MB MAX-MIN SCHEDULING DIAGRAM ...................................................................................................... 36
FIGURE 9. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED ............................................................................ 40
FIGURE 10. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED .................................................................................. 41
FIGURE 11. RTL8370MB SERIAL LED MODE SHIFT SEQUENCE (PER-PORT THREE SINGLE-COLOR LED) ....................................... 41
FIGURE 12. RTL8370MB+74HC164 SERIAL LED CONNECTION DIAGRAM (PER-PORT THREE SINGLE-COLOR LED) .................. 42
FIGURE 13. RTL8231 OUTPUT DATA SEQUENCE .......................................................................................................................... 42
FIGURE 14. RTL8370MB+RTL8231 SERIAL LED CONNECTION DIAGRAM (PER-PORT THREE SINGLE-COLOR LED) .................. 43
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FIGURE 15. RTL8370MB SERIAL LED MODE SHIFT SEQUENCE (PER-PORT TWO SINGLE-COLOR LED) .......................................... 43
FIGURE 16. RTL8370MB SERIAL LED MODE SHIFT SEQUENCE (PER-PORT ONE SINGLE-COLOR LED) ........................................... 44
FIGURE 17. I2C START AND STOP COMMAND ............................................................................................................................... 46
FIGURE 18. I2C MASTER FOR EEPROM AUTO-LOAD INTERFACE CONNECTION EXAMPLE .......................................................... 46
FIGURE 19. 8-BIT EEPROM SEQUENTIAL READ .......................................................................................................................... 46
FIGURE 20. 16-BIT EEPROM SEQUENTIAL READ ........................................................................................................................ 46
FIGURE 21. I2C-LIKE SLAVE FOR EXTERNAL CPU ACCESS INTERFACE CONNECTION EXAMPLE ................................................. 47
FIGURE 22. I2C-LIKE SLAVE INTERFACE WRITE COMMAND ........................................................................................................ 47
FIGURE 23. I2C-LIKE SLAVE INTERFACE READ COMMAND .......................................................................................................... 47
FIGURE 24. SLAVE MII MANAGEMENT SMI INTERFACE CONNECTION EXAMPLE......................................................................... 48
FIGURE 25. SLAVE SPI FOR EXTERNAL CPU ACCESS INTERFACE CONNECTION EXAMPLE .......................................................... 48
FIGURE 26. SLAVE SPI FOR EXTERNAL CPU ACCESS WRITE COMMAND ..................................................................................... 49
FIGURE 27. SLAVE SPI FOR EXTERNAL CPU ACCESS READ COMMAND ....................................................................................... 49
FIGURE 28. SPI FLASH INTERFACE CONNECTION EXAMPLE ....................................................................................................... 49
FIGURE 29. SIGNAL DIAGRAM OF RGMII MODE OF THE EXTENSION GMAC1 ............................................................................. 51
FIGURE 30. SIGNAL DIAGRAM OF RGMII MODE OF THE EXTENSION GMAC2 ............................................................................. 52
FIGURE 31. SIGNAL DIAGRAM OF MII PHY MODE OF THE EXTENSION GMAC1.......................................................................... 53
FIGURE 32. SIGNAL DIAGRAM OF MII MAC MODE OF THE EXTENSION GMAC1 ........................................................................ 54
FIGURE 33. SIGNAL DIAGRAM OF MII PHY MODE OF THE EXTENSION GMAC2.......................................................................... 55
FIGURE 34. SIGNAL DIAGRAM OF MII MAC MODE OF THE EXTENSION GMAC2 ........................................................................ 56
FIGURE 35. SIGNAL DIAGRAM OF TMII PHY MODE OF THE EXTENSION GMAC1 ....................................................................... 57
FIGURE 36. SIGNAL DIAGRAM OF TMII MAC MODE OF THE EXTENSION GMAC1 ...................................................................... 58
FIGURE 37. SIGNAL DIAGRAM OF TMII PHY MODE OF THE EXTENSION GMAC2 ....................................................................... 59
FIGURE 38. SIGNAL DIAGRAM OF TMII MAC MODE OF THE EXTENSION GMAC2 ...................................................................... 60
FIGURE 39. SIGNAL DIAGRAM OF RMII PHY MODE OF THE EXTENSION GMAC1 ....................................................................... 61
FIGURE 40. SIGNAL DIAGRAM OF RMII MAC MODE OF THE EXTENSION GMAC1 ...................................................................... 62
FIGURE 41. SIGNAL DIAGRAM OF RMII PHY MODE OF THE EXTENSION GMAC2 ....................................................................... 63
FIGURE 42. SIGNAL DIAGRAM OF RMII MAC MODE OF THE EXTENSION GMAC2 ...................................................................... 64
FIGURE 43. SIGNAL DIAGRAM OF SGMII MODE OF THE EXTENSION GMAC1 & GMAC2 ........................................................... 65
FIGURE 44. SIGNAL DIAGRAM OF 1000BASE-X/100BASE-FX MODE OF THE EXTENSION GMAC1/GMAC2 ............................... 66
FIGURE 45. MASTER I2C FOR EEPROM AUTO-LOAD TIMING CHARACTERISTICS ........................................................................ 71
FIGURE 46. MASTER I2C FOR EEPROM AUTO-LOAD POWER ON TIMING .................................................................................... 71
FIGURE 47. MASTER I2C FOR EEPROM AUTO-LOAD TIMING ...................................................................................................... 71
FIGURE 48. SPI FLASH TIMING CHARACTERISTICS ..................................................................................................................... 72
FIGURE 49. SLAVE I2C-LIKE FOR EXTERNAL CPU ACCESS INTERFACE TIMING CHARACTERISTICS ............................................ 73
FIGURE 50. MDIO SOURCED BY MASTER (EXTERNAL CPU) ........................................................................................................ 74
FIGURE 51. MDIO SOURCED BY SLAVE (RTL8370MB) ............................................................................................................... 74
FIGURE 52. SLAVE SPI FOR EXTERNAL CPU ACCESS INTERFACE TIMING CHARACTERISTICS...................................................... 75
FIGURE 53. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=0)................................................................. 76
FIGURE 54. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=2NS) ............................................................ 76
FIGURE 55. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=0) .................................................................... 76
FIGURE 56. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=2NS) ................................................................ 77
FIGURE 57. MII MAC MODE CLOCK TO DATA OUTPUT DELAY TIMING ...................................................................................... 78
FIGURE 58. MII MAC MODE INPUT T IMING ................................................................................................................................. 78
FIGURE 59. MII PHY MODE OUTPUT TIMING ............................................................................................................................... 79
FIGURE 60. MII PHY MODE INPUT TIMING .................................................................................................................................. 79
FIGURE 61. TMII MAC MODE CLOCK TO DATA OUTPUT DELAY TIMING .................................................................................... 80
FIGURE 62. TMII MAC MODE INPUT TIMING ............................................................................................................................... 80
FIGURE 63. TMII PHY MODE OUTPUT TIMING ............................................................................................................................ 81
FIGURE 64. TMII PHY MODE INPUT T IMING ................................................................................................................................ 81
FIGURE 65. RMII MAC MODE OUTPUT TIMING ........................................................................................................................... 82
FIGURE 66. RMII MAC MODE INPUT TIMING............................................................................................................................... 82
FIGURE 67. RMII PHY MODE OUTPUT TIMING ............................................................................................................................ 83
FIGURE 68. RMII PHY MODE INPUT T IMING................................................................................................................................ 83
FIGURE 69. SGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM ................................................................................................. 84
FIGURE 70. SGMII DIFFERENTIAL RECEIVER EYE DIAGRAM ....................................................................................................... 85
FIGURE 71. 1000BASE-X/100BASE-FX DIFFERENTIAL TRANSMITTER EYE DIAGRAM ................................................................. 86
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FIGURE 72. 1000BASE-X/100BASE-FX DIFFERENTIAL RECEIVER EYE DIAGRAM ........................................................................ 87
FIGURE 73. POWER AND RESET CHARACTERISTICS ....................................................................................................................... 88

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1. General Description
The Realtek RTL8370MB is a TQFP176 E-PAD, high-performance 8+2-port Gigabit Ethernet switch. It
integrates 8 low-power Giga-PHYs that support 1000Base-T/100Base-T/10Base-T, and provides two
extra RGMII/MII/TMII/RMII/SGMII/1000Base-X/100Base-FX ports for specific applications. The
RTL8370MB implements all the functions of a high-speed switch system; including SRAM for packet
buffering, non-blocking switch fabric, and internal register management into a single CMOS device. Only
a 25MHz crystal is required; an optional EEPROM is offered for internal register configuration.
The embedded packet storage SRAM in the RTL8370MB features superior memory management
technology to efficiently utilize memory space. The RTL8370MB integrates a 4096-entry look-up table
with a 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write
access from the EEPROM Serial Management Interface (SMI), and each of the entries can be configured
as a static entry. The entry aging time is between 200 and 400 seconds. Eight Filtering Databases are used
to provide Independent VLAN Learning and Shared VLAN Learning (IVL/SVL) functions.
The Extension GMAC1 and Extension GMAC2 of the RTL8370MB implement dual RGMII/MII/TMII/
RMII interfaces for connecting with an external PHY or MAC in specific applications. This interface
could be connected to an external CPU or RISC as 8-port Gigabit Router applications. In router
applications, the RTL8370MB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag
on egress. When using this function, VID information carried in the VLAN tag will be changed to PVID.
Note: The RTL8370MB Extra Interface (Extension GMAC1 and Extension GMAC2) supports:
Reduced Gigabit Media Independent Interface (RGMII)
Media Independent Interface (MII)
Turbo Media Independent Interface (TMII)
Reduced Media Independent Interface (RMII)
Serial Gigabit Media Independent Interface (SGMII)
IEEE 1000Base-X
IEEE 100Base-FX
The RTL8370MB supports standard 802.3x flow control frames for full duplex, and optional
backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the
availability of system resources, including the packet buffers and transmitting queues. The RTL8370MB
supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to
non-blocked ports only. For IP multicast applications, the RTL8370MB can forward IPv4 IGMPv1/v2/v3
and IPv6 MLDv1/v2 snooping.
In order to support flexible traffic classification, the RTL8370MB supports 96-entry ACL rule check and
multiple actions options. Each port can optionally enable or disable the ACL rule check function. The
ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an
ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value
in 802.1q/Q tag, and rate policing. The rate policing mechanism supports from 8Kbps to 1Gbps (in 8Kbps
steps).
To meet security and management application requirements, the RTL8370MB supports IEEE 802.1x
Port-based/MAC-based Access Control. For those ports that do not pass IEEE 802.1x authentication, the
RTL8370MB provides a Port-based/MAC-based Guest VLAN function for them to access limited
network resources. A 1-set Port Mirroring function is configured to mirror traffic (RX, TX, or both)
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appearing on one of the switch‟s ports. Support is provided on each port for multiple RFC MIB Counters,
for easy debug and diagnostics.
To improve real-time or multimedia networking applications, the RTL8370MB supports eight priority
assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q VLAN tag
priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority; (5) CVLAN-based priority;
(6) SVLAN-based priority; and (7) SMAC-based/LUTFWD-based priority. Each output port supports a
weighted ratio of eight priority queues to fit bandwidth requirements in different applications. The input
bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for average
packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority (SP) or
Weighted Fair Queue (WFQ) or mixed.
The RTL8370MB provides a 4096-entry VLAN table for 802.1Q port-based, tag-based, and
protocol-based VLAN operation to separate logical connectivity from physical connectivity. The
RTL8370MB supports four Protocol-based VLAN configurations that can optionally select EtherType,
LLC, and RFC1042 as the search key. Each port may be set to any topology via EEPROM upon reset, or
EEPROM SMI Slave after reset.
In router applications, the router may want to know the input port of the incoming packet. The
RTL8370MB supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress port.
The RTL8370MB also provides an option to admit VLAN tagged packet with a specific PVID only. If
this function is enabled, the RTL8370MB will drop all non-tagged packets and packets with an incorrect
PVID.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 2 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

2. Features
 Optional per-port enable/disable of ACL
 Single-chip 8+2-port gigabit non-blocking
function
switch architecture;
 Optional setting of per-port action to
 Embedded 8-port 10/100/1000Base-T PHY take when ACL mismatch

 Each port supports full duplex  Supports IEEE 802.1Q VLAN

10/100/1000M connectivity (half duplex
 Supports 4K VLANs and 32 Extra
only supported in 10/100M mode)
Enhanced VLANs
 Full-duplex and half-duplex operation with  Supports Un-tag definition in each
IEEE 802.3x flow control and backpressure VLAN

 Supports 9216-byte jumbo packet length  Supports VLAN policing and VLAN
forwarding at wire speed forwarding decision
 Supports Port-based, Tag-based, and
 Supports Realtek Cable Test (RTCT) Protocol-based VLAN
function
 Up to 4 Protocol-based VLAN entries
 Extra Interface (Extension GMAC1 and  Supports per-port and per-VLAN egress
Extension GMAC2) supports VLAN tagging and un-tagging
 Dual-port Full Duplex Media
Independent Interface (MII)  Supports IVL, SVL, and IVL/SVL

 Dual-port Full Duplex Turbo Media  Supports 4096-entry MAC address table
Independent Interface (TMII) with 4-way hash algorithm

 Dual-port Reduced Media Independent  Up to 4096 L2/L3 Filtering Database

Interface (RMII)
 Supports Spanning Tree port behavior
 Dual-port Reduced Gigabit Media configuration
Independent Interface (RGMII)
 IEEE 802.1w Rapid Spanning Tree
 Serial Gigabit Media Independent
 IEEE 802.1s Multiple Spanning Tree
Interface (SGMII)
with up to 16 Spanning Tree instances
 IEEE 1000Base-X/ IEEE 100Base-FX
 Supports IEEE 802.1x Access Control
 Supports 96-entry ACL Rules Protocol
 Search keys support physical port,  Port-Based Access Control
Layer2, Layer3, and Layer4 information
 MAC-Based Access Control
 Actions support mirror, redirect,
 Guest VLAN
dropping, priority adjustment, traffic
policing, CVLAN decision, and SVLAN  Supports Quality of Service (QoS)
assignment
 Supports per port Input Bandwidth
 Supports 5 types of user defined ACL Control
rule format for 64 ACL rules
Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 3 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet
 Traffic classification based on IEEE  Disable learning for each port
802.1p/Q priority definition, physical  Disable learning-table aging for each
Port, IP DSCP field, ACL definition, port
VLAN based priority, MAC based
priority, and SVLAN based priority  Drop unknown DA for each port
 Eight Priority Queues per port  Broadcast/Multicast/Unknown DA storm
 Per queue flow control control protects system from attack by
hackers
 Min-Max Scheduling
 Strict Priority and Weighted Fair Queue  Supports Realtek Green Ethernet features
(WFQ) to provide minimum bandwidth  Link-On Cable Length Power Saving
 One leaky bucket to constrain the  Link-Down Power Saving
average packet rate of each queue
 Supports 1 interrupt output to external CPU
 Supports rate limiting (64 shared meters, for notification
with 8kpbs granulation)
 Each port supports 3 parallel LEDs when
 Supports RFC MIB Counter Extension GMAC1&2 not work in
 MIB-II (RFC 1213) RGMII/MII/TMII/RMII mode
 Ethernet-Like MIB (RFC 3635)  Supports serial mode LED, per port
 Interface Group MIB (RFC 2863) one/two/three LEDs
 RMON (RFC 2819)  Supports Slave EEPROM
 Bridge MIB (RFC 1493) SMI/I2C-Like/SPI interface to access
configuration register
 Bridge MIB Extension (RFC 2674)
 Integrated 8051 microprocessor
 Supports Stacking VLAN and Port Isolation
with 8 Enhanced Filtering Databases  Supports SPI Flash Interface
 Supports IEEE 802.1ad Stacking VLAN  25MHz crystal
 Supports 64 SVLANs
 TQFP 176-pin E-PAD package
 Supports 32 L2/IPv4 Multicast mappings
to SVLAN

 Supports 4 IEEE 802.3ad Link aggregation

port groups

 Supports OAM and EEE LLDP (Energy

Efficient Ethernet Link Layer Discovery
Protocol

 Supports Loop Detection

 Security Filtering

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 4 Track ID: Rev. 0.2
 RTL8370MB
BRIEF Datasheet

3. Block Diagram

RTL8370MB Block Diagram

P0
UTP Giga-PHY PCS GMAC

P1 SRAM
UTP Giga-PHY PCS GMAC
Controller Packet Buffer
SRAM
P2
UTP Giga-PHY PCS GMAC

P3
UTP Giga-PHY PCS GMAC

P4
Queue
UTP Giga-PHY PCS Managment
GMAC Linking Lists
P5
UTP Giga-PHY PCS GMAC

P6
UTP Giga-PHY PCS GMAC 4096 MAC
Address Table
P7
Lookup
UTP Giga-PHY PCS GMAC Engine
RGMII/MII/
TMII/RMII EXT
SGMII/
MUX GMAC1 4096 VLAN
1000Base-X/
100Base-FX Table
RGMII/MII/ EXT
TMII/RMII
SGMII/
MUX GMAC2
1000Base-X/
100Base-FX
GNIC
MAC
LED LED
Control
GNIC 8051
Registers
PLL +
I2C Host I2C/SPI/S
MIB Counter
Flash Interface MI Slave

I2C/
25MHz FLASH
Crystal SPI/SMI

Figure 1 Block Diagram of RTL8370MB

5 Track ID: Rev. 1.0

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers
 RTL8370MB
DRAFT Datasheet

4. System Application
 8-Port 1000Base-T+2-Port 1000Base-X/100Base-FX Un-Management Switch
 8-Port 1000Base-T Router with Dual MII/RGMII
 8-Port 1000Base-T Router with Dual SGMII

4.1. 8-Port 1000Base-T+2-Port 1000Base-X/100Base-FX Switch

Address Table MIB Counter Extension Extension EEPROM

SMI Host
Giga Giga
/Slave
Packet Buffer MAC 1 MAC 2

Queue Manager ALE

ACL

Giga Giga Giga Giga Giga Giga Giga Giga

SerDes

SerDes
MAC 0 MAC 1 MAC 2 MAC 3 MAC 4 MAC 5 MAC 6 MAC 7

Giga Giga Giga Giga Giga Giga Giga Giga

PHY 0 PHY 1 PHY 2 PHY 3 PHY 4 PHY 5 PHY 6 PHY 7

Fiber Fiber
1000/ 1000/
Fiber Fiber
RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 100 100
Jack Jack Jack Jack Jack Jack Jack Jack

Figure 2 8-Port 1000Base-T+2-Port 1000Base-X/100Base-FX Switch

Note: In this application, Parallel or Serial Led is recommended.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 6 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

4.2. 8-Port 1000Base-T Router with Dual MII/RGMII

MII/RGMII

MII/RGMII CPU

Address Table MIB Counter

Extension Extension
Giga Giga
Packet Buffer MAC 1 MAC 2

Queue Manager ALE

Configuration
Slave SMI/
ACL I2C-Like/SPI

Giga Giga Giga Giga Giga Giga Giga Giga

MAC 0 MAC 1 MAC 2 MAC 3 MAC 4 MAC 5 MAC 6 MAC 7

Giga Giga Giga Giga Giga Giga Giga Giga

PHY 0 PHY 1 PHY 2 PHY 3 PHY 4 PHY 5 PHY 6 PHY 7

RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45

Jack Jack Jack Jack Jack Jack Jack Jack

Figure 3 8-Port 1000Base-T Router with Dual MII/RGMII

Note1: Extra Interface (Extension GMAC1 and Extension GMAC2) in MII/RGMII Mode.
Note2: In this application, Serial Led is recommended.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 7 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

4.3. 8-Port 1000Base-T Router with Dual SGMII

SGMII

SGMII CPU

Address Table MIB Counter

Extension Extension
Giga Giga
Packet Buffer MAC 1 MAC 2

Queue Manager ALE

Configuration
Slave SMI/
ACL I2C-Like/SPI

Giga Giga Giga Giga Giga Giga Giga Giga

MAC 0 MAC 1 MAC 2 MAC 3 MAC 4 MAC 5 MAC 6 MAC 7

Giga Giga Giga Giga Giga Giga Giga Giga

PHY 0 PHY 1 PHY 2 PHY 3 PHY 4 PHY 5 PHY 6 PHY 7

RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45

Jack Jack Jack Jack Jack Jack Jack Jack

Figure 4 8-Port 1000Base-T Router with Dual SGMII

Note1: Extra Interface (Extension GMAC1 and Extension GMAC2) in SGMII Mode.
Note2: In this application, Parallel or Serial Led is recommended.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 8 Track ID: Rev. 0.2
 5.

5.1.
AVDDH
AVDDL
AVDDH
AVDDH
AVDDL
AVDDH
AVDDL
AVDDH

P3MDIBN
P3MDIBP
P3MDIAN
P3MDIAP
P2MDIDN
P2MDIDP
P2MDICN
P2MDICP
P2MDIBN
P2MDIBP
P2MDIAN
P2MDIAP
PLLGND0
ATESTCK0
PLLVDDL0
P1MDIDN
P1MDIDP
P1MDICN
P1MDICP
P1MDIBN
P1MDIBP
P1MDIAN
P1MDIAP
P0MDIDN
P0MDIDP
P0MDICN
P0MDICP
P0MDIBN
P0MDIBP
P0MDIAN
P0MDIAP
nRESET
Slave_SPI_SS#

Slave_SPI_SO/EEPROM_MOD
SDA/MMD_MDIO/Slave_SPI_SI
SCK/MMD_MDC/Slave_SPI_SCK

176
175
174
173
172
171
170
169
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133

168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
AVDDL 1
132 XTALI
P3MDICP 2
131 XTALO
P3MDICN 3

E-PAD GND
130 DVDDL
P3MDIDP 4
129 LED_CK/P0LED0/SMI_SEL_0
P3MDIDN 5
128 LED_DA/P0LED1
AVDDH 6
127 DVDDL
NC 7
126 DVDDIO_1
AGND 8
125 RG1_TXD3/M1_TXD3/P1_RXD3/P0LED2/GPIO2/EN_PHY
NC 9
124 RG1_TXD2/M1_TXD2/P1_RXD2/P1LED1/DIS_8051
MDIREF 10
123 RG1_TXD1/M1_TXD1/P1_RXD1/P1LED0/MID29
11
Pin Assignments

NC
122 RG1_TXD0/M1_TXD0/P1_RXD0/P1LED2/SMI_SEL_1
AVDDL 12
121 RG1_TXCTL/M1_TXEN/P1_RXDV/P2LED1/GPIO4
RTT1 13
120 RG1_TXC/M1_TXC/P1_RXC/P2LED0
RTT2 14
119 RG1_RXC/M1_RXC/P1_TXC/P2LED2
AVDDH 15
118 RG1_RXCTL/M1_RXDV/P1_TXEN/P3LED0
DVDDIO 16
117 RG1_RXD0/M1_RXD0/P1_TXD0/P3LED2/GPIO18
DVDDL 17
116 RG1_RXD1/M1_RXD1/P1_TXD1/P3LED1/GPIO5
DVDDL 18
115 RG1_RXD2/M1_RXD2/P1_TXD2/P4LED1/GPIO6
INT 19

Package Identification
114 RG1_RXD3/M1_RXD3/P1_TXD3/P4LED0/GPIO17
BUZZER/DIS_LPD 20
113 P4LED2/GPIO3/DIS_SPIS
RESERVED1 21
112 DVDDL
RESERVED2 22

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers

111 DVDDIO_1
RESERVED3 23
110 SGND
GPIO_A/SPF_MUX_SEL 24
RESERVED4 109 S0RXP
25
108 S0RXN
P9LED0/EN_PWRLIGHT 26

9
P9LED1/DISAUTOLOAD 107 SVDDL
27

LLLLLLL
106 S0TXP
P9LED2/EEE_EN 28
P8LED2/DIS_FX_AUTO 105 S0TXN

RTL8370MB
29
104 SVDDL
GPIO_B/SPF_CLK 30
GPIO_C/SPF_SI_D0 103 S1RXN

Green package is indicated by the „G‟ in GXXXX (Figure 5).

31
102 S1RXP
GPIO_D/SPF_SO_D1

GXXXX TAIWAN
32
101 SGND
GPIO_E/SPF_CSn 33
100 S1TXN
DVDDL 34
99 S1TXP

Figure 5. Pin Assignments

DVDDL 35
98 SVDDL
DVDDIO 36
97 SVDDH
AVDDH 37
96 DVDDIO_2
P4MDIAP 38
95 DVDDL
P4MDIAN 39
94 RG2_RXD3/M2_RXD3/P2_TXD3/P5LED1/GPIO16
P4MDIBP 40
93 RG2_RXD2/M2_RXD2/P2_TXD2/P5LED0/GPIO15
P4MDIBN 41
92 RG2_RXD1/M2_RXD1/P2_TXD1/P5LED2/GPIO0
AVDDL 42
91 RG2_RXD0/M2_RXD0/P2_TXD0/P6LED1/GPIO7/UARTTX
P4MDICP 43
90 RG2_RXCTL/M2_RXDV/P2_TXEN/P6LED0/GPIO1/UARTRX

TQFP-176-EPAD
P4MDICN 44
89 RG2_RXC/M2_RXC/P2_TXC/P6LED2/GPIO14/SPF_CSn

55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
83
84
85
86
87
88

45
46
47
48
49
50
51
52
53
54
75
76
77
78
79
80
81
82

Package Size: 20mm x 20mm (TQFP176)

AVDDL
AVDDL
AVDDL

AVDDH
AVDDH

AVDDH
AVDDH
AVDDH

P5MDIAP
P5MDIBP
P6MDIAP
P6MDIBP
P7MDIAP
P7MDIBP

P4MDIDP
P5MDIAN
P5MDIBN
P5MDICP
P5MDIDP
P6MDIAN
P6MDIBN
P6MDICP
P6MDIDP
P7MDIAN
P7MDIBN
P7MDICP
P7MDIDP

P4MDIDN
P5MDICN
P5MDIDN
P6MDICN
P6MDIDN
P7MDICN
P7MDIDN

PLLGND1

PLLVDDL1
DVDDIO_2

ATESTCK1

Track ID:
RG2_TXC/M2_TXC/P2_RXC/GPIO13

RG2_TXD3/M2_TXD3/P2_RXD3/P8LED1/GPIO8/DIS_LED

Rev. 0.2
DRAFT Datasheet
RTL8370MB

RG2_TXD1/M2_TXD1/P2_RXD1/P7LED2/GPIO10/SPF_CLK
RG2_TXD2/M2_TXD2/P2_RXD2/P8LED0/GPIO9/EN_FLASH
RG2_TXD0/M2_TXD0/P2_RXD0/P7LED0/GPIO11/SPF_SI_D0
RG2_TXCTL/M2_TXEN/P2_RXDV/P7LED1/GPIO12/SPF_SO_D1
 RTL8370MB
DRAFT Datasheet

5.2. Pin Assignment Table

Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified „Upon Reset‟ time.

I: Input Pin AI: Analog Input Pin

O: Output Pin AO: Analog Output Pin

I/O: Bi-Directional Input/Output Pin AI/O: Analog Bi-Directional Input/Output Pin

P: Digital Power Pin AP: Analog Power Pin

G: Digital Ground Pin AG: Analog Ground Pin

IPU: Input Pin With Pull-Up Resistor; OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75K Ohm) (Typical Value = 75K Ohm)

IS: Input Pin With Schmitt Trigger

Table 1. Pin Assignment Table

Name Pin No. Type Name Pin No. Type
AVDDL 1 AP RESERVED4 25 I/OPU
P3MDICP 2 AI/O P9LED0/EN_PWRLIGHT 26 I/OPU
P3MDICN 3 AI/O P9LED1/DISAUTOLOAD 27 I/OPU
P3MDIDP 4 AI/O P9LED2/EEE_EN 28 I/OPU
P3MDIDN 5 AI/O P8LED2/DIS_FX_AUTO 29 I/OPU
AVDDH 6 AP GPIO_B/SPF_CLK 30 I/OPU
NC 7 - GPIO_C/SPF_SI_D0 31 I/OPU
AGND 8 AG GPIO_D/SPF_SO_D1 32 I/OPU
NC 9 - GPIO_E/SPF_CSn 33 I/OPU
MDIREF 10 AO DVDDL 34 P
NC 11 - DVDDL 35 P
AVDDL 12 AP DVDDIO 36 P
RTT1 13 AO AVDDH 37 AP
RTT2 14 AI P4MDIAP 38 AI/O
AVDDH 15 AP P4MDIAN 39 AI/O
DVDDIO 16 P P4MDIBP 40 AI/O
DVDDL 17 P P4MDIBN 41 AI/O
DVDDL 18 P AVDDL 42 AP
INT 19 O P4MDICP 43 AI/O
BUZZER/DIS_LPD 20 I/OPU P4MDICN 44 AI/O
RESERVED1 21 IPD P4MDIDP 45 AI/O
RESERVED2 22 I/OPD P4MDIDN 46 AI/O
RESERVED3 23 I/OPD AVDDH 47 AP
GPIO_A/SPF_MUX_SEL 24 I/OPU P5MDIAP 48 AI/O

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 10 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet
Name Pin No. Type Name Pin No. Type
P5MDIAN 49 AI/O RG2_RXC/M2_RXC/P2_TXC/P6 89
P5MDIBP 50 AI/O LED2/SPF_CSn/GPIO14 I/OPU
P5MDIBN 51 AI/O RG2_RXCTL/M2_RXDV/P2_TX 90
AVDDL 52 AP EN/P6LED0/GPIO1/UARTRX I/OPU
RG2_RXD0/M2_RXD0/P2_TXD0 91
P5MDICP 53 AI/O
/P6LED1/GPIO7/UARTTX I/OPU
P5MDICN 54 AI/O
RG2_RXD1/M2_RXD1/P2_TXD1 92
P5MDIDP 55 AI/O /P5LED2/GPIO0 I/OPU
P5MDIDN 56 AI/O RG2_RXD2/M2_RXD2/P2_TXD2 93
AVDDH 57 AP /P5LED0/GPIO15 I/OPU
PLLVDDL1 58 AP RG2_RXD3/M2_RXD3/P2_TXD3 94
ATESTCK1 59 AO /P5LED1/GPIO16 I/OPU
PLLGND1 60 AG DVDDL 95 P
AVDDH 61 AP DVDDIO_2 96 P
P6MDIAP 62 AI/O SVDDH 97 AP
P6MDIAN 63 AI/O SVDDL 98 AP
P6MDIBP 64 AI/O S1TXP 99 AO
P6MDIBN 65 AI/O S1TXN 100 AO
AVDDL 66 AP SGND 101 AG
P6MDICP 67 AI/O S1RXP 102 AI
P6MDICN 68 AI/O S1RXN 103 AI
P6MDIDP 69 AI/O SVDDL 104 AP
P6MDIDN 70 AI/O S0TXN 105 AO
AVDDH 71 AP S0TXP 106 AO
P7MDIAP 72 AI/O SVDDL 107 AP
P7MDIAN 73 AI/O S0RXN 108 AI
P7MDIBP 74 AI/O S0RXP 109 AI
P7MDIBN 75 AI/O SGND 110 AG
AVDDL 76 AP DVDDIO_1 111 P
P7MDICP 77 AI/O DVDDL 112 P
P7MDICN 78 AI/O P4LED2/GPIO3/DIS_SPIS 113 I/OPU
P7MDIDP 79 AI/O RG1_RXD3/M1_RXD3/P1_TXD3 114
P7MDIDN 80 AI/O /P4LED0/GPIO17 I/OPU
AVDDH 81 AP RG1_RXD2/M1_RXD2/P1_TXD2 115
/P4LED1/GPIO6 I/OPU
DVDDIO_2 82 P
RG1_RXD1/M1_RXD1/P1_TXD1 116
RG2_TXD3/M2_TXD3/P2_RXD3 83
/P3LED1/GPIO5 I/OPU
/P8LED1/GPIO8/DIS_LED I/OPU
RG1_RXD0/M1_RXD0/P1_TXD0 117
RG2_TXD2/M2_TXD2/P2_RXD2 84
/P3LED2/GPIO18 I/OPU
/P8LED0/GPIO9/EN_FLASH I/OPU
RG1_RXCTL/M1_RXDV/P1_TX 118
RG2_TXD1/M2_TXD1/P2_RXD1 85
EN/P3LED0 I/OPU
/P7LED2/GPIO10/SPF_CLK I/OPU
RG1_RXC/M1_RXC/P1_TXC/P2 119
RG2_TXD0/M2_TXD0/P2_RXD0 86
LED2 I/OPU
/P7LED0/GPIO11/SPF_SI_D0 I/OPU
RG1_TXC/M1_TXC/P1_RXC/P2 120
RG2_TXCTL/M2_TXEN/P2_RX 87
LED0 I/OPU
DV/P7LED1/GPIO12/SPF_SO_D1 I/OPU
RG1_TXCTL/M1_TXEN/P1_RX 121
RG2_TXC/M2_TXC/P2_RXC/GPI 88
DV/P2LED1/GPIO4 I/OPU
O13 I/OPU
Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 11 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet
Name Pin No. Type Name Pin No. Type
RG1_TXD0/M1_TXD0/P1_RXD0 122 P2MDIAP 163 AI/O
/P1LED2/SMI_SEL_1 I/OPU P2MDIAN 164 AI/O
RG1_TXD1/M1_TXD1/P1_RXD1 123 P2MDIBP 165 AI/O
/P1LED0/MID29 I/OPU P2MDIBN 166 AI/O
RG1_TXD2/M1_TXD2/P1_RXD2 124
AVDDL 167 AP
/P1LED1/DIS_8051 I/OPU
P2MDICP 168 AI/O
RG1_TXD3/M1_TXD3/P1_RXD3 125
/P0LED2/GPIO2/EN_PHY I/OPU P2MDICN 169 AI/O
DVDDIO_1 126 P P2MDIDP 170 AI/O
DVDDL 127 P P2MDIDN 171 AI/O
LED_DA/P0LED1 128 I/OPU AVDDH 172 AP
LED_CK/P0LED0/SMI_SEL_0 129 I/OPU P3MDIAP 173 AI/O
DVDDL 130 P P3MDIAN 174 AI/O
XTALO 131 AO P3MDIBP 175 AI/O
XTALI 132 AI P3MDIBN 176 AI/O
nRESET 133 I_S EPAD_GND 177 G
Slave_SPI_SS# 134 IPU
SCK/MMD_MDC/Slave_SPI_SC
K 135 I/OPU
SDA/MMD_MDIO/Slave_SPI_SI 136 I/OPU
Slave_SPI_SO/EEPROM_MOD 137 I/OPU
AVDDH 138 AP
P0MDIAP 139 AI/O
P0MDIAN 140 AI/O
P0MDIBP 141 AI/O
P0MDIBN 142 AI/O
AVDDL 143 AP
P0MDICP 144 AI/O
P0MDICN 145 AI/O
P0MDIDP 146 AI/O
P0MDIDN 147 AI/O
AVDDH 148 AP
P1MDIAP 149 AI/O
P1MDIAN 150 AI/O
P1MDIBP 151 AI/O
P1MDIBN 152 AI/O
AVDDL 153 AP
P1MDICP 154 AI/O
P1MDICN 155 AI/O
P1MDIDP 156 AI/O
P1MDIDN 157 AI/O
AVDDH 158 AP
PLLVDDL0 159 AP
ATESTCK0 160 AO
PLLGND0 161 AG
AVDDH 162 AP
Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 12 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

6. Pin Descriptions
6.1. Media Dependent Interface Pins
Table 2. Media Dependent Interface Pins
Pin Name Pin No. Type Drive Description
(mA)
P0MDIAP/N 139 AI/O 10 Port 0 Media Dependent Interface A~D.
140 For 1000Base-T operation, differential data from the media is
P0MDIBP/N 141 transmitted and received on all four pairs. For 100Base-Tx and
142 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
P0MDICP/N 144 MDIX can reverse the pairs MDIAP/N and MDIBP/N.
145
P0MDIDP/N 146 Each of the differential pairs has an internal 100-ohm termination
147 resistor.
P1MDIAP/N 149 AI/O 10 Port 1 Media Dependent Interface A~D.
150 For 1000Base-T operation, differential data from the media is
P1MDIBP/N 151 transmitted and received on all four pairs. For 100Base-Tx and
152 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
P1MDICP/N 154 MDIX can reverse the pairs MDIAP/N and MDIBP/N.
155
P1MDIDP/N 156 Each of the differential pairs has an internal 100-ohm termination
157 resistor.
P2MDIAP/N 163 AI/O 10 Port 2 Media Dependent Interface A~D.
164 For 1000Base-T operation, differential data from the media is
P2MDIBP/N 165 transmitted and received on all four pairs. For 100Base-Tx and
166 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
P2MDICP/N 168 MDIX can reverse the pairs MDIAP/N and MDIBP/N.
169
P2MDIDP/N 170 Each of the differential pairs has an internal 100-ohm termination
171 resistor.
P3MDIAP/N 173 AI/O 10 Port 3 Media Dependent Interface A~D.
174 For 1000Base-T operation, differential data from the media is
P3MDIBP/N 175 transmitted and received on all four pairs. For 100Base-Tx and
176 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
P3MDICP/N 2 MDIX can reverse the pairs MDIAP/N and MDIBP/N.
3
P3MDIDP/N 4 Each of the differential pairs has an internal 100-ohm termination
5 resistor.
P4MDIAP/N 38 AI/O 10 Port 4 Media Dependent Interface A~D.
39 For 1000Base-T operation, differential data from the media is
P4MDIBP/N 40 transmitted and received on all four pairs. For 100Base-Tx and
41 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
P4MDICP/N 43 MDIX can reverse the pairs MDIAP/N and MDIBP/N.
44
P4MDIDP/N 45 Each of the differential pairs has an internal 100-ohm termination
46 resistor.

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 RTL8370MB
DRAFT Datasheet

Pin Name Pin No. Type Drive Description

(mA)
P5MDIAP/N 48 AI/O 10 Port 5 Media Dependent Interface A~D.
49 For 1000Base-T operation, differential data from the media is
P5MDIBP/N 50 transmitted and received on all four pairs. For 100Base-Tx and
51 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
P5MDICP/N 53 MDIX can reverse the pairs MDIAP/N and MDIBP/N.
54
P5MDIDP/N 55 Each of the differential pairs has an internal 100-ohm termination
56 resistor.
P6MDIAP/N 62 AI/O 10 Port 6 Media Dependent Interface A~D.
63 For 1000Base-T operation, differential data from the media is
P6MDIBP/N 64 transmitted and received on all four pairs. For 100Base-Tx and
65 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
P6MDICP/N 67 MDIX can reverse the pairs MDIAP/N and MDIBP/N.
68
P6MDIDP/N 69 Each of the differential pairs has an internal 100-ohm termination
70 resistor.
P7MDIAP/N 72 AI/O 10 Port 7 Media Dependent Interface A~D.
73 For 1000Base-T operation, differential data from the media is
P7MDIBP/N 74 transmitted and received on all four pairs. For 100Base-Tx and
75 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
P7MDICP/N 77 MDIX can reverse the pairs MDIAP/N and MDIBP/N.
78
P7MDIDP/N 79 Each of the differential pairs has an internal 100-ohm termination
80 resistor.

6.2. RGMII Interface Pins

Table 3. RGMII Interface Pins
Drive
Pin Name Pin No. Type Description
(mA)
RG1_RXCTL, 118, IPU - RGMII Receive Control.
RG2_RXCTL 90 The RG_RXCTL indicates RXDV at rising of
RG_RXCLK and the logical derivative of RXER and
RXDV at the falling edge of RG_RXCLK.
RG1_RXD[3:0] 114,115,116,117 IPU - RGMII Receive Data Bus.
RG2_RXD[3:0] 94,93,92,91 In RGMII 1000Base-T mode, RXD[3:0] runs at a double
data rate with bit[3:0] presented on the rising edge of the
RG_RXCLK and bit[7:4] presented on the falling edge of
the RG_RXCLK. RXD[7:4] are ignored in this mode.
In RGMII 10/100Base-T modes, the received data nibble is
presented on RXD[3:0] on the rising edge of RG_RXCLK
and duplicated on the falling edge of RG_RXCLK.

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DRAFT Datasheet
Drive
Pin Name Pin No. Type Description
(mA)
RG1_RXC, 119, IPU - RGMII Receive Clock Input.
RG2_RXC 89 Used for RG_RXD[3:0] and RG_RXCTL synchronization
at both RG_RXCLK rising and falling edges.
The frequency (with ±50ppm tolerance) depends on the
link speed.
1000M: 125MHz
100M: 25MHz
10M: 2.5MHz
RG1_TXC, 120, OPU - RGMII Transmit Clock Output.
RG2_TXC 88 Used for RG_TXD[3:0] and RG_TXCTL synchronization
at both RG_TXCLK rising and falling edges.
The frequency (with ±50ppm tolerance) depends on the
link speed.
1000M: 125MHz
100M: 25MHz
10M: 2.5MHz
RG1_TXD[3:0] 125,124,123,122 OPU - RGMII Transmit Data Bus.
RG2_TXD[3:0] 83,84,85,86 In RGMII 1000Base-T mode, TXD[3:0] runs at a double
data rate with bits[3:0] presented on the rising edge of the
RG_TXCLK and bit[7:4] presented on the falling edge of
the RG_TXCLK. TXD[7:4] are ignored in this mode.
In RGMII 10/100Base-T modes, the transmitted data
nibble is presented on TXD[3:0] on the rising edge of
RG_TXCLK and duplicated on the falling edge of
RG_TXCLK.
RG1_TXCTL, 121, OPU - RGMII Transmit Control.
RG2_TXCTL 87 The RG_TXCTL indicates TXEN at rising of
RG_TXCLK, and the logical derivative of TXER and
TXEN at the falling edge of RG_TXCLK.

6.3. MII/TMII Interface Pins

Table 4. MII/TMII Interface Pins
Drive
Pin Name Pin No. Type Description
(mA)
M1_RXDV/P1_TXEN, 118,90 IPU - 1\M_RXDV Pin in TMII/MII MAC Mode.
M2_RXDV/P2_TXEN MII Receive Data Valid.
This synchronous input is asserted when valid data is
driven on M_RXD. M_RXDV is synchronous to M_RXC.
2\P_TXEN Pin in TMII/MII PHY Mode.
MII Transmit Enable.
The synchronous input indicates that valid data is being
driven on the P_TXD bus. P_TXEN is synchronous to
P_TXC.

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DRAFT Datasheet
Drive
Pin Name Pin No. Type Description
(mA)
M1_RXD[3:0]/P1_TXD 114,115,116,117 IPU - 1\M_RXD[3:0] Pin in TMII/MII MAC Mode.
[3:0], 94,93,92,91 MII Receive Data Bus. M_RXD[3:0] is synchronous to
M2_RXD[3:0]/P2_TXD M_RXC.
[3:0] 2\P_TXD[3:0] Pin in TMII/MII PHY Mode.
MII Transmit Data Bus. P_TXD[3:0] is synchronous to
P_TXC .
M1_RXC/P1_TXC, 119, I/OPU - 1\M_RXC Pin in TMII/MII MAC Mode.
M2_RXC/P2_TXC 89 MII Receive Clock.(input)
Used to synchronize M_RXD[3:0], and M_RXDV.
The frequency depends on the link speed.
MII:100Base-Tx25MHz, 10Base-T2.5MHz
TMII:200Mbps50MHz, 20Mbps5MHz
2\P_TXC Pin in TMII/MII PHY Mode.
MII Transmit Clock. (output)
Used to synchronize P_TXD[3:0], and P_TXEN.
It provides 25MHz clock reference at 100Base-TX , and
2.5MHz clock reference at 10Base-T.
In TMII mode it povides 50MHz clock reference at
200Mbps, and 5MHz clock at 20Mbps.
M1_TXC/P1_RXC, 120, I/OPU - 1\ M_TXC Pin in TMII/MII MAC Mode.
/M2_TXC/P2_RXC 88 MII Transmit Clock. (input)
Used to synchronize M_TXD[3:0], and M_TXEN.
The frequency depends on the link speed.
MII:100Base-Tx25MHz, 10Base-T2.5MHz
TMII:200Mbps50MHz, 20Mbps5MHz
2\P_RXC Pin in TMII/MII PHY Mode.
MII Receive Clock. (output)
Used to synchronize P_RXD[3:0], and P_RXDV.
It provides 25MHz clock reference at 100Base-TX , and
2.5MHz clock reference at 10Base-T.
In TMII mode it povides 50MHz clock reference at
200Mbps, and 5MHz clock at 20Mbps.
M1_TXD[3:0]/P1_RXD 125,124,123,122 OPU - 1\ M_TXD[3:0] Pin in TMII/MII MAC Mode.
[3:0], 83,84,85,86 MII Transmit Data Bus.
M2_TXD[3:0]/P2_RXD M_TXD[3:0] is synchronous to M_TXC in
[3:0] 10/100Base-TX mode.
2\ P_RXD[3:0] Pin in TMII/MII PHY Mode.
MII Receive Data Bus.
P_RXD[3:0] is synchronous to P_RXC.
M1_TXEN/P1_RXDV, 121, OPU - 1\M_ TXEN Pin in TMII/MII MAC Mode.
M2_TXEN/P2_RXDV 87 MII Transmit Enable.
The synchronous output indicates that valid data is being
driven on the M_TXD bus.
M_TXEN is synchronous to M_TXC in 10/100Base-TX
mode.
2\P_ RXDV Pin in TMII/MII PHY Mode.
MII Receive Data Valid.
This synchronous output is asserted when valid data is
driven on the P_RXD bus.
P_ RXDV is synchronous toP_ RXC.

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 RTL8370MB
DRAFT Datasheet

6.4. RMII Interface Pins

Table 5. RMII Interface Pins
Drive
Pin Name Pin No. Type Description
(mA)
M1_RXDV/P1_TXEN, 118,90 IPU - 1\CRSDV Pin in RMII MAC Mode.
M2_RXDV/P2_TXEN Carrier Sense/Receive Data Valid.
This synchronous input is asserted by the PHY when the
receive medium is non-idle. It is synchronous to REFCLK.
2\TXEN Pin in RMII PHY Mode.
The synchronous output indicates that valid data is being
driven on the P_TXD[1:0] bus.
It is synchronous to REFCLK.
M1_RXD[1:0]/P1_TXD[1:0], 116,117 IPU - 1\RXD[1:0] Pin in RMII MAC Mode.
M2_RXD[1:0]/P2_TXD[1:0] 92,91 MII Receive Data Bus.
M_RXD[1:0] is synchronous to REFCLK.
2\TXD[1:0] Pin in RMII PHY Mode.
MII Transmit Data Bus.
P_TXD[1:0] is synchronous to REFCLK.
M1_TXC/P1_RXC, 120, I/OPU - REFCLK Pin in RMII Mode.
M2_TXC/P2_RXC 88 This pin is bi-directional.
When Mac mode, REFCLK is an input pin.
When Phy mode, REFCLK outputs a 50MHz reference
clock.
All transmissions must be synchronized to this clock
during 10/100M operation.
M1_TXD[1:0]/P1_RXD[1:0], 123,122 OPU - 1\ TXD[1:0] Pin in RMII MAC Mode.
M2_TXD[1:0]/P2_RXD[1:0] 85,86 MII Transmit Data Bus.
M_TXD[1:0] is synchronous to REFCLK in
10/100Base-TX mode.
2\ RXD[1:0] Pin in RMII PHY Mode.
MII Receive Data Bus.
P_RXD[1:0] is synchronous to REFCLK.
M1_TXEN/P1_RXDV, 121, OPU - 1\TXEN Pin in RMII MAC Mode.
M2_TXEN/P2_RXDV 87 The synchronous output indicates that valid data is being
driven on the TXD[1:0] bus.
M_TXEN is synchronous to REFCLK.
2\CRSDV Pin in RMII PHY Mode.
Carrier Sense/Receive Data Valid.
This synchronous output is asserted by the PHY when the
receive medium is non-idle. It is synchronous to REFCLK.

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 RTL8370MB
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6.5. SerDes Interface Pins

Table 6. SerDes Interface Pins
Drive
Pin Name Pin No. Type Description
(mA)
S0RXP, 109 AI - 100FX/1000Base-X/SGMII SerDes 0 Interface Receive
S0RXN 108 Data Differential Input Pair.
S0TXP, 106 AO - 100FX/1000Base-X/SGMII SerDes 0 Interface Transmit
S0TXN 105 Data Differential Output Pair.
S1RXP, 102 AI - 100FX/1000Base-X/SGMII SerDes 1 Interface Receive
S1RXN 103 Data Differential Input Pair.
S1TXP, 99 AO - 100FX/1000Base-X/SGMII SerDes 1 Interface Transmit
S1TXN 100 Data Differential Output Pair.

6.6. Parallel LED Pins

Table 7. Parallel LED Pins
Pin Name Pin No. Type Drive Description
(mA)
P9LED2 28 OPU - Port 9 Parallel LED LED2 Output Signal.
P7LED2 indicates information is defined by register or EEPROM.
P9LED1 27 OPU - Port 9 Parallel LED LED1 Output Signal.
P7LED1 indicates information is defined by register or EEPROM.
P9LED0 26 OPU - Port 9 Parallel LED LED0 Output Signal.
P7LED0 indicates information is defined by register or EEPROM.
P8LED2 29 OPU - Port 8 Parallel LED LED2 Output Signal.
P7LED2 indicates information is defined by register or EEPROM.
P8LED1 83 OPU - Port 8 Parallel LED LED1 Output Signal.
P7LED1 indicates information is defined by register or EEPROM.
P8LED0 84 OPU - Port 8 Parallel LED LED0 Output Signal.
P7LED0 indicates information is defined by register or EEPROM.
P7LED2 85 OPU - Port 7 Parallel LED LED2 Output Signal.
P7LED2 indicates information is defined by register or EEPROM.
P7LED1 87 OPU - Port 7 Parallel LED LED1 Output Signal.
P7LED1 indicates information is defined by register or EEPROM.
P7LED0 86 OPU - Port 7 Parallel LED LED0 Output Signal.
P7LED0 indicates information is defined by register or EEPROM.
P6LED2 89 OPU - Port 6 Parallel LED LED2 Output Signal.
P6LED2 indicates information is defined by register or EEPROM.
P6LED1 91 OPU - Port 6 Parallel LED LED1 Output Signal.
P6LED1 indicates information is defined by register or EEPROM.
P6LED0 90 OPU - Port 6 Parallel LED LED0 Output Signal.
P6LED0 indicates information is defined by register or EEPROM.
P5LED2 92 OPU - Port 5 Parallel LED LED2 Output Signal.
P5LED2 indicates information is defined by register or EEPROM.

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 RTL8370MB
DRAFT Datasheet

Pin Name Pin No. Type Drive Description

(mA)
P5LED1 94 OPU - Port 5 Parallel LED LED1 Output Signal.
P5LED1 indicates information is defined by register or EEPROM.
P5LED0 93 OPU - Port 5 Parallel LED LED0 Output Signal.
P5LED0 indicates information is defined by register or EEPROM.
P4LED2 113 OPU - Port 4 Parallel LED LED2 Output Signal.
P4LED2 indicates information is defined by register or EEPROM.
P4LED1 115 OPU - Port 4 Parallel LED LED1 Output Signal.
P4LED1 indicates information is defined by register or EEPROM.
P4LED0 114 OPU - Port 4 Parallel LED LED0 Output Signal.
P4LED0 indicates information is defined by register or EEPROM.
P3LED2 117 OPU - Port 3 Parallel LED LED2 Output Signal.
P3LED2 indicates information is defined by register or EEPROM.
P3LED1 116 OPU - Port 3 Parallel LED LED1 Output Signal.
P3LED1 indicates information is defined by register or EEPROM.
P3LED0 118 OPU - Port 3 Parallel LED LED0 Output Signal.
P3LED0 indicates information is defined by register or EEPROM.
P2LED2 119 OPU - Port 2 Parallel LED LED2 Output Signal.
P2LED2 indicates information is defined by register or EEPROM.
P2LED1 121 OPU - Port 2 Parallel LED LED1 Output Signal.
P2LED1 indicates information is defined by register or EEPROM.
P2LED0 120 OPU - Port 2 Parallel LED LED0 Output Signal.
P2LED0 indicates information is defined by register or EEPROM.
P1LED2 122 OPU - Port 1 Parallel LED LED2 Output Signal.
P1LED2 indicates information is defined by register or EEPROM.
P1LED1 124 OPU - Port 1 Parallel LED LED1 Output Signal.
P1LED1 indicates information is defined by register or EEPROM.
P1LED0 123 OPU - Port 1 Parallel LED LED0 Output Signal.
P1LED0 indicates information is defined by register or EEPROM.
P0LED2 125 OPU - Port 0 Parallel LED LED2 Output Signal.
P0LED2 indicates information is defined by register or EEPROM.
P0LED1 128 OPU - Port 0 Parallel LED LED1 Output Signal.
P0LED1 indicates information is defined by register or EEPROM.
P0LED0 129 OPU - Port 0 Parallel LED LED0 Output Signal.
P0LED0 indicates information is defined by register or EEPROM.

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 RTL8370MB
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6.7. Serial Mode LED Pins

Table 8. Serial Mode LED Pins
Pin Name Pin No. Type Drive Description
(mA)
LED_CK 129 OPU - Serial Mode LED Clock Signal.
LED_DA 128 OPU - Serial Mode LED Data Signal.

6.8. SPI FLASH Interface Pins

Table 9. SPI FLASH Interface Pins
Pin Name Pin No. Type Drive Description
(mA)
SPF_CSn 89 OPU -SPI FLASH chip select signal.
SPF_SO_D1 87 I/OPU -In Serial I/O Mode
SPI Serial FLASH Serial Data Output (RTL8370 MB input pin)
In Dual I/O Mode
SPI FLASH bi-directional pin (this is MSB)
SPF_SI_D0 86 I/OPU - In Serial I/O Mode
SPI Serial FLASH Serial Data Input (RTL8370 MB output pin)
In Dual I/O Mode
SPI FLASH bi-directional pin (this is LSB)
SPF_CLK 85 OPU - SPI FLASH Clock.
GPIO_E/SPF_CSn 33 OPU - SPI FLASH chip select signal.
GPIO_D/SPF_SO_D1 32 I/OPU - In Serial I/O Mode
SPI Serial FLASH Serial Data Output (RTL8370 MB input pin)
In Dual I/O Mode
SPI FLASH bi-directional pin (this is MSB)
GPIO_C/SPF_SI_D0 31 I/OPU - In Serial I/O Mode
SPI Serial FLASH Serial Data Input (RTL8370MB output pin)
In Dual I/O Mode
SPI FLASH bi-directional pin (this is LSB)
GPIO_B/SPF_CLK 30 OPU - SPI FLASH Clock.
Note: when strapping SPF_MUX_SEL pulls down SPI FLASH interface position is pin 30\31\32\33, else is pin 89\87\86\85.

6.9. UART Interface Pins

Table 10. UART Interface Pins
Pin Name Pin No. Type Drive Description
(mA)
UARTRX 90 IPU - UART Rx Input Signal.
UARTTX 91 OPU - UART Tx Output Signal.

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 RTL8370MB
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6.10. CPU Interface Pins

Table 11. CPU Interface Pins
Pin Name Pin No. Type Drive Description
(mA)
Slave_SPI_SS# 134 IPU - SPI slave Mode Chip Select Input.
- 1\EEPROM auto load mode serial clock output
2\I2C slave mode serial clock input
SCK/MMD_MDC/Sla 3\MDC/MDIO slave mode serial clock input
ve_SPI_SCK 135 I/OPU 4\ SPI slave Mode serial clock input
- 1\EEPROM auto load mode serial data input
2\I2C slave mode serial data (bidirectional)
SDA/MMD_MDIO/Sl 3\MDC/MDIO slave mode serial data (bidirectional)
ave_SPI_SI 136 I/OPU 4\ SPI slave Mode serial data input
Slave_SPI_SO 137 OPU - SPI slave Mode serial data output

6.11. GPIO Interface Pins

Table 12. GPIO Interface Pins
Pin Name Pin No. Type Drive Description
(mA)
GPIO0 92 I/OPU - General Purpose Input/Output Interfaces IO0.
GPIO1 90 I/OPU - General Purpose Input/Output Interfaces IO1.
GPIO2 125 I/OPU - General Purpose Input/Output Interfaces IO2.
GPIO3 113 I/OPU - General Purpose Input/Output Interfaces IO3.
GPIO4 121 I/OPU - General Purpose Input/Output Interfaces IO4.
GPIO5 116 I/OPU - General Purpose Input/Output Interfaces IO5.
GPIO6 115 I/OPU - General Purpose Input/Output Interfaces IO6.
GPIO7 91 I/OPU - General Purpose Input/Output Interfaces IO7.
GPIO8 83 I/OPU - General Purpose Input/Output Interfaces IO8
GPIO9 84 I/OPU - General Purpose Input/Output Interfaces IO9.
GPIO10 85 I/OPU - General Purpose Input/Output Interfaces IO10.
GPIO11 86 I/OPU - General Purpose Input/Output Interfaces IO11.
GPIO12 87 I/OPU - General Purpose Input/Output Interfaces IO12.
GPIO13 88 I/OPU - General Purpose Input/Output Interfaces IO13.
GPIO14 89 I/OPU - General Purpose Input/Output Interfaces IO14.
GPIO15 93 I/OPU - General Purpose Input/Output Interfaces IO15.
GPIO16 94 I/OPU - General Purpose Input/Output Interfaces IO16.
GPIO17 114 I/OPU - General Purpose Input/Output Interfaces IO17.
GPIO18 117 I/OPU - General Purpose Input/Output Interfaces IO18.
GPIO_A 24 I/OPU - General Purpose Input/Output Interfaces IO_A.
GPIO_B 30 I/OPU - General Purpose Input/Output Interfaces IO_B
GPIO_C 31 I/OPU - General Purpose Input/Output Interfaces IO_C.
GPIO_D 32 I/OPU - General Purpose Input/Output Interfaces IO_D.
GPIO_E 33 I/OPU - General Purpose Input/Output Interfaces IO_E.

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 RTL8370MB
DRAFT Datasheet

6.12. Configuration Strapping Pins

Table 13. Configuration Strapping Pins
Pin Name Pin No. Type Description

Slave_SPI_SO/EEPROM_ 137 I/OPU EEPROM Mode Selection.

MOD Pull Up: EEPROM 24Cxx Size greater than 16Kbits (24C32~)
Pull Down: EEPROM 24Cxx Size less than or equal to 16Kbit
(24C02~24C16).
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
P9LED0/EN_PWRLIGHT 26 I/OPU Enable Power On Light.
Pull Up: Enable Power On Light
Pull Down: Disable Power On Light.
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
RG2_TXD2/M2_TXD2/P2 84 I/OPU
C C Enable SPI FLASH Interface.
_RXD2/P8LED0/GPIO9/E Pull Up: Enable FLASH interface
N_FLASH Pull Down: Disable FLASH interface
Note 1: The strapping pin DISAUTOLOAD, DIS_8051, and EN_SPIF
are for power on or reset initial stage configuration. (Refer to Table
14. Configuration Strapping Pins Configure Note.)
Note 2: Pull high or low via an external 4.7k ohm resistor upon
power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
RG1_TXD2/M1_TXD2/P1 124 I/OPU Disable Embedded 8051.
_RXD2/P1LED1/DIS_805 Pull Up: Disable embedded 8051 upon power on or reset
1 Pull Down: Enable embedded 8051 upon power on or reset
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
P9LED1/DISAUTOLOAD 27 I/OPU Disable EEPROM Autoload.
Pull Up: Disable EEPROM autoload upon power on or reset
Pull Down: Enable EEPROM autoload upon power on or reset
Note1: When DIS_8051=1 and DISAUTOLOAD=0, the EEPROM
data will be treat as register configuration data upon power on or
reset initial stage. When DIS_8051 = 0 and DISAUTOLOAD =0,
the EEPROM data will be loaded to embedded 8051 instruction
memory upon power on or reset.
Note2: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.

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 RTL8370MB
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Pin Name Pin No. Type Description

RG1_TXD0/M1_TXD0/P1 122 I/OPU Slave I2C/Slave MII Management Interface Selection 1.

_RXD0/P1LED2/SMI_SE Slave I2C/Slave MII Management Interface Selection 0.
L_1 [SMI_SEL_1, SMI_SEL_0]
LED_CK/P0LED0/SMI_S 129 I/OPU 00：LSB I2C
EL_0 01：MSB I2C
10：MDC/MDIO
11：RTK I2C
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
P4LED2/GPIO3/DIS_SPIS 113 I/OPU Disable SPI Slave Interface for External CPU Access RTL8370MB
Register
Pull Up: Disable SPI Slave Interface and refer [SMI_SEL_1,
SMI_SEL_0]
Pull Down: Enable SPI Slave Interface
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
RG1_TXD1/M1_TXD1/P1_ 123 I/OPU Slave SMI (MDC/MDIO) Device Address.
RXD1/P1LED0/MID29 Pull Up: Slave SMI (MDC/MDIO) Device Address is d‟29
Pull Down: Slave SMI (MDC/MDIO) Device Address is 0
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
RG1_TXD3/M1_TXD3/P1 125 I/OPU Enable Embedded PHY.
_RXD3/P0LED2/GPIO2/E Pull Up: Enable embedded PHY
N_PHY Pull Down: Disable embedded PHY
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset..
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
P9LED2/EEE_EN 28 I/OPU Enable 802.3az EEE.
Pull Up: Enable 802.3az EEE.
Pull Down: Disable 802.3az EEE.
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
GPIO_A/SPF_MUX_SEL 24 I/OPU SPI FLASH interface position select
Pull Up: select Spi-Flash-1 pin 89\87\86\85.
Pull Down: select Spi-Flash-2 pin 30\31\32\33.
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.

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Pin Name Pin No. Type Description

P8LED2/DIS_FX_AUTO 29 I/OPU Disable SerDes 1000BASE-X/100BASE-FX auto detect mode

Pull Down：Default set SDS mode to 1000BASE-X/100BASE-FX
auto detect mode
Pull Up：Default set SDS mode to 0x1F （SerDes in reset mode）
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
RG2_TXD3/M2_TXD3/P2_ 83 I/OPU Disable/Enable LED function when power on.
RXD3/P8LED1/GPIO8/DIS Pull Down: Enable LED
_LED Pull Up: Disable LED.
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
BUZZER/DIS_LPD 20 I/OPU Realtek Loop Detection Configuration.
Pull Up: Disable Loop detection function
Pull Down: Enable Loop detection function
2KHz signal out when looping is detected
Note: Pull high or low via an external 4.7k ohm resistor upon power
on or reset.

Table 14. Configuration Strapping Pins Configure Note

DISAUTOLOAD DIS_8051 EN_FLASH Initial Stage (Power On or Reset) Loading Data
From To
0 0 0 EEPROM Embedded 8051 Instruction Memory
0 0 1 FLASH Embedded 8051 Instruction Memory
0 1 0 EEPROM Register
1 Irrelevant Irrelevant Do Nothing Do Nothing

6.13. Miscellaneous Pins

Table 15. Miscellaneous Pins
Pin Name Pin No. Type Description

XTALI 132 AI 25MHz Crystal Clock Input and Feedback Pin.

25MHz +/-50ppm tolerance crystal reference or oscillator input.
XTALO 131 AO 25MHz Crystal Clock Output Pin.
25MHz +/-50ppm tolerance crystal output.

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Pin Name Pin No. Type Description

MDIREF 10 AO Reference Resistor.

A 2.49K ohm (1%) resistor must be connected between MDIREF and
GND.
NC 7,8,9 - Not connect. Must be left floating in normal operation.
SCK/MMD_MDC/Slave_ 135 I/O Master I2C Interface Clock for EEPROM auto download
SPI_SCK Slave I2C Interface Clock for external CPU to access DUT
Slave MII Management Interface Clock (selected via the hardware
strapping SMI_SEL1 & SMI_SEL0).
SDA/MMD_MDIO/Slave 136 I/O Master I2C Interface Data for EEPROM auto download
_SPI_SI Slave I2C Interface Data for external CPU to access DUT
Slave MII Management Interface Data (selected via the hardware
strapping SMI_SEL1 & SMI_SEL0).
nRESET 133 IS System Reset Input Pin.
When low active will reset the RTL8370MB.
INT 19 I/OPU Interrupt Output for External CPU.
RESERVED1 21 IPD Reserved. This pin must be pulled low via an external 4.7k ohm
resistor upon power on.
RESERVED2 22 I/OPD Reserved. This pin must be pulled low via an external 4.7k ohm
resistor upon power on.
RESERVED3 23 I/OPD Reserved. This pin must be pulled low via an external 4.7k ohm
resistor upon power on.
RESERVED4 25 I/OPU Reserved. This pin must be left floating in normal operation.

6.14. Test Pins

Table 16. Test Pins
Pin Name Pin No. Type Description

ATESTCK0 160 AO Reserved for Internal Use. Must be left floating.

ATESTCK1 59 AO Reserved for Internal Use. Must be left floating.
RTT1 13 AO Reserved for Internal Use. Must be left floating.
RTT2 14 AI Reserved for Internal Use. Must be left floating.

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6.15. Power and GND Pins

Table 17. Power and GND Pins
Pin Name Pin No. Type Description

DVDDIO 16,36 P Digital I/O High Voltage Power.

DVDDIO_1 111,126 P Digital I/O High Voltage Power for Extension Port 1 General Purpose
Interfaces.
DVDDIO_2 82,96 P Digital I/O High Voltage Power for Extension Port 2 General Purpose
Interfaces.
DVDDL 17,18,34,35,95,112, P Digital Low Voltage Power.
127,130
AVDDH 6,15,37,47,57,61,71, AP Analog High Voltage Power.
81,138,148,158,162,
172
AVDDL 1,12,42,52,66,76,14 AP Analog Low Voltage Power.
3,153,167
SVDDL 98,104,107 AP SerDes Low Voltage Power.
SVDDH 97 AP SerDes High Voltage Power.
PLLVDDL0 159 AP PLL0 Low Voltage Power.
PLLVDDL1 58 AP PLL1 Low Voltage Power.
GND EPAD_GND G GND.
AGND 8 AG Analog GND.
SGND 101,110 AG SerDes GND.
PLLGND0 161 AG PLL0 GND.
PLLGND1 60 AG PLL1 GND.

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7. Physical Layer Functional Overview

7.1. MDI Interface
The RTL8370MB embeds eight Gigabit Ethernet PHYs. The Gigabit Ethernet PHY uses a single
common MDI interface to support 1000Base-T, 100Base-TX, and 10Base-T. This interface consists of
four signal pairs-A, B, C, and D. Each signal pair consists of two bi-directional pins that can transmit and
receive at the same time. For 1000Base-T, all four pairs are used in both directions at the same time. For
10/100 links and during auto-negotiation, only pairs A and B are used.

7.2. 1000Base-T Transmit Function

The 1000Base-TX transmit function performs 8B/10B coding, scrambling, and 4D-PAM5 encoding.
These code groups are passed through a waveform-shaping filter to minimize EMI effects, and are
transmitted onto 4-pair CAT5 cable at 125MBaud/s through a D/A converter.

7.3. 1000Base-T Receive Function

Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the
transmitted signal from the input signal for effective reduction of near-end echo. The received signal is
then processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz.
The RX MAC retrieves the packet data from the internal receive MII/GMII interface and sends it to the
packet buffer manager.

7.4. 100Base-TX Transmit Function

The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,
NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then
scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such
that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit
stream is driven onto the network media in the form of MLT-3 signaling. The MLT-3 multi-level
signaling technology moves the power spectrum energy from high frequency to low frequency, which
also reduces EMI emissions.

7.5. 100Base-TX Receive Function

The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to
compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to
convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error
rate. A de-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL
circuit. Finally, the converted parallel data is fed into the MAC.
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7.6. 10Base-T Transmit Function

The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The
internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external
filter.

7.7. 10Base-T Receive Function

The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit
detects the signal level is above squelch level.

7.8. Auto-Negotiation for UTP

The RTL8370MB obtains the states of duplex, speed, and flow control ability for each port in UTP mode
through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During
auto-negotiation, each port advertises its ability to its link partner and compares its ability with
advertisements received from its link partner. By default, the RTL8370MB advertises full capabilities
(1000Full-only Giga PHY, 100Full, 100Half, 10Full, 10Half) together with flow control ability.

7.9. Crossover Detection and Auto Correction

The RTL8370MB automatically determines whether or not it needs to crossover between pairs (see
Table 18) so that an external crossover cable is not required. When connecting to another device that does
not perform MDI crossover, when necessary, the RTL8370MB automatically switches its pin pairs to
communicate with the remote device. When connecting to another device that does have MDI crossover
capability, an algorithm determines which end performs the crossover function.
The crossover detection and auto correction function can be disabled via register configuration. The pin
mapping in MDI and MDI Crossover mode is given below.
Table 18. Media Dependent Interface Pin Mapping
Pairs MDI MDI Crossover
1000Base-T 100Base-TX 10Base-T 1000Base-T 100Base-TX 10Base-T
A A TX TX B RX RX
B B RX RX A TX TX
C C Unused Unused D Unused Unused
D D Unused Unused C Unused Unused

7.10. Polarity Correction

The RTL8370MB automatically corrects polarity errors on the receiver pairs in 1000Base-T and
10Base-T modes. In 100Base-TX mode, the polarity is irrelevant.

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In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle
symbols. Once the de-scrambler is locked, the polarity is also locked on all pairs. The polarity becomes
unlocked only when the receiver loses lock.
In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The
detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The
polarity becomes unlocked when the link is down.

Link Partner RTL8370MB

+ +
RX _ _ TX

+ _ +
TX _ + _ RX

Figure 6. Conceptual Example of Polarity Correction

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8. General Function Description

8.1. Reset
8.1.1. Hardware Reset
In a power-on reset, an internal power-on reset pulse is generated and the RTL8370MB will start the reset
initialization procedures. These are:
 Determine various default settings via the hardware strap pins at the end of the nRESET signal
 Autoload the configuration from EEPROM if EEPROM is detected
 Complete the embedded SRAM BIST process
 Initialize the packet buffer descriptor allocation
 Initialize the internal registers and prepare them to be accessed by the external CPU

8.1.2. Software Reset

The RTL8370MB supports two software resets; a chip reset and a soft reset.
8.1.2.1 CHIP_RESET
When CHIP_RESET is set to 0b1 (write and self-clear), the chip will take the following steps:
1. Download configuration from strap pin and EEPROM
2. Start embedded SRAM BIST (Built-In Self Test)
3. Clear all the Lookup and VLAN tables
4. Reset all registers to default values
5. Restart the auto-negotiation process
8.1.2.2 SOFT_RESET
When SOFT_RESET is set to 0b1 (write and self-clear), the chip will clear the FIFO and re-start the
packet buffer link list.

8.2. IEEE 802.3x Full Duplex Flow Control

The RTL8370MB supports IEEE 802.3x flow control in 10/100/1000M modes. Flow control can be
decided in two ways:
 When Auto-Negotiation is enabled, flow control depends on the result of NWay
 When Auto-Negotiation is disabled, flow control depends on register definition

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8.3. Half Duplex Flow Control

In half duplex mode, the CSMA/CD media access method is the means by which two or more stations
share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the
medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If
the message collides with that of another station, then each transmitting station intentionally transmits for
an additional predefined period to ensure propagation of the collision throughout the system. The station
remains silent for a random amount of time (backoff) before attempting to transmit again.
When a transmission attempt has terminated due to a collision, it is retried until it is successful. The
scheduling of the retransmissions is determined by a controlled randomization process called “truncated
binary exponential backoff”. At the end of enforcing a collision (jamming), the switch delays before
attempting to retransmit the frame. The delay is an integer multiple of slot time (512 bit times). The
number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed
random integer „r‟ in the range:
0 ≤ r < 2k
where:
k = min (n, backoffLimit). The backoffLimit for the RTL8370MB is 10.
The half duplex back-off algorithm in the RTL8370MB does not have the maximum retry count
limitation of 16 (as defined in IEEE 802.3). This means packets in the switch will not be dropped if the
back-off retry count is over 16.

8.3.1. Back-Pressure Mode

In Back-Pressure mode, the RTL8370MB sends a 4-byte jam pattern (data=0xAA) to collide with
incoming packets when congestion control is activated. The Jam pattern collides at the fourth byte
counted from the preamble. RTL8370MB supports 48PASS1, which receives one packet after 48
consecutive jam collisions (data collisions are not included in the 48). Enable this function to prevent port
partition after 63 consecutive collisions (data collisions + consecutive jam collisions).

8.4. Search and Learning

Search
When a packet is received, the RTL8370MB uses the destination MAC address, Filtering Identifier (FID)
and enhanced Filtering Identifier (FID) to search the 8K-entry look-up table. The 48-bit MAC address,
12-bit FID and 3-bit EFID use a hash algorithm to calculate an 11-bit index value. The RTL8370MB uses
the index to compare the packet MAC address with the entries (MAC addresses) in the look-up table.
This is the „Address Search‟. If the destination MAC address is not found, the switch will broadcast the
packet according to VLAN configuration.
Learning
The RTL8370MB uses the source MAC address, FID, and EFID of the incoming packet to hash into a
11-bit index. It then compares the source MAC address with the data (MAC addresses) in this index. If
there is a match with one of the entries, the RTL8370MB will update the entry with new information. If
there is no match and the 8K entries are not all occupied by other MAC addresses, the RTL8370MB will
record the source MAC address and ingress port number into an empty entry. This process is called
„Learning‟.
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The RTL8370MB supports a 64-entry Content Addressable Memory (CAM) to avoid look-up table hash
collisions. When all 8K entries in the look-up table index are occupied, the source MAC address can be
learned into the 64-entry CAM. If both the look-up table and the CAM are full, the source MAC address
will not be learned in the RTL8370MB.
Address aging is used to keep the contents of the address table correct in a dynamic network topology.
The look-up engine will update the time stamp information of an entry whenever the corresponding
source MAC address appears. An entry will be invalid (aged out) if its time stamp information is not
refreshed by the address learning process during the aging time period. The aging time of the
RTL8370MB is between 200 and 400 seconds (typical is 300 seconds).

8.5. SVL and IVL/SVL

The RTL8370MB supports a 4K-group Filtering Identifier (FID) for L2 search and learning. In default
operation, all VLAN entries belong to the same FID. This is called Shared VLAN Learning (SVL). If
VLAN entries are configured to different FIDs, then the same source MAC address with multiple FIDs
can be learned into different look-up table entries. This is called Independent VLAN Learning and Shared
VLAN Learning (IVL/SVL).

8.6. Illegal Frame Filtering

Illegal frames such as CRC error packets, runt packets (length <64 bytes), and oversize packets
(length >maximum length) will be discarded by the RTL8370MB. The maximum packet length may be
set to 1522, 1536, 1552, or 16K bytes.

8.7. IEEE 802.3 Reserved Group Addresses Filtering Control

The RTL8370MB supports the ability to drop/forward IEEE 802.3 specified reserved group MAC
addresses: 01-80-C2-00-00-00 to 01-80-C2-00-00-2F. The default setting enables forwarding of these
reserved group MAC address control frames. Frames with group MAC address 01-80-C2-00-00-01
(802.3x Pause) and 01-80-C2-00-00-02 (802.3ad LACP) will always be filtered. Table 19 shows the
Reserved Multicast Address (RMA) configuration mode from 01-80-C2-00-00-00 to 01-80-C2-00-00-2F.
Table 19. Reserved Multicast Address Configuration Table
Assignment Value
Bridge Group Address 01-80-C2-00-00-00
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation 01-80-C2-00-00-01
IEEE Std 802.3ad Slow Protocols-Multicast Address 01-80-C2-00-00-02
IEEE Std 802.1X PAE Address 01-80-C2-00-00-03
All LANs Bridge Management Group Address 01-80-C2-00-00-10
GMRP Address 01-80-C2-00-00-20
GVRP Address 01-80-C2-00-00-21
Undefined 802.1 Bridge Address 01-80-C2-00-00-04
|
01-80-C2-00-00-0F

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Assignment Value
Undefined GARP Address 01-80-C2-00-00-22
|
01-80-C2-00-00-2F

8.8. Broadcast/Multicast/Unknown DA Storm Control

The RTL8370MB enables or disables per-port broadcast/multicast/unknown DA storm control by setting
registers (default is disabled). After the receiving rate of broadcast/multicast/unknown DA packets
exceeds a reference rate, all other broadcast/multicast/unknown DA packets will be dropped. The
reference rate is set via register configuration.

8.9. Port Security Function

The RTL8370MB supports three types of security function to prevent malicious attacks:
 Per-port enable/disable SA auto-learning for an ingress packet
 Per-port enable/disable look-up table aging update function for an ingress packet
 Per-port enable/disable drop all unknown DA packets

8.10. MIB Counters

The RTL8370MB supports a set of counters to support management functions.
 MIB-II (RFC 1213)
 Ethernet-Like MIB (RFC 3635)
 Interface Group MIB (RFC 2863)
 RMON (RFC 2819)
 Bridge MIB (RFC 1493)
 Bridge MIB Extension (RFC 2674)

8.11. Port Mirroring

The RTL8370MB supports one set of port mirroring functions for all ports. The TX, or RX, or both
TX/RX packets of the source port can be monitored from a mirror port.

8.12. VLAN Function

The RTL8370MB supports 4K VLAN groups. These can be configured as port-based VLANs,
IEEE 802.1Q tag-based VLANs, and Protocol-based VLANs. Two ingress-filtering and egress-filtering
options provide flexible VLAN configuration:
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Ingress Filtering
 The acceptable frame type of the ingress process can be set to „Admit All‟ or „Admit All Tagged‟
 „Admit‟ or „Discard‟ frames associated with a VLAN for which that port is not in the member set
Egress Filtering
 „Forward‟ or „Discard‟ Leaky VLAN frames between different VLAN domains
 „Forward‟ or „Discard‟ Multicast VLAN frames between different VLAN domains
The VLAN tag can be inserted or removed at the output port. The RTL8370MB will insert a Port VID
(PVID) for untagged frames, or remove the tag from tagged frames. The RTL8370MB also supports a
special insert VLAN tag function to separate traffic from the WAN and LAN sides in Router and
Gateway applications.
In router applications, the router may want to know which input port this packet came from. The
RTL8370MB supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on egress.
Using this function, VID information carried in the VLAN tag will be changed to PVID. The
RTL8370MB also provides an option to admit VLAN tagged packets with a specific PVID only. If this
function is enabled, it will drop non-tagged packets and packets with an incorrect PVID.

8.12.1. Port-Based VLAN

This default configuration of the VLAN function can be modified via an attached serial EEPROM or
EEPROM SMI Slave interface. The 4K-entry VLAN Table designed into the RTL8370MB provides full
flexibility for users to configure the input ports to associate with different VLAN groups. Each input port
can join with more than one VLAN group.
Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a
VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to
determine their VLAN association. All the packets received on a given input port will be forwarded to
this port‟s VLAN members.

8.12.2. IEEE 802.1Q Tag-Based VLAN

The RTL8370MB supports 4K VLAN entries to perform 802.1Q tag-based VLAN mapping. In 802.1Q
VLAN mapping, the RTL8370MB uses a 12-bit explicit identifier in the VLAN tag to associate received
packets with a VLAN. The RTL8370MB compares the explicit identifier in the VLAN tag with the 4K
VLAN Table to determine the VLAN association of this packet, and then forwards this packet to the
member set of that VLAN. Two VIDs are reserved for special purposes. One of them is all 1‟s, which is
reserved and currently unused. The other is all 0‟s, which indicates a priority tag. A priority-tagged frame
should be treated as an untagged frame.
When „802.1Q tag aware VLAN‟ is enabled, the RTL8370MB performs 802.1Q tag-based VLAN
mapping for tagged frames, but still performs port-based VLAN mapping for untagged frames. If „802.1Q
tag aware VLAN‟ is disabled, the RTL8370MB performs only port-based VLAN mapping both on
non-tagged and tagged frames. The processing flow when „802.1Q tag aware VLAN‟ is enabled is
illustrated below.
Two VLAN ingress filtering functions are supported in registers by the RTL8370MB. One is the „VLAN
tag admit control, which provides the ability to receive VLAN-tagged frames only. Untagged or priority
tagged (VID=0) frames will be dropped. The other is „VLAN member set ingress filtering‟, which will
drop frames if the ingress port is not in the member set.
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8.12.3. Protocol-Based VLAN

The RTL8370MB supports a 4-group Protocol-based VLAN configuration. The packet format can be
RFC 1042, LLC, or Ethernet, as shown in Figure 7. There are 4 configuration tables to assign the frame
type and corresponding field value. Taking IP packet configuration as an example, the user can configure
the frame type to be „Ethernet‟ and value to be „0x0800‟. Each table will index to one of the entries in the
4K-entry VLAN table. The packet stream will match the protocol type and the value will follow the
VLAN member configuration of the indexed entry to forward the packets.
Ethernet DA/SA TYPE ……

RFC_1042 DA/SA Length AA- AA-03 00-00-00 TYPE ……

LLC_Other DA/SA Length DSAP/SSAP ……

Frame Input

Type/Length is Frame Type

No
00-00~05-FF? = Ethernet

6 bytes after
Type/Length are Frame Type
No
AA-AA-03-00-00-00? = LLC_ Other

Frame Type
= RFC_1042

Figure 7. Protocol-Based VLAN Frame Format and Flow Chart

8.12.4. Port VID

In a router application, the router may want to know which input port this packet came from. The
RTL8370MB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag for untagged or
priority tagged packets on egress. When 802.1Q tag-aware VLAN is enabled, VLAN tag admit control is
enabled, and non-PVID Discard is enabled at the same time. When these functions are enabled, the
RTL8370MB will drop non-tagged packets and packets with an incorrect PVID.

8.13. QoS Function

The RTL8370MB supports 8 priority queues and input bandwidth control. Packet priority selection can
depend on Port-based priority, 802.1p/Q Tag-based priority, IPv4/IPv6 DSCP-based priority, and
ACL-based priority. When multiple priorities are enabled in the RTL8370MB, the packet‟s priority will
be assigned based on the priority selection table.
Each queue has one leaky bucket for Average Packet Rate. Per-queue in each output port can be set as
Strict Priority (SP) or Weighted Fair Queue (WFQ) for packet scheduling algorithm.

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8.13.1. Input Bandwidth Control

Input bandwidth control limits the input bandwidth. When input traffic is more than the RX Bandwidth
parameter, this port will either send out a „pause ON‟ frame, or drop the input packet depending on
register setup. Per-port input bandwidth control rates can be set from 8Kbps to 1Gbps (in 8Kbps steps).

8.13.2. Priority Assignment

Priority assignment specifies the priority of a received packet according to various rules. The
RTL8370MB can recognize the QoS priority information of incoming packets to give a different egress
service priority.
The RTL8370MB identifies the priority of packets based on several types of QoS priority information:
 Port-based priority
 802.1p/Q-based priority
 IPv4/IPv6 DSCP-based priority
 ACL-based priority

8.13.3. Priority Queue Scheduling

The RTL8370MB supports MAX-MIN packet scheduling.
Packet scheduling offers two modes:
 APR leaky bucket, which specifies the average rate of one queue
 Weighted Fair Queue (WFQ), which decides which queue is selected in one slot time to guarantee the
minimal packet rate of one queue
In addition, each queue of each port can select Strict Priority or WFQ packet scheduling according to
packet scheduling mode. Figure 8 shows the RTL8370MB packet-scheduling diagram.
Guaranteed Max. Guaranteed Min.
APR Leaky WFQ Leaky Bucket
Bucket

Queue 0

Queue 1 Scheduler

Queue 7

Figure 8. RTL8370MB MAX-MIN Scheduling Diagram

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8.13.4. IEEE 802.1p/Q and DSCP Remarking

The RTL8370MB supports the IEEE 802.1p/Q and IP DSCP (Differentiated Services Code Point)
remarking function. When packets egress from one of the 4 queues, the packet‟s 802.1p/Q priority and IP
DSCP can optionally be remarked to a configured value. Each output queue has a 3-bit 802.1p/Q, and a
6-bit IP DSCP value configuration register.

8.13.5. ACL-Based Priority

The RTL8370MB supports 64-entry ACL (Access Control List) rules. When a packet is received, its
physical port, Layer2, Layer3, and Layer4 information are recorded and compared to ACL entries.
If a received packet matches multiple entries, the entry with the lowest address is valid. If the entry is
valid, the action bit and priority bit will be applied.
 If the action bit is „Drop‟, the packet will be dropped. If the action bit is „CPU‟, the packet will be
trapped to the CPU instead of forwarded to non-CPU ports (except where it will be dropped by rules
other than the ACL rule)
 If the action bit is „Permit‟, ACL rules will override other rules
 If the action bit is „Mirror‟, the packet will be forwarded to the mirror port and the L2 lookup result
destination port. The mirror port indicates the port configured in the port mirror mechanism
 The priority bit will take effect only if the action bit is „CPU‟, „Permit‟, and „Mirror‟. The Priority bit
is used to determine the packet queue ID according to the priority assignment mechanism

8.14. IGMP & MLD Snooping Function

The RTL8370MB supports IGMP v1/v2/v3 and MLD v1/v2 snooping. The RTL8370MB can trap all
IGMP and MLD packets to the CPU port. The CPU processes these packets, gets the IP multicast group
information of all ports, and writes the correct multicast entry to the lookup table via EEPROM SMI.

8.15. IEEE 802.1x Function

The RTL8370MB supports IEEE 802.1x Port-based/MAC-based Access Control.
 Port-Based Access Control for each port
 Authorized Port-Based Access Control for each port
 Port-Based Access Control Direction for each port
 MAC-Based Access Control for each port
 MAC-Based Access Control Direction
 Optional Unauthorized Behavior
 Guest VLAN

8.15.1. Port-Based Access Control

Each port of the RTL8370MB can be set to 802.1x port-based authenticated checking function usage and
authorized status. Ports with 802.1X unauthorized status will drop received/transmitted frames.
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8.15.2. Authorized Port-Based Access Control

If a dedicated port is set to 802.1x port-based access control, and passes the 802.1x authorization, then its
port authorization status can be set to authorized.

8.15.3. Port-Based Access Control Direction

Ports with 802.1X unauthorized status will drop received/transmitted frames only when port authorization
direction is „BOTH‟. If the authorization direction of an 802.1X unauthorized port is IN, incoming frames
to that port will be dropped, but outgoing frames will be transmitted.

8.15.4. MAC-Based Access Control

MAC-Based Access Control provides authentication for multiple logical ports. Each logical port
represents a source MAC address. There are multiple logical ports for a physical port. When a logical port
or a MAC address is authenticated, the relevant source MAC address has the authorization to access the
network. A frame with a source MAC address that is not authenticated by the 802.1x function will be
dropped or trapped to the CPU.

8.15.5. MAC-Based Access Control Direction

Unidirectional and Bi-directional control are two methods used to process frames in 802.1x. As the
system cannot predict which port the DA is on, a system-wide MAC-based access control direction setup
is provided for determining whether receiving or bi-direction must be authorized.
If MAC-based access control direction is BOTH, then received frames with unauthenticated SA or
unauthenticated DA will be dropped. When MAC-based access control direction is IN, only received
frames with unauthenticated SA will be dropped.

8.15.6. Optional Unauthorized Behavior

Both in Port-Based Network Access Control and MAC-Based Access Control, a whole system control
setup is provided to determine unauthorized frame dropping, trapping to CPU, or tagging as belonging to
a Guest VLAN (see the following „Guest VLAN‟ section).

8.15.7. Guest VLAN

When the RTL8370MB enables the Port-based or MAC-based 802.1x function, and the connected PC
does not support the 802.1x function or does not pass the authentication procedure, the RTL8370MB will
drop all packets from this port.
The RTL8370MB also supports one Guest VLAN to allow unauthorized ports or packets to be forwarded
to a limited VLAN domain. The user can configure one VLAN ID and member set for these unauthorized
packets.

8.16. IIEEE 802.1D Function

When using IEEE 802.1D, the RTL8370MB supports 16 sets and four status‟ for each port for CPU
implementation 802.1D (STP) and 802.1s (MSTP) function:
 Disabled: The port will not transmit/receive packets, and will not perform learning

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 Blocking: The port will only receive BPDU spanning tree protocol packets, but will not transmit any
packets, and will not perform learning
 Learning: The port will receive any packet, including BPDU spanning tree protocol packets, and will
perform learning, but will only transmit BPDU spanning tree protocol packets
 Forwarding: The port will transmit/receive all packets, and will perform learning
The RTL8370MB also supports a per-port transmission/reception enable/disable function. Users can
control the port state via register.

8.17. Embedded 8051

An 8051 MCU is embedded in the RTL8370MB to support management functions. The 8051 MCU can
access all of the registers in the RTL8370MB through the internal bus. With the Network Interface Circuit
(NIC) acting as the data path, the 8051 MCU connects to the switch core and can transmit frames to or
receive frames from the Ether network. The features of the 8051 MCU are listed below:
 256 Bytes fast internal RAM
 On-chip 48K data memory
 On-chip 16K code memory
 Supports code-banking
 12KBytes NIC buffer
 EEPROM read/write ability

8.18. Realtek Cable Test (RTCT)

The RTL8370MB physical layer transceivers use DSP technology to implement the Realtek Cable Test
(RTCT) feature. The RTCT function can be used to detect short, open, or impedance mismatch in each
differential pair. The RTL8370MB also provides LED support to indicate test status and results.

8.19. LED Indicator

The RTL8370MB supports parallel and serial mode LEDs for each port. Each pin may have different
indicator information (defined in Table 20). Upon reset, the RTL8370MB supports chip diagnostics and
LED operation test by blinking all LEDs once. LED0 group default indicate Link/Act, LED1 group
default indicate Spd1000, LED2 group default indicate Spd100.
Table 20. LED Definitions
LED Statuses Description
LED_Off LED pin Output disable.
Dup/Col Duplex/Collision, Indicator. Blinking when collision occurs. Low for full duplex, and high for
half duplex mode.
Link/Act Link, Activity Indicator. Low for link established. Link/Act Blinking when the corresponding
port is transmitting or receiving.
Spd1000 1000Mbps Speed Indicator. Low for 1000Mbps.

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LED Statuses Description
Spd100 100Mbps Speed Indicator. Low for 100Mbps.
Spd10 10Mbps Speed Indicator. Low for 10Mbps.
Spd1000/Act 1000Mbps Speed/Activity Indicator. Low for 1000Mbps. Blinking when the corresponding
port is transmitting or receiving.
Spd100/Act 100Mbps Speed/Activity Indicator. Low for 100Mbps. Blinking when the corresponding port
is transmitting or receiving.
Spd10/Act 10Mbps Speed/Activity Indicator. Low for 10Mbps. Blinking when the corresponding port is
transmitting or receiving.
Spd100 (10)/Act 10/100Mbps Speed/Activity Indicator. Low for 10/100Mbps. Blinking when the corresponding
port is transmitting or receiving.
Act Activity Indicator. Act blinking when the corresponding port is transmitting or receiving.

8.19.1. Parallel LED Mode

The RTL8370MB supports parallel LED mode. Each port has three LED indicator pins. The parallel LED
pin also supports pin strapping configuration functions. The PnLED0, PnLED1, and PnLED2 pins are
dual-function pins: input operation for configuration upon reset, and output operation for LED after reset.
If the pin input is pulled high upon reset, the pin output is active low after reset. If the pin input is pulled
down upon reset, the pin output is active high after reset. For details refer to Figure 9 and Figure 10.
Typical values for pull-up/pull-down resistors are 4.7K.
The PnLED1 can be combined with PnLED0 or PnLED2 as a Bi-color LED.
LED_PnLED1 should operate with the same polarity as other Bi-color LED pins. For example:
 P0LED1 should pull up upon reset if P0LED1 is combined with P0LED2 as a Bi-color LED, and
P0LED2 input is pulled high upon reset. In this configuration, the output of these pins is active low
after reset
 P0LED1 should be pulled down upon reset if P0LED1 is combined with P0LED2 as a Bi-color LED,
and P0LED2 input is pulled down upon reset. In this configuration, the output of these pins is active
high after reset
Pull-Up Pull-Down
DVDDIO

4.7K LED Pin

ohm 470 ohm RTL 8370MB

4.7K 470 ohm

RTL 8370MB ohm
LED Pin

LED Pins Output Active Low LED Pins Output Active High

Figure 9. Pull-Up and Pull-Down of LED Pins for Single-Color LED

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Pull-Up Pull-Down
4.7K
SPD 1000 ohm DVDDIO SPD 100 4.7K ohm

470ohm 470ohm
RTL8370MB RTL8370MB
Yellow Green Yellow Green

SPD100 4.7K SPD1000 4.7K ohm

ohm

LED Pins Output Active Low LED Pins Output Active High

Figure 10. Pull-Up and Pull-Down of LED Pins for Bi-Color LED

8.19.2. Serial LED Mode

The RTL8370MB supports serial shift LED mode to show the speed, link status and other information of
the port status. The parallel LED pins are shared with EXT1 RGMII/GPIO and so on, if work in these
modes, the serial LED mode can be used to show port status. In serial mode each port supports up to three
LED indicator pins, LED0, LED1, and LED2.
8.19.2.1 Serial Shift LED Default Mode, per-port three single-color LED
T3=16ms

T2=3.54us

T1 = 120ns T4 = (0.4~0.6) * T1

LED_CK

P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 P9 P8 P7
LED_DA LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED2 LED2 LED2 LED2 LED2 LED2 LED2 LED2 LED2 LED2 LED0 LED0 LED0

Figure 11. RTL8370MB serial led mode shift sequence (per-port three single-color LED)

A 74HC164 8-Bit Serial-In, Parallel-Out Shift Register captures the per-port link status and diagnostic
information. The related circuit design is shown in the following diagram.

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3.3V

470 ohm
LED_DA A QA
P0_LED2
3.3V B
QB
P1_LED2
LED_CK CLK
QC
P2_LED2
QD
P3_LED2
74HC164 P4_LED2
The first QE
74HC164 QF
P5_LED2
QG
P6_LED2
QH P7_LED2

LED_DA A QA
P8_LED2
3.3V B P9_LED2
QB
LED_CK CLK
P0_LED1
QC

QD P1_LED1
The second 74HC164 P2_LED1
QE
74HC164 P3_LED1
QF
P4_LED1
QG

QH
P5_LED1

LED_DA A QA
P6_LED1
3.3V B
QB
P7_LED1
CLK
LED_CK P8_LED1
QC

QD
P9_LED1
The third 74HC164 P0_LED0
QE
74HC164 P1_LED0
QF
P2_LED0
QG

QH
P3_LED0

LED_DA A
P4_LED0
QA
3.3V B
QB
P5_LED0
CLK
LED_CK P6_LED0
QC

QD
P7_LED0
The fourth
74HC164 P8_LED0
QE
74HC164 QF
P9_LED0
QG

QH

Figure 12. RTL8370MB+74HC164 Serial LED Connection Diagram (per-port three single-color LED)

The RTL8231 shift register mode could reserve the serial data, and output parallel data in order. There are
36 shift registers in the RTL8231. The output data sequence is shown below:
LED Pin Output

LED[0] LED[1] LED[2] LED[35]

SI Q Q Q Q SO
D D D D

CLK_IN

Figure 13. RTL8231 Output Data Sequence

To latch the currently serial data which receive at the SI pin and shift the preceding data to the next stage
at the each rising edge of the serial clock. At the first the serial data input the RTL8231 output from the
pin 15 LED[0]. At the last shift register, the serial data output to LED[35] pin and the SO pin at the same
time.
The strapping pins configuration of RTL8231 in Shift Register Mode is depicted in Table 21.

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Table 21. RTL8231 Shift Register Mode Strapping Pins Configuration
Pin Configuration
Pin Name Type Description
Num for serial LED mode
Select RTL8231 in the SMI mode or Shift Register mode.
LED[0]/Dis_SMI 15 I/OPD 0: SMI mode.(default) Pull high
1: Shift register mode.
MOD[1:0] defines the parallel output initial value after finish reset.
2b‟00: LED[15] initial high, others parallel output initial low.
SO/MOD[1] 16 I/O 2b‟01: all parallel output initial high. Pull low
2b‟10: LED[0] initial high, others parallel output initial low.
2b‟11: LED[15] initial low, others parallel output initial high.
LED[15]/MOD[0] 42 I/ OPU Pull high

The related circuit design is shown in following diagram.

3.3V
4.7K
3.3V
RTL8370MB RTL8231 470 ohm
P0_LED2
Controller 3.3V LED0/Dis_SMI
4.7K*
33 ohm P1_LED2
LED1
LED_CK/STRP_SMI_SEL_0 4.7K* CLK_IN

...
NI_5pf 3.3V

...

...
...
4.7K
3.3V
4.7K* P5_LED1
33 ohm
LED15/MOD[0]

...

...
LED_DA

...
SI

...
4.7K* NI_5pf
P9_LED0
LED29

4.7K
3.3V SO/MOD[1]
4.7K*
STRP_DIS_LED

Figure 14. RTL8370MB+RTL8231 Serial LED Connection Diagram (per-port three single-color LED)
Note: A 4.7K ohm pull up or pull down resistor maybe used for proper strapping configuration.
8.19.2.2 Serial Shift LED, per-port two single-color LED
T3=16ms

T2=2.34us

T1 = 120ns T4 = (0.4~0.6) * T1

LED_CK

P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 P9 P8 P7
LED_DA LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED0 LED0 LED0

Figure 15. RTL8370MB serial led mode shift sequence (per-port two single-color LED)

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8.19.2.3 Serial Shift LED, per-port one single-color LED

T3=16ms
T2=1.14us

T4 = (0.4~0.6) * T1
T1 = 120ns

LED_CK

P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 P9 P8 P7
LED_DA LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0

Figure 16. RTL8370MB serial led mode shift sequence (per-port one single-color LED)

8.20. Green Ethernet

8.20.1. Link-On and Cable Length Power Saving
The RTL8370MB provides link-on and dynamic detection of cable length and dynamic adjustment of
power required for the detected cable length. This feature provides high performance with minimum
power consumption.

8.20.2. Link-Down Power Saving

The RTL8370MB implements link-down power saving on a per-port basis, greatly cutting power
consumption when the network cable is disconnected. After it detects an incoming signal, it wakes up
from link-down power saving and operates in normal mode.

8.21. IEEE 802.3az Energy Efficient Ethernet (EEE) Function

The RTL8370MB support IEEE 802.3az Energy Efficient Ethernet ability for 1000Base-T, 100Base-TX
in full duplex operation, and 10Base-T in full/half duplex mode.
The Energy Efficient Ethernet (EEE) optional operational mode combines the IEEE 802.3 Media Access
Control (MAC) sub-layer with 100Base-T and 1000Base-T Physical Layers defined to support operation
in Low Power Idle mode. When Low Power Idle mode is enabled, systems on both sides of the link can
disable portions of the functionality and save power during periods of low link utilization.
 For 1000Base-T PHY: Supports Energy Efficient Ethernet with the optional function of Low Power
Idle
 For 100Base-TX PHY: Supports Energy Efficient Ethernet with the optional function of Low Power
Idle
 For 10Base-T, EEE defines a 10Mbps PHY (10Base-Te) with reduced transmit amplitude
requirements. 10Base-Te is fully interoperable with 10Base-T PHYs over 100m of class-D (Cat-5)
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cable
The RTL8370MB MAC uses Low Power Idle signaling to indicate to the PHY, and to the link partner,
that a break in the data stream is expected, and components may use this information to enter power
saving modes that require additional time to resume normal operation. Similarly, it informs the LPI Client
that the link partner has sent such an indication.

8.22. Interrupt Pin for External CPU

The RTL8370MB provides one Interrupt output pin to interrupt an external CPU. The polarity of the
Interrupt output pin can be configured via register access. In configuration registers, each port has link-up
and link-down interrupt flags with mask.
When port link-up or link-down interrupt mask is enabled, the RTL8370MB will raise the interrupt signal
to alarm the external CPU. The CPU can read the interrupt flag to determine which port has changed to
which status.

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9. Interface Descriptions
9.1. I2C Master for EEPROM Auto-load
The EEPROM interface of the RTL8370MB uses the serial bus I2C to read the Serial EEPROM. When
the RTL8370MB is powered up, it drives SCK and SDA to read the configuration/code data from the
EEPROM by strapping configuration.

SCK

SDA

START STOP

Figure 17. I2C Start and Stop Command

3.3V
1.5K ohm
I2C Master EERPOM
SCK EEPROM_SCL
3.3V
1.5K ohm
33 ohm
SDA EEPROM_SDA

4.7K ohm
STRP_DISAUTOLOAD

Figure 18. I2C Master for EEPROM Auto-load Interface Connection Example
The EEPROM can be divided into two sizes: 2Kb~8Kb and 32Kb~512Kb. The address of the small size
EEPROM is 8-bits, however the larger EEPROM has word-high addressing and word-low addressing,
and it is 16-bits (two bytes). The RTL8370MB supports these two types EEPROM.
1 ADDRESS BYTE
1 CONTROL BYTE 1 CONTROL BYTE The 1st DATA BYTE The 2nd DATA BYTE N
O
R/ A A R/ A A A
S 1 0 1 0 0 0 0 W# C ADDR[7:0] C S 1 0 1 0 0 0 0 W# C C C P
(0) K K (1) K K K
MSB to LSB MSB to LSB MSB to LSB

ACK by ACK by ACK by ACK by Master NOACK by Master

Slave(EEPROM) Slave(EEPROM) Slave(EEPROM)

Figure 19. 8-Bit EEPROM Sequential Read

The 1st ADDRESS The 2nd ADDRESS
1 CONTROL BYTE BYTE (Word High BYTE (Word Low 1 CONTROL BYTE The 1st DATA BYTE The 2nd DATA BYTE N
Addressing) Addressing) O
R/ A A A R/ A A A
S 1 0 1 0 0 0 0 W# C ADDR[15:8] C ADDR[7:0] C S 1 0 1 0 0 0 0 W# C C C P
(0) K K K (1) K K K
MSB to LSB MSB to LSB MSB to LSB MSB to LSB

ACK by ACK by ACK by ACK by ACK by Master NOACK by Master

Slave(EEPROM) Slave(EEPROM) Slave(EEPROM) Slave(EEPROM)

Figure 20. 16-Bit EEPROM Sequential Read

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9.2. I2C-Like Slave Interface for External CPU to Access

RTL8370MB
When EEPROM auto-load is complete, the RTL8370MB registers can be accessed via SCK and SDA
(I2C-Like) via an external CPU (Decided by Strapping Configuration).
3.3V
1.5K ohm
I2C Slave External CPU
S_SCK M_SCL
3.3V
1.5K ohm

S_SDA M_SDA
3.3V

4.7K ohm*
STRP_SMI_SEL_1
4.7K ohm*
STRP_SMI_SEL_0

Figure 21. I2C-Like Slave for External CPU Access Interface Connection Example
Note: For RTL8370MB, the Strapping STRP_DIS_SPIS need floating or pull up by a 4.7K ohm Resistor.
The 1st ADDRESS The 2nd ADDRESS The 1st DATA BYTE The 2nd DATA BYTE
1 CONTROL BYTE BYTE (reg_addr[7:0]) BYTE (reg_addr[15:8]) (write_data[7:0]) (write_data[15:8])
R/ A A A A A
S 1 0 1 1 1 0 0 W# C ADDR[7:0] C ADDR[15:8] C C C P
(0) K K K K K
MSB to LSB MSB to LSB MSB to LSB MSB to LSB

ACK by Slave ACK by Slave ACK by Slave ACK by Slave ACK by Slave

Figure 22. I2C-Like Slave Interface Write Command

The 1st ADDRESS The 2nd ADDRESS The 1st DATA BYTE The 2nd DATA BYTE
1 CONTROL BYTE BYTE (reg_addr[7:0]) N
BYTE (reg_addr[15:8]) (read_data[7:0]) (read_data[15:8])
O
R/ A A A A A
S 1 0 1 1 1 0 0 W# C ADDR[7:0] C ADDR[15:8] C C C P
(1) K K K K K
MSB to LSB MSB to LSB MSB to LSB MSB to LSB

ACK by Slave ACK by Slave ACK by Slave ACK by Master NOACK by Master

Figure 23. I2C-Like Slave Interface Read Command

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9.3. Slave MII Management SMI Interface for External CPU to

Access RTL8370MB
The RTL8370MB registers can be accessed via Slave MDC and MDIO via an external CPU (Decided by
Strapping Configuration).

SMI Slave 33 ohm

External CPU
S_MDC M_MDC
3.3V
1.5K ohm

S_MDIO 3.3V
M_MDIO

4.7K ohm
STRP_SMI_SEL_1
4.7K ohm
STRP_SMI_SEL_0

Figure 24. Slave MII Management SMI Interface Connection Example

Note: For RTL8370MB, the Strapping STRP_DIS_SPIS need floating or pull up by a 4.7K ohm Resistor.
Table 22. Slave MII Management SMI Access Format
Management Frame Fields
PRE ST OP DEVAD REGAD TA DATA IDLE
Read 1…1 01 10 AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD Z
Write 1…1 01 01 AAAAA RRRRR 10 DDDDDDDDDDDDDDDD Z

Note: The Slave needs no less than 32bit Preambles (PRE) for accessing slave by Slave SMI interface
default. External CPU can configure the Slave to enable preamble suppression function, and then the
Slave doesn‟t need preamble for accessing slave.

9.4. Slave SPI Interface for External CPU to Access

RTL8370MB
The RTL8370MB registers can be accessed via Slave SPI Interface via an external CPU (Decided by
Strapping Configuration).

SPI Slave 33 ohm

External CPU
S_SPI_CLK M_SPI_CLK
3.3V
4.7K ohm

S_SPI_CSn M_SPI_CS#
33 ohm

33 ohm
S_SPI_DI M_SPI_DO
33 ohm

S_SPI_DO M_SPI_DI

4.7K ohm
STRP_DIS_SPIS

Figure 25. Slave SPI for External CPU Access Interface Connection Example

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S_SPI_CSn

0 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

S_SPI_CLK

Instruction (02h) 16-bits Reg Address Data Byte 1 (write_data[15:8]) Data Byte 2 (write_data[7:0])

S_SPI_DI
15 14 13 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Slave Input)

Figure 26. Slave SPI for External CPU Access Write Command

S_SPI_CSn

0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

S_SPI_CLK

Instruction (03h) 16-bits Reg Address

S_SPI_DI
15 14 13 10 9 8 7 6 5 4 3 2 1 0
(Slave Input)

S_SPI_DO Data Out Byte 1 (read_data[15:8]) Data Out Byte 2 (read_data[7:0])

(Slave Output) High Impedance
x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Figure 27. Slave SPI for External CPU Access Read Command

9.5. SPI FLASH Interface

The RTL8370MB supports Serial IO and Dual IO mode SPI Interface to Connect SPI FLASH. The
RTL8370MB only supports 3-byte address mode access. No more than 4Mbyte capacity of the SPI
FLASH is better for RTL8370MB application.

Controller SPI FLASH

SPI_F_CLK CLK
3.3V
NC-4.7K ohm

nSPI_F_CS /CS

SPI_F_D1 DO(IO1)

SPI_F_D0 DI(IO0)

Figure 28. SPI FLASH Interface Connection Example

9.6. Extension GMAC1 & GMAC2 RGMII/MII/TMII/RMII

Interface
The RTL8370MB shares two extension interfaces and an LED interface with the General Purpose
Interface. When the extension interfaces are configured as dual RGMII/MII/TMII/RMII mode, the LED
interface only supports LED_DA and LED_CK pins in serial LED mode.
Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 49 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet
Table 23. RTL8370MB General Purpose Interfaces Pin Definitions
RGMII MAC MII PHY MII MAC TMII PHY TMII MAC RMII PHY RMII
RG1_RXD3 M1_MRXD3 M1_PTXD3 TM1_MRXD3 TM1_PTXD3
RG1_RXD2 M1_MRXD2 M1_PTXD2 TM1_MRXD2 TM1_PTXD2
RG1_RXD1 M1_MRXD1 M1_PTXD1 TM1_MRXD1 TM1_PTXD1 RM1_MRXD1 RM1_PTXD1
RG1_RXD0 M1_MRXD0 M1_PTXD0 TM1_MRXD0 TM1_PTXD0 RM1_MRXD0 RM1_PTXD0
RG1_RXCTL M1_MRXDV M1_PTXEN TM1_MRXDV TM1_PTXEN RM1_MCRSDV RM1_PTXEN
RG1_RXC M1_MRXC M1_PTXC TM1_MRXC TM1_PTXC
RG1_TXC M1_MTXC M1_PRXC TM1_MTXC TM1_PRXC RM1_MREFCK RM1_PREFCK
RG1_TXCTL M1_MTXEN M1_PRXDV TM1_MTXEN TM1_PRXDV RM1_MTXEN RM1_PCRSDV
RG1_TXD0 M1_MTXD0 M1_PRXD0 TM1_MTXD0 TM1_PRXD0 RM1_MTXD0 RM1_RXD0
RG1_TXD1 M1_MTXD1 M1_PRXD1 TM1_MTXD1 TM1_PRXD1 RM1_MTXD1 RM1_RXD0
RG1_TXD2 M1_MTXD2 M1_PRXD2 TM1_MTXD2 TM1_PRXD2
RG1_TXD3 M1_MTXD3 M1_PRXD3 TM1_MTXD3 TM1_PRXD3

RG2_TXD3 M2_MTXD3 M2_PRXD3 TM2_MTXD3 TM2_PRXD3

RG2_TXD2 M2_MTXD2 M2_PRXD2 TM2_MTXD2 TM2_PRXD2
RG2_TXD1 M2_MTXD1 M2_PRXD1 TM2_MTXD1 TM2_PRXD1 RM2_MTXD1 RM2_RXD1
RG2_TXD0 M2_MTXD0 M2_PRXD0 TM2_MTXD0 TM2_PRXD0 RM2_MTXD0 RM2_RXD0
RG2_TXCTL M2_MTXEN M2_PRXDV TM2_MTXEN TM2_PRXDV RM2_MTXEN RM2_PCRSDV
RG2_TXC M2_MTXC M2_PRXC TM2_MTXC TM2_PRXC
RG2_RXC M2_MRXC M2_PTXC TM2_MRXC TM2_PTXC
RG2_RXCTL M2_MRXDV M2_PTXEN TM2_MRXDV TM2_PTXEN RM2_MCRSDV RM2_PTXEN
RG2_RXD0 M2_MRXD0 M2_PTXD0 TM2_MRXD0 TM2_PTXD0 RM2_MRXD0 RM2_PTXD0
RG2_RXD1 M2_MRXD1 M2_PTXD1 TM2_MRXD1 TM2_PTXD1 RM2_MRXD1 RM2_PTXD1
RG2_RXD2 M2_MRXD2 M2_PTXD2 TM2_MRXD2 TM2_PTXD2
RG2_RXD3 M2_MRXD3 M2_PTXD3 TM2_MRXD3 TM2_PTXD3

9.6.1. Extension GMAC1 and GMAC2 RGMII Mode

The Extension GMAC1 and Extension GMAC2 of the RTL8370MB support RGMII interfaces to an
external CPU.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 50 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
RGMII DVDDIO_1 RGMII
4.7K*

RG1_TXD3 4.7K* RG_RXD3

DVDDIO_1
4.7K*

RG1_TXD2 4.7K* RG_RXD2

DVDDIO_1
4.7K*

RG1_TXD1 4.7K* RG_RXD1

DVDDIO_1
4.7K*

RG1_TXD0 4.7K* RG_RXD0

RG1_TXCTL 4.7K RG_RXCTL

RG1_TXC RG_RXC

RG1_RXC RG_TXC
DVDDIO_1
4.7K*

RG1_RXCTL 4.7K* RG_TXCTL

DVDDIO_1
4.7K*

RG1_RXD0 4.7K* RG_TXD3

DVDDIO_1
4.7K*

RG1_RXD1 4.7K* RG_TXD2

DVDDIO_1
4.7K*

RG1_RXD2 4.7K* RG_TXD1

DVDDIO_1
4.7K*

RG1_RXD3 4.7K* RG_TXD0

Management Interface
I2C/SMI/SPI

nRESET Reset
DVDDIO_1
4.7K*
STRP_DIS_LED

Figure 29. Signal Diagram of RGMII Mode of the Extension GMAC1

Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 51 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
RGMII DVDDIO_2
RGMII
4.7K*

RG2_RXD3 4.7K* RG_TXD3

DVDDIO_2
4.7K*

RG2_RXD2 4.7K* RG_TXD2

DVDDIO_2
4.7K*

RG2_RXD1 4.7K* RG_TXD1

DVDDIO_2
4.7K*

RG2_RXD0 4.7K* RG_TXD0

DVDDIO_2
4.7K*

RG2_RXCTL 4.7K* RG_TXCTL

RG2_RXC RG_TXC

RG2_TXC RG_RXC

RG2_TXCTL 4.7K RG_RXCTL

DVDDIO_2
4.7K*

RG2_TXD0 4.7K* RG_RXD0

DVDDIO_2
4.7K*

RG2_TXD1 4.7K* RG_RXD1

DVDDIO_2
4.7K*

RG2_TXD2 4.7K* RG_RXD2

DVDDIO_2
4.7K*

RG2_TXD3 RG_RXD3
Management Interface
I2C/SMI/SPI

nRESET Reset

Figure 30. Signal Diagram of RGMII Mode of the Extension GMAC2

Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 52 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

9.6.2. Extension GMAC1 and GMAC2 Full Duplex MII MAC/PHY

Mode Interface
Both the Extension GMAC1 and Extension GMAC2 of the RTL8370MB support full duplex MII
MAC/PHY mode interfaces to an external CPU.
RTL8370MB CPU
PHY Mode MII DVDDIO_1 MAC Mode MII
4.7K*

M1_PRXD3 4.7K* M_MRXD3

DVDDIO_1
4.7K*

M1_PRXD2 4.7K* M_MRXD2

DVDDIO_1
4.7K*

M1_PRXD1 4.7K* M_MRXD1

DVDDIO_1
4.7K*

M1_PRXD0 4.7K* M_MRXD0

M1_PRXDV 4.7K M_MRXDV

M1_PRXC M_MRXCLK

M1_PTXC M_MTXCLK
DVDDIO_1
4.7K*

M1_PTXEN 4.7K* M_MTXEN

DVDDIO_1
4.7K*

M1_PTXD0 4.7K* M_MTXD0

DVDDIO_1
4.7K*

M1_PTXD1 4.7K* M_MTXD1

DVDDIO_1
4.7K*

M1_PTXD2 4.7K* M_MTXD2

DVDDIO_1
4.7K*

M1_PTXD3 4.7K* M_MTXD3

Management Interface
I2C/SMI/SPI

nRESET Reset
DVDDIO_1
4.7K*
M_CRS
STRP_DIS_LED M_COL

Figure 31. Signal Diagram of MII PHY Mode of the Extension GMAC1
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 53 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
MAC Mode MII DVDDIO_1 PHY Mode MII
4.7K*

M1_MTXD3 4.7K* M_PTXD3

DVDDIO_1
4.7K*

M1_MTXD2 4.7K* M_PTXD2

DVDDIO_1
4.7K*

M1_MTXD1 4.7K* M_PTXD1

DVDDIO_1
4.7K*

M1_MTXD0 4.7K* M_PTXD0

M1_MTXEN 4.7K M_PTXEN

M1_MTXC M_PTXCLK

M1_MRXC M_PRXCLK
DVDDIO_1
4.7K*

M1_MRXDV 4.7K* M_PRXDV

DVDDIO_1
4.7K*

M1_MRXD0 4.7K* M_PRXD0

DVDDIO_1
4.7K*

M1_MRXD1 4.7K* M_PRXD1

DVDDIO_1
4.7K*

M1_MRXD2 4.7K* M_PRXD2

DVDDIO_1
4.7K*

M1_MRXD3 4.7K* M_PRXD3

Management Interface
I2C/SMI/SPI

nRESET Reset
DVDDIO_1
4.7K*
M_CRS
STRP_DIS_LED M_COL

Figure 32. Signal Diagram of MII MAC Mode of the Extension GMAC1
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 54 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
PHY Mode MII DVDDIO_2
MAC Mode MII
4.7K*

M2_PTXD3 4.7K* M_MTXD3

DVDDIO_2
4.7K*

M2_PTXD2 4.7K* M_MTXD2

DVDDIO_2
4.7K*

M2_PTXD1 4.7K* M_MTXD1

DVDDIO_2
4.7K*

M2_PTXD0 4.7K* M_MTXD0

DVDDIO_2
4.7K*

M2_PTXEN 4.7K* M_MTXEN

M2_PTXC M_MTXCLK

M2_PRXC M_MRXCLK

M2_PRXDV 4.7K M_MRXDV

DVDDIO_2
4.7K*

M2_PRXD0 4.7K* M_MRXD0

DVDDIO_2
4.7K*

M2_PRXD1 4.7K* M_MRXD1

DVDDIO_2
4.7K*

M2_PRXD2 4.7K* M_MRXD2

DVDDIO_2
4.7K*

M2_PRXD3 M_MRXD3
Management Interface
I2C/SMI/SPI

nRESET Reset
M_CRS
M_COL

Figure 33. Signal Diagram of MII PHY Mode of the Extension GMAC2
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 55 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
MAC Mode MII DVDDIO_2
PHY Mode MII
4.7K*

M2_MRXD3 4.7K* M_PRXD3

DVDDIO_2
4.7K*

M2_MRXD2 4.7K* M_PRXD2

DVDDIO_2
4.7K*

M2_MRXD1 4.7K* M_PRXD1

DVDDIO_2
4.7K*

M2_MRXD0 4.7K* M_PRXD0

DVDDIO_2
4.7K*

M2_MRXDV 4.7K* M_PRXDV

M2_MRXC M_PRXCLK

M2_MTXC M_PTXCLK

M2_MTXEN 4.7K M_PTXEN

DVDDIO_2
4.7K*

M2_MTXD0 4.7K* M_PTXD0

DVDDIO_2
4.7K*

M2_MTXD1 4.7K* M_PTXD1

DVDDIO_2
4.7K*

M2_MTXD2 4.7K* M_PTXD2

DVDDIO_2
4.7K*

M2_MTXD3 M_PTXD3
Management Interface
I2C/SMI/SPI

nRESET Reset
M_CRS
M_COL

Figure 34. Signal Diagram of MII MAC Mode of the Extension GMAC2
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 56 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

9.6.3. Extension GMAC1 and GMAC2 Full Duplex TMII MAC/PHY

Mode Interface
Both the Extension GMAC1 and Extension GMAC2 of the RTL8370MB support full duplex TMII
(Turbo MII) MAC/PHY mode interfaces to an external CPU.
RTL8370MB CPU
PHY Mode TMII DVDDIO_1 MAC Mode TMII
4.7K*

TM1_PRXD3 4.7K* TM_MRXD3

DVDDIO_1
4.7K*

TM1_PRXD2 4.7K* TM_MRXD2

DVDDIO_1
4.7K*

TM1_PRXD1 4.7K* TM_MRXD1

DVDDIO_1
4.7K*

TM1_PRXD0 4.7K* TM_MRXD0

TM1_PRXDV 4.7K TM_MRXDV

TM1_PRXC TM_MRXCLK

TM1_PTXC TM_MTXCLK
DVDDIO_1
4.7K*

TM1_PTXEN 4.7K* TM_MTXEN

DVDDIO_1
4.7K*

TM1_PTXD0 4.7K* TM_MTXD0

DVDDIO_1
4.7K*

TM1_PTXD1 4.7K* TM_MTXD1

DVDDIO_1
4.7K*

TM1_PTXD2 4.7K* TM_MTXD2

DVDDIO_1
4.7K*

TM1_PTXD3 4.7K* TM_MTXD3

Management Interface
I2C/SMI/SPI

nRESET Reset
DVDDIO_1
4.7K*
TM_CRS
STRP_DIS_LED TM_COL

Figure 35. Signal Diagram of TMII PHY Mode of the Extension GMAC1
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 57 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
MAC Mode TMII DVDDIO_1 PHY Mode TMII
4.7K*

TM1_MTXD3 4.7K* TM_PTXD3

DVDDIO_1
4.7K*

TM1_MTXD2 4.7K* TM_PTXD2

DVDDIO_1
4.7K*

TM1_MTXD1 4.7K* TM_PTXD1

DVDDIO_1
4.7K*

TM1_MTXD0 4.7K* TM_PTXD0

TM1_MTXEN 4.7K TM_PTXEN

TM1_MTXC TM_PTXCLK

TM1_MRXC TM_PRXCLK
DVDDIO_1
4.7K*

TM1_MRXDV 4.7K* TM_PRXDV

DVDDIO_1
4.7K*

TM1_MRXD0 4.7K*
TM_PRXD0

DVDDIO_1
4.7K*

TM1_MRXD1 4.7K* TM_PRXD1

DVDDIO_1
4.7K*

TM1_MRXD2 4.7K* TM_PRXD2

DVDDIO_1
4.7K*

TM1_MRXD3 4.7K* TM_PRXD3

Management Interface
I2C/SMI/SPI

nRESET Reset
DVDDIO_1
4.7K*
TM_CRS
STRP_DIS_LED TM_COL

Figure 36. Signal Diagram of TMII MAC Mode of the Extension GMAC1
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 58 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
PHY Mode TMII DVDDIO_2
MAC Mode TMII
4.7K*

TM2_PTXD3 4.7K* TM_MTXD3

DVDDIO_2
4.7K*

TM2_PTXD2 4.7K* TM_MTXD2

DVDDIO_2
4.7K*

TM2_PTXD1 4.7K* TM_MTXD1

DVDDIO_2
4.7K*

TM2_PTXD0 4.7K* TM_MTXD0

DVDDIO_2
4.7K*

TM2_PTXEN 4.7K* TM_MTXEN

TM2_PTXC TM_MTXCLK

TM2_PRXC TM_MRXCLK

TM2_PRXDV 4.7K TM_MRXDV

DVDDIO_2
4.7K*

TM2_PRXD0 4.7K* TM_MRXD0

DVDDIO_2
4.7K*

TM2_PRXD1 4.7K* TM_MRXD1

DVDDIO_2
4.7K*

TM2_PRXD2 4.7K* TM_MRXD2

DVDDIO_2
4.7K*

TM2_PRXD3 TM_MRXD3
Management Interface
I2C/SMI/SPI

nRESET Reset
TM_CRS
TM_COL

Figure 37. Signal Diagram of TMII PHY Mode of the Extension GMAC2
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 59 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
MAC Mode TMII DVDDIO_2
PHY Mode TMII
4.7K*

TM2_MRXD3 4.7K* TM_PRXD3

DVDDIO_2
4.7K*

TM2_MRXD2 4.7K* TM_PRXD2

DVDDIO_2
4.7K*

TM2_MRXD1 4.7K* TM_PRXD1

DVDDIO_2
4.7K*

TM2_MRXD0 4.7K* TM_PRXD0

DVDDIO_2
4.7K*

TM2_MRXDV 4.7K* TM_PRXDV

TM2_MRXC TM_PRXCLK

TM2_MTXC TM_PTXCLK

TM2_MTXEN 4.7K TM_PTXEN

DVDDIO_2
4.7K*

TM2_MTXD0 4.7K* TM_PTXD0

DVDDIO_2
4.7K*

TM2_MTXD1 4.7K* TM_PTXD1

DVDDIO_2
4.7K*

TM2_MTXD2 4.7K* TM_PTXD2

DVDDIO_2
4.7K*

TM2_MTXD3 TM_PTXD3
Management Interface
I2C/SMI/SPI

nRESET Reset
TM_CRS
TM_COL

Figure 38. Signal Diagram of TMII MAC Mode of the Extension GMAC2
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 60 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

9.6.4. Extension GMAC1 and GMAC2 RMII MAC/PHY Mode Interface

Both the Extension GMAC1 and Extension GMAC2 of the RTL8370MB support RMII MAC/PHY mode
interfaces to an external CPU.

RTL8370MB CPU
PHY Mode RMII MAC Mode RMII
DVDDIO_1
4.7K*

RM1_PRXD1 4.7K* RM_MRXD1

DVDDIO_1
4.7K*

RM1_PRXD0 RM_MRXD0
4.7K*

DVDDIO_1
4.7K*

RM1_PRXDV RM_MRXDV
4.7K*

DVDDIO_1
4.7K*

RM1_REFCLK RM_REFCLK
4.7K*

DVDDIO_1
4.7K*

RM1_PTXEN RM_MTXEN
4.7K*

DVDDIO_1
4.7K*

RM1_PTXD0 RM_MTXD0
4.7K*

DVDDIO_1
4.7K*

RM1_PTXD1 4.7K* RM_MTXD1

Management Interface
I2C/SMI/SPI

nRESET Reset
DVDDIO_1
4.7K*
STRP_DIS_LED

Figure 39. Signal Diagram of RMII PHY Mode of the Extension GMAC1
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 61 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
MAC Mode RMII PHY Mode RMII
DVDDIO_1
4.7K*

RM1_MTXD1 4.7K* RM_PTXD1

DVDDIO_1
4.7K*

RM1_MTXD0 RM_PTXD0
4.7K*

DVDDIO_1
4.7K*

RM1_MTXEN RM_PTXEN
4.7K*

DVDDIO_1
4.7K*

RM1_REFCLK RM_REFCLK
4.7K*

DVDDIO_1
4.7K*

RM1_MRXDV RM_PRXDV
4.7K*

DVDDIO_1
4.7K*

RM1_MRXD0 RM_PRXD0
4.7K*

DVDDIO_1
4.7K*

RM1_MRXD1 4.7K* RM_PRXD1

Management Interface
I2C/SMI/SPI

nRESET Reset
DVDDIO_1
4.7K*
STRP_DIS_LED

Figure 40. Signal Diagram of RMII MAC Mode of the Extension GMAC1
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 62 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
PHY Mode RMII MAC Mode RMII
DVDDIO_2
4.7K*

RM2_PRXD1 4.7K* RM_MRXD1

DVDDIO_2
4.7K*

RM2_PRXD0 RM_MRXD0
4.7K*

DVDDIO_2
4.7K*

RM2_PRXDV RM_MRXDV
4.7K*

DVDDIO_2
4.7K*

RM2_REFCLK RM_REFCLK
4.7K*

DVDDIO_2
4.7K*

RM2_PTXEN RM_MTXEN
4.7K*

DVDDIO_2
4.7K*

RM2_PTXD0 RM_MTXD0
4.7K*

DVDDIO_2
4.7K*

RM2_PTXD1 4.7K* RM_MTXD1

Management Interface
I2C/SMI/SPI

nRESET Reset
DVDDIO_1
4.7K*
STRP_DIS_LED

Figure 41. Signal Diagram of RMII PHY Mode of the Extension GMAC2
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 63 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RTL8370MB CPU
MAC Mode RMII PHY Mode RMII
DVDDIO_2
4.7K*

RM2_MTXD1 4.7K* RM_PTXD1

DVDDIO_2
4.7K*

RM2_MTXD0 RM_PTXD0
4.7K*

DVDDIO_2
4.7K*

RM2_MTXEN RM_PTXEN
4.7K*

DVDDIO_2
4.7K*

RM2_REFCLK RM_REFCLK
4.7K*

DVDDIO_2
4.7K*

RM2_MRXDV RM_PRXDV
4.7K*

DVDDIO_2
4.7K*

RM2_MRXD0 RM_PRXD0
4.7K*

DVDDIO_2
4.7K*

RM2_MRXD1 4.7K* RM_PRXD1

Management Interface
I2C/SMI/SPI

nRESET Reset
DVDDIO_1
4.7K*
STRP_DIS_LED

Figure 42. Signal Diagram of RMII MAC Mode of the Extension GMAC2
Note: A 4.7K pull up or pull down resistor maybe used for proper strapping configuration. User should
take care the setting of the RTL8370MB and external CPU.
The termination network on the transmitter (for example, serial termination resistor) may be used for
better signal integrity.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 64 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

9.7. Extension GMAC1 & GMAC2

SGMII/1000Base-X/100Base-FX Interface
The RTL8370MB support SGMII/1000Base-X/100Base-FX interface for Extension GMAC1 & GMAC2
to connect external CPU or SFP transceiver.

9.7.1. Extension GMAC1 and GMAC2 SGMII Interface

RTL8370MB CPU
SGMII SGMII
0.1uF
S0RXP SG0_TX+
S0RXN SG0_TX-
0.1uF
0.1uF
S0TXN SG0_RX-
S0TXP SG0_RX+
0.1uF

0.1uF
S1RXP SG1_TX+
S1RXN SG1_TX-
0.1uF
0.1uF
S1TXN SG1_RX-
S1TXP SG1_RX+
0.1uF

Management Interface
I2C/SMI/SPI
nRESET Reset

Figure 43. Signal Diagram of SGMII Mode of the Extension GMAC1 & GMAC2

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 65 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

9.7.2. Extension GMAC1 and GMAC2 1000Base-X/100Base-FX

Interface
RTL8370MB
1000Base-X/
100Base-FX 0.1uF
S0RXP SG0_TX+
S0RXN Fiber Transceiver
SG0_TX-
0.1uF
0.1uF
S0TXP SG0_RX+
S0TXN SG0_RX-
0.1uF
Management Interface
GPIO

0.1uF
S1RXN SG1_TX- Fiber Transceiver
S1RXP SG1_TX+
0.1uF
0.1uF
S1TXN SG1_RX-
S1TXP SG1_RX+
0.1uF
Management Interface
GPIO

Figure 44. Signal Diagram of 1000Base-X/100Base-FX Mode of the Extension GMAC1/GMAC2

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 66 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

10. Electrical Characteristics

10.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 24. Absolute Maximum Ratings
Parameter Min Max Units
Junction Temperature (Tj) - +125 C
Storage Temperature -45 +125 C
DVDDIO_2, DVDDIO, DVDDIO_1, AVDDH, Supply
GND-0.3 +3.63 V
Referenced to GND and AGND
DVDDL, AVDDL, PLLVDDL0, PLLVDDL1 Supply Referenced
GND-0.3 +1.21 V
to GND, AGND, PLLGND0, and PLLGND1
Digital Input Voltage GND-0.3 VDDIO+0.3 V

10.2. Recommended Operating Range

Table 25. Recommended Operating Range
Parameter Min Typical Max Units
Ambient Operating Temperature TA (RTL8370MB) 0 - 70 C
DVDDIO, AVDDH Supply Voltage Range 3.135 3.3 3.465 V
DVDDIO_1 Supply Voltage Range 3.3V 3.135 3.3 3.465 V
2.5V 2.375 2.5 2.626 V
DVDDIO_2 Supply Voltage Range 3.3V 3.135 3.3 3.465 V
2.5V 2.375 2.5 2.626 V
1.8V 1.7 1.8 1.9 V
DVDDL, AVDDL, PLLVDDL0, PLLVDDL1 Supply Voltage
1.045 1.1 1.155 V
Range

10.3. Thermal Characteristics

10.3.1. TQFP-176-EPAD
10.3.1.1 Assembly Description
Table 26. Assembly Description
Package Type TQFP-176-EPAD
Dimension (L x W) 20 x 20mm
Thickness 1.0mm
PCB PCB Dimension (L x W) 130 x 75mm
PCB Thickness 1.6mm

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 67 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet
2-Layer:
- Top layer (1oz): 20% coverage of Cu
- Bottom layer (1oz): 75% coverage of Cu
4-Layer:
Number of Cu Layer-PCB
- 1st layer (1oz): 20% coverage of Cu
- 2nd layer (1oz): 80% coverage of Cu
- 3rd layer (1oz): 80% coverage of Cu
- 4th layer (1oz): 75% coverage of Cu

10.3.1.2 Material Properties

Table 27. Material Properties
Item Material Thermal Conductivity K (W/m-k)
Die Si 147
Silver Paste 1033BF 2.5
Package
Lead Frame CDA7025 168
Mold Compound 7372 0.9
Cu 400
PCB
FR4 0.2

10.3.1.3 Simulation Conditions

Table 28. Simulation Conditions
Input Power 2.8W
Test Board (PCB) 2L (2S)/4L (2S2P)
Control Condition Air Flow = 0, 1, 2 m/s

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 68 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

10.3.1.4 Thermal Performance of E-Pad TQFP-176 on PCB Under Still Air

Convection
Table 29. Thermal Performance of E-Pad TQFP-176 on PCB Under Still Air Convection
θJA θJB θJC ΨJB
4L PCB 25.3 18.2 6.2 15.7
2L PCB 38.2 24.5 6.9 18.8
Note:
θJA: Junction to ambient thermal resistance
θJB: Junction to board thermal resistance
θJC: Junction to case thermal resistance
ΨJB: Junction to bottom surface center of PCB thermal characterization

10.3.1.5 Thermal Performance of E-Pad TQFP-176 on PCB under Forced

Convection
Table 30. Thermal Performance of E-Pad TQFP-176 on PCB Under Forced Convection
Air Flow (m/s) 0 1 2
θJA 25.3 22.8 21.8
4L PCB
ΨJB 15.7 15.6 15.4
θJA 38.2 34.9 33
2L PCB
ΨJB 18.8 18.7 18.4

10.4. DC Characteristics
Table 31. DC Characteristics
Parameter SYM Min Typical Max Units
Power Supply Current for RGMII1 DVDDIO_1 (3.3V) IDVDDIO_1 - TBD - mA
Power Supply Current for RGMII2 DVDDIO_2 (3.3V) IDVDDIO_2 - TBD - mA
Power Supply Current for RGMII1 DVDDIO_1 (2.5V) IDVDDIO_1 - TBD - mA
Power Supply Current for RGMII2 DVDDIO_2 (2.5V) IDVDDIO_2 - TBD - mA
Power Supply Current for RGMII2 DVDDIO_2 (1.8V) IDVDDIO_2 - TBD - mA
Power Supply Current for RMII1 DVDDIO_1 (100M) IDVDDIO_1 - TBD - mA
Power Supply Current for RMII1 DVDDIO_1 (10M) IDVDDIO_1 - TBD - mA
Power Supply Current for RMII2 DVDDIO_2 (100M) IDVDDIO_2 - TBD - mA
Power Supply Current for RMII2 DVDDIO_2 (10M) IDVDDIO_2 - TBD - mA
System Idle (No UTP Port Link Up, 1 System Power LED)
Power Supply Current for VDDH IDVDDIO, IAVDDH - TBD - mA
Power Supply Current for VDDL IDVDDL, IAVDDL, - TBD - mA
IPLLVDDL
Total Power Consumption for All Ports PS - TBD - mW
1000M Active (8 UTP Ports Link Up, 1 System Power LED, 8 Activity LEDs, 8 Speed LEDs)
Power Supply Current for VDDH IDVDDIO, IAVDDH - TBD - mA
Power Supply Current for VDDL IDVDDL, IAVDDL, - TBD - mA
IPLLVDDL
Total Power Consumption for All Ports PS - TBD - mW
100M Active (8 UTP Ports Link Up, 1 System Power LED, 8 Activity LEDs, 8 Speed LEDs)
Power Supply Current for VDDH IDVDDIO, IAVDDH - TBD - mA
Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 69 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet
Parameter SYM Min Typical Max Units
Power Supply Current for VDDL IDVDDL, IAVDDL, - TBD - mA
IPLLVDDL
Total Power Consumption for All Ports PS - TBD - mW
10M Active (8 UTP Ports Link Up, 1 System Power LED, 8 Activity LEDs)
Power Supply Current for VDDH IDVDDIO, IAVDDH - TBD - mA
Power Supply Current for VDDL IDVDDL, IAVDDL, - TBD - mA
IPLLVDDL
Total Power Consumption for All Ports PS - TBD - mW
VDDIO=3.3V
TTL Input High Voltage Vih 1.9 - - V
TTL Input Low Voltage Vil - - 0.7 V
Output High Voltage Voh 2.7 - - V
Output Low Voltage Vol - - 0.6 V
VDDIO=2.5V
TTL Input High Voltage Vih 1.7 - - V
TTL Input Low Voltage Vil - - 0.7 V
Output High Voltage Voh 2.25 - - V
Output Low Voltage Vol - - 0.4 V
VDDIO=1.8V
TTL Input High Voltage Vih 1.1 - - V
TTL Input Low Voltage Vil - - 0.6 V
Output High Voltage Voh 1.25 - - V
Output Low Voltage Vol - - 0.45 V
Note1: DVDDIO=3.3V, AVDDH=3.3V, DVDDIO_1=3.3V/2.5V, DVDDIO_2=3.3V/2.5V/1.8V, DVDDL=1.1V,
AVDDL=1.1V PLLVDDL=1.1V.
Note2: power DVDDIO_1 is for RGMII/MII/TMII/RMII interface of Extension GMAC1, DVDDIO_2 is for
RGMII/MII/TMII/RMII interface of Extension GMAC2.
Note3: Both IDVDDIO_1 & IDVDDIO_2 should be added to the total current consumption when the dual extension ports of the
RTL8370MB are enabled.

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 70 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

10.5. AC Characteristics
10.5.1. I2C Master for EEPROM Auto-load Interface Timing
Characteristics
Tsck

t1 t2

SCK

t3 t4 t7 t5 t6 t8

SDA Data Output Data Output Data Input Data Input

t11

Figure 45. Master I2C for EEPROM Auto-load Timing Characteristics

t9

nRESET

SCK

SDA

Figure 46. Master I2C for EEPROM Auto-load Power on Timing

t10

SCK

SDA Data Valid

Start Stop
Condition Condition

Figure 47. Master I2C for EEPROM Auto-load Timing

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 RTL8370MB
DRAFT Datasheet

Table 32. Master I2C for EEPROM Auto-load Timing Characteristics

Symbol Description Type Min Typical Max Units
Tsck SCK Clock Period O 6 - µs
t1 SCK High Time O 2.7 3 - µs
t2 SCK Low Time O 2.7 3 - µs
t3 START Condition Setup Time O 1.35 1.5 - µs
t4 START Condition Hold Time O 1.35 1.5 - µs
t5 Data Input Hold Time I 0 - ns
t6 Data Input Setup Time I 10 - ns
t7 Data output delay O 1.4 1.5 1.6 µs
t8 STOP Condition Setup Time O 1.35 1.5 - µs
t9 SCK/SDA Active from Reset Ready O - ms
t10 8K-bits EEPROM Auto-Load Time O - ms
t11 Time the bus free before new START O 11.25 13.5 µs
- SCK Rise Time (10% to 90%) O 100 ns
- SCK Fall Time (90% to 10%) O - 100 ns
- Duty Cycle O 40 50 60 %
Note: t9, and t10 are measured with the ATMEL AT24C08 EEPROM.

10.5.2. SPI FLASH Interface Timing Characteristics

tSLCH tCHSH
SPI_CS#

SPI_SCK
tsetup:O thold:O tsetup:I
SPI_SI (Output) thold:I
MSB

High-Z
SPI_SO (Input) Data In

Figure 48. SPI FLASH Timing Characteristics

Table 33. SPI FLASH AC Timing

Symbol Description Type Min Typical Max Units
fSPI_SCK Clock Frequency of the SPI_SCK O - 62.5 MHz
Duty Duty Cycle of the SPI_SCK O 45 50 55 %
tSLCH CS# Active Setup Time O 6 - - ns
tCHSH CS# Active Hold Time O 6 - - ns
tsetup:O Data Output Setup Time O 5 - - ns
thold:O Data Output Hold Time O 6 - - ns
tsetup:I Data Input Setup Time I 2 - - ns
thold:I Data Input Hold Time I 0 - - ns
Test Condition: FSPI_SCK=62.5MHz
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 RTL8370MB
DRAFT Datasheet

10.5.3. I2C-Like Slave Mode for External CPU Access Interface Timing
Characteristics
t1 t2

SCK

t3 t4 t5 t6 t7 t8 t9

SDA Data Input Data Input Data Output

Figure 49. Slave I2C-Like for External CPU Access Interface Timing Characteristics

Table 34. Slave I2C-Like for External CPU Access Interface Timing Characteristics
Symbol Description Type Min Typical Max Units
t1 SCK High Time I 4.0 - - µs
t2 SCK Low Time I 4.0 - - µs
t3 START Condition Setup Time I 0.25 - - µs
t4 START Condition Hold Time I 0.25 - - µs
t5 Data Input Hold Time I 0 - - µs
t6 Data Input Setup Time I 100 - - ns
t7 Clock to Data Output Delay O 10 - 100 ns
t8 STOP Condition Setup Time I 0.25 - - µs
t9 Time the bus free before new START I 0.5 µs

10.5.4. Slave MII Management SMI for External CPU Access Interface
Timing Characteristics
The RTL8370MB supports MDIO slave mode. The Master (the RTL8370MB link partner CPU) can
access the Slave (RTL8370MB) registers via the MDIO interface. The MDIO is a bi-directional signal
that can be sourced by the Master or the Slave. In a write command, the Master sources the MDIO signal.
In a read command, the Slave sources the MDIO signal.
 The timing characteristics (t1, t2, and t3 in Table 35) of the Master (the RTL8370MB link partner
CPU) are provided by the Master when the Master sources the MDIO signal (Write command)
 The timing characteristics (t4 in Table 35)of the Slave (RTL8370MB) are provided by the
RTL8370MB when the RTL8370MB sources the MDIO signal (Read command)

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 73 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

t1

VIH
MDC
VIL

VIH
MDIO
VIL

t2 t3
Figure 50. MDIO Sourced by Master (External CPU)

VIH
MDC
VIL

VIH
MDIO
VIL

t4
Figure 51. MDIO Sourced by Slave (RTL8370MB)

Table 35. Slave SMI (MDC/MDIO) Timing Characteristics and Requirements

Parameter SYM Description/Condition Type Min Typical Max Units
MDC Clock Period t1 Clock Period I 125 - - ns
MDIO to MDC Rising Setup t2 Input Setup Time
I 8 - - ns
Time (Write Data)
MDIO to MDC Rising Hold t3 Input Hold Time
I 8 - - ns
Time (Write Data)
MDC to MDIO Delay Time t4 Clock (Rising Edge) to Data Delay
O 0 - 25 ns
(Read Data) Time

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 74 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

10.5.5. Slave SPI for External CPU Access Interface Timing

Characteristics

t2 t9 t5 t7
S_SPI_CSn t1 t6
t10
S_SPI_CLK
t3 t4
S_SPI_DI
t8
Data In
(Slave Input)
High-Z
S_SPI_DO Data Out
(Slave Output)
Figure 52. Slave SPI for External CPU Access Interface Timing Characteristics

Table 36. Slave SPI for External CPU Access Interface Timing Characteristics and Requirements
Symbol Description Type Min Typical Max Units
Fs_spi_sck S_SPI_CLK I 5 MHz
t1 S_SPI_CSn Not Active Hold time relative I 22 ns
to S_SPI_CLK
t2 S_SPI_CSn Active Setup time relative to I 22 ns
S_SPI_CLK
t3 S_SPI_DI to S_SPI_CLK Setup Time I 22 ns
t4 S_SPI_DI to S_SPI_CLK Hold Time I 22 ns
t5 S_SPI_CSn Not Active Setup time I 22 ns
relative to S_SPI_CLK
t6 S_SPI_CSn Active Hold time relative to I 22 ns
S_SPI_CLK
t7 S_SPI_CSn Deselect Time I 44 ns
t8 S_SPI_CLK Falling Edge to S_SPI_DO O 12 35 ns
Output Delay Time
t9 S_SPI_CLK Clock High Time I 50 ns
t10 S_SPI_CLK Clock Low Time I 80 ns

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 75 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

10.5.6. RGMII Timing Characteristics

TCYC

RGx_TXCLK
T DUTY

TskewT

RGx_TXD[3:0],
RGx_TXCTL

Figure 53. RGMII Output Timing Characteristics (RGx_TXCLK_DELAY=0)

RGx_TXCLK

TTX_SU TTX_HO

RGx_TXD[3:0],
RGx_TXCTL

Figure 54. RGMII Output Timing Characteristics (RGx_TXCLK_DELAY=2ns)

RGx_RXCLK

TRX_SU TRX_HO

RGx_RXD[3:0],
RGx_RXCTL

Figure 55. RGMII Input Timing Characteristics (RGx_RXCLK_DELAY=0)

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 76 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

RGx_RXCLK

TskewR

RGx_RXD[3:0],
RGx_RXCTL

Figure 56. RGMII Input Timing Characteristics (RGx_RXCLK_DELAY=2ns)

Table 37. RGMII Timing Characteristics

Parameter SYM Description/Condition Type Min Typical Max Units
1000M RGx_TXCLKc Output Cycle TTX_CYC 125MHz Clock Output. O 7.7 8 8.3 ns
Time
100M RGx_TXCLK Output Cycle TTX_CYC 25MHz Clock Output. O 38 40 42 ns
Time
10M RGx_TXCLK Output Cycle TTX_CYC 2.5MHz Clock Output. O 380 400 420 ns
Time
RGx_TXD[3:0] and RGx_TXCTL to TskewT Disable Output Clock Delay. O -500 -140 500 ps
RGx_TXCLK Output Skew (RGx_TXCLK_DELAY=0).
RGx_TXD[3:0] and RGx_TXCTL to TTX_SU Enable Output Clock Delay. O 1.2 2.0 - ns
RGx_TXCLK Output Setup Time (RGx_TXCLK_DELAY=1).
RGx_TXD[3:0] and RGx_TXCTL to TTX_HO Enable Output Clock Delay. O 1.2 1.8 - ns
RGx_TXCLK Output Hold Time (RGx_TXCLK_DELAY=1).
RGx_RXD[3:0] and RGx_RXCTL TRX_SU Disable Input Clock Delay. I 1.0 - - ns
to RGx_RXCLK Input Setup Time (RGx_RXCLK_DELAY=0).
RGx_RXD[3:0] and RGx_RXCTL TRX_HO Disable Input Clock Delay. I 1.0 - - ns
to RGx_RXCLK Input Hold Time (RGx_RXCLK_DELAY=0).
RGx_RXD[3:0] and RGx_RXCTL TskewR Enable Input Clock Delay. I -600 - 600 ps
to RGx_RXCLK Input Skew (RGx_RXCLK_DELAY=1).

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 77 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

10.5.7. MII MAC Mode Timing

TMM_TX_CYC

VIH
MxM_TXCLK
VIL

MxM_TXD[3:0] VIH
MxM_TXEN
VIL

TMM_COD
Figure 57. MII MAC Mode Clock to Data Output Delay Timing

TMM_RX_CYC

VIH
MxM_RXCLK
VIL

TMM_RX_SU TMM_RX_HO

MxM_RXD[3:0] VIH
MxM_RXDV
VIL

Figure 58. MII MAC Mode Input Timing

Table 38. MII MAC Mode Timing

Parameter SYM Description/Condition Type Min Typical Max Units
100Base-T MxM_TXC and TMM_TX_CYC 25MHz Clock Input. I - 40 - ns
MxM_RXC Input Cycle Time TMM_RX_CYC
10Base-T MxM_TXC and TMM_TX_CYC 2.5MHz Clock Input. I - 400 - ns
MxM_RXC Input Cycle Time TMM_RX_CYC
MxM_TXC to MxM_TXD[3:0], TMM_COD - O 5 - 15 ns
MxM_TXEN Output Delay Time
MxM_RXD[3:0], MxM_RXDV TMM_RX_SU - I 5 - - ns
Input Setup Time
MxM_RXD[3:0], MxM_RXDV TMM_RX_HO - I 5 - - ns
Input Hold Time

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 RTL8370MB
DRAFT Datasheet

10.5.8. MII PHY Mode Timing

TMP_RX_CYC

MxP_RXCLK VIH

V IL

T MP_RX_SU TMP_RX_HO

MxP_RXD[3:0], VIH
MxP_RXDV
V IL

Figure 59. MII PHY Mode Output Timing

TMP_TX_CYC

MxP_TXCLK VIH

V IL

T MP_TX_SU TMP_TX_HO

MxP_TXD[3:0], VIH

MxP _TXEN V IL

Figure 60. MII PHY Mode Input Timing

Table 39. MII PHY Mode Timing Characteristics

Parameter SYM Description/Condition Type Min Typical Max Units
100 Base-T MxP_RXC and TMP_RX_CYC 25MHz Clock Output. O - 40 - ns
MxP_TXC Output Cycle Time TMP_TX_CYC
10 Base-T MxP_RXC and MxP_TXC TMP_RX_CYC 2.5MHz Clock Output. O - 400 - ns
Output Cycle Time TMP_TX_CYC
MxP_RXD[3:0], MxP_RXDV to TMP_RX_SU - O 15 - - ns
MxP_RXC Output Setup Time
MxP_RXD[3:0], MxP_RXDV to TMP_RX_HO - O 15 - - ns
MxP_RXC Output Hold Time
MxP_TXD[3:0], MxP_TXEN to TMP_TX_SU - I 2.5 - - ns
MxP_TXC Input Setup Time
MxP_TXD[3:0], MxP_TXEN to TMP_TX_HO I 0 - - ns
MxP_TXC Input Hold Time

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 79 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

10.5.9. TMII MAC Mode Timing

TTMxM_TX_CYC

VIH
TMxM_TXCLK
VIL

TMxM_TXD[3:0] VIH
TMxM_TXEN VIL

TTMxM_COD
Figure 61. TMII MAC Mode Clock to Data Output Delay Timing

TTMxM_RX_CYC

VIH
TMxM_RXCLK
VIL

TTMxM_RX_SU TTMxM_RX_HO

TMxM_RXD[3:0] VIH
TMxM_RXDV
VIL

Figure 62. TMII MAC Mode Input Timing

Table 40. TMII MAC Mode Timing

Parameter SYM Description/Condition Type Min Typical Max Units
200Base-T TMxM_TXC and TTMxM_TX_CYC 50MHz Clock Input. I - 20 - ns
TMxM_RXC Input Cycle Time TTMxM_RX_CYC
20Base-T TMxM_TXC and TTMxM_TX_CYC 5MHz Clock Input. I - 200 - ns
TMxM_RXC Input Cycle Time TTMxM_RX_CYC
TMxM_TXC to TMxM_TXD[3:0], TTMxM_COD - O 0 - 12.5 ns
TMxM_TXEN Output Delay Time
TMxM_RXD[3:0], TMxM_RXDV TTMxM_RX_SU - I 2.5 - - ns
Input Setup Time
TMxM_RXD[3:0], TMxM_RXDV TTMxM_RX_HO - I 2.5 - - ns
Input Hold Time

Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers 80 Track ID: Rev. 0.2
 RTL8370MB
DRAFT Datasheet

10.5.10. TMII PHY Mode Timing

TTMxP_RX_CYC

VIH
TMxP_RXCLK
V IL

TTMxP_RX_SU TTMxP_RX_HO

TMxP_RXD[3:0] VIH
TMxP_RXDV
V IL

Figure 63. TMII PHY Mode Output Timing

TTMxP_TX_CYC

VIH
TMxP_TXCLK
V IL

TTMxP_TX_SU TTMxP_TX_HO

TMxP_TXD[3:0] VIH
TMxP_TXEN
V IL

Figure 64. TMII PHY Mode Input Timing

Table 41. TMII PHY Mode Timing Characteristics

Parameter SYM Description/Condition Type Min Typical Max Units
200Base-T TMxP_RXC and TTMxP_RX_CYC 50MHz Clock Output. O - 20 - ns
TMxP_TXC Output Cycle Time TTMxP_TX_CYC
20Base-T TMxP_RXC and TTMxP_RX_CYC 5MHz Clock Output. O - 200 - ns
TMxP_TXC Output Cycle Time TTMxP_TX_CYC
TMxP_RXD[3:0], TMxP_RXDV to TTMxP_RX_SU - O 7.5 - ns
TMxP_RXC Output Setup Time
TMxP_RXD[3:0], TMxP_RXDV to TTMxP_RX_HO - O 7.5 - ns
TMxP_RXC Output Hold Time
TMxP_TXD[3:0], TMxP_TXEN to TTMxP_TX_SU - I 2.5 - - ns
TMxP_TXC Input Setup Time
TMxP_TXD[3:0], TMxP_TXEN to TTMxP_TX_HO I 0 - - ns
TMxP_TXC Input Hold Time

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10.5.11. RMII MAC Mode Timing

TREFCLK_CYC

REFCLK(input)
VIH

V IL

TTX_SU TTX_HO

VIH
TXD[1:0](output)
TXEN(output)
V IL

Figure 65. RMII MAC Mode Output Timing

TREFCLK_CYC

REFCLK(input)
VIH

V IL

TRX_SU TRX_HO

VIH
RXD[1:0](input)
CRSDV(input)
V IL

Figure 66. RMII MAC Mode Input Timing

Table 42. RMII MAC Mode Timing Characteristics

Parameter SYM Description/Condition Type Min Typical Max Units
REFCLK Cycle Time TREFCLK 50MHz Clock Input. I - 20 - ns
TXD[1:0], TXEN to REFCLK Output TTX_SU - O 6 - - ns
Setup Time
TXD[1:0], TXEN to REFCLK Output TTX_HO - O 4 - - ns
Hold Time
RXD[1:0], CRSDV to REFCLK Input TRX_SU - I 2 - ns
Setup Time
RXD[1:0], CRSDV to REFCLK Input TRX_HO I 0 - - ns
Hold Time

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10.5.12. RMII PHY Mode Timing

TREFCLK_CYC

REFCLK(output)
VIH

V IL

TRX_SU TRX_HO

VIH
RXD[1:0](output)
CRSDV(output)
V IL

Figure 67. RMII PHY Mode Output Timing

TREFCLK_CYC

REFCLK(output)
VIH

V IL

TTX_SU TTX_HO

VIH
TXD[1:0](input)
TXEN(input)
V IL

Figure 68. RMII PHY Mode Input Timing

Table 43. RMII PHY Mode Timing Characteristics

Parameter SYM Description/Condition Type Min Typical Max Units
REFCLK Cycle Time TREFCLK 50MHz Clock Input. O - 20 - ns
TXD[1:0], TXEN to REFCLK Input TTX_SU - I 2 - - ns
Setup Time
TXD[1:0], TXEN to REFCLK Input TTX_HO - I 0 - - ns
Hold Time
RXD[1:0], CRSDV to REFCLK TRX_SU - O 6 - ns
Output Setup Time
RXD[1:0], CRSDV to REFCLK TRX_HO O 4 - - ns
Output Hold Time

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10.5.13. SGMII Differential Transmitter Characteristics

Table 44. SGMII Differential Transmitter Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval 799.76 800 800.24 ps 800ps±300ppm
T_X1 Eye Mask - - 0.1875 UI -
T_X2 Eye Mask - - 0.4 UI -
T_Y1 Eye Mask 200 - - mV -
T_Y2 Eye Mask - - 500 mV -
VTX-DIFFp-p Output Differential Voltage 400 700 900 mV
TTX-EYE Minimum TX Eye Width 0.625 - - UI -
TTX-JITTER Output Jitter - - 0.375 UI -
RTX Differential Resistance 80 100 120 ohm -
CTX AC Coupling capacitor 75 100 200 nF -
LTX Transmit Length in PCB - - 10 inch -

TTX-EYE-MIN

T_Y2

T_Y1

Amplitude 0V VTX-DIFFp-p-MIN VTX-DIFFp-p-MAX

-T_Y1

-T_Y2

0.0 T_X1 T_X2 1-T_X2 1-T_X1 1.0

Time UI
Figure 69. SGMII Differential Transmitter Eye Diagram

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10.5.14. SGMII Differential Receiver Characteristics

Table 45. SGMII Differential Receiver Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval 799.76 800 800.24 ps 800ps±300ppm
R_X1 Eye Mask - - 0.3125 UI -
R_Y1 Eye Mask 50 - - mV -
R_Y2 Eye Mask - - 600 mV -
VRX-DIFFp-p Input Differential Voltage 100 - 1200 mV -
TRX-EYE Minimum RX Eye Width 0.375 - - UI -
TRX-JITTER Input Jitter Tolerance - - 0.625 UI -
RRX Differential Resistance 80 100 120 ohm -

TRX-EYE-MIN

R_Y2

R_Y1

Amplitude 0V VRX-DIFFp-p-MIN VRX-DIFFp-p-MAX

-R_Y1

-R_Y2

0.0 R_X1 0.5 1-R_X1 1.0

Time UI
Figure 70. SGMII Differential Receiver Eye Diagram

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10.5.15. 1000Base-X/100Base-FX Differential Transmitter Characteristics

Table 46. 1000Base-X/100Base-FX Differential Transmitter Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval (1000Base-X) 799.76 800 800.24 ps 800ps±300ppm
Unit Interval (100Base-FX) 7.9976 8.0 8.0024 ns 8ns±300ppm
T_X1 Eye Mask - - 0.1875 UI -
T_X2 Eye Mask - - 0.4 UI -
T_Y1 Eye Mask 200 - - mV -
T_Y2 Eye Mask - - 650 mV -
VTX-DIFFp-p Output Differential Voltage 400 800 1300 mV -
TTX-EYE Minimum TX Eye Width 0.625 - - UI -
TTX-JITTER Output Jitter - - 0.375 UI -
RTX Differential Resistance 80 100 120 ohm -
CTX AC Coupling capacitor 75 100 200 nF -
LTX Transmit Length in PCB - - 10 inch -

TTX-EYE-MIN

T_Y2

T_Y1

Amplitude 0V VTX-DIFFp-p-MIN VTX-DIFFp-p-MAX

-T_Y1

-T_Y2

0.0 T_X1 T_X2 1-T_X2 1-T_X1 1.0

Time UI
Figure 71. 1000Base-X/100Base-FX Differential Transmitter Eye Diagram

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10.5.16. 1000Base-X/100Base-FX Differential Receiver Characteristics

Table 47. 1000Base-X/100Base-FX Differential Receiver Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval (1000Base-X) 799.76 800 800.24 ps 800ps±300ppm
Unit Interval (100Base-FX) 7.9976 8.0 8.0024 ns 8ns±300ppm
R_X1 Eye Mask - - 0.3125 UI -
R_Y1 Eye Mask 100 - - mV -
R_Y2 Eye Mask - - 1000 mV -
VRX-DIFFp-p Input Differential Voltage 200 - 2000 mV -
TRX-EYE Minimum RX Eye Width 0.375 - - UI -
TRX-JITTER Input Jitter Tolerance - - 0.625 UI -
RRX Differential Resistance 80 100 120 ohm -

TRX-EYE-MIN

R_Y2

R_Y1

Amplitude 0V VRX-DIFFp-p-MIN VRX-DIFFp-p-MAX

-R_Y1

-R_Y2

0.0 R_X1 0.5 1-R_X1 1.0

Time UI
Figure 72. 1000Base-X/100Base-FX Differential Receiver Eye Diagram

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10.6. Power and Reset Characteristics

t1
t3

DVDDL
AVDDL

DVDDIO
DVDDIO_0
DVDDIO_1 t2
AVDDH
t4
nRESET

Figure 73. Power and Reset Characteristics

Table 48. Power and Reset Characteristics

Parameter SYM Description/Condition Type Min Typical Max Units
Reset Delay Time t1 The duration from all powers steady to
I 10 - - ms
the reset signal released to high.
Reset Low Time t2 The duration of reset signal remain low
I 10 - - ms
time for issuing a reset to RTL8370MB.
VDDL Power Rising Settling t3 DVDDL and AVDDL power rising
I 0.5 - - ms
Time settling time.
VDDH Power Rising t4 DVDDIO, DVDDIO_0, DVDDIO_1,
I 0.5 - - ms
Settling Time and AVDDH power rising settling time.

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11. Mechanical Dimensions

Thermally Enhanced Thin Quad Flat Pack (TQFP) 176 Leads 20x20mm Outline.

Dimension in mm Dimension in inch

Symbol
Min Nom Max Min Nom Max
A — — 1.20 — — 0.047
A1 0.05 — 0.15 0.002 — 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.13 0.18 0.23 0.005 0.007 0.009
D/ E 22.00BSC 0.866BSC
D1/ E1 20.00BSC 0.787BSC
D2/ E2 17.20BSC 0.677BSC
D3/ E3 5.75 6.00 6.25 0.226 0.236 0.246
e 0.40BSC 0.016BSC
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 REF 0.039 REF

Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).

Note 2: REFERENCE DOCUMENT: JEDEC MS-26.

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12. Ordering Information

Table 49. Ordering Information
Part Number Package Status
RTL8370MB-CG TQFP 176-Pin E-PAD „Green‟ Package -

Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com

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