UNIT 2
VLSI Logic Circuits, Design Process and Layout: Pass transistor and transmission gates
inverter- NAND gates and NOR Gates for n MOS, CMOS and Bi CMOS – parity generator –
multiplexers- code converters – PLA – Clocked sequential circuits- Memories and
Registers.
INTRODUCTION :
Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
– static CMOS
Serial and parallel combination
q nMOS: 1 = ON
q pMOS: 0 = ON
q Series: both must be ON
q Parallel: either can be ON
Compound gates
Compound gates can do any inverting function
Ex: Y =
SWITCH LOGIC
Switch logic is based on the 'pass transistor' or on transmission gates. This approach is fast for small arrays
and takes no static current from the supply. The power dissipation of such arrays is small since current only
flows on switching.
Switch (pass transistor) logic is similar to logic arrays based on relay contacts in that the path through each
switch is isolated from the signal activating the switch. In consequence, the designer has a considerable
amount of freedom in implementing architectural features compared with bipolar logic-based designs.
Some switch logic arrangements
Pass Transistors and Transmission Gates
Switches and switch logic formed from simple n- or p-pass transistors or from transmission gates
(complementary switches) comprising an n-pass and a p-pass transistor in parallel. The reason for adopting
the apparent complexity of the transmission gate, rather than using a simple n-switch or p-switch in most
CMOS applications, is to eliminate the undesirable threshold voltage effects which give rise to the loss of
logic levels in pass transistors.
n- switch p- switch
Transmission Gate Logic Levels Transmission Gate Symbol
Pass Transistor Logic
'On' resistance, however, is lower than that of the simple pass transistor switches. When using nMOS switch
logic, there is one restriction which must always be observed: no pass transistor gate input may be driven
through one or more pass transistors. logic levels propagated through pass transistors are degraded by
threshold voltage effects. Since the sign~l out of pass transistor T1 does not reach a full logic 1, but rather a
voltage one transistor threshold below a true logic 1, this degraded voltage would not permit the output of
T2 to reach an acceptable logic 1 level.
GATE (restoring) LOGIC
Gate logic is based on the general arrangement typified by the inverter circuits.
Both Nand and Nor and, with CMOS, And and Or gate arrangements are available.
Inverters are also employed to complement and restore logic levels that have been degraded
The Inverter
The most commonly used inverter circuit diagrams-the inverter symbol, and the corresponding stick
and symbolic diagram
The nMOS inverter Zp.u / Zp.d. ratio and/or the channel length to width ratio for each MOS
transistor
The CMOS inverter carries no static current and thus has no power dissipation unless switching
Two-Input nMOS, CMOS and BICMOS Nand Gates
The nMOS (and pseudo-nMOS) L: W ratios carefully noted since they must be chosen to achieve the
desired overall Zp.u / Z p d ratio (where Zpd. is contributed in this case by both input transistors in
series)
In order to arrive at the required L: W ratios for an nMOS (or pseudo-nMOS) Nand gate with n
inputs, it is only necessary to consider the very simple circuit model of the gate in the condition
when all n pull-down transistors
The critical factor here is that the output voltage V0 u1 must be near enough to ground to turn off
any following inverter-like stages, that is
Vout ≤ Vt= 0.2VDD
Thus
where ZP d applies for any one pull-down transistor. The boundary condition then is
When nMOS Nand ratio =
nMOS, CMOS and BICMOS 2-input Nand gates
that is, the ratio between Zp.u. and the sum of all the pull-down Zp.d.s.must be 4:1 (as for the nMOS
inverter). This ratio must be adjusted appropriately if input signals are derived through pass transistors.
Further consideration of the nMOS Nand gate geometry reveals two significant factors:
1. nMOS Nand gate area requirements are considerably greater than those of a corresponding nMOS
inverter, since not only must pull-down transistors be added in series to provide the desired number of
inputs, but, as inputs are added, so must there be a corresponding adjustment of the length of the pull-up
transistor channel to maintain the required overall ratio.
2. nMOS Nand gate delays are also increased in direct proportion to the number of inputs added. If each
pull-down transistor is kept to minimum size (2A. x 2A.), then each will present 10Cg at its iQput, but if
there are n such inputs, .tf\en the length and resistance of the pull-up transistor must be increased by a factor
of n to keep the correct ratio. Thus, delays associated · with the nMOS Nand are
where n is the number of inputs and is the corresponding nMOS inverter delay.
The nMOS Nand gate is used only where absolutely necessary and the number of inputs is restricted.
The CMOS Nand gate has no such restrictions, but, it is necessary to allow for extended fall-times
on capacitive loads owing to the number of n-transistors in series forming the pull-down.
The BiCMOS gate is thus more complex than the simple intuitive version. However, it has
considerable load-driving capabilities and is most useful where a large fan-out is required or where
there is some other form gf high capacitance load on the output.
Two-Input nMOS, CMOS and BICMOS Nor Gates
Two-input Nor gate arrangements are the nMOS (or pseudo nMOS) form of Nor gate can be
expanded to accommodate any reasonable number of inputs and is preferred to the Nand gate.
Since both 'legs' of the two-input nMOS Nor gate· provide a path to ground from the pull-up
transistor, the ratios must be such that any one conducting pull-down leg will give the appropriate
inverter-like transfer characteristic.
Each leg has the same ratio as would be the case for an nMOS inverter. This applies irrespective of
the number of inputs accommodated.
The area occupied by the nMOS (or pseudo-nMOS) Nor gate is reasonable since the pull-up
transistor dimensions are unaffected by the number of inputs accommodated.
In consequence, the Nor gate is as fast as the corresponding inverter and is the preferred inverter-
based nMOS (or pseudo-nMOS) logic gate when a choice is possible.
The ratio between Zp.u. and Zp.d. of any one leg must be appropriate to the source from which that
input is driven for nMOS design but will be uniformly 3: 1 for a pseudo-nMOS design where any
series switching is by transmission gate.
The CMOS Nor gate consists of a pull-up p-transistor-based structure, which implements the logic 1
conditions and a complementary n-transistor arrangement to implement the logic 0 -conditions at the
output.
In the case of the Nor gate, the p-structure consists of transistors in series, one for each input, while
the n pull-down arrangement has as many transistors in parallel as there are inputs to the Nor gate.
Rise time and fall-time asymmetry on capacitive loads is thus increased and there will also be a shift.
in the transfer (Vin vs Vout) characteristic which will reduce noise immunity.
For these reasons, CMOS (complementary logic) Nor gates with more than two inputs may require
adjustment of the p- and/or n-transistor geometries (L: W ratios).
nMOS, CMOS and BiCMOS two-input Nor gate
A BiCMOS two-input Nor gate
A Parity Generator
A circuit is to be designed to indicate the parity of a binary number or word. The requirement is (n +
1)-bit input.
Since the number of bits is undefined, find a general solution on a cascadable bit-wise basis so that n
can have any value.
The parity information is passed from one cell to the next and is modified or not by a cell, depending on the state of
the input lines Ai and
A little reflection will readily reveal that the requirements are:
Ai = 1 parity is changed Pi = i-1
Ai = 0 parity is unchanged Pi = P i-1
The circuit implements the function
Pi = i-1* Ai + P i-1* i
When converting stick diagrams to layouts, care must be taken that the boundary is set so that no
design rule violations occur when cells are butted together.
The boundary must also be chosen so that wastage of area is avoided and, where possible, so that
design rule errors are not present when a cell is checked in isolation, although this may not always
be possible.
The inlet and corresponding outlet points should match up both in layer and position, so that direct
interconnection between cells is achieved when cells are butted.
Parity generator-basic one-bit cell
Stick diagrams (parity generator)
Multiplexers
Multiplexers are widely used and have many applications.
They are also commonly available in a number of standard configurations in TTL and other logic
families. In order to arrive at a standard cell for multiplexers, consider a commonly used circuit, the
four-way multiplexer.
The requirements and general arrangement of a four-way multiplexer are
Z= I0. 1. 0 + I1. 1. 0 + I2. 1. 0 + I3. 1. 0
where S1 and S0 are the selector inputs. if S1 and S0 have defined logic states, output Z must always be
connected to one of I0 to I3.
Switch logic Implementations of a four-way multiplexer
A mask layout of Color plate ll and it can be seen that all n-transistors are placed below the
demarcation line and close to the Vss rail to allow ready configuration of the p-well and Vss contacts.
The p-transistors are similarly placed above the notional demarcation line and close to VDD·
We can establish standard cells from which a four-way multiplexer can be composed, and then cover
the case of the two-way multiplexer.
For the nMOS case a standard cell is measured 7 λ X 11λ.
Two versions of the cell are needed to complete the network, one version with a pass transistor as
shown and the other version without.
If computer-aided design tools are used, the two versions may be designed as one cell suitably
parameterized to include or exclude the pass transistor.
A Four-line Gray Code to Binary Code Converter
The Programmable Logic Array (PLA)
An elegant solution to the mapping of irregular combinational logic functions into regular structures
is provided by the PLA. The PLA provides the designer with a systematic and regular way of
implementing multiple output functions of n variables in sum of products (SOP) form.
The general arrangement of a PLA is seen to consist of a programmable two-level And / Or
structure.
The number of input variables v, the number of product (And) terms p, and the number of output
functions (Or terms) z.
If there are v input variables, for complete generality each of the product forming And gates must
have v inputs, and if there are p product terms, each output Or gate must have p inputs.
In VLSI design custom PLAs can be readily designed and must be 'programmed' during the design
process.
The VLSI designer, PLAs is tailored to specific tasks with little wastage of functions or space.
However, the PLA structure is regular and readily expanded, contracted, or modified during design.
This contrasts with the attributes of random logic.
In VLSI design our objective is to map circuits onto silicon to meet particular specifications . The
way in which a PLA maps onto the chip may be indicated by a 'floor plan' which gives the not ional
areas and relative disposition of the particular circuits and subsystems.
For MOS fabrication, And and Or gates are neither as simple nor as suitable as the Nor gate. Thus, we look
to De Morgan's theorem to manipulate And-Or combinational logic requirements into Nor form.
For an n input Nor gate,
X =A + B+C + ... + N
where X is the output and A to N the inputs.
By De Morgan's theorem
X = A' + B' + C ... N'
In other words, the Nor gate is an And gate to inverted input levels. A PLA, tailored to meet the particular
needs and drawn in mixed circuit and logic symbol notation. It can be clearly seen how the factors v, p, and
z affect the PLA dimensions. A PLA circuit is readily turned into a stick diagram and then to mask layout
form. A similar 4 x 8 x 4 programmed PLA is given in stick diagram
And / Or based
Nor based
Nor gate-based PLA realization for the multiple output functions.
PLA arrangement for multiple output function.
CMOS (dynamic logic) stick diagram for a 4 x 8 x 4 PLA.
