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MAX1473 315MHz/433MHz ASK Superheterodyne

Receiver with Extended Dynamic Range

General Description Features

The MAX1473 fully integrated low-power CMOS ●● Optimized for 315MHz or 433MHz ISM Band
superheterodyne receiver is ideal for receiving amplitude- ●● Operates from Single 3.3V or 5.0V Supplies
shift-keyed (ASK) data in the 300MHz to 450MHz frequency
range. Its signal range is from -114dBm to 0dBm. With few ●● High Dynamic Range with On-Chip AGC
external components and a low-current power-down mode, ●● Selectable Image-Rejection Center Frequency
it is ideal for cost- and power-sensitive applications typical
●● Selectable x64 or x32 fLO/fXTAL Ratio
in the automotive and consumer markets. The chip consists
of a low-noise amplifier (LNA), a fully differential image- ●● Low 5.2mA Operating Supply Current
rejection mixer, an on-chip phase-locked-loop (PLL) with ●● < 2.5μA Low-Current, Power-Down Mode for Efficient
integrated voltage-controlled oscillator (VCO), a 10.7MHz IF Power Cycling
limiting amplifier stage with received-signal-strength indicator
(RSSI), and analog baseband data-recovery circuitry. The ●● 250μs Startup Time
MAX1473 also has a discrete one-step automatic gain ●● Built-In 50dB RF Image Rejection
control (AGC) that drops the LNA gain by 35dB when the RF
●● Receive Sensitivity of -114dBm
input signal is greater than -57dBm.
The MAX1473 is available in 28-pin TSSOP and 32-pin Ordering Information
thin QFN packages. Both versions are specified for the PART TEMP RANGE PIN-PACKAGE
extended (-40°C to +85°C) temperature range.
MAX1473EUI+ -40°C to +85°C 28 TSSOP
Applications
MAX1473ETJ+ -40°C to +85°C 32 Thin QFN-EP*
●● Automotive Remote ●● Security Systems
Keyless Entry ●● Home Automation + Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
●● Garage Door Openers ●● Local Telemetry
●● Remote Controls Systems Functional Diagram and Typical Application Circuit appear
●● Wireless Sensors at end of data sheet.

Pin Configurations
TOP VIEW
LNASRC

+
PWRDN
PDOUT
XTAL1

XTAL2
LNAIN

AVDD

XTAL1 1 28 XTAL2
N.C.

AVDD 2 27 PWRDN
+
25
32

31

30
29

28
27
26

LNAIN 3 26 PDOUT
LNASRC 4 25 DATAOUT N.C. 1 24 DATAOUT
AGND 5 24 VDD5 AGND 2 23 VDD5
MAX1473
LNAOUT 6 23 DSP LNAOUT 3 22 DSP
AVDD 7 22 DFFB AVDD 4 MAX1473 21 N.C.
MIXIN1 8 21 OPP MIXIN1 5 20 DFFB
MIXIN2 9 20 DSN MIXIN2 6 19 OPP
AGND 10 19 DFO AGND 7 18 DSN
IRSEL 11 18 IFIN2 IRSEL 8 17 DFO
MIXOUT 12 17 IFIN1

DGND 13 16 XTALSEL
10

11
12

13
14
15
16
9

DVDD 14 15 AGCDIS
MIXOUT

DGND

DVDD
AGCDIS

N.C.
XTALSEL
IFIN1
IFIN2

TSSOP
THIN QFN

19-2748; Rev 7; 1/19

MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Absolute Maximum Ratings

VDD5 to AGND......................................................-0.3V to +6.0V Continuous Power Dissipation (TA = +70°C)
AVDD to AGND.....................................................-0.3V to +4.0V 28-Pin TSSOP (derate 12.8mW/°C above +70°C).. 1025.6mW
DVDD to DGND.....................................................-0.3V to +4.0V 32-Pin Thin QFN (derate 21.3mW/°C
AGND to DGND....................................................-0.1V to +0.1V above +70°C)..........................................................1702.1mW
IRSEL, DATAOUT, XTALSEL, AGCDIS, Operating Temperature Ranges
PWRDN to AGND.................................... -0.3V to (VDD5 + 0.3V) MAX1473E__...................................................... -40°C to +85°C
All Other Pins to AGND........................... -0.3V to (AVDD + 0.3V) Storage Temperature Range............................. -60°C to +150°C
Lead Temperature (soldering 10s)................................... +300°C
Soldering Temperature (reflow)........................................ +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

DC Electrical Characteristics (3.3V Operation)

(Typical Application Circuit, AVDD = DVDD = VDD5 = 3.0V to 3.6V, no RF signal applied, TA = -40°C to +85°C, unless otherwise noted.
Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VDD 3.3V nominal supply 3.0 3.3 3.6 V
fRF = 315MHz 5.2 6.23
Supply Current IDD V PWRDN = VDD5 mA
fRF = 433MHz 5.8 6.88

V PWRDN = 0V, fRF = 315MHz 1.6

Shutdown Supply Current IPWRDN µA
VXTALSEL = 0V fRF = 433MHz 2.5 5.3
Input Voltage Low VIL 0.4 V
Input Voltage High VIH AVDD - 0.4 V
Input Logic Current High IIH 10 µA
fRF = 433MHz, VIRSEL = AVDD AVDD - 0.4
Image Reject Select (Note 2) fRF = 375MHz, VIRSEL = AVDD/2 1.1 AVDD - 1.5 V
fRF = 315MHz, VIRSEL = 0V 0.4
DATAOUT Voltage Output Low VOL 0.4 V
RL = 5kΩ
DATAOUT Voltage Output High VOH VDD5 - 0.4 V

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Electrical Characteristics (5V Operation)

(Typical Application Circuit, VDD5 = 4.5V to 5.5V, AVDD = DVDD = ~3.2V, no RF signal applied, TA = -40°C to +85°C, unless otherwise
noted. Typical values are at VDD = 5.0V and TA = +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VDD 5.0V nominal supply 4.5 5.0 5.5 V
fRF = 315MHz 5.2 6.04
Supply Current IDD V PWRDN = VDD5 mA
fRF = 433MHz 5.7 6.76

V PWRDN = 0V, fRF = 315MHz 2.3

Shutdown Supply Current IPWRDN µA
VXTALSEL = 0V fRF = 433MHz 2.8 6.2
Input Voltage Low VIL 0.4 V
Input Voltage High VIH AVDD - 0.4 V
Input Logic Current High IIH 10 µA
fRF = 433MHz, VIRSEL = AVDD AVDD - 0.4
Image Reject Select (Note 2) fRF = 375MHz, VIRSEL = AVDD/2 1.1 AVDD - 1.5 V
fRF = 315MHz, VIRSEL = 0V 0.4
DATAOUT Voltage Output Low VOL 0.4 V
RL = 5kΩ
DATAOUT Voltage Output High VOH VDD5 - 0.4 V

AC Electrical Characteristics
(Typical Application Circuit, AVDD = DVDD = VDD5 = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to
+85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1).

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GENERAL CHARACTERISTICS
Time for valid signal detection after
Startup Time tON 250 µs
V PWRDN = VOH
Receiver Input Frequency fRF 300 450 MHz
Maximum Receiver Input Level PRFIN_MAX Modulation depth > 18dB 0 dBm
Sensitivity (Note 3) PRFIN_MIN Peak power level -114 dBm
8 dB
AGC Hysteresis LNA gain from low to high
150 ms
LNA IN HIGH-GAIN MODE
Power Gain 16 dB
fRF = 433MHz 1 - j3.4
Input Impedance (Note 4) ZIN_LNA Normalized to 50Ω fRF = 375MHz 1 - j3.9
fRF = 315MHz 1 - j4.7
1dB Compression Point P1dBLNA -22 dBm
Input-Referred 3rd-Order Intercept IIP3LNA -12 dBm

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

AC Electrical Characteristics (continued)

(Typical Application Circuit, AVDD = DVDD = VDD5 = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to
+85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1).

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LO Signal Feedthrough to Antenna -80 dBm
Noise Figure NFLNA 2 dB
LNA IN LOW-GAIN MODE
fRF = 433MHz 1 - j3.4
Input Impedance (Note 4) ZIN_LNA Normalized to 50Ω fRF = 375MHz 1 - j3.9
fRF = 315MHz 1 - j4.7
1dB Compression Point P1dBLNA -10 dBm
Input-Referred 3rd-Order Intercept IIP3LNA -7 dBm
LO Signal Feedthrough to Antenna -80 dBm
Noise Figure NFLNA 2 dB
Power Gain 0 dB
Voltage Gain Reduction AGC enabled (depends on tank Q) 35 dB
MIXER
Input-Referred 3rd-Order Intercept IIP3MIX -18 dBm
Output Impedance ZOUT_MIX 330 Ω
Noise Figure NFMIX 16 dB
fRF = 433MHz, VIRSEL = AVDD 42
Image Rejection
fRF = 375MHz, VIRSEL = AVDD/2 44 dB
(not Including LNA Tank)
fRF = 315MHz, VIRSEL = 0V 44
Conversion Gain 330Ω IF filter load 13 dB
INTERMEDIATE FREQUENCY (IF)
Input Impedance ZIN_IF 330 Ω
Operating Frequency fIF Bandpass response 10.7 MHz
3dB Bandwidth 20 MHz
RSSI Linearity ±0.5 dB
RSSI Dynamic Range 80 dB
PRFIN < -120dBm 1.15
RSSI Level V
PRFIN > 0dBm, AGC enabled 2.35
RSSI Gain 14.2 mV/dB
LNA gain from low to high 1.45
AGC Threshold V
LNA gain from high to low 2.05

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

AC Electrical Characteristics (continued)

(Typical Application Circuit, AVDD = DVDD = VDD5 = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to
+85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1).

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DATA FILTER
Maximum Bandwidth BWDF 100 kHz
DATA SLICER
Comparator Bandwidth BWCMP 100 kHz
Output High Voltage VDD5 V
Output Low Voltage 0 V
CRYSTAL OSCILLATOR
VXTALSEL = 0V 6.6128
fRF = 433MHz MHz
VXTALSEL = AVDD 13.2256
Crystal Frequency (Note 5) fXTAL
VXTALSEL = 0V 4.7547
fRF = 315MHz MHz
VXTALSEL = AVDD 9.5094
Crystal Tolerance 50 ppm
Input Capacitance From each pin to ground 6.2 pF
Recommended Crystal Load
CLOAD 3 pF
Capacitance
Maximum Crystal Load
CLOAD 10 pF
Capacitance

Note 1: Note 1: 100% tested at TA = +25°C. Guaranteed by design and characterization over temperature.
Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image rejection setting is desired. A 1nF
capacitor is recommended in noisy environments.
Note 3: BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz.
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration con-
nected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF.
Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for
XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = AVDD.

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Typical Operating Characteristics

(Typical Application Circuit, VDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT SUPPLY CURRENT BIT-ERROR RATE

vs. SUPPLY VOLTAGE vs. RF FREQUENCY vs. AVERAGE RF INPUT POWER
5.6 MAX1473 toc01
7.0 100

MAX1473 toc02

MAX1473 toc03
5.5 +105°C fRF = 433MHz
6.5
10
SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

5.4 +105°C

BIT-ERROR RATE (%)

+85°C
6.0
5.3
1
5.2 +25°C
5.5 fRF = 315MHz
+85°C
5.1
+25°C 0.1
5.0
5.0 -40°C -40°C
4.9 4.5 0.01
3.0 3.1 3.2 3.3 3.4 3.5 3.6 250 300 350 400 450 500 -121 -120 -119 -118 -117 -116 -115 -114
SUPPLY VOLTAGE (V) RF FREQUENCY (MHz) AVERAGE INPUT POWER (dBm)
RSSI AND DELTA
SENSITIVITY vs. TEMPERATURE RSSI vs. RF INPUT POWER vs. IF INPUT POWER
MAX1473 toc06
-100 2.4 2.4 3.5
MAX1473 toc04

MAX1473 toc05

PEAK RF INPUT POWER IF BANDWIDTH = 280kHz

-102 0.2% BER 2.5
2.2 2.2
-104 IF BANDWIDTH = 280kHz VAGCDIS = VDD
2.0 2.0 1.5
SENSITIVITY (dBm)

-106

DELTA (dB)
fRF = 433MHz 1.8 1.8 0.5
RSSI (V)

RSSI (V)

-108
-110 1.6 VAGCDIS = 0V 1.6 -0.5
DELTA
-112
1.4 1.4 -1.5
-114 fRF = 315MHz
RSSI
1.2 1.2 -2.5
-116
-118 1.0 1.0 -3.5
-40 -20 0 20 40 60 80 100 120 -140 -120 -100 -80 -60 -40 -20 0 -90 -70 -50 -30 -10 10
TEMPERATURE (°C) RF INPUT POWER (dBm) IF INPUT POWER (dBm)
IMAGE REJECTION IMAGE REJECTION
SYSTEM GAIN vs. FREQUENCY vs. RF FREQUENCY vs. TEMPERATURE
30 55 45
MAX1473 toc07

MAX1473 toc08

MAX1473 toc09

UPPER fRF = 315MHz

45
20 SIDEBAND
50 44
IMAGE REJECTION (dB)
IMAGE REJECTION (dB)
SYSTEM GAIN (dB)

10 44
50dB IMAGE 45
REJECTION LOWER 43
0 SIDEBAND fRF = 375MHz
43
40
-10 42 fRF = 433MHz
fRF = 375MHz
FROM RFIN TO 42
35 fRF = 315MHz
-20 MIXOUT
fRF = 315MHz fRF = 433MHz 41
-30 30 41
0 5 10 15 20 25 30 280 330 380 430 480 -40 -15 10 35 60 85
IF FREQUENCY (MHz) RF FREQUENCY (MHz) TEMPERATURE (°C)

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 MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Typical Operating Characteristics (continued)

(Typical Application Circuit, VDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.)

NORMALIZED IF GAIN
vs. IF FREQUENCY S11 MAGNITUDE-LOG PLOT OF RFIN S11 SMITH PLOT OF RFIN
5 30 MAX1473 toc12
MAX1473 toc10

MAX1473 toc11
20
600MHz
0 10
NORMALIZED IF GAIN (dB)

0
MAGNITUDE (dB)

-5 -10
-20
-10 -30 100MHz

-40 315MHz
-34dB
-15 -50
-60
-20 -70
1 10 100 10 109 208 307 406 505 604 703 802 901 1000
IF FREQUENCY (MHz) RF FREQUENCY (MHz)

REGULATOR VOLTAGE PHASE NOISE PHASE NOISE

vs. REGULATOR CURRENT vs. OFFSET FREQUENCY vs. OFFSET FREQUENCY
3.1 0 0
MAX1473 toc13

MAX1473 toc14

MAX1473 toc15
fRF = 315MHz fRF = 433MHz
3.0 -20 -20
REGULATOR VOLTAGE (V)

-40°C
+25°C -40 -40
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

2.9 +85°C
+105°C
-60 -60
2.8
-80 -80
2.7
-100 -100
2.6
-120 -120
VDD = 5.0V
2.5 -140 -140
5 15 25 35 45 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01
REGULATOR CURRENT (mA) OFFSET FREQUENCY (MHz) OFFSET FREQUENCY (MHz)

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Pin Description
PIN
NAME FUNCTION
TSSOP TQFN
1 29 XTAL1 1st Crystal Input. (See the Phase-Locked Loop section.)
Positive Analog Supply Voltage. For +5V operation, pin 2 (TSSOP package) is the output of an on-
chip +3.2V low-dropout regulator and should be bypassed to AGND with a 0.1µF capacitor as close
2, 7 4, 30 AVDD as possible to the pin. Pin 7 must be externally connected to the supply from pin 2 and bypassed to
AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section and
the Typical Application Circuit).
3 31 LNAIN Low-Noise Amplifier Input. (See the Low-Noise Amplifier section.)
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set
4 32 LNASRC
LNA input impedance. (See the Low-Noise Amplifier section.)
5 2 AGND Analog Ground
Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See the Low-Noise Amplifier
6 3 LNAOUT
section.)
8 5 MIXIN1 1st Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT.
9 6 MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to AVDD side of the LC tank.
10 7 AGND Analog Ground
Image Rejection Select Pin. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
11 8 IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = AVDD to center image rejection at 433MHz.
Input logic level based on AVDD, ~3.2V supply.
12 9 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
13 10 DGND Digital Ground
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01µF
14 11 DVDD
capacitor as close as possible to the pin (see the Typical Application Circuit).
15 12 AGCDIS AGC Control Pin. Pull high to disable AGC. Input logic level based on VDD5 voltage.
Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL
16 14 XTALSEL
high to select divider ratio of 32. Input logic level based on AVDD, ~3.2V supply.
1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF
17 15 IFIN1
capacitor.
2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
18 16 IFIN2
bandpass filter.
19 17 DFO Data Filter Output
20 18 DSN Negative Data Slicer Input
21 19 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
22 20 DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23 22 DSP Positive Data Slicer Input
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For
24 23 VDD5 +5V operation, VDD5 is the input to an on-chip voltage regulator whose +3.2V output appears at the
pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit.)
25 24 DATAOUT Digital Baseband Data Output. Output logic level based on VDD5 voltage.
26 26 PDOUT Peak Detector Output
Power-Down Select Input. Drive this pin with a logic high to power on the IC.
27 27 PWRDN
Input logic level based on VDD5 voltage.
28 28 XTAL2 2nd Crystal Input
1, 13,
— N.C. No Connection
21, 25
— — EP Exposed Pad (TQFN Only). Connect EP to GND.

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Detailed Description The LC tank filter connected to LNAOUT comprises L3

The MAX1473 CMOS superheterodyne receiver and a few and C2 (see the Typical Application Circuit). Select L3 and
external components provide the complete receive chain C2 to resonate at the desired RF input frequency. The
from the antenna to the digital output data. Depending on resonant frequency is given by:
signal power and component selection, data rates as high 1
as 100kbps can be achieved. The MAX1473 is designed f=
to receive binary ASK data modulated in the 300MHz 2 π L TOTAL × C TOTAL
to 450MHz frequency range. ASK modulation uses a where:
difference in amplitude of the carrier to represent logic 0
LTOTAL = L3 + LPARASITICS
and logic 1 data.
CTOTAL = C2 + CPARASITICS
Voltage Regulator
LPARASITICS and CPARASITICS include inductance and
For operation with a single +3.0V to +3.6V supply voltage, capacitance of the PCB traces, package pins, mixer input
connect AVDD, DVDD, and VDD5 to the supply voltage. impedance, LNA output impedance, etc. These parasitics
For operation with a single +4.5V to +5.5V supply voltage, at high frequencies cannot be ignored, and can have a
connect VDD5 to the supply voltage. An on-chip voltage dramatic effect on the tank filter center frequency. Lab
regulator drives one of the AVDD pins to approximately experimentation should be done to optimize the center
+3.2V. For proper operation, DVDD and both the AVDD frequency of the tank.
pins must be connected together. Bypass VDD5, DVDD,
and the pin 7 AVDD pin to AGND with 0.01μF capacitors, Mixer
and the pin 2 AVDD pin to AGND with a 0.1μF capacitor, A unique feature of the MAX1473 is the integrated image
all placed as close as possible to the pins. rejection of the mixer. This device eliminates the need
for a costly front-end SAW filter for most applications.
Low-Noise Amplifier
Advantages of not using a SAW filter are increased
The LNA is an NMOS cascode amplifier with off-chip sensitivity, simplified antenna matching, less board space,
inductive degeneration that achieves approximately 16dB and lower cost.
of power gain with a 2.0dB noise figure and an IIP3 of
-12dBm. The gain and noise figure are dependent on both The mixer cell is a pair of double balanced mixers that
the antenna matching network at the LNA input and the LC perform an IQ downconversion of the RF input to the
tank network between the LNA output and the mixer inputs. 10.7MHz IF from a low-side injected LO (i.e., fLO = fRF
- fIF). The image-rejection circuit then combines these
The off-chip inductive degeneration is achieved by signals to achieve a minimum 45dB of image rejection
connecting an inductor from LNASRC to AGND. This over the full temperature range. Low-side injection is
inductor sets the real part of the input impedance at required due to the on-chip image rejection architecture.
LNAIN, allowing for a more flexible input impedance The IF output is driven by a source-follower biased to
match, such as a typical PCB trace antenna. A nominal create a driving impedance of 330Ω; this provides a good
value for this inductor with a 50Ω input impedance is match to the off-chip 330Ω ceramic IF filter. The voltage
15nH, but is affected by PCB trace. See the Typical conversion gain is approximately 13dB when the mixer is
Operating Characteristics for the relationship between the driving a 330Ω load.
inductance and the LNA input impedance.
The IRSEL pin is a logic input that selects one of the three
The AGC circuit monitors the RSSI output. When the possible image-rejection frequencies. The input logic level
RSSI output reaches 2.05V, which corresponds to an RF is based on the AVDD, supply voltage generated by the
input level of approximately -57dBm, the AGC switches on-chip voltage regulator (~3.2V). When VIRSEL = 0V, the
on the LNA gain reduction resistor. The resistor reduces image rejection is tuned to 315MHz. VIRSEL = AVDD/2
the LNA gain by 35dB, thereby reducing the RSSI output tunes the image rejection to 375MHz, and when VIRSEL =
by about 500mV. The LNA resumes high-gain mode when AVDD, the image rejection is tuned to 433MHz. The IRSEL
the RSSI level drops back below 1.45V (approximately pin is internally set to AVDD/2 (image rejection at 375MHz)
-65dBm at RF input) for 150ms. The AGC has a hysteresis when it is left unconnected, thereby eliminating the need
of ~8dB. With the AGC function, the MAX1473 can reliably for an external AVDD/2 voltage.
produce an ASK output for RF input levels up to 0dBm
with a modulation depth of 18dB.

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Phase-Locked Loop causing the receiver to be tuned to 315.1MHz rather than

The PLL block contains a phase detector, charge pump/ 315.0MHz, an error of about 100kHz, or 320ppm.
integrated loop filter, VCO, asynchronous 64x clock In actuality, the oscillator pulls every crystal. The crystal’s
divider, and crystal oscillator driver. Besides the crystal, natural frequency is really below its specified frequency,
this PLL does not require any external components. but when loaded with the specified load capacitance, the
The VCO generates a low-side local oscillator (LO). The crystal is pulled and oscillates at its specified frequency.
relationship between the RF, IF, and crystal reference This pulling is already accounted for in the specification of
frequencies is given by: the load capacitance.
fXTAL = (fRF - fIF)/(32 x M) Additional pulling can be calculated if the electrical
where: parameters of the crystal are known. The frequency
pulling is given by:
M = 1 (VXTALSEL = AVDD) or 2 (VXTALSEL = 0V)
Cm  1 1 
To allow the smallest possible= IF bandwidth (for best fp  -  × 10 6
sensitivity), the tolerance of the reference must be 2  C case + C load C case + C spec 

minimized.
where:
Intermediate Frequency/RSSI fp is the amount the crystal frequency pulled in ppm.
The IF section presents a differential 330Ω load to
Cm is the motional capacitance of the crystal.
provide matching for the off-chip ceramic filter. The six
internal AC-coupled limiting amplifiers produce an overall Ccase is the case capacitance.
gain of approximately 65dB, with a bandpass filter-type Cspec is the specified load capacitance.
response centered near the 10.7MHz IF frequency with Cload is the actual load capacitance.
a 3dB bandwidth of approximately 11.5MHz. The RSSI
circuit demodulates the IF by producing a DC output When the crystal is loaded as specified, i.e., Cload =
proportional to the log of the IF signal level, with a slope Cspec, the frequency pulling equals zero.
of approximately 14.2mV/dB (see the Typical Operating Data Filter
Characteristics).
The data filter is implemented as a 2nd-order lowpass
The AGC circuit monitors the RSSI output. When the Sallen-Key filter. The pole locations are set by the
RSSI output reaches 2.05V, which corresponds to an RF combination of two on-chip resistors and two external
input level of approximately -57dBm, the AGC switches capacitors. Adjusting the value of the external capacitors
on the LNA gain reduction resistor. The resistor reduces changes the corner frequency to optimize for different
the LNA gain by 35dB, thereby reducing the RSSI output data rates. The corner frequency should be set to
by about 500mV. The LNA resumes high-gain mode when approximately 1.5 times the fastest expected data rate
the RSSI level drops back below 1.45V (approximately from the transmitter. Keeping the corner frequency near
-65dBm at RF input) for 150ms. The AGC has a hysteresis the data rate rejects any noise at higher frequencies,
of ~8dB. With the AGC function, the MAX1473 can reliably resulting in an increase in receiver sensitivity.
produce an ASK output for RF input levels up to 0dBm
with modulation depth of 18dB. The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
Applications Information offers a very flat amplitude response in the passband and
a rolloff rate of 40dB/decade for the two-pole filter. The
Crystal Oscillator Bessel filter has a linear phase response, which works well
The XTAL oscillator in the MAX1473 is designed to for filtering digital data. To calculate the value of C7 and
present a capacitance of approximately 3pF between the C6, use the following equations along with the coefficients
XTAL1 and XTAL2. If a crystal designed to oscillate with in Table 1:
a different load capacitance is used, the crystal is pulled
away from its stated operating frequency, introducing an Table 1. Coefficents to Calculate C7 and C6
error in the reference frequency. Crystals designed to
operate with higher differential load capacitance always FILTER TYPE a b
pull the reference frequency higher. For example, a Butterworth (Q = 0.707) 1.414 1.000
4.7547MHz crystal designed to operate with a 10pF load
Bessel (Q = 0.577) 1.3617 0.618
capacitance oscillates at 4.7563MHz with the MAX1473,

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Data Slicer
b
C7 = The purpose of the data slicer is to take the analog
a (100k ) (π) (f c )
output of the data filter and convert it to a digital signal.
a This is achieved by using a comparator and comparing
C6 =
4(100k ) (π) (f c ) the analog input to a threshold voltage. The output logic
level is based on VDD5 voltage supply. One input is
where fC is the desired 3dB corner frequency. supplied by the data filter output. Both comparator inputs
are accessible off chip to allow for different methods of
For example, choose a Butterworth filter response with a generating the slicing threshold, which is applied to the
corner frequency of 5kHz: second comparator input.
1.000 The suggested data slicer configuration uses a resistor
C7 ≈ 450pF
(1.414) (100kΩ) (3.14) (5kHz) (R1) connected between DSN and DSP with a capacitor
(C8) from DSN to DGND (Figure 2). This configuration
Choosing standard capacitor values changes C7 to 470pF averages the analog output of the filter and sets the
and C6 to 220pF, as shown in the Typical Application threshold to approximately 50% of that amplitude. With
Circuit. this configuration, the threshold automatically adjusts as
the analog signal varies, minimizing the possibility for
errors in the digital data. The sizes of R1 and C8 affect
how fast the threshold tracks to the analog amplitude. Be
MAX1473 sure to keep the corner frequency of the RC circuit much
lower than the lowest expected data rate.
RSSI
Note that a long string of zeros or 1s can cause the
threshold to drift. This configuration works best if a coding
RDF2 RDF1 scheme, such as Manchester coding, which has an equal
100kΩ 100kΩ number of zeros and 1s, is used.
To prevent continuous toggling of DATAOUT in the
19 21 22 absence of an RF signal due to noise, hysteresis can be
DFO OPP DFFB added to the data slicer as shown in Figure 3.
C6 C7 For further information on Data Slicer options, please refer
to Maxim Application Note 3671, Data Slicing Techniques

Figure 1. Sallen-Key Lowpass Data Filter

MAX1473

DATA
MAX1473 SLICER

DATA 25 23 20 19
SLICER DATAOUT DSP DSN DFO
R1
R2
R3
25 20 23 19
DATAOUT DSN DSP DFO
R* *OPTIONAL C8
C8 R1

Figure 2. Generating Data Slicer Threshold Figure 3. Generating Data Slicer Hysteresis

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

for UHF ASK Receivers.

Peak Detector
The peak detector output (PDOUT), in conjunction with MAX1473
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor provides
a path for the capacitor to discharge, allowing the peak DATA
detector to dynamically follow peak changes of the data SLICER
filter output voltage. For faster receiver startup, the circuit
shown in Figure 4 can be used.
25 20 23 19 26
Layout Considerations DATAOUT DSN DSP DFO PDOUT
25kΩ
A properly designed PCB is an essential part of any RF/
microwave circuit. On high-frequency inputs and outputs,
use controlled-impedance lines and keep them as short 47nF
as possible to minimize losses and radiation. At high
frequencies, trace lengths that are on the order of λ/10 or
longer act as antennas.
Keeping the traces short also reduces parasitic inductance.
Figure 4. Using PDOUT for Faster Startup
Generally, 1in of a PCB trace adds about 20nH of parasitic
inductance. The parasitic inductance can have a dramatic
effect on the effective inductance of a passive component. Control Interface Considerations
For example, a 0.5in trace connecting a 100nH inductor When operating the MAX1473 with a +4.5V to +5.5V
adds an extra 10nH of inductance or 10%. supply voltage, the PWRDN and AGCDIS pins may be
driven by a microcontroller with either 3V or 5V interface
To reduce the parasitic inductance, use wider traces and
logic levels. When operating the MAX1473 with a +3.0V
a solid ground or power plane below the signal traces.
to +3.6V supply, the microcontroller must produce logic
Also, use low-inductance connections to ground on all
levels which conform to the VIH and VIL specifications in
GND pins, and place decoupling capacitors close to all
the DC Electrical Characteristics Table for the MAX1473.
power-supply pins.

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Table 2. Component Values for Typical Application Circuit

COMPONENT VALUE FOR fRF = 433MHz VALUE FOR fRF = 315MHz DESCRIPTION
C1 100pF 100pF 5%
C2 2.7pF 4.7pF ±0.1pF
C3 100pF 100pF 5%
C4 100pF 100pF 5%
C5 1500pF 1500pF 10%
C6 220pF 220pF 5%
C7 470pF 470pF 5%
C8 0.47µF 0.47µF 20%
C9 220pF 220pF 10%
C10 0.01µF 0.01µF 20%
C11 0.1µF 0.1µF 20%
C12 15pF 15pF Depends on XTAL
C13 15pF 15pF Depends on XTAL
C14 0.01µF 0.01µF 20%
C15 0.01µF 0.01µF 20%
L1 56nH 120nH 5% or better**
L2 15nH 15nH 5% or better**
L3 15nH 27nH 5% or better**
R1 5.1kΩ 5.1kΩ 5%
R2 Open Open —
R3 Short Short —
X1(÷64) 6.6128MHz* 4.7547MHz* Crystek or Hong Kong X’tal
X1 (÷32) 13.2256MHz* 9.5094MHz* Crystek or Hong Kong X’tal
Y1 10.7MHz ceramic filter 10.7MHz ceramic filter Murata
*Crystal frequencies shown are for ÷64 (VXTALSEL = 0V) and ÷32 (VXTALSEL = VDD).
**Wirewound recommended.

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Typical Application Circuit

AVDD VDD
IF VDD IS THEN AVDD IS
(SEE TABLE)
3.0V TO 3.6V CONNECTED TO VDD
4.5V TO 5.5V CREATED BY LDO, X1
AVAILABLE AT AVDD
(PIN 2)

C11 C13 C12

1 28
RF INPUT XTAL1 XTAL2
2 27 TO/FROM µP
AVDD PWRDN POWER DOWN
C1 L1 DATA OUT
3 26
LNAIN PDOUT
4 R2
LNASRC
MAX1473 DATAOUT 25
L2 C15
5 24
AGND VDD5
R3
6 23
AVDD C14 LNAOUT DSP

L3 7 22
AVDD DFFB
C3
C2 8 21
MIXIN1 OPP
C7
9 20
MIXIN2 DSN
C4 10 19
C9 AGND DFO
11 18
IRSEL IFIN2
**
12 17 R1
MIXOUT IFIN1
13 16
DGND XTALSEL
14 15
DVDD AGCDIS
FROM µP

Y1 * C5 C6 C8
IF FILTER
C10 IN OUT
GND

COMPONENT VALUES
IN TABLE 2

** SEE MIXER SECTION * SEE PHASE-LOCKED LOOP SECTION

Chip Information
PROCESS: CMOS

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Functional Diagram

LNASRC AGCDIS LNAOUT MIXIN1 MIXIN2 IRSEL MIXOUT IFIN1 IFIN2

4 15 6 8 9 11 12 17 18

0˚ IF LIMITING
AUTOMATIC
3 Q AMPS
LNAIN LNA GAIN IMAGE
CONTROL ∑
REJECTION
2 90˚
AVDD MAX1473
24 3.2V REG I RSSI
VDD5
7
AVDD
14 DIVIDE DATA
DVDD VCO FILTER
BY 64
RDF2 RDF1
100kΩ 100kΩ
13 PHASE LOOP
DGND DETECTOR FILTER
DATA
5,10 1 CRYSTAL POWER SLICER
AGND
2 DRIVER DOWN

16 1 28 27 25 20 23 19 26 21 22
XTALSEL XTAL1 XTAL2 PWRDN DATAOUT DSN DSP DFO PDOUT OPP DFFB

Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

28 TSSOP U28+1 21-0066 90-0171
32 Thin QFN-EP T3255+3 21-0140 90-0001

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MAX1473 315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
Added lead-free parts and exposed pad in Ordering Information and Pin Description
4 5/10 1, 8
tables
Updated Absolute Maximum Ratings, AC Electrical Characteristics, Pin Description,
2, 3, 4, 8, 9, 12,
5 1/11 Layout Considerations, Typical Application Circuit, Functional Diagram, and Package
13, 14
Information; added Voltage Regulator section to the Detailed Description section
Updated DC Electrical and AC Electrical Characteristics tables, replaced TOC 4,
6 1/12 updated Tables 1 and 2 and Figure 1; updated Phase-Locked Loop, Data Filter, Data 3, 5, 6, 10–13
Slicer, and Layout Considerations sections

Updated Absolute Maximum Ratings, DC Electrical Characteristics, DC Electrical

7 1/19 2–5, 8–11, 14
Characteristics, Pin Description table, Detailed Description, and Typical Application Circuit

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2019 Maxim Integrated Products, Inc. │ 16