EVALUATION KIT AVAILABLE

MAX2871 23.5MHz to 6000MHz Fractional/

Integer-N Synthesizer/VCO

General Description Benefits and Features

The MAX2871 is an ultra-wideband phase-locked loop (PLL) ● Output Binary Buffers/Dividers Enable Extended
with integrated voltage control oscillators (VCOs) capable Frequency Range
of operating in both integer-N and fractional-N modes. • Divider Ratios of 1/2/4/8/16/32/64/128
When combined with an external reference oscillator and • 23.5MHz to 6000MHz
loop filter, the MAX2871 is a high-performance frequency
synthesizer capable of synthesizing frequencies from ● High-Performance Phase Frequency Detector (PFD)
23.5MHz to 6.0GHz while maintaining superior phase and Reference Frequency Reduces Spectral Noise
noise and spurious performance. • PFD Up to 140MHz
The ultra-wide frequency range is achieved with the • Reference Frequency Up to 210MHz
help of multiple integrated VCOs covering 3000MHz to ● Low Normalized Inband Phase Noise of -230dBc/Hz
6000MHz, and output dividers ranging from 1 to 128. The Reduces System Noise Floor Contribution
device also provides dual differential output drivers, which
can be independently programmed to deliver -1dBm to ● Manual/Automatic VCO Selection Permits Fast
+8dBm differential output power. Both outputs can be Switching
muted by either software or hardware control. ● Output Phase Reset and Adjustment Allow
The MAX2871 is controlled by a 4-wire serial interface and Synchronization of Multiple Synthesizers
is compatible with 1.8V control logic. The device is available
● On-Chip Temperature Sensor with 7-Bit ADC Ensures
in a lead-free, RoHS-compliant, 5mm x 5mm, 32-pin TQFN
package, and operates over an extended -40°C to +85°C Optimum VCO Selection
temperature range. ● Cycle Slip Reduction and Fast Lock Features
The MAX2871 has an improved feature set and better overall Improve Accuracy and Acquisition Time
phase noise and is fully pin and software-compatible with the ● VCO Lock Maintained Over Entire Temperature
MAX2870. Range Provides Glitch-Free Operation
Applications ● Dual Differential Programmable Outputs Maximize
● Wireless Infrastructure ● Clock Generation Flexibility of Use
● Test and Measurement ● Microwave Radios
Ordering Information and “Typical Application Circuit”
appears at end of data sheet.
Functional Diagram

MUX
MUX
MAX2871
LD
LOCK DETECT

REF_IN MUX R COUNTER DIVIDE-BY-2 MUX CHARGE CP_OUT

X2 PUMP
GND_CP
CLK
TUNE
DATA SPI AND
LE REGISTERS

VCO
INTEGER FRAC MODULUS
RFOUTA_P
DIV-BY- DIV-BY-
1/2/4/8/16 1/2/4/8 RFOUTA_N

RFOUT_EN
MAIN
MODULATOR RFOUTB_P
MUX RFOUTB_N
N COUNTER

MUX

19-7106; Rev 4; 6/20

MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Absolute Maximum Ratings

VCC_ to GND_.......................................................-0.3V to +3.9V Junction Temperature.......................................................+150°C
All Other Pins to GND_..............................-0.3V to VCC_ + 0.3V Operating Temperature Range............................ -40°C to +85°C
Continuous Power Dissipation (TA = +70°C) Storage Temperature Range............................. -65°C to +150°C
TQFN-EP Multilayer Board Lead Temperature (soldering, 10s)................................. +300°C
(derate 34.5mW/°C above +70°C)..........................2758.6mW Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Package Thermal Characteristics (Note 1)

TQFN
Junction-to-Ambient Thermal Resistance (θJA)...........29°C/W Junction-to-Case Thermal Resistance (θJC)...............1.7°C/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

DC Electrical Characteristics
(Measured using MAX2871 EV Kit. VCC_ = 3V to 3.6V, VGND_ = 0V, fREF_IN = 50MHz, fPFD = 50MHz, TA = -40°C to +85°C. Typical
values measured at VCC_ = 3.3V; TA = +25°C; register settings (Reg 0:5) 00780000, 20000141, 01005E42, 00000013, 610F423C,
01400005;. unless otherwise noted.) (Note 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage 3 3.3 3.6 V
IRFOUT_, minimum output power, single channel 9
RFOUT_ Current Consumption mA
IRFOUT_, maximum output power, single channel 25
Total, including RFOUT, both
165 200
Both channels channel (Note 3)
enabled, Each output divide-by-2 8
Supply Current mA
maximum output
power ICCVCO + ICCRF (Note 3) 122
Low-power sleep mode 1

AC Electrical Characteristics
(Measured using MAX2871 EV Kit. VCC_ = 3V to 3.6V, VGND_ = 0V, fREF_IN = 50MHz, fPFD = 25MHz, fRFOUT_ = 6000MHz,
TA = -40°C to +85°C. Typical values measured at VCC_ = 3.3V, TA = +25°C, register settings (Reg 0:5) 00780000, 20000141,
01005E42, 00000013, 610F423C, 01400005; unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
REFERENCE OSCILLATOR INPUT (REF_IN)
REF_IN Input Frequency Range 10 210 MHz
REF_IN Input Sensitivity 0.7 VCC_ VP-P
REF_IN Input Capacitance 2 pF
REF_IN Input Current -60 +60 µA
PHASE DETECTOR
Integer-N mode 140
Phase Detector Frequency MHz
Fractional-N mode 125

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

AC Electrical Characteristics (continued)

(Measured using MAX2871 EV Kit. VCC_ = 3V to 3.6V, VGND_ = 0V, fREF_IN = 50MHz, fPFD = 25MHz, fRFOUT_ = 6000MHz,
TA = -40°C to +85°C. Typical values measured at VCC_ = 3.3V, TA = +25°C, register settings (Reg 0:5) 00780000, 20000141,
01005E42, 00000013, 610F423C, 01400005; unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
CHARGE PUMP
CP[3:0] = 1111, RSET = 5.1kΩ 5.12
Sink/Source Current mA
CP[3:0] = 0000, RSET = 5.1kΩ 0.32
RSET Range 2.7 10 kΩ
RF OUTPUTS
Fundamental Frequency Range 3000 6000 MHz
Divided Frequency Range With output dividers (1/2/4/8/16/32/64/128) 23.4375 6000 MHz
VCO Sensitivity 100 MHz/V
Frequency Pushing Open loop 0.8 MHz/V
Frequency Pulling Open loop into 2:1 VSWR 70 kHz
2nd Harmonic Fundamental VCO output -40 dBc
3rd Harmonic Fundamental VCO output -34 dBc
2nd Harmonic VCO output divided-by-2 -25 dBc
3rd Harmonic VCO output divided-by-2 -20 dBc
Maximum Output Power fRFOUT_ = 3000MHz (Note 4) 5 dBm
Minimum Output Power fRFOUT_ = 3000MHz (Note 4) -4 dBm
-40°C ≤ TA ≤ +85°C 1
Output Power Variation (Note 4) dB
3V ≤ VCC_ ≤ 3.6V 0.2
Muted Output Power (Note 4) -40 dBm
VCO AND FREQUENCY SYNTHESIZER NOISE
10kHz offset -83
100kHz offset -111
VCO at 3000MHz
1MHz offset -136
5MHz offset -149
10kHz offset -77
100kHz offset -106
VCO Phase Noise (Note 5) VCO at 4500MHz dBc/Hz
1MHz offset -132
5MHz offset -147
10kHz offset -71
100kHz offset -101
VCO at 6000MHz
1MHz offset -128
5MHz offset -144
In-Band Noise Floor Normalized (Note 6) -230 dBc/Hz
1/f Noise Normalized (Note 7) -122 dBc/Hz
In-Band Phase Noise (Note 8) -102 dBc/Hz
Integrated RMS Jitter (Note 9) 0.2 ps

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

AC Electrical Characteristics (continued)

(Measured using MAX2871 EV Kit. VCC_ = 3V to 3.6V, VGND_ = 0V, fREF_IN = 50MHz, fPFD = 25MHz, fRFOUT_ = 6000MHz,
TA = -40°C to +85°C. Typical values measured at VCC_ = 3.3V, TA = +25°C, register settings (Reg 0:5) 00780000, 20000141,
01005E42, 00000013, 610F423C, 01400005; unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Spurious Signals Due to PFD Frequency 50kHz loop bandwidth -88 dBc
VCC_
VCO Tune Voltage 0.5 V
- 0.5
TEMPERATURE SENSOR AND ADC
ADC Resolution 7 Bits
Temperature Sensor Accuracy 3 °C

DIGITAL I/O CHARACTERISTICS

(VCC_ = +3V to +3.6V, VGND_ = 0V, TA = -40°C to +85°C. Typical values at VCC_ = 3.3V, TA = +25°C.) (Note 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS

SERIAL INTERFACE INPUTS (CLK, DATA, LE, CE, RFOUT_EN)
Input Logic-Level Low VIL 0.4 V
Input Logic-Level High VIH 1.5 V
Input Current IIH/IIL -1 +1 µA
Input Capacitance 1 pF
SERIAL INTERFACE OUTPUTS (MUX, LD)
Output Logic-Level Low 0.3mA sink current 0.4 V
VCC -
Output Logic-Level High 0.3mA source current V
0.4
Output Current Level High 0.5 mA

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

SPI TIMING CHARACTERISTICS

(VCC_ = +3V to +3.6V, VGND_ = 0V, TA = -40°C to +85°C. Typical values at VCC_= 3.3V, TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Guaranteed by CLK pulse-width
CLK Clock Period tCP 50 ns
low and high
CLK Pulse-Width Low tCL 25 ns
CLK Pulse-Width High tCH 25 ns
LE Setup Time tLES 20 ns
LE Hold Time tLEH 10 ns
LE Minimum Pulse-Width High tLEW 20 ns
DATA Setup Time tDS 25 ns
DATA Hold Time tDH 25 ns
MUX Valid tDOT MUX transition valid after CLK rise 10 ns
Note 2: Production tested at TA = +25°C. Cold and hot are guaranteed by design and characterization.
Note 3: fREF_IN = 100MHz, phase detector frequency = 25MHz, RF output = 6000MHz.
Register setting: 00780000, 00400061, 34011242, F8010003, 638FF1FC, 80400005.
Note 4: Measured single ended with 27nH to VCC_RF into 50Ω load. Power measured with single output enabled. Unused output
has 27nH to VCC_RF with 50Ω termination.
Note 5: VCO phase noise is measured open loop.
Note 6: Measured at 200kHz using a 50MHz Bliley NV108C19554 OCVCXO with 2MHz loop bandwidth. Register setting
801E0000, 8000FFF9, 80005FC2, 6C10000B, 638E80FC, 400005. EV kit loop filter: C2 = 1500pF, C1 = 33pF, R2A = 0Ω,
R2B = 1100Ω, R3 = 0Ω, C3 = open.
Note 7: 1/f noise contribution to the in-band phase noise is computed by using 1/f noise + 10log(10kHz/fOFFSET) +
20log(fRF/1GHz). Register setting: 803A0000, 8000FFF9, 81005F42, F4000013, 6384803C, 001500005.
Note 8: fREF_IN = 50MHz; fPFD = 25MHz; offset frequency = 10kHz; VCO frequency = 4227MHz, output divide-by-2 enabled.
RFOUT = 2113.5MHz; N = 169; loop BW = 40kHz, CP[3:0] = 1111; integer mode.
Note 9: fREF_IN = 50MHz; fPFD = 50MHz; VCO frequency = 4400MHz, fRFOUT_ = 4400MHz; loop BW = 65kHz. Register setting:
002C0000, 200303E9, 80005642, 00000133, 638E82FC, 01400005. EV kit loop filter: C2 = 0.1µF, C1 = 0.012µF,
R2A = 0Ω, R2B = 120Ω, R3 = 250Ω, C3 = 820pF.

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Typical Operating Characteristics

(Measured with MAX2871 EV Kit. VCC_ = 3.3V, VGND_ = 0V, fREF_IN = 50MHz, TA = +25°C, see the Typical Operating Characteristics
Testing Conditions Table Table.)

3.0GHz VCO OPEN-LOOP PHASE NOISE 4.5GHz VCO OPEN-LOOP PHASE NOISE 6.0GHz VCO OPEN-LOOP PHASE NOISE
vs. FREQUENCY toc01 vs. FREQUENCY toc02
vs. FREQUENCY toc03
-40 -40 -40
-50 -50 -50
-60 -60 -60
-70 -70 -70
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

-80
PHASE NOISE (dBc/Hz)

-80 -80
-90 -90 -90
-100 -100 -100
-110 -110 -110
-120 -120 -120
-130 -130 -130
-140 -140 -140
-150 -150 -150
-160 -160 -160
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)
FREQUENCY (Hz)

3.0GHZ CLOSED-LOOP PHASE NOISE 4.5GHZ CLOSED-LOOP PHASE NOISE 6.0GHZ CLOSED-LOOP PHASE NOISE
vs. FREQUENCY toc04
vs. FREQUENCY toc05
vs. FREQUENCY toc06
-70 -70 -70
-80 DIV1
-80 DIV1 -80 DIV1
DIV2 DIV2 DIV2
-90 DIV4 -90 DIV4 -90 DIV4
DIV8 DIV8 DIV8
-100 -100
PHASE NOISE (dBc/Hz)

-100
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)

DIV16 DIV16 DIV16

-110 DIV32 -110 DIV32 -110 DIV32
DIV64 DIV64 DIV64
-120 -120 -120
DIV128 DIV128 DIV128
-130 -130 -130
-140 -140 -140
-150 -150 -150
-160 -160 -160
-170 -170 -170
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)

904MHz INTEGER-N MODE PHASE NOISE 2687.5MHz INTEGER-N MODE PHASE NOISE 2113.5MHz FRACTIONAL-N PHASE NOISE
AND SPUR PERFORMANCE vs. FREQUENCY AND SPUR PERFORMANCE vs. FREQUENCY vs. FREQUENCY (LOW-NOISE MODE)
toc07 toc08 toc09
0 0 -70

-20 -20 -80

-90
-40 -40
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

-100
SPURS (dBc)

-60 -60
SPURS (dBc)

-110
-80 -80 -120

-100 -100 -130

-140
-120 -120
-150
-140 -140
-160
-160 -160 -170
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Typical Operating Characteristics (continued)

(Measured with MAX2871 EV Kit. VCC_ = 3.3V, VGND_ = 0V, fREF_IN = 50MHz, TA = +25°C, see the Typical Operating Characteristics
Testing Conditions Table Table.)

2113.5MHz FRACTIONAL-N PHASE NOISE 2679.4MHz FRACTIONAL-N PHASE NOISE 2679.4MHz FRACTIONAL-N PHASE NOISE
vs. FREQUENCY (LOW-SPUR MODE) vs. FREQUENCY (LOW-NOISE MODE) vs. FREQUENCY (LOW-SPUR MODE)
toc10 toc11 toc12
-70 -70 -70
-80 -80 -80
-90 -90 -90
-100 -100 -100
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

-110 -110 -110

-120 -120 -120
-130 -130 -130
-140 -140 -140
-150 -150 -150
-160 -160 -160
-170 -170 -170
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)

SUPPLY CURRENT vs. FREQUENCY

SUPPLY CURRENT vs. OUTPUT POWER SUPPLY CURRENT vs. OUTPUT POWER
(ONE CHANNEL ACTIVE,
SETTING (ONE CHANNEL ACTIVE, 3GHz) SETTING (TWO CHANNELS ACTIVE, 3GHz)
MAXIMUM OUTPUT POWER) toc15
toc13 toc14
160 250 200

150 230 TA = +25˚C

TA = +85˚C 180
140 210 TA = -40˚C
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)

130 190
SUPPLY CURRENT (mA)

160
120 170
110 150 140
100 130
120
90 110
TA = +25˚C TA = +25˚C
80 90
TA = +85˚C 100 TA = +85˚C
70 TA = -40˚C 70 TA = -40˚C

60 50 80
00 01 10 11 10 100 1k 10k 00 01 10 11
PWR SETTING FREQUENCY (MHz) PWR SETTING

SUPPLY CURRENT vs. FREQUENCY

(TWO CHANNELS ACTIVE,
PLL LOCK vs. TIME
MAXIMUM OUTPUT POWER)
toc16 toc17
300 3.85
FASTLOCK OFF
280 TA = +25˚C 3.84
FASTLOCK ON
TA = +85˚C
260 TA = -40˚C 3.83
SUPPLY CURRENT (mA)

240 3.82
FREQUENCY (GHz)

220 3.81
200 3.8
180 3.79
160 3.78
140 3.77
120 3.76
100 3.75
10 100 1K 10K 0 50 100 150 200
FREQUENCY (MHz) TIME (µs)

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Typical Operating Characteristics Testing Conditions Table

REGISTER LOOP MAX2871 EV KIT COMPONENT VALUES
fREF fPFD
TOC TITLE SETTINGS FILTER C2 R2A + C1 R3 C3 COMMENTS
(MHz) (MHz)
(hex) BW (Hz) (F) R2B (I) (F) (I) (F)
80B40000,
3.0GHz VCO 80000141, VCO bits set
OPEN-LOOP 0000405A, for 3GHz
N/A N/A N/A N/A N/A N/A N/A N/A
PHASE NOISE XX00013, output,
vs. FREQUENCY 648020FC, VAS_SHDN = 1
00000005

80B40000,
4.5GHz VCO 80000141, VCO bits set
OPEN-LOOP 0000405A, for 4.5GHz
N/A N/A N/A N/A N/A N/A N/A N/A
PHASE NOISE XX00013 output,
vs. FREQUENCY 648020FC, VAS_SHDN = 1
00000005

80B40000,
6.0GHz VCO 80000141 VCO bits set
OPEN-LOOP 0000405A for 6.0GHz
N/A N/A N/A N/A N/A N/A N/A N/A
PHASE NOISE XX00013, output,
vs. FREQUENCY 648020FC VAS_SHDN = 1
00000005

803C0000
3.0GHz 80000141
CLOSED-LOOP 00009E42,
50 25 40k 0.1F 120 0.012F 250 820p
PHASE NOISE E8000013,
vs. FREQUENCY 618160FC,
00400005

805A0000,
4.5GHz 80000141,
CLOSED-LOOP 00009E42,
50 25 40k 0.1F 120 0.012F 250 820p
PHASE NOISE E8000013,
vs. FREQUENCY 618160FC,
00400005

80780000,
6.0GHz 80000141,
CLOSED-LOOP 00009E42,
50 25 40k 0.1F 120 0.012F 250 820p
PHASE NOISE EA000013,
vs. FREQUENCY 608C80FC,
00400005

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Typical Operating Characteristics Testing Conditions Table (continued)

REGISTER LOOP MAX2871 EV KIT COMPONENT VALUES S
fREF fPFD
TOC TITLE SETTINGS FILTER C2 R2A + C1 R3 C3 COMMENTS
(MHz) (MHz)
(hex) BW (Hz) (F) R2B (I) (F) (I) (F)
82350000,
904MHz INTEGER-N
800007D1
MODE PHASE
E1065FC2,
NOISE AND SPUR 40 0.8 16k 0.1F 806 3300p 1201 470p
2C000013
PERFOMANCE
6020803C
vs. FREQUENCY
00400005

2687.5MHz 94FF0000,
INTEGER-N PHASE 803207D1,
NOISE 010A1E42,
40 0.5 5k 0.1F 1000 6800p 300 0.01F
AND SPUR B00000A3,
PERFORMANCE vs. 6090803C,
FREQUENCY 00400005

00548050,
2113.5MHz
400003E9,
FRACTIONAL-N
81005FC2,
PHASE NOISE 50 25 40k 0.1F 120 0.012F 250 820p
E8000013,
(LOW-NOISE MODE)
609C80FC,
vs. FREQUENCY
00400005

00548050,
2113.5MHz
400003E9,
FRACTIONAL-N
E1005FC2,
PHASE NOISE vs. 50 25 40k 0.1F 120 0.012F 250 820p
E8000013,
FREQUENCY
609C80FC,
(LOW-SPUR MODE)
00400005

00358160,
2679.4MHz
203207D1,
FRACTIONAL-N
01005E42,
PHASE NOISE vs. 50 25 40k 0.1F 120 0.012F 250 820p
B20000A3,
FREQUENCY
6010003C,
(LOW-NOISE MODE)
00400005

00358160,
2679.4MHz
203207D1,
FRACTIONAL-N
41005E42,
PHASE NOISE vs. 50 25 40k 0.1F 120 0.012F 250 820p
B20000A3,
FREQUENCY
6010003C,
(LOW-SPUR MODE)
00400005

003C0000,
SUPPLY CURRENT
20000321,
vs. OUTPUT POWER
01005E42, APWR swept
SETTING 50 25
00000013, from 00 to 11
(ONE CHANNEL
610F423C,
ACTIVE, 3GHz)
01400005,

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Typical Operating Characteristics Testing Conditions Table (continued)

REGISTER LOOP MAX2871 EV KIT COMPONENT VALUES
fREF fPFD
TOC TITLE SETTINGS FILTER C2 R2A + C1 R3 C3 COMMENTS
(MHz) (MHz)
(hex) BW (Hz) (F) R2B (I) (F) (I) (F)
003C0000,
SUPPLY CURRENT
20000321,
vs. FREQUENCY N and F values
01005E42,
(ONE CHANNEL 50 25 changed for
00000013,
ACTIVE, MAXIMUM each frequency
610F423C,
OUTPUT POWER)
01400005

003C0000,
SUPPLY CURRENT 20000321,
APWR and
vs. OUTPUT POWER 01005E42,
50 25 BPWR swept
SETTING (TWO 00000013,
from 00 to 11
CHANNELS ACTIVE) 610F43FC,
01400005

003C0000,
SUPPLY CURRENT
20000321,
vs. FREQUENCY N and F values
01005E42,
(TWO CHANNELS 50 25 swept for each
00000013,
ACTIVE MAXIMUM frequency
610F43FC,
OUTPUT POWER)
01400005

00250120,
20320141,
00004042, CDM changed
PLL LOCK vs. TIME 40 40 40k 0.1F 120 0.012F 250 820p
000000A3, from 00 to 01
0184023C,
01400005

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Pin Configuration

NOISE_FILT
GND_TUNE

GND_VCO
BIAS_FILT

VCC_VCO
TOP VIEW

TUNE
RSET
REG
24 23 22 21 20 19 18 17
LD 25 16 VCC_RF

RFOUT_EN 26 15 RFOUTB_N

GND_DIG 27 14 RFOUTB_P

VCC_DIG 28 13 RFOUTA_N

REF_IN 29 MAX2871 12 RFOUTA_P

MUX 30 11 GND_RF

GND_SD 31 EP 10 VCC_PLL
+
VDD_SD 32 9 GND_PLL
1 2 3 4 5 6 7 8
CLK

DATA

LE

CE

SW

VCC_CP

CP_OUT

GND_CP

TQFN

Pin Description
PIN NAME FUNCTION
Serial Clock Input. The data is latched into the 32-bit shift register on the rising edge of the
1 CLK
CLK line.
2 DATA Serial Data Input. The serial data is loaded MSB first. The 3 LSBs identify the register address.
Load Enable Input. When LE goes high the data stored in the shift register is loaded into the
3 LE
appropriate latches.
4 CE Chip Enable. A logic-low powers the part down and the charge pump becomes high impedance.
Fast-Lock Switch. Connect to the loop filter when using the fast-lock mode. No connect in
5 SW
Normal mode
6 VCC_CP Power Supply for Charge Pump. Place decoupling capacitors as close as possible to the pin.
7 CP_OUT Charge-Pump Output. Connect to external loop filter input.
8 GND_CP Ground for Charge-Pump. Connect to board ground, not to the paddle.
9 GND_PLL Ground for PLL. Connect to board ground, not to the paddle.
10 VCC_PLL Power Supply for PLL. Place decoupling capacitors as close as possible to the pin.
11 GND_RF Ground for RF Outputs. Connect to board ground plane, not to the paddle.
Open Collector Positive RF Output A. See RFOUTA± and RFOUTB± section in Detailed
12 RFOUTA_P
Description.
Open Collector Negative RF Output A. See RFOUTA± and RFOUTB± section in Detailed
13 RFOUTA_N
Description.

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Pin Description (continued)

PIN NAME FUNCTION
Open Collector Positive RF Output B. See RFOUTA± and RFOUTB± section in Detailed
14 RFOUTB_P
Description.
Open Collector Negative RF Output B. See RFOUTA± and RFOUTB± section in Detailed
15 RFOUTB_N
Description.
Power Supply for RF Output and Dividers. Place decoupling capacitors as close as possible to
16 VCC_RF
the pin.
17 VCC_VCO VCO Power Supply. Place decoupling capacitors to the analog ground plane.
18 GND_VCO Ground for VCO. Connect to main board ground plane, not directly to the paddle.
19 NOISE_FILT VCO Noise Decoupling. Place a 1µF capacitor to ground.
20 TUNE Control Input to the VCO. Connect to external loop filter.
Ground for Control Input to the VCO. Connect to main board ground plane, not directly to the
21 GND_TUNE
paddle.
Charge-Pump Current Range Input. Connect an external resistor to ground to set the minimum
22 RSET
CP current. ICP = 1.63/RSET x (1 + CP[3:0])
23 BIAS_FILT VCO Noise Decoupling. Place a 1µF capacitor to ground.
24 REG Reference Voltage Compensation. Place a 1µF capacitor to ground.
Lock Detect Output. Logic-high when locked, and logic-low when unlocked. See register
25 LD
description for more details (Table 9).
26 RFOUT_EN RF Output Enable. A logic-low disables the RF outputs.
27 GND_DIG Ground for Digital Circuitry. Connect to main board ground plane, not directly to the paddle.
28 VCC_DIG Power Supply for Digital Circuitry. Place decoupling capacitors as close as possible to pin.
Reference Frequency Input. This is a high-impedance input with a nominal bias voltage of VCC_
29 REF_IN
DIG/2. AC-couple to reference signal.
30 MUX Multiplexed I/Os. See Table 5.
Ground for Sigma-Delta Modulator. Connect to main board ground plane, not directly to
31 GND_SD
the paddle.
Power Supply for Sigma-Delta Modulator. Place decoupling capacitors as close as possible
32 VCC_SD
to the pin.
— EP Exposed Pad. Connect to board ground.

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Detailed Description ● Register 4, set bit 5 and 8 to 0 to keep RFOUT disable.

4-Wire Serial Interface ● Register 3, Address 0X03

The MAX2871 can be controlled by 3-wire SPI for write ● Register 2, Address 0X02
operation using CLK, DATA, LE pins, refer Figure 1. For ● Register 1, Address 0X01
read operation, in addition to the above 3 pins, MUX pin ● Register 0, Address 0X00
can be used to access Reg, 0x06, refer Figure 2. The
MAX2871 serial interface contains six write-only and To enable RFOUT, Register 4, Address 0X04, set bit 5
one read-only 32-bit registers. The 29 most-significant and 8 to 1.
bits (MSBs) are data, and the three least-significant bits Register programming order should be address 0x05,
(LSBs) are the register address. Register data is loaded 0x04, 0x03, 0x02, 0x01, and 0x00. Several bits are
MSB first through the 4-wire serial interface (SPI). When double buffered to update the settings at the same time.
LE is logic-low, the logic level at DATA is shifted at the ris- See the register descriptions for double buffered settings.
ing edge of CLK. At the rising edge of LE, the 29 data bits
are latched into the register selected by the address bits. Read Sequence
The user must program all register values after power-up. Register 0x06 can be read back through the MUX pin.
The user must set MUX (register 5, bit 18 and register
Upon power-up, the registers should be programmed
2, bits 28:26) = 1100. To begin the read sequence, set
twice with at least a 20ms pause between cycle of
LE to logic-low, send 32 periods of CLK, and set LE to
write. The first write ensures that the device is enabled,
and the second write starts the VCO selection pro- logic-high. While the CLK is running, the DATA pin can
cess. Recommended to turn-off the outputs during this be held at logic-high or logic-low for 29 clocks, but the
sequence and then turn-on the outputs using RFA_EN, last 3 bits must be 110 to indicate register 6, then set LE
RFB_EN. back to logic-high after the 32nd clock. Finally, send 1
period of the clock. The MSB of register 0x06 appears
For a clean clock at start up, after power on, follow this
after the rising edge of the next clock and continues to
sequence of programming:
shift out for the next 29 clock cycles (Figure 2). After the
● Register 5, Address 0X05. Wait 20ms LSB of register 0x06 has been read, the user can reset
● Register 4, set bit 5 and 8 to 0 to keep RFOUT disable. MUX register = 0000.
● Register 3, Address 0X03 Power Modes
● Register 2, Address 0X02 The MAX2871 can be put into low-power mode by setting
● Register 1, Address 0X01 SHDN = 1 (register 2, bit 5) or by setting the CE pin to log-
ic-low. In low-power mode, all blocks except SPI are off.
● Register 0, Address 0X00
● Register 5, Address 0X05

t LES t LEH
LE t CP
t LEW
t CL

CLK
t CH

tDS t DH

DATA BIT31 BIT30 BIT1 BIT0

Figure 1. SPI Timing Diagram

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

DATA DON’T CARE 1 1 0

LE

CLK

1 29 30 31 32 33 34 35 36

MSB of R 6
MU X

tDOT

Figure 2. Initiating Readback

REF_IN MUX R COUNTER DIVIDE-BY-2 MUX To PFD

X2

Figure 3. Reference Input

After exiting low-power mode, allow at least 20ms for 140MHz for int-N mode. The R-divider can be held in reset
external capacitors to charge to their final values before when RST (register 2, bit 3) = 1.
programming the final VCO frequency.
Int, Frac, Mod, and R Counter Relationship
Reference Input The VCO frequency (fVCO), N, F, and M can be deter-
The reference input stage is configured as a CMOS mined based on desired RF output frequency (fRFOUTA)
inverter with shunt resistance from input to output. In shut- as follows:
down mode this input is set to high impedance to prevent Set DIVA value property based on fRFOUTA and Table 4
loading of the reference source. (register 4, bits 22:20)
The reference input signal path also includes optional x2 fVCO = fRFOUTA x DIVA
and ÷2 blocks. When the reference doubler is enabled
(DBR = 1), the maximum reference input frequency is lim- If bit FB = 1, (DIVA is not in PLL feedback loop):
ited to 105MHz. When the doubler is disabled, the refer- N + (F/M) = fVCO/fPFD
ence input frequency is limited to 210MHz. The minimum If bit FB = 0, (DIVA is in PLL feedback loop) and DIVA ≤
reference frequency is 10MHz. The minimum R counter 16:
divide ratio is 1, and the maximum divide ratio is 1023. N + (F/M) = (fVCO/fPFD)/DIVA
PFD Frequency If bit FB = 0, (DIVA is in PLL feedback loop) and DIVA > 16:
The phase-detector frequency is determined as follows: N + (F/M) = (fVCO/fPFD)/16
fPFD = fREF x [(1 + DBR)/(R x (1 + RDIV2))]
N is the value of the 16-bit N counter (16 to 65535), pro-
fREF represents the external reference input frequency. grammable through bits 30:15 of register 0. M is the frac-
DBR (register 2, bit 25) sets the fREF input frequency dou- tional modulus value (2 to 4095), programmable through
bler mode (0 or 1). RDIV2 (register 2, bit 24) sets the fREF bits 14:3 of register 1. F is the fractional division value (0
divide-by-2 mode (0 or 1). R (register 2, bits 23:14) is the to MOD - 1), programmable through bits 14:3 of register 0.
value of the 10-bit programmable reference counter (1 to In frac-N mode, the minimum N value is 19 and maximum
1023). The maximum fPFD is 125MHz for frac-N mode and

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

N value is 4091. The N counter is held in reset when RST The charge-pump output can be put into high-impedance
= 1 (register 2, bit 3). DIVA is the RF output divider setting mode when TRI = 1 (register 2, bit 4). The output is in
(0 to 7), programmable through bits 22:20 of register 4. normal mode when TRI = 0.
The division ratio is set by 2DIVA. The phase detector polarity can be changed if an active
The RF B output frequency is determined as follows: inverting loop filter topology is used. For noninverting loop
If BDIV = 0 (register 4, bit 9), fRFOUTB = fRFOUTA. filters, set PDP = 1 (register 2, bit 6). For inverting loop
filters, set PDP = 0.
If BDIV = 1, fRFOUTB = fVCO.
MUX
Int-N/Frac-N Modes
MUX is a multipurpose input/output for observing and
Integer-N mode is selected by setting bit INT = 1 (register controlling various internal functions of the MAX2871.
0, bit 31). When operating in integer-N mode, it is also MUX can also be configured as serial data output. Bits
necessary to set bit LDF (register 2, bit 8) to set the lock MUX (register 5, bit 18 and register 2, bit 28:26) are used
detect to integer-N mode. to select the desired MUX function (see Table 5).
The device’s frac-N mode is selected by setting bit INT = 0
(register 0, bit 31). Additionally, set bit LDF = 0 (register 2, Lock Detect
bit 8) for frac-N lock-detect mode. Lock detect can be monitored through the LD output by
setting the LD bits (register 5, bits 23:22). For digital lock
If the device is in frac-N mode, it will remain in frac-N
detect, set LD = 01. The digital lock detect is dependent
mode when fractional division value F = 0, which can
on the mode of the synthesizer. In frac-N mode set LDF =
result in unwanted spurs. To avoid this condition, the
0, and in int-N mode set LDF = 1. To set the accuracy of
device can automatically switch to integer-N mode when
the digital lock detect, see Table 1 and Table 2.
F = 0 if the bit F01 = 1 (register 5, bit 24).
Analog lock detect can be set with LD = 10. In this mode,
Phase Detector and Charge Pump LD is an open-drain output and requires an external
The device’s charge-pump current is determined by the pullup resistor of 10kΩ typical value.
value of the resistor from pin RSET to ground and the The lock detect output validity is dependent on many
value of bits CP (register 2, bits 12:9) as follows: factors. The lock detect output is not valid during VCO
ICP = 1.63/RSET x (1+ CP<3:0>) auto selection process. After the VCO auto selection
process has completed, the lock detect output is not
To reduce spurious in frac-N mode, set charge-pump
valid until the TUNE voltage has settled. TUNE voltage
linearity bits CPL = 00/01/10/11 (register 1, bits 30:29).
settling time is dependent on loop filter bandwidth, and
The user can determine which mode works best for their
can be calculated using EE-Sim Simulation tool found at
application. For int-N mode, set CPL = 00.
www.maximintegrated.com.

Table 1. Frac-N Digital Lock-Detect Settings

LOCKED UP/DOWN NUMBER OF LOCKED UP/DOWN TIME SKEW
PFD FREQUENCY LDS LDP
TIME SKEW (ns) CYCLES TO SET LD TO UNSET LD (ns)
≤ 32MHz 0 0 10 40 15
≤ 32MHz 0 1 6 40 15
> 32MHz 1 X 4 40 4

Table 2. Int-N Digital Lock-Detect Settings

LOCKED UP/DOWN NUMBER OF LOCKED UP/DOWN TIME SKEW
PFD FREQUENCY LDS LDP
TIME SKEW (ns) CYCLES TO SET LD TO UNSET LD (ns)
≤ 32MHz 0 0 10 5 15
≤ 32MHz 0 1 6 5 15
> 32MHz 1 X 4 5 4

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Cycle Slip Reduction

Cycle slip reduction is one of the two methods available to
improve lock time. It is enabled by setting CSM bit (register
3, bit 18) to 1. In this mode, the charge pump must be set R3
to its minimum value. 7 CP_OUT
Fast-Lock C3 C2 C1
Another method to decrease lock time is to use a fast-lock MAX2871
mode. This mode requires that CP = 0000 (register 2, R2A
bits 12:9) and that the shunt resistive portion of the loop
5 SW
filter be segmented into two parts, where one resistor
(R2A) is 1/4 of the total resistance, and the other resistor R2B
(R2B) is 3/4 of the total resistance. The larger resistor
(R2B) should be connected from SW to Ground, and the
smaller resistor (R2A) from SW to the loop filter capacitor
(see Figure 4). When CDM = 01 (register 3, bits 16:15), 20 TUNE
fast-lock is active after the VAS has completed. During
fast-lock, the charge pump is increased to CP = 1111 and
the shunt loop filter resistance is set to 1/4 of the total
resistance by changing pin SW from high impedance to
ground. Fast-lock deactivates after a timeout set by the
user. This timeout is loop filter dependent, and is set by: Figure 4. Fast Lock Filter Topology
tFAST-LOCK = M x CDIV/fPFD
where M is the modulus setting and CDIV is the clock To prevent undesired frequencies from being output while
divider setting. The user must determine the CDIV setting acquiring lock, the output power can be disabled when
based on their loop filter time constant. The SW pin can the PLL is unlocked by using MTLD (register 4, bit 10). A
be left open/ no connect when fast lock mode is not used. logic 1 will disable the outputs when the digital lock detect
is logic low. When acquiring lock the output can over-
RFOUTA± and RFOUTB± shoot and pass through the desired frequency. In some
The device has dual differential open-collector RF out- circumstances, the digital lock detect will flicker high dur-
puts that require an external RF choke or a 50Ω resistor ing these periods. To prevent this from happening, a timer
to supply for each output. Each differential output can can be used to delay the output from enabling after losing
be independently enabled or disabled by setting bits lock. Enable MUTEDEL (register 3, bit 17) with MTLD
RFA_EN (register 4, bit 5) and RFB_EN (register 4, bit 8). enabled to use this function. The delay for enabling the
Both outputs are also controlled by applying a logic-high output is set by:
(enabled) or logic-low (disabled) to pin RFOUT_EN. Delay = CDIV x M/fPFD
The output power of each output can be individually con- where CDIV (register 3, bits 14:3) is the clock divider,
trolled with APWR (register 4, bits 4:3) for RFOUTA and M (register 1, bits 14:3) is the variable modulus for the
BPWR (register 4, bits 7:6) for RFOUTB. The available dif- fractional N modulator, and fPFD is the phase detector
ferential output power settings are from -4dBm to +5dBm, frequency.
in 3dB steps with 50Ω pullup to supply. The available
single-ended output power ranges from -4dBm to +5dBm Voltage-Controlled Oscillator
in 3dB steps with a RF choke to supply. Across the entire The fundamental VCO frequency of the device guarantees
frequency range different pullup elements (L or R) are gap-free coverage from 3.0GHz to 6.0GHz using four
required for optimal output power. If single-ended output individual VCO core blocks with 16 sub-bands within each
is used, the unused output should be supplied and termi- block. Connect the output of the loop filter to the TUNE
nated in the same manner as the corresponding load. If a input. The TUNE input is used to control the VCO.
differential output is unused then those RFOUT pins should
be directly connected to VCC_RF (pin 16).

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Tune ADC If VAS_SHDN = 1, then the VCO can be manually

A 7-bit ADC is used to read back the VCO tuning voltage. selected by bits VCO (register 3, bits 31:26). Refer to
The ADC value can be read back through register 6, bits Applications Information for detailed implementation of
22:16. To digitize the tuning voltage, do the following: VCO manual selection.
1) Set bits CDIV (register 3, bits 14:3) = fPFD/100kHz to Phase Adjustment
set the clock speed for the ADC. After achieving lock, the phase of the single MAX2871
2) Set bits ADCM (register 5, bits 5:3) = 100 to enable device’s RF output can be changed in increments of P
the ADC to read the TUNE pin voltage. (register 1, bits 26:15) /M (register 1, bits 14:3) x 360°.
3) Set bit ADCS (register 5, bit 6) = 1 to start the ADC Also, multiple MAX2871 devices’ RF Outputs can be
conversion process. phase synchronized with a single reference input. See
Applications Information for detailed implementation.
4) Wait 100µs for the conversion process to finalize.
5) Read back register 6. The ADC value is located in bits Low-Spur Mode
22:16. The device offers three modes for the sigma-delta modu-
6) Reset bits ADCM = 0 and ADCS = 0. lator. Low-noise mode offers lower in-band noise at the
expense of spurs. The spurs can be reduced by setting
The voltage on the TUNE pin can be calculated as:
SDN = 10 (register 2, bits 30:29) or SDN = 11 for different
V = 0.315 + ADC x 0.0165 modes of dithering. The user can determine which mode
works best for their application.
VCO Autoselect (VAS) State Machine Temperature Sensor
An internal VCO autoselect state machine is initiated The device is equipped with an on-chip temperature sen-
when register 0 is programmed to automatically select sor and 7-bit ADC.
the correct VCO if bit VAS_SHDN = 0 (register 3, bit 25).
To read the digitized output of the temperature sensor:
The state machine clock, fBS, must be set to 50kHz. This
is set by the BS bits (register 4, bits 25:24, 19:12). The 1) Set bits CDIV (register 3, bits 14:3) = fPFD/100kHz to
formula for setting BS is: set the clock speed for the ADC.

BS = fPFD/50kHz 2) Set bits ADCM (register 5, bits 5:3) = 001 to enable the
ADC to read the temperature.
where fPFD is the phase-detector frequency. The BS value
should be rounded to the nearest integer. If the calcu- 3) Set bit ADCS (register 5, bit 6) = 1 to start the ADC
lated BS is higher than 1023, then set BS = 1023. If fPFD conversion process.
is lower than 50kHz, then set BS = 1. The time needed to 4) Wait 100µs for the conversion process to finalize.
select the correct VCO is 10/fBS. 5) Read back register 6. The ADC value is located in bits
The VAS_TEMP bit (register 3, bit 24) can be used to 22:16.
select the best VCO for the given ambient temperature 6) Reset bits ADCM=0 and ADCS=0.
to ensure that the VCO will not drift out of lock if the tem-
The approximate ambient temperature can be converted
perature changes within -40°C to +85°C. Bits RFA_EN
as:
(register 4, bit 5) and RFB_EN (register 4, bit 8) must be
0, and bits 30:29 of register 5 must be set to 11 during t = 95 – 1.14 x ADC
VCO acquisition. Setting VAS_TEMP = 1 will increase the This formula is most accurate when the VCO is enabled
time needed to achieve lock from 10/fBS to approximately and RFOUTA is enabled at full output power. The tem-
100ms. perature can vary based on output power and if one or
both outputs are enabled.

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Register and Bit Descriptions be written with default values. In low-power mode, the
The operating mode of the device is controlled by six on- register values are retained. Upon power-up, the registers
chip registers. should be programmed twice with at least a 20ms pause
between writes. The first write ensures that the device is
Defaults are not guaranteed upon power-up and are enabled, and the second write starts the VCO selection
provided for reference only. All reserved bits should only process.

Table 3. Register 0 (Address: 000, Default: 007D0000HEX)

BIT LOCATION BIT ID NAME DEFINITION
0 = Enables the fractional-N mode
Int-N or Frac-N
31 INT 1 = Enables the integer-N mode
Mode Control
The LDF bit must also be set to the appropriate mode.

Sets integer part (N-divider) of the feedback divider factor. All integer
Integer Division values from 16 to 65,535 are allowed for integer mode. Integer values
30:15 N[15:0]
Value from 0 to 15 are not allowed. Integer values from 19 to 4091 are allowed
for fractional mode.

Sets fractional value:

000000000000 = 0 (see F0I bit description)
Fractional 000000000001 = 1
14:3 FRAC[11:0]
Division Value ----
111111111110 = 4094
111111111111 = 4095

2:0 ADDR[2:0] Address Bits Control Register address bits, 000

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Table 4. Register 1 (Address: 001, Default: 2000FFF9HEX)

BIT LOCATION BIT ID NAME DEFINITION
31 Reserved Reserved Reserved. Program to 0.

Sets CP linearity mode.

00 = Disables the CP linearity mode (integer-N mode)
30:29 CPL[1:0] CP Linearity 01 = CP linearity 10% mode (frac-N mode)
10 = CP linearity 20% mode (frac-N mode)
11 = CP linearity 30% mode (frac-N mode)

Sets charge-pump test modes.

Charge Pump 00 = Normal mode
28:27 CPT[1:0] Test 01 = Long Reset mode
10 = Force CP into source mode
11 = Force CP into sink mode

Sets phase value. See the Phase Adjustment section.

000000000000 = 0
26:15 P[11:0] Phase Value 000000000001 = 1 (recommended)
-----
111111111111 = 4095

Fractional modulus value used to program fVCO. See the Int, Frac, Mod
and R Counter Relationship section. Double buffered by register 0.
000000000000 = Not Valid
Modulus Value
14:3 M[11:0] 000000000001 = Not Valid
(M)
000000000010 = 2
-----
111111111111 = 4095

2:0 ADDR[2:0] Address Bits Control Register address bits, 001

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Table 5. Register 2 (Address: 010, Default: 00004042HEX)

BIT LOCATION BIT ID NAME DEFINITION
Lock-detect speed adjustment.
Lock-Detect
31 LDS 0 = fPFD ≤ 32MHz
Speed
1 = fPFD > 32MHz

Sets noise mode (see the Low-Spur Mode section.)

Frac-N Sigma 00 = Low-noise mode
30:29 SDN[1:0] Delta Noise 01 = Reserved
Mode 10 = Low-spur mode 1
11 = Low-spur mode 2

Sets MUX pin configuration (MSB bit located register 05).

0000 = Three-state output
0001 = D_VDD
0010 = D_GND
0011 = R-divider output
MUX 0100 = N-divider output/2
28:26 MUX[2:0]
Configuration 0101 = Analog lock detect
0110 = Digital lock detect
0111 = Sync Input
1000 : 1011 = Reserved
1100 = Read SPI registers 06
1101 : 1111= Reserved

Sets reference doubler mode.

Reference
25 DBR 0 = Disable reference doubler
Doubler Mode
1 = Enable reference doubler
Sets reference divide-by-2 mode.
Reference Div2
24 RDIV2 0 = Disable reference divide-by-2
Mode
1 = Enable reference divide-by-2

Sets reference divide value (R). Double buffered by register 0.

Reference 0000000000 = 0 (unused)
23:14 R[9:0] 0000000001 = 1
Divider Mode
-----
1111111111 = 1023

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Table 5. Register 2 (Address: 010, Default: 00004042HEX) (continued)

BIT LOCATION BIT ID NAME DEFINITION

Sets double buffer mode.

13 REG4DB Double Buffer 0 = Disabled
1 = Enabled

Sets charge-pump current in mA (RSET = 5.1kΩ). Double buffered by

Charge-Pump
12:9 CP[3:0] register 0.
Current
ICP = 1.63/RSET × (1+CP[3:0])

Lock-Detect Sets lock-detect function.

8 LDF 0 = Frac-N lock detect
Function
1 = Int-N lock detect

Lock-Detect Sets lock-detect precision.

7 LDP 0 = 10ns
Precision
1 = 6ns

Phase Detector Sets phase detector polarity.

6 PDP 0 = Negative
Polarity
1 = Positive (default)

Shutdown Sets power-down mode.

5 SHDN 0 = Normal mode
Mode
1 = Device shutdown
Charge Pump
Output High- Sets charge-pump output high-impedance mode.
4 TRI 0 = Disabled
Impedance
Mode 1 = Enabled

Sets counter reset mode.

3 RST Counter Reset 0 = Normal operation
1 = R and N counters reset
2:0 ADDR[2:0] Address Bits Control Register address bits, 010

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Table 6. Register 3 (Address: 011, Default: 0000000BHEX)

BIT LOCATION BIT ID NAME DEFINITION
Manual selection of VCO and VCO sub-band when VAS is disabled.
000000 = VCO0
31:26 VCO[5:0] VCO
….
111111 = VCO63

Sets VAS shutdown mode.

25 VAS_SHDN VAS_SHDN 0 = VAS enabled
1 = VAS disabled
Sets VAS response to temperature drift.
24 VAS_TEMP VAS_TEMP 0 = VAS temperature compensation disabled
1 = VAS temperature compensation enabled
23:19 Reserved Reserved Reserved.

Cycle Slip Mode

Cycle Slip
18 CSM 0 = Disable Cycle Slip Reduction
Mode
1 = Enable Cycle Slip Reduction

Mute Delay
Mute Delay
17 MUTEDEL 0 = Do not delay LD to MTLD function to prevent flickering
Mode
1= Delay LD to MTLD function to prevent flickering

Sets clock divider mode.

00 = Mute until Lock Delay
Clock Divider
16:15 CDM[1:0] 01 = Fast-lock enabled
Mode
10 = Phase Adjustment mode
11 = Reserved

Sets 12-bit clock divider value.

000000000000 = Unused
Clock Divider 000000000001 = 1
14:3 CDIV[11:0]
Value 000000000010 = 2
-----
111111111111 = 4095

2:0 ADDR[2:0] Address Bits Control Register address bits, 011

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Table 7. Register 4 (Address: 100, Default: 6180B23CHEX)

BIT LOCATION BIT ID NAME DEFINITION
31:29 Reserved Reserved Reserved. Program to 011.
Sets Shutdown VCO LDO mode.
Shutdown VCO
28 SDLDO 0 = Enables LDO
LDO
1 = Disables LDO
Sets Shutdown VCO Divider mode.
Shutdown VCO
27 SDDIV 0 = Enables VCO Divider
Divider
1 = Disables VCO Divider
Sets Shutdown Reference input mode.
Shutdown
26 SDREF 0 = Enables Reference Input
Reference Input
1 = Disables Reference Input
25:24 BS[9:8] Band-Select MSBs Sets Band-Select clock divider MSBs. See bits[19:12].
Sets VCO to N counter feedback mode.
VCO Feedback
23 FB 0 = Divided
Mode
1 = Fundamental

Sets RFOUT_ output divider mode. Double buffered by register 0 when

REG4DB = 1.
000 = Divide by 1, if 3000MHz ≤ fRFOUTA ≤ 6000MHz
001 = Divide by 2, if 1500MHz ≤ fRFOUTA < 3000MHz
RFOUT_ Output 010 = Divide by 4, if 750MHz ≤ fRFOUTA < 1500MHz
22:20 DIVA[2:0] 011 = Divide by 8, if 375MHz ≤ fRFOUTA < 750MHz
Divider Mode
100 = Divide by 16, if 187.5MHz ≤ fRFOUTA < 375MHz
101 = Divide by 32, if 93.75MHz ≤ fRFOUTA < 187.5MHz
110 = Divide by 64, if 46.875MHz ≤ fRFOUTA < 93.75MHz
111 = Divide by 128, if 23.5MHz ≤ fRFOUTA< 46.875MHz

Sets band select clock divider value. MSB are located in bits [25:24].
0000000000 = Reserved
0000000001 =1
19:12 BS[7:0] Band Select
0000000010 = 2
----
1111111111 = 1023
Sets VCO Shutdown mode.
11 SDVCO VCO Shutdown 0 = Enables VCO
1 = Disables VCO
Sets RFOUT Mute until Lock Detect Mode
RFOUT Mute until
10 MTLD 0 = Disables RFOUT Mute until Lock Detect Mode
Lock Detect
1 = Enables RFOUT Mute until Lock Detect Mode
Sets RFOUTB output path select.
RFOUTB Output
9 BDIV 0 = VCO divided output
Path Select
1 = VCO fundamental frequency
Sets RFOUTB output mode.
RFOUTB Output
8 RFB_EN 0 = Disabled
Mode
1 = Enabled
Sets RFOUTB single-ended output power. See the RFOUTA± and
RFOUTB± section.
RFOUTB Output 00 = -4dBm
7:6 BPWR[1:0]
Power 01 = -1dBm
10 = +2dBm
11 = +5dBm

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Table 7. Register 4 (Address: 100, Default: 6180B23CHEX) (continued)

BIT LOCATION BIT ID NAME DEFINITION

Sets RFOUTA output mode.

RFOUTA Output
5 RFA_EN 0 = Disabled
Mode
1 = Enabled
Sets RFOUTA single-ended output power. See the RFOUTA± and
RFOUTB± section.
RFOUTA Output 00 = -4dBm
4:3 APWR[1:0]
Power 01 = -1dBm
10 = +2dBm
11 = +5dBm
2:0 C[2:0] Register Address Control Register address bits, 100

Table 8. Register 5 (Address: 101, Default: 00400005HEX)

BIT LOCATION BIT ID NAME DEFINITION
31 Reserved Reserved Reserved. Program to 0.

VCO Autoselect Delay.

30:29 VAS_DLY VAS_DLY Program to 11 when VAS_TEMP=1
Program to 00 when VAS_TEMP=0
28:26 Reserved Reserved Reserved. Program to 000.
Sets Shutdown PLL mode.
25 SDPLL Shutdown PLL 0 = Enables PLL
1 = Disables PLL

Sets integer mode for F = 0.

24 F01 F01 0 = If F[11:0] = 0, then fractional-N mode is set
1 = If F[11:0] = 0, then integer-N mode is auto set
Sets lock-detect pin function.
00 = Low
Lock-Detect Pin
23:22 LD[1:0] 01 = Digital lock detect
Function
10 = Analog lock detect
11 = High
21:19 Reserved Reserved Reserved. Program to 000.
18 MUX[3] MUX MSB Sets mode at MUX pin (see register 2 [28:26])
17:7 Reserved Reserved Reserved. Program to 00000000000.

Sets ADC Start mode.

6 ADCS ADC Start 0 = ADC normal operation
1 = Start ADC conversion process
Sets ADC mode.
000 = Disabled
001 = Temperature sensor
010 = Reserved
5:3 ADCM[2:0] ADC Mode 011 = Reserved
100 = Tune pin
101 = Reserved
110 = Reserved
111 = Reserved
2:0 ADDR[2:0] Register Address Control Register address bits, 101

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Table 9. Register 6 (Address: 110, Read-Only Register)

BIT LOCATION BIT ID NAME DEFINITION

Die ID.
31:28 DIE[3:0] Die ID 0110 = MAX2870
0111 = MAX2871

27:24 Reserved Reserved Reserved.

Power-On-Reset
0 = Power has not been cycled since last read
23 POR Power On Reset
1 = Power has not been cycled since last read. All registers have been
reset to default values.
22:16 ADC[6:0] ADC Code ADC Code.
Determines ADC code validity.
15 ADCV ADC Valid 0 = Invalid ADC code
1 = Valid ADC code
14:10 Reserved Reserved Reserved.
Determines if VAS is Active.
9 VASA VAS Active 0 = VCO Autoselect complete
1 = VCO Autoselect searching for correct VCO
8:3 V[5:0] Current VCO Current VCO.
2:0 ADDR[2:0] Register Address Control Register address bits, 110

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Typical Application Circuit

VCC_RF

NOISE_FILT
GND_TUNE

GND_VCO
BIAS_FILT

VCC_VCO
TUNE
RSET
REG

VCC_RF
24 23 22 21 20 19 18 17

LD VCC_RF
TO GPIO 25 16

RFOUT_EN RFOUTB_N
FROM GPIO 26 15
RFOUTB

GND_DIG RFOUTB_P
VCC_DIG 27 14

VCC_DIG RFOUTA_N
28 13
MAX2871 RFOUTA

REF_IN RFOUTA_P
29 12

MUX GND_RF
30 11

VCC_PLL
GND_SD VCC_PLL
31 EP 10
VCC_DIG
VDD_SD GND_PLL
32 9
VCC_RF
1 2 3 4 5 6 7 8
CLK

DATA

LE

CE

SW

VCC_CP

CP_OUT

GND_CP

VCC_PLL

R3
FROM
GPIO
C3
SPI C1 C2
INTERFACE

FOR BEST PERFORMANCE GENERATE

THREE SUPPLIES USING SEPARATE LDOS R2A
VCC_RF
VCC_DIG
VCC_PLL

R2B

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Applications Information
REFERENCE REF_IN1
VCO Manual Selection Operation
VCO manual selection operation (VAS_SHDN = 1) allows
shorter lock time, typically 200µS saving. It is also required SYNC PULSE MUX 1
that multiple MAX2871 devices phase synchronization.
MAX2871
The following steps need to be implemented:
1. Building VCO lookup table (Required ONLY once after
each power cycle) REF_IN2

● Set VAS_SHDN = 0, follow “VCO Autoselect (VAS)

State Machine” section to set BS bits properly
MUX 2
● Write proper N and Frac value to Reg 0, triggering
MAX2871 to first desired frequency point, i.e freq1. MAX2871
Wait for PLL to lock
● Read back register 6[8:3] from MUX pin and save REF_IN3
the value to memory as vco1, see detail at 4-Wire
Serial Interface section about register readback
● Repeat above steps for all desired frequency points MUX 3

2. VCO manual selection normal operation MAX2871

● Set VAS_SHDN = 1
● Based on the VCO lookup table obtained from
step 1, write desired frequency’s corresponding
VCO value to reg3[31:26]
● Write proper N and Frac value to reg0, triggering
Figure 5. Phase Synchronization Application Setup
MAX2871 to desired frequency
Phase synchronization of multiple
MAX2871 devices
REF 1
Multiple MAX2871 devices can be phase synchronized.
This feature works in the frequency range of 187.5MHz to
6000 MHz and in Fractional-N mode ONLY.
REF 2
Proper hardware/register guidelines MUST be followed:
Hardware Design Guidelines
1. Connect all MAX2871 to same reference source. REF 3
Refer, Figure 5
2. Connect MUX pins of all MAX2871 to 4 wire interface’s
readback
DELAY 12 AND DELAY 13 CAN
3. Connect MUX pins of all MAX2871 to same sync pulse NOT BE RANDOM
source DELAY 12
4. The relative delay of reference signal at each
MAX2871s reference pin can NOT be random. Refer DELAY 13
Figure 6.
Figure 6. Reference Signal Relative Delay

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

5. At each MAX2871 REF_IN pin and MUX pin, the sync

rising edge can NOT occur inside the setup hold time
window around reference signal rising edge. Refer to
Figure 7. REF CLOCK AT REF_IN PIN
tSETUP = (4/N) x tPFD + 2.6nS
tHOLD = (4/N) x tPFD
where: N is MAX2871’s N counter ratio, reg0[30:15]
tPFD = 1/(PFD frequency)
SYNC PULSE AT MUX PIN
Register Design Guidelines
1. The reference doubler and reference divide-by-2 must
be disabled.
DBR (reg2[25]) = 0
SYNC RISING EDGE NOT
RDIV2 (reg2[24]) = 0 INSIDE SETUP/HOLD TIME
2. R divider ratio must be set to 1 WINDOW

R (register 2, bits 23:14) = 1.

3. Set MAX2871 in Fractional mode
INT (reg0[31]) = 0
F01 (reg5[24]) = 0
HOLD TIME
4. Output divider has to be inside the PLL loop
FBMUX (reg4[23]) =0.
5. If OUTPUT B is used, it has to be set to “VCO divided
SETUP TIME
output” mode
BDIV (reg4[ 9]) = 0 Figure 7. Setup Time/ Hold Time Window
6. Sigma delta modulator has to be in low noise mode
SDN (reg2[30:29]) = 00. 5. Force the voltage on the MUX pins to VIH. This resets
7. N counter ratio has to be in allowable range the MAX2871s so they are synchronous. The MUX
19 < N (reg0[30:15]) < 4091 sync pulse rising edge cannot occur inside setup/hold
8. DIVA (register 4, bits 22:20) ≤ 100_binary (less than or time window around the reference signal rising edge.
equal to divide-by-16, which limits the minimum output 6. (Optional) If the user plans to use MUX pin’s other
frequency to 187.5MHz) function (i.e., register readback, follow steps below):
9. Set VAS_SHDN = 1, for normal operation a. Force the voltage on the MUX pins back to VIL
b. Set MUX (reg5[18] and reg2[28:26]) = 0000
Steps to Execute Phase Sync (HiZ mode)
1. Follow “VCO Manual Selection Operation” section to c. Remove the forced voltage from the MUX pin
build VCO lookup table for each MAX2871 devices in d. Now the MUX pin is ready for other functions
the system, only required once after each power cycle 7. Set ONLY P(reg1[26:15]) for the desired amount of
2. Force the voltage on the MUX pin to VIL phase shift for each part.
3. Set MUX (reg5[18] & reg2[28:26]) = 0111 which allows 8. Set CDM (reg3[16:15]) = 10
MUX to take external ‘SYNC INPUT’ 9. Reset CDM (reg3[16:15]) = 00. All MAX2871s are
4. Program the MAX2871s for the desired frequency and frequency synchronized with phase difference defined
allow them to lock. Ensure to use “VCO Manual selec- in step 7. The initial phase sync is completed
tion Operation” 10.Repeat step 2-10 for new frequency points

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Layout Issues Ordering Information

The MAX2871 EV kit can be used as a starting point for
PART TEMP RANGE PIN-PACKAGE
layout. For best performance, take into consideration
grounding and routing of RF, baseband, and power sup- MAX2871ETJ+ -40°C to +85°C 32 TQFN-EP*
ply PCB proper line. Make connections from vias to the +Denotes lead(Pb)-free/RoHS-compliant package.
ground plane as short as possible. On the high imped- *EP = Exposed pad.
ance ports, keep traces short to minimize shunt capaci-
tance. EV kit Gerber files can be requested/ downloaded
at www.maximintegrated.com.
Package Information
Power-Supply Layout For the latest package outline information and land patterns
To minimize coupling between different sections of the (footprints), go to www.maximintegrated.com/packages. Note
IC, a star power-supply routing configuration with a large that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
decoupling capacitor at a central VCC_ node is recom-
the drawing pertains to the package regardless of RoHS status.
mended. The VCC_ traces branch out from this node,
each going to a separate VCC_ node in the circuit. Place PACKAGE PACKAGE OUTLINE LAND
a bypass capacitor as close as possible to each supply TYPE CODE NO. PATTERN NO.
pin This arrangement provides local decoupling at each
32 TQFN-EP T3255+5 21-0140 90-0013
VCC_ pin. Use at least one via per bypass capacitor for
a low-inductance ground connection. Do not share the
capacitor ground vias with any other branch.

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MAX2871 23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 9/14 Initial release —
1 4/15 Updated Phase Adjustment section and other minor updates to data sheet 1, 13, 17, 19, 24
Updated Phase Adjustment section, Register 6 readout timing, other 3, 5, 11–13, 15, 18,
2 5/16
general updates 19, 21, 22, 24,
Added VCO Manual Selection and Phase Sync sections, as well as other 1–4, 11, 13–19, 21,
3 4/17
general updates/corrections 22, 24, 25, 27
4 6/20 Updated Detailed Description section 13

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2020 Maxim Integrated Products, Inc. │ 30