STM32H562xx and STM32H563xx

Arm® Cortex®-M33 32-bit MCU + TrustZone® + FPU, 375 DMIPS,

250 MHz, 2-Mbyte flash, 640-Kbyte RAM, math accelerators
Datasheet - production data

Features
Includes ST state-of-the-art patented
technology LQFP64 (10 x 10 mm) VFQFPN68 (8 x 8 mm)
LQFP100 14 x 14 mm)
Core LQFP144 (20 x 20 mm)
UFBGA
® ® ® LQFP176 (24 x 24 mm)
• Arm Cortex -M33 CPU with TrustZone ,
FPU, frequency up to 250 MHz, MPU,
375 DMIPS (Dhrystone 2.1) UFBGA169 (7 x 7 mm)
UFBGA 176+25 (10 x 10 mm)
ART Accelerator WLCSP80 (3.50 X 3.27 mm)

• 8-Kbyte instruction cache allowing

0-wait-state execution from flash and external Clock management
memories
• Internal oscillators: 64 MHz HSI,
• 4-Kbyte data cache for external memories 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI

Benchmarks • External oscillators: 4-50 MHz HSE,

32.768 kHz LSE
• 1.5 DMIPS/MHz (Drystone 2.1)
• 1023 CoreMark® (4.092 CoreMark®/MHz) General-purpose inputs/outputs
• Up to 140 fast I/Os with interrupt capability
Memories (most of them 5 V-tolerant)
• Up to 2 Mbytes of embedded flash memory • Up to ten I/Os with independent supply down to
with ECC, two banks read-while-write 1.08 V
• Up to 48-Kbyte per bank with high-cycling
capability (100 K cycles) for data flash Low-power consumption
• 2-Kbyte OTP (one-time programmable) • Sleep, Stop, and Standby modes
• 640 Kbytes of SRAM (64-Kbyte SRAM2 with • VBAT supply for RTC, 32 backup registers
ECC and 320-Kbyte SRAM3 with flexible ECC) (32-bit)
• 4 Kbytes of backup SRAM available in the
lowest power modes
Security
• Flexible external memory controller with up to • Arm® TrustZone® with Armv8-M mainline
16-bit data bus: SRAM, PSRAM, FRAM, security extension
SDRAM/LPSDR SDRAM, NOR/NAND • Up to eight configurable SAU regions
memories • TrustZone® aware and securable peripherals
• One Octo-SPI memory interface with support • Flexible life cycle scheme with secure debug
for serial PSRAM/NAND/NOR, hyper authentication
RAM/flash frame formats
• SFI (secure firmware installation)
• Two SD/SDIO/MMC interfaces
• Secure firmware upgrade support with TF-M

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This is information on a product in full production. www.st.com
 STM32H562xx and STM32H563xx

• HASH hardware accelerator • One I3C

• ECDSA signature verification • Up to 12 U(S)ARTs (ISO7816 interface, LIN,
• True random number generator, NIST IrDA, modem control) and one LPUART
SP800-90B compliant • Up to six SPIs, including three muxed in
• 96-bit unique ID full-duplex I2S audio class accuracy via
internal audio PLL or external clock, and up to
• Active tampers five additional SPIs from five USARTs when
configured in Synchronous mode (one
Two DMA controllers to offload the CPU additional SPI with OctoSPI)
• Two dual-port DMAs with FIFO • Two SAIs

Mathematical acceleration • Two FDCANs

• One 8- to 14-bit camera interface
• CORDIC for trigonometric functions
acceleration • One 16-bit parallel slave synchronous-
interface
• FMAC (filter mathematical accelerator)
• One HDMI-CEC
Reset and supply management • One Ethernet MAC interface with DMA
• 1.71 V to 3.6 V application supply and I/O controller
• POR, PDR, PVD, and BOR • One USB 2.0 full-speed host and device
• Embedded regulator (LDO) or SMPS step- • One USB Type-C®/USB Power Delivery r3.1
down converter regulator with configurable
scalable output to supply the digital circuitry Analog
• Two 12-bit ADCs with up to 5 Msps in 12-bit
Up to 24 timers
• One 12-bit DAC with two channels
• 18 16-bit timers (including six low-power • Digital temperature sensor
16-bit timers available in Stop mode)
• Two 32-bit timers with up to four IC/OC/PWM Debug
or pulse counters and quadrature (incremental)
• Authenticated debug and flexible device life
encoder input
cycle
• Two watchdogs
• Serial wire-debug (SWD), JTAG, Embedded
• Two SysTick timers Trace Macrocell™ (ETM)

Up to 34 communication interfaces ECOPACK2 compliant packages

• Up to four I2Cs Fm+ (SMBus/PMBus®)
Table 1. Device summary
Reference Part numbers
STM32H562AG, STM32H562AI, STM32H562IG, STM32H562II, STM32H562RG,
STM32H562xx
STM32H562RI, STM32H562VG, STM32H562VI, STM32H562ZG, STM32H562ZI
STM32H563AG, STM32H563AI, STM32H563IG, STM32H563II, STM32H563MI,
STM32H563xx STM32H563RG, STM32H563RI, STM32H563VG, STM32H563VI, STM32H563ZG,
STM32H563ZI

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Arm Cortex-M33 core with TrustZone and FPU . . . . . . . . . . . . . . . . . . . . 19
3.2 ART Accelerator (ICACHE and DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 Data cache (DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.1 FLASH security and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.2 FLASH privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.1 SRAMs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.2 SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Security overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7.1 STM32H562/H563xx boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9.2 Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10.3 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10.4 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10.5 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.11 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12.1 RCC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.13 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.14.1 GPIOs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.15 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.16 General purpose direct memory access controller (GPDMA) . . . . . . . . . 35
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37
3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 37
3.18 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 38
3.19 CORDIC coprocessor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.20 Filter math accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.21 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.21.1 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.21.2 FMC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.22 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.22.1 OCTOSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.23 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.24 Analog-to-digital converters (ADC1 and ADC2) . . . . . . . . . . . . . . . . . . . . 41
3.24.1 Analog temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.24.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.24.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.25 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.26 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.27 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.28 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 44
3.30 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.31 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.32 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.33 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.33.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.33.2 General-purpose timers
(TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . 47
3.33.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.33.4 Low-power timers
(LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6) . . . . . . . . . . . 47

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3.33.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.33.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.33.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.34 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 49
3.34.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.34.2 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.35 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.36 Improved inter-integrated circuit (I3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.37 Universal synchronous/asynchronous receiver transmitter
(USART/UART) and low-power universal asynchronous
receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.37.1 Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.37.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 55
3.38 Serial peripheral interface (SPI) / inter-integrated sound interfaces (I2S) 56
3.39 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.40 Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 59
3.41 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.42 USB full speed (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.43 USB Type-C/USB Power Delivery controller (UCPD) . . . . . . . . . . . . . . . 61
3.44 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 61
3.45 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.46 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.46.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.46.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4 Pinout, pin description, and alternate functions . . . . . . . . . . . . . . . . . 63

4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

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5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.3.4 Operating conditions at power-up/down . . . . . . . . . . . . . . . . . . . . . . . 133
5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 133
5.3.6 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 159
5.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.3.17 Extended interrupt and event controller input (EXTI) characteristics . . 175
5.3.18 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.3.19 Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.3.20 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
5.3.21 DCMI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
5.3.22 PSSI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
5.3.23 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.3.24 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
5.3.25 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 214
5.3.26 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 215
5.3.27 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.3.28 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.3.29 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
5.3.30 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
5.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

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5.3.32 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

5.3.33 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.2 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.3 VFQFPN68 package information (B029) . . . . . . . . . . . . . . . . . . . . . . . . 243
6.4 WLCSP80 package information (B0D4) . . . . . . . . . . . . . . . . . . . . . . . . . 245
6.5 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
6.6 LQFP144 package information (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
6.7 UFBGA169 package information (A0YV) . . . . . . . . . . . . . . . . . . . . . . . . 255
6.8 LQFP176 package information (1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.9 UFBGA(176+25) package information (A0E7) . . . . . . . . . . . . . . . . . . . . 262
6.10 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
6.10.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

DS14258 Rev 5 7/270

List of tables STM32H562xx and STM32H563xx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32H56xxx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. STM32H562/H563 boot mode when TrustZone is disabled (TZEN = 0xC3) . . . . . . . . . . . 24
Table 4. STM32H562/H563 boot mode when TrustZone is enabled (TZEN = 0xB4). . . . . . . . . . . . 25
Table 5. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 6. Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 7. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 8. I3C peripheral controller/target features versus MIPI v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 9. USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 10. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 11. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 12. SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 14. STM32H562xx and STM32H563xx pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 15. Alternate functions AF0 to AF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 16. Alternate functions AF8 to AF15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 17. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 18. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 19. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 21. Maximum allowed clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 22. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 23. Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 130
Table 24. Operating conditions at power-up/down (regulator ON) . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 26. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 27. Internal reference voltage calibration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory, 2-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 136
Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory, 1-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 137
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from SRAM with cache 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from SRAM with cache 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 32. Typical consumption in Run mode with CoreMark running
from flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 33. Typical consumption in Run mode with SecureMark running from
flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 34. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 140
Table 35. Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 36. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 141
Table 37. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 142
Table 38. Peripheral current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 39. Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 42. 4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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Table 43. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 44. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 45. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 46. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 47. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 48. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 49. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 50. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 51. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 52. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 53. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 54. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 55. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 56. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 57. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 58. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 59. Output voltage characteristics for all I/Os except PC13, PC14, PC15, and PI8 . . . . . . . . 163
Table 60. Output voltage characteristics for FT_c I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 61. Output voltage characteristics for PC13 and PI8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 62. Output voltage characteristics for PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 63. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 64. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 65. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF) . . . . . . . . . . . . . . . . . . . 171
Table 66. Output timing characteristics VDDIO2 1.2 V (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 67. Output timing characteristics for FT_c I/Os (PB13/PB14). . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 68. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 69. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 177
Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 177
Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 178
Table 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 179
Table 74. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 75. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 180
Table 76. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 77. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 182
Table 78. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 79. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 80. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 81. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 82. Switching characteristics for NAND flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 83. Switching characteristics for NAND flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 84. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 85. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 86. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 87. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 88. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 89. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 90. OCTOSPI characteristics in DTR mode (with DQS) / HyperBus . . . . . . . . . . . . . . . . . . . 197
Table 91. Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 92. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 93. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 94. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

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List of tables STM32H562xx and STM32H563xx

Table 95. 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 96. Minimum sampling time versus RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 97. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 98. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 99. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 100. Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 101. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 102. Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 103. VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 104. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 105. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 106. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 107. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 108. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 109. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 110. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 111. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 112. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 113. I3C open-drain measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 114. I3C push-pull measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 115. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 116. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 117. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 118. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 119. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 120. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 121. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 122. Dynamic characteristics: SD/MMC, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 123. Dynamic characteristics: eMMC, VDD = 1.71 to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 124. Dynamic characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 125. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 126. Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 127. Dynamic JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 128. Dynamic SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 129. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 130. VFQFPN68 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 131. WLCSP80 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 132. WLCSP80 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 133. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 134. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 135. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 136. UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 257
Table 137. LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 138. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 139. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 263
Table 140. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 141. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

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STM32H562xx and STM32H563xx List of figures

List of figures

Figure 1. STM32H562xx and STM32H563xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2. STM32H562xx and STM32H563xx power supply overview (with SMPS) . . . . . . . . . . . . . 29
Figure 3. STM32H562xx and STM32H563xx power supply overview (with LDO). . . . . . . . . . . . . . . 30
Figure 4. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 6. VFQFPN68 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 7. WLCSP80 SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 8. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 9. LQFP100 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 10. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 11. LQFP144 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 12. UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 13. UFBGA169 SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 14. LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 15. LQFP176 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 16. UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 17. UFBGA176+25 SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 18. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 19. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 20. Power supply scheme with SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 21. Power supply scheme with LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 22. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 23. SMPS efficiency versus load current in Run, Sleep, and Stop modes
with SVOS3 mode, TJ = 30 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 24. SMPS efficiency versus load current in Run, Sleep, and Stop modes
with SVOS3 mode, TJ = 130 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 25. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 30 °C. . . . . . . . . . . . 132
Figure 26. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 130 °C. . . . . . . . . . . 132
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 28. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 31. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 32. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 33. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 176
Figure 34. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 178
Figure 35. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 36. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 37. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 38. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 39. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 40. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 41. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 42. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 43. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 190
Figure 44. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 191
Figure 45. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 46. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

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12
List of figures STM32H562xx and STM32H563xx

Figure 47. OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 48. OCTOSPI timing diagram - DTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 49. OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 50. OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 51. OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 52. DCMI timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 53. PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 54. PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 55. ADC conversion timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 56. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 57. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 58. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 209
Figure 59. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 210
Figure 60. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 61. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 62. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 63. SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 64. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 65. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 66. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 67. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 68. USB timings - definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 69. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 70. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 71. SDIO high-speed/eMMC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 72. SD default speed timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 73. DDR mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 74. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 75. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 76. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 77. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 78. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 79. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 80. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 81. VFQFPN68 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 82. VFQFPN68 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 83. WLCSP80 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 84. WLCSP80 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 85. WLCSP80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 86. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 87. LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 88. LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 89. LQFP144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 90. UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 91. UFBGA169 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 92. LQFP176 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 93. LQFP176 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 94. UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 95. UFBGA(176+25) - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

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STM32H562xx and STM32H563xx Introduction

1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32H562xx and STM32H563xx microcontrollers.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32H562xx and STM32H563xx errata sheet.

For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33

Technical Reference Manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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13
Description STM32H562xx and STM32H563xx

2 Description

The STM32H562xx and STM32H563xx devices are high-performance microcontrollers of

the STM32H5 series, based on the high-performance Arm® Cortex®-M33 32-bit RISC core.
They operate at a frequency of up to 250 MHz.
The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports
all the Arm® single-precision data-processing instructions and all the data types. This core
implements a full set of DSP (digital signal processing) instructions and a memory protection
unit (MPU) that enhances the application security.
The devices embed high-speed memories (up to 2 Mbytes of dual bank flash memory and
640 Kbytes of SRAM), a flexible external memory controller (FMC) for devices with
packages of 100 pins and more, one OCTOSPI memory interface (at least one Quad-SPI
available on all packages), and an extensive range of enhanced I/Os and peripherals
connected to three APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix.
The devices offer security foundation compliant with the trusted-based security architecture
(TBSA) requirements from Arm®. They embed the features to implement a secure firmware
update. Besides these capabilities, the devices incorporate a secure firmware installation
that allows the customer to secure the provisioning of the code during its production. A
flexible life cycle is managed thanks to multiple levels of protection and secure debug
authentication. Firmware hardware isolation is supported thanks to securable peripherals,
memories, and I/Os, and to privilege configuration of peripherals and memories.
The devices feature several protection mechanisms for embedded flash memory and
SRAM: readout protection, write protection, secure, and hide protection areas.
Dedicated peripherals reinforce security: an HASH hardware accelerator, and a true random
number generator.
The devices offer active tamper detection and protection against transient and
environmental perturbation attacks, thanks to several internal monitoring, generating secret
data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications.
The devices offer two fast 12-bit ADCs, two DAC channels, an internal voltage reference
buffer, a low-power RTC, two 32-bit general-purpose timers, two 16-bit PWM timers
dedicated to motor control, eight 16-bit general-purpose timers, two 16-bit basic timers, and
six 16-bit low-power timers.
The devices also feature standard and advanced communication interfaces, namely: four
I2Cs, one I3C, six SPIs, three I2Ss, six USARTs, six UARTs and one low-power UART, two
SAIs, one digital camera interface (DCMI), up to two SDMMCs, up to two FDCANs, one
USB full-speed, one USB Type-C®/USB power delivery controller, an Ethernet interface
(available only on STM32H563xx).
The devices operate in the -40 to +85 °C (+130 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges, with a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes allow the design of low-power applications.
Independent power supplies are supported: an analog independent supply input for ADC,
DACs, a 3.3 V dedicated supply input for USB, and a dedicated supply input for some
GPIOs and SDMMC. A VBAT input is available to connect a backup battery, to preserve the
RTC functionality, and to backup 32 32-bit registers and a 4-Kbyte SRAM.

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STM32H562xx and STM32H563xx Description

The devices offer eight packages, from 64 to 176 pins.

All packages are available with LDO or SMPS supply options for the VCORE (except for
LQFP64 and VFQFPN68 packages, not available in SMPS, and WLCSP80, not available in
LDO).

Table 2. STM32H56xxx features and peripheral counts

STM32H563RI/G

STM32H562RI/G

STM32H563AI/G

STM32H562AI/G
STM32H563VI/G

STM32H562VI/G

STM32H563ZI/G

STM32H562ZI/G

STM32H563II/G

STM32H562II/G
STM32H563MI
Peripherals

Flash memory Up to 2 Mbytes

System 640 (256 + 64 + 320) Kbytes
SRAM
Backup 4 Kbytes
Flexible memory controller for Yes
No Yes(1) (2) Yes
external memories (FMC)
OCTOSPI 1
Advanced
2 (16 bits)
control
General
2 (32 bits) and 8 (16 bits)
purpose
Basic 2 (16 bits)
Timers Low power 6 (16 bits)
SysTick timer 2
Watchdog
timers
2
(independent,
window)

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18
Description STM32H562xx and STM32H563xx

Table 2. STM32H56xxx features and peripheral counts (continued)

STM32H563RI/G

STM32H562RI/G

STM32H563AI/G

STM32H562AI/G
STM32H563VI/G

STM32H562VI/G

STM32H563ZI/G

STM32H562ZI/G

STM32H563II/G

STM32H562II/G
STM32H563MI
Peripherals

SPI / I2S 4/3 5/3 6/3

I2C 4
I3C 1(3)
USART 5 6
UART 5 6
LPUART 1
SAI 2

Communication FDCAN 2 1 2 1 2 1 2 1 2 1
interfaces USB Yes
UCPD Yes
SDMMC 1 2 1 2 1 2 1 2 1
Digital camera
interface Yes
(DCMI)/PSSI(4)
Ethernet Yes/ Yes/ Yes/ Yes/ Yes/
No No/Yes No No No No
(legacy/SMPS) No No No Yes Yes
HDMI-CEC Yes
CORDIC co-processor Yes
Filter mathematical accelerator
Yes
(FMAC)
Real time clock (RTC) Yes
Tamper pins (legacy/SMPS) 5/NA NA/5 8/8
(5)
Active tampers (legacy/SMPS) 4/NA NA/4 7/7
True random number generator Yes
HASH (SHA-512) Yes
PKA
Yes
(ECDSA signature verification)
80 80 112 112 136 136 140(7) 140
GPIOs (legacy/SMPS) 53(6)/NA NA/57 (7)
/78 /NA /110 /NA /134 /eNA /139
7 7 8 8
Wake-up pins (legacy/SMPS) 6/NA(8) NA/6 7/7 7/7 8/8 8/8
/NA /NA /NA /NA
Number of I/Os down to 1.08 V 0 10 10 10 10
0/NA NA/0 0/0 10/7 10/7
(legacy/SMPS) /NA /10 /NA /NA /NA

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STM32H562xx and STM32H563xx Description

Table 2. STM32H56xxx features and peripheral counts (continued)

STM32H563RI/G

STM32H562RI/G

STM32H563AI/G

STM32H562AI/G
STM32H563VI/G

STM32H562VI/G

STM32H563ZI/G

STM32H562ZI/G

STM32H563II/G

STM32H562II/G
STM32H563MI
Peripherals

12-bit ADC 2

ADC Number of
16 16 20 20 20 20/ 20 20/
channels 16/NA NA / 16
/14 /NA /18 /NA /20 NA /20 NA
(legacy/SMPS)
12-bit DAC
1
controller
DAC Number of
12-bit D to A 2
converters
Internal voltage reference buffer No Yes
Maximum CPU frequency 250 MHz
Operating voltage 1.71 to 3.6 V
Ambient -40 to 85 or 105 °C / -40 to 125 °C
Operating
temperature Voltage range VOS0 (up to 250 MHz): -40 to 105 °C
Junction
Voltage range VOS1 (up to 200 MHz): -40 to 130 °C
LQFP64 LQFP176
Package WLCSP80 LQFP100 LQFP144 UFBGA169
VFQFPN68 UFBGA176
1. 8-bit to interface LCD controller.
2. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 chip select.
3. Shares the I/Os with I2C4.
4. DCMI and PSSI cannot be used at the same time, as they share the same circuitry.
5. Active tampers in output sharing mode (one output shared by all inputs).
6. 49 for LQFP64.
7. 136 for LQFP176.
8. 5 for VFQFPN68.

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18
Description STM32H562xx and STM32H563xx

Figure 1. STM32H562xx and STM32H563xx block diagram

CLK, NE[4:1], NL, NBL[1:0],
NJTRST, JTDI, JTCK/SWCLK, JTAG/ SW MPU A[25:0], D[15:0], NOE,
JTMS/SWDIO, JTDO NWE, NWAIT, NCE, INT,
ETM NVIC SDCLK,SDCLKE[1:0],
Flexible memory controller (FMC): SDNE[1:0], SDNWE,

(8 Kbytes)
TRACECLK, SDRAM, SRAM, PSRAM, NOR flash, FRAM, NAND flash

ICACHE
NRAS, NCAS, as AF
TRACED[3:0] Arm Cortex-M33
250 MHz IO[7:0], CLK, NCLK,
C-BUS OCTOSPI1 memory interface NCS. DQS as AF
TrustZone FPU

S-BUS

(4 Kbytes)
DCACHE

AHB bus-matrix
Flash memory RNG
(up to 2 Mbytes)
HASH
D[7:0], D[3:1]dir

FIFO
CMD, CMDdir,CK, CKin SDMMC1 SRAM1 (256 Kbytes)
VDDA
D0dir, D2dir DAC1_OUT1
SRAM2 (64 Kbytes)

FIFO
ITF DAC1
SDMMC2
SRAM3 (320 Kbytes) DAC1_OUT2
FIFO
MAC ETHERNET
DCMI/PSSI D[15:0], CK, CMD as AF

AHB2 250 MHz

SRAM
4 KB

GPDMA1

VDD
VDD Power management
VDD
GPDMA2
Voltage regulator LDO or VDD = 1.71 to 3.6 V
HSI48 SMPS 3.3 to 1.2 V VSS

HS64 VDD
Reset Supply supervision
CSI BOR
VBAT Int
VDDIO, VDDUSB, VDDA,
LSI PVD, PVM VSSA, VDD, VSS, NRST
PA[15:0] GPIO port A BKPSRAM
(4 Kbytes) VDD
PB[15:0] GPIO port B PLL 1, 2, 3
AHB1 250 MHz

AHB3 250 MHz

XTAL OSC OSC_IN
PC[15:0] GPIO port C
4- 50 MHz OSC_OUT
PD[15:0] GPIO port D
IWDG
RAMCFG
PE[15:0] GPIO port E
Reset and clock control
PF[15:0] GPIO port F GTZC1 Standby
interface WKUPx (x=1 to 8)
PG[15:0] GPIO port G
CRC

FCLK

HCLKx

PCLKx
PH[15:0] GPIO port H TIM2 32-bit 4 channels, ETR as AF

PI[7:0] GPIO port I CORDIC TIM3 16-bit 4 channels, ETR as AF

16 AF EXT IT. WKP
FMAC TIM4 16-bit 4 channels, ETR as AF
VDDA CRS
20xIN ADC1 ITF SRAM
TIM5 32-bit 4 channels, ETR as AF
ADC2 512 B EXTI

3 compl. channels smcard RX, TX, CK, CTS,

(TIM1_CH[1:3]N), AHB/APB2 AHB/APB1 USART2 irDA RTS_DE as AF
TIM1/PWM 16-bit
6 channels (TIM1_CH[1:4]), smcard RX, TX, CK, CTS,

APB1 250 MHz (max)

ETR, BKIN, BKIN2 as AF USART3 irDA RTS_DE as AF

3 compl. channels RX, TX, CTS,

UART4
(TIM1_CH[1:3]N), RTS_DE as AF
TIM8/PWM 16-bit
6 channels (TIM1_CH[1:4]), RX, TX, CTS,
ETR, BKIN, BKIN2 as AF UART5
RTS_DE as AF

2 channels, TIM15 16-bit smcard RX, TX, CK, CTS,

APB2 250 MHz

1 compl. channel, BKIN as AF USART6 irDA RTS_DE as AF

1 channel, MOSI, MISO, SCK,

TIM16 16-bit SPI2/I2S2
1 compl. channel, BKIN as AF NSS as AF
MOSI, MISO, SCK,
1 channel, TIM17 16-bit SPI3/I2S3
NSS as AF
1 compl. channel, BKIN as AF
smcard DTS I2C1/SMBUS SCL, SDA, SMBA as AF
RX, TX, CK,CTS, USART1
RTS_DE as AF irDA
WWDG I2C2/SMBUS SCL, SDA, SMBA as AF
MOSI, MISO, SCK, SPI1/I2S1
NSS as AF
IWDG
MOSI, MISO, SCK, FDCAN1 TX, RX as AF
FIFO

SPI4
NSS as AF
FDCAN2 TX, RX as AF
TIM6 16-bit
MOSI, MISO, SCK, SPI6
NSS as AF CC1, DBCC1, CC2,
PHY

TIM7 16-bit UCPD1 DBCC2, FRSCC1,

MCLK_A, SD_A, FS_A,
SCK_A, MCLK_B, SD_B, FRSCC2 as AF
SAI1
FS_B, SCK_B as AF
IN1, IN2, CH1, CH2,
LPTIM2
AUDIOCLK as AF ETR as AF

MCLK_A, SD_A, FS_A, SAI2

TIM12 16-bit 2 channels, ETR as AF
SCK_A, MCLK_B, SD_B,
FS_B, SCK_B as AF VDDUSB
TIM13 16-bit 1 channel, ETR as AF
FIFO
PHY

DP USB FS
DM AHB/APB3 TIM14 16-bit 1 channel, ETR as AF

Temperature
AHB3 250 MHz

UART7 RX, TX, CTS, RTS_DE as AF

monitoring
VBAT
UART8 RX, TX, CTS, RTS_DE as AF
RTC_OUT1, RTC_OUT2, XTAL 32k
RTC_REFIN, RTC_TS
RTC
UART9 RX, TX, CTS, RTS_DE as AF
RTC_OUT[8:1],
TAMP
RTC_IN[8:1]
smcard RX, TX, CK, CTS,
VDDA USART10 irDA RTS_DE as AF
VREF+
VREF buffer
smcard RX, TX, CK, CTS,
APB3 250 MHz

USART11 irDA
RTS_DE as AF
IN1, IN2, CH1, CH2,
LPTIM1
ETR as AF
UART12 RX, TX, CTS, RTS_DE as AF

SCL, SDA, SMBA as AF I2C3/SMBUS

HDMI-CEC CEC

SCL, SDA, SMBA as AF I2C4/SMBUS

I3C1 SCL, SDA
RX, TX, CTS, RTS_DE as
LPUART1
AF
MOSI, MISO, SCK, SPI5
NSS as AF

SBS

IN1, IN2, CH1, CH2,

LPTIM3
ETR as AF

IN1, ETR as AF LPTIM4 VDD power domain VDDA power domain

IN1, IN2, CH1, CH2,
LPTIM5
ETR as AF
IN1, IN2, CH1, CH2,
VDDUSB power domain VBAT power domain
LPTIM6
ETR as AF
MSv67308V6

Note: PC[15:13] are in the VBAT domain.

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3 Functional overview

3.1 Arm Cortex-M33 core with TrustZone and FPU

The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor designed for
microcontrollers and deeply embedded applications, especially those requiring efficient
security. This processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. It features:
• Arm TrustZone technology, using the Armv8-M main extension supporting secure and
nonsecure states
• Memory protection units (MPUs), supporting up to 16 regions for secure and
nonsecure applications
• Configurable secure attribute unit (SAU) supporting up to eight memory regions as
secure or nonsecure
• Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces:
• System AHB bus:
The system AHB (S-AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
• Code AHB bus:
The code AHB (C-AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32H562xx and STM32H563xx
devices.

3.2 ART Accelerator (ICACHE and DCACHE)

3.2.1 Instruction cache (ICACHE)

The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex-M33 processor
to improve performance when fetching instruction (or data) from both internal and external
memories.
ICACHE offers the following features:
• Multi-bus interface:
– slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
– master1 port performing refill requests to internal memories (flash memory and
SRAMs)
– master2 port performing refill requests to external memories (external flash
memory and RAMs through Octo-SPI and FMC interfaces)
– a second slave port dedicated to ICACHE registers access

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• Close to 0 wait-states instructions/data access performance:

– 0 wait-states on cache hit
– hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
– critical-word-first refill policy, minimizing processor stalls on cache miss
– hit ratio improved by two-way set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– dual master ports allowing to decouple internal and external memory traffic,
respectively, on fast and slow buses, minimizing impact on interrupt latency
– optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– performance monitoring by means of a hit counter and a miss counter
• Extension of cacheable region beyond the code memory space, by means of address
remapping logic that allows four cacheable external regions to be defined
• Power consumption reduced intrinsically (more accesses to cache memory rather than
to bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default two-way set-associative mode)
• TrustZone security support
• Maintenance operation for software management of cache coherency
• Error management: detection of unexpected cacheable write access, with optional
interrupt raising

3.2.2 Data cache (DCACHE)

The data cache (DCACHE) is introduced on S-AHB system bus of Cortex-M33 processor to
improve the performance of data traffic to/from external memories.
DCACHE offers the following features:
• Multi-bus interface:
– slave port receiving the memory requests from the Cortex-M33 S-AHB system
port
– master port performing refill requests to external memories (external flash memory
and RAMs through Octo-SPI and FMC interfaces)
– a second slave port dedicated to DCACHE registers access
• Close to zero wait-states external data access performance:
– zero wait-states on cache hit
– hit-under-miss capability, allowing to serve new processor requests to cached
data, while a line refill (due to a previous cache miss) is still ongoing
– critical-word-first refill policy for read transactions, minimizing processor stalls on
cache miss
– hit ratio improved by two-way set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– performance monitoring by means of two hit counters (for read and write) and two
miss counters (for read and write)

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• Supported cache accesses:

– supports both write-back and write-through policies (selectable with AHB
bufferable attribute)
– read and write-back always allocated
– write-through always non-allocated (write-around)
– supports byte, half-word and word writes
• TrustZone security support
• Maintenance operations for software management of cache coherency:
– full cache invalidation (non interruptible)
– address range clean and/or invalidate operations (background task, interruptible)
• Error management: detection of error for master port request initiated by DCACHE (line
eviction or clean operation), with optional interrupt raising

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by other
active tasks. This memory area is organized into up to 20 protected areas (12 secure and 8
nonsecure). The MPU regions and registers are banked across secure and nonsecure
states.
The MPU is especially helpful for applications where critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by an RTOS
(real-time operating system).
If a program accesses a memory location prohibited by the MPU, the RTOS can detect it
and take action. In an RTOS environment, the kernel can dynamically update the MPU area
settings based on the process to be executed.

3.4 Embedded flash memory

The devices feature up to 2 Mbytes of embedded flash memory for storing programs and
data. The flash memory supports a high-cycle data area of up to 100 K cycles.
The flash memory interface features dual-bank operating modes, and read-while-write
(RWW). This allows a read operation to be performed on one bank while an erase or
program operation is performed on the other bank. Each bank contains 128 8-Kbyte pages.
The flash memory embeds a 2-Kbyte OTP (one-time programmable) for user data, and up
to 96 Kbytes supporting high cycling capability (100 K cycles), to use for data (EEPROM
emulation).

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Option bytes are available to set the flash memory protection mechanisms:
• Different product states for protecting memory content from debug access
• Write protection (WRP) to protect areas against erasing and programming. Two areas
per bank can be selected with 8-Kbyte granularity.
• Sector group write-protection (WRPSG), protecting up to 32 groups of four sectors
(32 Kbytes) per bank
• Two secure-only areas (one per user flash memory bank). When enabled, this area is
accessible only if the device operates in Secure-access mode
• One HDP area per bank providing temporal isolation for startup code
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• Single-error detection and correction
• Double-error detection
• ECC fail address report

3.4.1 FLASH security and protections

Sensitive information is stored in the flash memory and it is important to protect the memory
against unwanted operations such as reading confidential areas, illegal programming of
immutable sectors, or malicious flash memory erasing.
For that purpose the following protection mechanisms are implemented:
• TrustZone backed watermark and block security protection
• Temporal isolation protection (HDP)
• Configuration protection
• User flash memory write protection
• Device non-volatile security life cycle and application boot state management
• OTP locking
Refer to the product reference manual for a detailed description of the security mechanisms.

3.4.2 FLASH privilege protection

Each flash memory sector can be programmed on the fly as privileged or unprivileged.

3.5 Embedded SRAMs

Four SRAMs are embedded in the STM32H562xx and STM32H563xx devices, each with
specific features. SRAM1, SRAM2, and SRAM3 are the main SRAMs.
These SRAMs are made of several blocks that can be powered down in Stop mode to
reduce consumption:
• SRAM1: 256 Kbytes
• SRAM2: 64 Kbytes with ECC
• SRAM3: 320 Kbytes with optional ECC (when enabled, 64 bytes are reserved for it)
• BKPSRAM (backup SRAM): 4 Kbytes with optional ECC, can be retained in all low-
power modes and when VDD is off in VBAT mode

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Note: The ECC is supported by SRAM2, SRAM3, and BKPSRAM when enabled with the
SRAM2_ECC, SRAM3_ECC, and BKPRAM_ECC user option bits.

3.5.1 SRAMs TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM1,
SRAM2, SRAM3, can be programmed as secure or nonsecure by blocks, using the MPCBB
(block-based memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions
can be programmed as secure or nonsecure with watermark, using the TZSC (TrustZone
security controller) in the GTZC (global TrustZone controller).

3.5.2 SRAMs privilege protection

The SRAM1, SRAM2, SRAM3, can be programmed as privileged or non-privileged by
blocks, using the MPCBB. The granularity of SRAM privilege block based is a page of
512 bytes. Backup SRAM regions can be programmed as privileged or non-privileged with
watermark, using the TZSC (TrustZone security controller) in the GTZC (global TrustZone
controller).

3.6 Security overview

The STM32H562xx and STM32H563xx security enables the possibility to reopen the debug
mode even if the product is in secure state.
The reopening of the debug mode is controlled with a debug authentication procedure which
permits the authentication of the host.
Sensible assets (such as keys or secret codes) must be protected when opening the debug
mode. The protection is made via code protection and hardware keys storage solutions
where all root of trust can be protected thanks to hardware mechanisms.
In cases where sensitive information cannot be protected, a partial or a full regression can
be launched to start a debug. Regressions are enabled by a debug authentication method.
Developers can introduce their own root of trust solution (OEM-iROT), including their
installation in a non-trusted environment, thanks to a secure firmware install (SFI) solution.
The boot stages are isolated via a hardware mechanism called HDPL (temporal isolation
level). The HDPL guarantees isolation of the different boot stages: ST assets, iROT
(immutable root of trust), uROT (updatable root of trust), secure operating system and
nonsecure applications.
The devices embed a hardware key storage solution with a dedicated flash memory area
per boot stages with access-control based on HDPL, which can be secure or nonsecure.
STM32H562xx and STM32H563xx are powered by an Arm Cortex-M33 core, associated
with all the TrustZone isolation infrastructure. This design permits to benefit from a run time
isolation to run secure applications.

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3.7 Boot modes

At startup, a BOOT0 pin and NSBOOTADD[31:8]/SECBOOTADD[31:8] option bytes are
used to select the boot memory address that includes:
• Boot from any address in user flash memory
• Boot from system memory
– Bootloader
– ST immutable root of trust (ST-iROT)
– Root security service (RSS)
– Debug authentication library (RSS-DA)

Embedded bootloader
The embedded bootloader is located in the system memory, programmed by ST during
production. It is used to reprogram the flash memory by using USART, I2C, I3C, SPI,
FDCAN, or USB_FS in device mode through the DFU (device firmware upgrade).
Refer to AN2606 “STM32 microcontroller system memory boot mode”.

Embedded root security services (RSS)

The embedded RSS are located in the secure information block, programmed by ST during
production.
Refer to AN4992 “Overview secure firmware install (SFI)”.

Embedded immutable root of trust (ST-iROT)

The embedded ST-iROT in the system memory, programmed by ST during production. ST-
iROT is the immutable root of trust managing the secure boot and secure install of the first
updatable level to execute in a boot sequence.

Embedded debug authentication (ST-DA)

The embedded ST-DA in the system memory is programmed by ST during production.
ST-DA is the library that manages the debug authentication protocol, making it possible to
securely reopen the debug or to launch regressions on secured products in the field.

3.7.1 STM32H562/H563xx boot modes

Table 3 and Table 4, respectively, provide the detail of the boot mode when TrustZone is
disabled (TZEN = 0xC3) and enabled (TZEN = 0xB4).

Table 3. STM32H562/H563 boot mode when TrustZone is disabled (TZEN = 0xC3)

Boot address ST programmed
PRODUCT_STATE BOOT0 pin Boot area
option byte selection default value

Boot address defined

Open 0 NSBOOTADD[31:8] by user option byte Flash: 0x0800 0000
NSBOOTADD[31:8]
- 1 NA Bootloader Bootloader
Provisioning x NA RSS RSS

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Table 3. STM32H562/H563 boot mode when TrustZone is disabled (TZEN = 0xC3) (continued)
Boot address ST programmed
PRODUCT_STATE BOOT0 pin Boot area
option byte selection default value

Boot address defined

Provisioned, Closed,
x NSBOOTADD[31:8] by user option byte Flash: 0x0800 0000
Locked
NSBOOTADD[31:8]

Table 4. STM32H562/H563 boot mode when TrustZone is enabled (TZEN = 0xB4)

Boot address option- ST programmed
PRODUCT_STATE BOOT0 pin Boot area
byte selection default value

Boot address defined by

Open 0 SECBOOTADD[31:8] user option byte Flash: 0x0C00 0000
SECBOOTADD[31:8]
- 1 NA Bootloader Bootloader
Provisioning x NA RSS RSS
Provisioned, Boot address defined by
TZ_Closed, x SECBOOTADD[31:8] user option byte Flash: 0x0C00 0000
Closed, Locked SECBOOTADD[31:8]

When TrustZone is enabled the boot space must be in secure area. SECBOOTADD0[24:0]
option bytes are used to select the boot secure memory address. A unique boot entry option
can be selected by setting the SECBOOT_LOCK option bit.

3.8 Global TrustZone controller (GTZC)

GTZC is used to configure TrustZone and privileged attributes within the full system.
The GTZC includes three different sub-blocks:
• TZSC: TrustZone security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the nonsecure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
• TZIC: TrustZone illegal access controller
This sub-block gathers all security illegal access events in the system and generates a
secure interrupt towards NVIC.
• MPCBB: MPCBB: block-based memory protection controller
This sub-block controls secure states of all memory blocks (512-byte pages) of the
associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone
system product having segmented SRAM with programmable-security and privileged
attributes.

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The GTZC main features are:

• Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
• MPCBB and TZIC accessible only with secure transactions
– Enable illegal access events that may trigger a secure interrupt
• Secure and nonsecure access supported for privileged/non-privileged part of TZSC
• Set of registers to define product security settings:
– Secure/privilege regions for external memories
– Secure/privilege access mode for securable peripherals
– Secure/privilege access mode for securable legacy masters

3.9 TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the access permissions based on secure
and nonsecure state.
• SAU: up to eight SAU configurable regions are available for security attribution.
• IDAU: It provides a first memory partition as nonsecure or nonsecure callable
attributes. It is then combined with the results from the SAU security attribution and the
higher security state is selected.
Based on IDAU security attribution, the flash memory, system SRAMs and peripherals
memory space is aliased twice for secure and nonsecure states. However, the external
memories space is not aliased.

3.9.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-
aware type as follows:
• securable: peripheral protected by an AHB/APB firewall gate controlled from TZSC to
define security properties
• TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing
a specific TrustZone behavior such as a subset of registers being secure

3.9.2 Default TrustZone security state

The default system security state is detailed below:
• CPU:
– Cortex-M33 is in secure state after reset. The boot address must be in secure
address.
• Memory map:
– SAU is fully secure after reset. Consequently, all memory map is fully secure. Up
to eight SAU configurable regions are available for security attribution.
• Flash memory:
– Flash memory security area is defined by watermark user options.

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– Flash memory block based area is nonsecure after reset.

• SRAMs:
– All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
• External memories:
– FMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) is secure.
• Peripherals
– Securable peripherals are nonsecure after reset.
– TrustZone-aware peripherals are nonsecure after reset. Their secure configuration
registers are secure.
• All GPIOs are secure after reset.
• Interrupts:
– NVIC: All interrupts are secure after reset. NVIC is banked for secure and
nonsecure state.
• TZIC: All illegal access interrupts are disabled after reset.

3.10 Power supply management

The power controller (PWR) main features are:
• Power supplies and supply domains
– Core domain (VCORE)
– VDD domain
– Backup domain (VBAT)
– Analog domain (VDDA)
– SMPS power stage (VDDSMPS, available only on SMPS packages)
– VDDIO2 domain
– VDDUSB for USB transceiver
• System supply voltage regulation
– SMPS step down converter
– Voltage regulator (LDO)
• Power supply supervision
– POR/PDR monitor
– BOR monitor
– PVD monitor
• Power management
– Operating modes
– Voltage scaling control
– Low-power modes
• VBAT battery charging
• TrustZone security and privileged protection

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3.10.1 Power supply schemes

The devices require a 1.71 to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
• VDDA = 1.62 V (ADCs), 1.8 V (DACs), or 2.1 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for ADCs, DACs and voltage reference
buffer. This voltage level is independent from VDD, and must preferably be connected to
VDD when these peripherals are not used.
• VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step down converter. It is provided
externally through VDDSMPS supply pin and must be connected to the same supply
than VDD.
• VLXSMPS is the switched SMPS step down converter output. The SMPS power supply
pins are available only on packages with SMPS step down converter option.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. It is
independent from VDD, and must preferably be connected to VDD when the USB is not
used.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 10 I/Os (PD6, PD7, PG9:14, PB8, PB9). This
voltage level is independent from VDD, voltage and must preferably be connected to
VDD when those pins are not used.
• VBAT = 1.2 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
VREF+ can be grounded when ADC and DAC are not active.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled.
VREF- must always be equal to VSSA.
Depending upon the package, the devices embed an LDO and/or an SMPS regulator, to
provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3, and embedded
flash memory. The SMPS generates this voltage on VCAP (two pins), with a total external
capacitor of 10 μF (typical). The SMPS requires an external coil. The LDO generates this
voltage on VCAP pin connected to an external capacitor of 2x 2.2 μF (typical).
Both regulators can provide four different voltages (voltage scaling), and can operate in Stop
modes.

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Figure 2. STM32H562xx and STM32H563xx power supply overview (with SMPS)

VDDA domain
A/D converters
VDDA
D/A converters
VSSA
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS

VDD domain
VDDIO1 I/O ring

Reset block
Temperature sensor
3 x PLL VCORE domain
Internal RC oscillators
Core
VSS Standby circuitry
(Wakeup logic, IWDG) SRAM1
VDD SRAM2
Voltage regulator SRAM3

VCORE
2x VCAP Digital
VLXSMPS peripherals
SMPS regulator
VDDSMPS
VSSSMPS
Flash memory
Low-voltage detector

Backup domain
LSE crystal 32kHz oscillator
VBAT Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM

MSv64010V2

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Figure 3. STM32H562xx and STM32H563xx power supply overview (with LDO)

VDDA domain
A/D converters
VDDA
D/A converters
VSSA
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS

VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temperature sensor Core
3 x PLL
VSS Internal RC oscillators SRAM1
SRAM2
Standby circuitry SRAM3
VDD (Wakeup logic, IWDG)
VCORE
VCAP Digital
peripherals
LDO regulator

Flash memory
Low-voltage detector

Backup domain
LSE crystal 32kHz oscillator
VBAT Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
MSv64011V1

During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain
below VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
• During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-
down transient phase.

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Figure 4. Power-up/down sequence

V

3.6
VDDX(1)

VDD

VBOR0

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1

1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.

3.10.2 Power supply supervisor

The devices have an integrated ultra-low-power brownout reset (BOR) active in all modes;
The BOR ensures proper operation of the devices after power on and during power down.
The devices remain in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD
is higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor that compares the independent
supply voltages VDDA, VDDUSB and VDDIO2 to ensure that the peripheral is in its functional
supply range.
The devices support dynamic voltage scaling to optimize power consumption in Run mode.
The voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system maximum operating frequency.
The main regulator operates in the following ranges:
• VOS0 (VCORE = 1.35 V) with CPU and peripherals running at up to 250 MHz
• VOS1 (VCORE = 1.2 V) with CPU and peripherals running at up to 200 MHz
• VOS2 (VCORE = 1.1 V) with CPU and peripherals running at up to 150 MHz
• VOS3 (VCORE = 1.0 V) with CPU and peripherals running at up to 100 MHz

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Low-power modes
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
Only the CPU is stopped. All peripherals continue to operate and can wake up the CPU
when an interrupt/event occurs.
• Stop mode
This mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the CSI, the
HSI, the HSI48, and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
The system clock when exiting from Stop mode can be either HSI up to 64 MHz, or CSI
(4 MHz), depending on software configuration.
• Standby mode
This mode is used to achieve the lowest power consumption with BOR. The PLL, the
HSI, the CSI, the HSI48, and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active.
The I/Os state during Standby mode can be retained.
After entering Standby mode, SRAMs and register contents are lost, except for
registers and backup SRAM in the Backup domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
WKUP pin event (configurable rising or falling edge), an RTC event (alarm, periodic
wake-up, timestamp), or a tamper detection occurs. The tamper detection can be due
to external pins or to an internal failure detection.
The system clock after wake-up is HSI at 32 MHz.

3.10.3 Reset mode

To improve the consumption under reset, the I/Os state under and after reset is “analog
state” (the I/O Schmitt trigger is disabled).

3.10.4 VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or by
an external super-capacitor.
The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers,
and 4-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.

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3.10.5 PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security secures the following configuration:
• Low-power mode
• Wake-up (WKUP) pins
• Voltage detection and monitoring
• VBAT mode
Some of the PWR configuration bits security are defined by the security of other peripherals:
• The voltage scaling (VOS) configuration is secure when the system clock selection is
secure in RCC.
• The I/O pull-up/pull-down in Standby mode configuration is secure when the
corresponding GPIO is secure.
• The backup domain write protection is secure when the RTC is secure.

3.11 Peripheral interconnect matrix

Several peripherals have direct connections between them, for autonomous
communication, and to support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run and Sleep modes.

3.12 Reset and clock controller (RCC)

The clock controller distributes the clocks coming from the different oscillators to the core
and to the peripherals. It also manages the clock gating for low-power modes and ensures
the clock robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
• Clock security system: clock sources can be changed safely on the fly in Run mode
through a configuration register.
• Clock management: to reduce the power consumption, the clock controller can stop
the clock to the core, individual peripherals, or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 4 to 50 MHz high-speed external crystal or ceramic resonator (HSE), can supply a
PLL. The HSE can also be configured in bypass mode for an external clock.
– 64 MHz high-speed internal RC oscillator (HSI), trimmable by software, can
supply a PLL.
– 4 MHz low-power internal oscillator (CSI), trimmable by software, can supply a
PLL.
– System PLL, which can be fed by HSE, HSI, or CSI, with a maximum frequency at
250 MHz.

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• RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48),
can be used to drive the USB.
• UCPD kernel clock, derived from HSI clock. The HSI RC oscillator must be enabled
prior to the UCPD kernel clock use.
• Auxiliary clock source: two ultra-low power clock sources that can be used to drive
the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
• Peripheral clock sources: several peripherals have their own independent clock,
whatever the system clock. Three PLLs, each having three independent outputs
allowing the highest flexibility, can generate independent clocks for the ADC, USB,
SDMMC, RNG, FDCAN1, OCTOSPI, and the two SAIs.
• Startup clock: after reset, the microcontroller restarts by default with an internal
32 MHz clock (HSI/2). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock automatically switches to HSI and a software interrupt
is generated if enabled. LSE failure can also be detected and generates an interrupt.
• Clock-out capability:
– MCO (microcontroller clock output): outputs one of the internal clocks for
external use by the application.
– LSCO (low-speed clock output): outputs LSI or LSE in all low-power modes
(except VBAT mode).
Several prescalers allow AHB and APB frequencies configuration. The maximum frequency
of the AHB and the APB clock domains is 250 MHz.

3.12.1 RCC TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security secures some RCC system configuration and peripheral
configuration clock from being read or modified by nonsecure accesses: when a peripheral
is secure, the related peripheral clock, reset, clock source selection and clock enable during
low-power modes control bits are secure.
A peripheral is in secure state:
• when its corresponding SEC security bit is set in the TZSC (TrustZone security
controller), for securable peripherals.
• when a security feature of this peripheral is enabled through its dedicated bits, for
TrustZone-aware peripherals.

3.13 Clock recovery system (CRS)

The devices embed a special block that allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. The
trimming is based on the external synchronization signal, derived from USB SOF
signalization, from LSE oscillator, from an external signal on CRS_SYNC pin, or generated

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by user software. For faster lock-in during startup, automatic and manual trimming actions
can be combined.

3.14 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in analog mode to reduce power consumption.
If needed, the I/Os alternate function configuration can be locked following a specific
sequence, to avoid spurious writing to the I/Os registers.
Ten I/Os (PD6, PD7, PG9:14, PB8, PB9) can be independently supplied by a dedicated
VDDIO supply.

3.14.1 GPIOs TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a nonsecure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.

3.15 Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, GPDMA1, GPDMA2,
SDMMC1, SDMMC2, Ethernet) and the slaves (flash memory, FMC, OCTOSPI, SRAMs,
AHB and APB) peripherals. It ensures seamless and efficient operation, even when several
high-speed peripherals work simultaneously.

3.16 General purpose direct memory access controller (GPDMA)

The GPDMA controller is a bus master and system peripheral. It used to perform
programmable data transfers between memory-mapped peripherals and/or memories via
linked-lists, upon the control of an off-loaded CPU. The GPDMA main features are:
• Dual bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep mode
• Transfers arbitration based on a four-grade programmed priority at a channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)

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• Per channel event generation, on any of the following events: transfer complete or half
transfer complete or data transfer error or user setting error, and/or update linked-list
item error or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable per
event
• Eight concurrent DMA channels:
– Per channel FIFO for queuing source and destination transfers
– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– 12 channels with linear source and destination addressing: either fixed or
contiguously incremented addressing, programmed at a block level, between
successive single transfers
– Four channels with 2D source and destination addressing: programmable signed
address offsets between successive burst transfers (non-contiguous addressing
within a block, combined with programmable signed address offsets between
successive blocks, at a second 2D/repeated block level)
– Support for scatter-gather (multi-buffer transfers), data interleaving and
de-interleaving via 2D addressing
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting including FIFO level and event flags
• TrustZone support:
– Support for secure and nonsecure DMA transfers, independently at a first channel
level, and independently at a source/destination and link sub-levels
– Secure and nonsecure interrupts reporting, resulting from any of the respectively
secure and nonsecure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a nonsecure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at a channel
level
– Privileged-aware AHB slave port

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3.17 Interrupts and events

3.17.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels
and to handle up to 125 maskable interrupt channels plus the 16 interrupt lines of the
Cortex-M33.
The NVIC benefits are the following:
• closely coupled NVIC giving low-latency interrupt processing
• interrupt entry vector table address passed directly to the core
• early processing of interrupts
• processing of late arriving higher priority interrupts
• support for tail chaining
• processor state automatically saved
• interrupt entry restored on interrupt exit with no instruction overhead
• TrustZone support: NVIC registers banked across secure and nonsecure states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.

3.17.2 Extended interrupt/event controller (EXTI)

The extended interrupts and event controller (EXTI) manages the individual CPU and
system wake-up through configurable event inputs. It provides wake-up requests to the
power control, and generates an interrupt request to the CPU NVIC and events to the CPU
event input. For the CPU an additional event generation block (EVG) is needed to generate
the CPU event signal.
The EXTI wake-up requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes. The
EXTI also includes the EXTI multiplexer IO port selection.
The EXTI main features are the following:
• All event inputs allowed to wake up the system
• Configurable events (signals from I/Os or peripherals able to generate a pulse)
– Selectable active trigger edge
– Interrupt pending status register bit independent for the rising and falling edge
– Individual interrupt and event generation mask, used for conditioning the CPU
wake-up, interrupt and event generation
– Software trigger possibility
• TrustZone secure events
– The access to control and configuration bits of secure input events can be made
secure
• EXTI IO port selection

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3.18 Cyclic redundancy check calculation unit (CRC)

The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and that can be
stored at a given memory location.

3.19 CORDIC coprocessor (CORDIC)

The CORDIC coprocessor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications. It speeds up the calculation of these functions
compared to a software implementation, allowing a lower operating frequency, or freeing up
processor cycles in order to perform other tasks.
The CORDIC main features are:
• 24-bit CORDIC rotation engine
• Circular and hyperbolic modes
• Rotation and vectoring modes
• Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root, natural
logarithm
• Programmable precision
• Low-latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels
• Multiple register read/write by DMA

3.20 Filter math accelerator (FMAC)

The FMAC performs arithmetic operations on vectors. It comprises a multiplier/accumulator
(MAC) unit, together with address generation logic that allows it to index vector elements
held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be done.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
The FMAC main features are:
• 16 x 16-bit multiplier
• 24 + 2-bit accumulator with addition and subtraction
• 16-bit input and output data

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• 256 x 16-bit local memory

• Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
• Input and output buffers can be circular
• Filter functions: FIR, IIR (direct form 1)
• Vector functions: dot product, convolution, correlation
• AHB slave interface
• DMA read and write data channels

3.21 Flexible memory controller (FMC)

The FMC includes three memory controllers:
• NOR/PSRAM memory controller
• NAND memory controller
• SDRAM memory controller
The main features of the FMC controller are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (four memory banks)
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data
– Ferroelectric RAM (FRAM, FeRAM)
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM)
• 8-,16- bit data bus width
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO

3.21.1 LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to
specific LCD interfaces.
This LCD parallel interface capability makes it easy to build cost effective graphic
applications using LCD modules with embedded controllers or high-performance solutions
using external controllers with dedicated acceleration.

3.21.2 FMC TrustZone security

When the TrustZone security is enabled, the whole FMC banks are secure after reset.
Nonsecure area can be configured using the TZSC MPCWMx controller.
• The FMC NOR/PSRAM bank:
– Up to two nonsecure area can be configured thought the TZSC MPCWM2
controller with a 64-Kbyte granularity
• The FMC NAND bank:

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– Can be either configured as fully secure or fully nonsecure using the TZSC
MPCWM3 controller
The FMC registers can be configured as secure through the TZSC controller.

3.22 Octo-SPI interface (OCTOSPI)

The OCTOSPI supports most external serial memories such as serial PSRAMs, serial
NAND and serial NOR flash memories, HyperRAMs™ and HyperFlash™ memories, with
the following functional modes:
• Indirect mode: all the operations are performed using the OCTOSPI registers.
• Status-polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation.
The OCTOSPI supports the following protocols with associated frame formats:
• the standard frame format with the command, address, alternate byte, dummy cycles
and data phase
• the HyperBus™ frame format
The OCTOSPI offers the following features:
• Three functional modes: Indirect, Status-polling, and Memory-mapped
• Read and write support in Memory-mapped mode
• Supports for single, dual, quad and octal communication
• Dual-quad mode, where eight bits can be sent/received simultaneously by accessing
two quad memories in parallel.
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• HyperBus support
• Integrated FIFO for reception and transmission
• 8-, 16-, and 32-bit data accesses allowed
• DMA channel for Indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error

3.22.1 OCTOSPI TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two nonsecure area can be configured thought the TZSC MPCWM1 controller with a
granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.

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3.23 Delay block (DLYB)

The delay block (DLYB) is used to generate an output clock dephased from the input clock.
The phase of the output clock must be programmed by the user application. The output
clock is then used to clock the data received by another peripheral such as an SDMMC or
Octo-SPI interface. The delay is voltage and temperature dependent, that may require the
application to re-configure and recenter the output clock phase with the received data.
The delay block main features are:
• Input clock frequency ranging from 25 to 250 MHz
• Up to 12 oversampling phases

3.24 Analog-to-digital converters (ADC1 and ADC2)

The devices embed two successive approximation analog-to-digital converters.

Table 5. ADC features

Mode/feature ADC1 ADC2

Resolution 12 bit
Maximum sampling speed 5 Msps (12-bit resolution)
Dual mode operation X
Hardware offset calibration X
Hardware linearity calibration -
Single-end input X
Differential input X
Injected channel conversion X
Oversampling Up to x256
Data register 16 bits
Data register FIFO depth 3 stages
DMA support X
Parallel data output to ADF -
Offset compensation X
Gain compensation -
Number of analog watchdogs 3
Option register - X

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3.24.1 Analog temperature sensor

This sensor generates a voltage (VSENSE) that varies linearly with temperature. It is
internally connected to an ADC input channel used to convert the output voltage into a
digital value.
The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the
temperature measurement. As the offset depends upon process variation, the uncalibrated
internal temperature sensor is suitable for applications that detect only temperature
changes.
To improve the measurement accuracy, each device is individually factory-calibrated by ST.
The calibration data are stored in the system memory area, accessible in read-only mode.

3.24.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. The VREFINT is internally connected to ADC input channel.
The precise voltage of VREFINT is individually measured for each part during manufacturing,
and stored in the system memory area. It is accessible in read-only mode.

3.24.3 VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage using
ADC or input channel. As the VBAT voltage may be higher than the VDDA, and thus outside
the ADC input range, the VBAT pin is internally connected to a bridge divider by four. As a
consequence, the converted digital value is a quarter of the VBAT voltage.

3.25 Digital temperature sensor (DTS)

The devices embeds a sensor that converts the temperature into a square wave, whose
frequency is proportional to the temperature. The PCLK or the LSE clock can be used as
reference clock for the measurements. Use the formula given in the product reference
manual to calculate the temperature according to the measured frequency stored in the
DTS_DR register.

3.26 Digital to analog converter (DAC)

The DAC module is a 12-bit voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode, and can be used in conjunction with the DMA controller. In
12-bit mode, the data can be left- or right-aligned.
The DAC features two output channels, each with its own converter. In dual DAC channel
mode, conversions can be done independently or simultaneously when both channels are
grouped together for synchronous update operations. An input reference pin, VREF+
(shared with others analog peripherals), is available for better resolution. An internal
reference can also be set on the same input.
The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to allow a high drive output current. An individual

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calibration can be applied on each DAC output channel. The DAC output channels support
a low power mode, the Sample and hold mode.
The digital interface supports the following features:
• One DAC interface, maximum two output channels
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and triangular-wave generation
• Sawtooth wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• Double data DMA capability to reduce the bus activity
• External triggers for conversion
• DAC output channel buffered/unbuffered modes
• Buffer offset calibration
• Each DAC output can be disconnected from the DAC_OUTx output pin
• DAC output connection to on chip peripherals
• Sample and Hold mode for low-power operation in Stop mode. The DAC voltage can
be changed autonomously with the DMA while the device is in Stop mode.
• Voltage reference input

3.27 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as reference for ADCs and
DACs, and also as reference for external components through the VREF+ pin.
The internal voltage reference buffer supports three voltages: 1.8, 2.048, and 2.5 V.
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.

3.28 Digital camera interface (DCMI)

The digital camera is a synchronous parallel interface able to receive a high-speed data flow
from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data
formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG). It can be
used with black and white cameras, X24 and X5 cameras (it is assumed that all
preprocessing such as resizing is performed in the camera module).
Main features:
• 8-, 10-, 12-, or 14-bit parallel interface
• Embedded/external line and frame synchronization
• Continuous or snapshot mode
• Crop feature
• Support of the following data formats:

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– 8/10/12/14-bit progressive video: monochrome or raw Bayer

– YCbCr 4:2:2 progressive video
– RGB 565 progressive video
– Compressed data: JPEG

3.29 Parallel synchronous slave interface (PSSI)

The PSSI peripheral and the DCMI (digital camera interface) use the same circuitry. As a
result, these two peripherals cannot be used at the same time: when using the PSSI, the
DCMI registers cannot be accessed, and vice versa. In addition, the PSSI and the DCMI
share the same alternate functions and the same interrupt vector.
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
enables the transmitter to send a data valid signal that indicates when the data is valid, and
the receiver to output a flow control signal that indicates when it is ready to sample the data.
The PSSI peripheral main features are the following:
• Slave mode operation
• 8-bit or 16-bit parallel data input or output
• 4-word (16-byte) FIFO
• Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate
function output
When selected, these inputs can either enable the transmitter to indicate when the data is
valid, or allow the receiver to indicate when it is ready to sample the data, or both.

3.30 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
non-deterministic random bit generator (NDRBG).
The true random generator:
• delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage
• can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG)
• produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise)
• embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration)
• has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored)

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3.31 HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash (SHA-1, SHA-224,
SHA-256, SHA-512) and the HMAC (keyed-hash message authentication code) algorithms.
HMAC is suitable for applications requiring message authentication.
The HASH computes FIPS (Federal information processing standards) approved digests of
length of 160, 224, 256, 512 bits, for messages of up to (264 – 1).
The HASH main features are:
• Suitable for data authentication applications, compliant with:
– FIPS PUB 180-4, Secure Hash Standard (SHA-1 and SHA-2 family)
– FIPS PUB 186-4, Digital Signature Standard (DSS)
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
• Fast computation of SHA-1, SHA-224, SHA-256, SHA-512
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit string
– Word swapping supported: bits, bytes, half-words and 32-bit words
• Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)
• Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size
• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
• 8 × 32-bit words (H0 to H7) for output message digest
• Automatic data flow control with support of direct memory access (DMA) using one
channel. Single or fixed burst of 4 supported.
• Interruptible message digest computation, on a per-32-bit word basis
– Re-loadable digest registers
– Hashing computation suspend/resume mechanism, including using DMA

3.32 Public key accelerator (PKA)

The PKA can verify ECDSA signatures, with all needed computation performed within the
accelerator. The application CPU is needed only to manage the inputs and the outputs of
the operation.

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The PKA main features are:

• ECDSA signature verification
• Capability to handle operands up to 640 bits
• AMBA AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated, and write accesses are ignored)

3.33 Timers and watchdogs

The devices include two advanced control timers, up to seven general-purpose timers, two
basic timers, six low-power timers, two watchdog timers and two SysTick timers.
Table 6 compares the features of the advanced control, general-purpose and basic timers.

Table 6. Timer features

DMA Capture/
Counter Counter Prescaler Complementary
Type Timer request compare
resolution type factor outputs
generation channels

Advanced
TIM1, TIM8 16 bits 4 3
control
Up, down,
General TIM2, TIM5 32 bits up/down 4 No
purpose TIM3, TIM4 16 bits Any integer 4 No
between 1 and Yes
TIM12, TIM15 65536 2 1
General
TIM13, TIM14, 16 bits Up
purpose 1 1
TIM16, TIM17
Basic TIM6, TIM7 16 bits Up 0 No

3.33.1 Advanced-control timers (TIM1, TIM8)

These timers can be seen as a three-phase PWM multiplexed on six channels. They have
complementary PWM outputs with programmable inserted dead-times. They can also be
seen as complete general-purpose timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability
(0 - 100 %)
• One-pulse mode output
In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in the next
section) using the same architecture, so the advanced-control timers can work together with
the TIMx timers via the Timer Link feature for synchronization or event chaining.

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3.33.2 General-purpose timers

(TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17)
The devices embed up to seven synchronizable general-purpose timers (see Table 6), each
of them can be used to generate PWM outputs, or act as a simple time base.
• TIM2 and TIM5
Full-featured general-purpose timers with 32-bit auto-reload up/down counter and
32-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in Debug mode. All have independent DMA request
generation and support quadrature encoders.
• TIM3 and TIM4
Full-featured general-purpose timers, with 16-bit auto-reload up/down counter and
16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output.
They can work together, or with the other general-purpose timers via the Timer Link
feature for synchronization or event chaining.
The counters can be frozen in Debug mode. All have independent DMA request
generation and support quadrature encoders.
• TIM12, TIM13, TIM14, TIM15, TIM16, and TIM17
General-purpose timers with mid-range features, with 16-bit auto-reload up counter
and 16-bit prescaler.
– TIM12 and TIM15 have two channels and one complementary channel
– TIM13, TIM14, TIM16, and TIM17 have one channel and one complementary
channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in Debug mode.

3.33.3 Basic timers (TIM6, TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit timebase.

3.33.4 Low-power timers

(LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6)
The devices embed six low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wake up the system from Stop mode.
The low-power timers support the following features:
• 16-bit up counter with 16-bit autoreload register

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• 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)
• Selectable clock
– Internal clock sources: LSE, LSI, HSI or APB clock
– External clock source over LPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
• 16-bit ARR autoreload register
• 16-bit capture/compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable digital glitch filter
• Configurable output: pulse, PWM
• Configurable I/O polarity
• Encoder mode (except for LPTIM4)
• Repetition counter
• Up to two independent channels (except for LPTIM4) for:
– Input capture
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on ten events
• DMA request generation on the following events:
– Update event
– Input capture

3.33.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in Debug mode.

3.33.6 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.

3.33.7 SysTick timer

The Cortex-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
• SysTick, secure instance
• SysTick, nonsecure instance

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When TrustZone is disabled, only one SysTick timer is available. This timer (secure or
nonsecure) is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.

3.34 Real-time clock (RTC), tamper and backup registers

3.34.1 Real-time clock (RTC)

The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date,
month, year, in BCD (binary-coded decimal) format
• Binary mode with 32-bit free-running counter
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Two programmable alarms
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
• 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable
resolution and period
• TrustZone support:
– RTC fully securable
– Alarm A, alarm B, wake-up timer and timestamp individual secure or nonsecure
configuration
– Alarm A, alarm B, wake-up timer and timestamp individual privileged protection
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be one of the following:
• 32.768 kHz external crystal (LSE)
• external resonator or oscillator (LSE)
• internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.

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All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake up
the device from the low-power modes.

3.34.2 Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks.
32 32-bit backup registers are retained in all low-power modes and in VBAT mode. The
backup registers, as well as other secrets in the device, are protected by this anti-tamper
detection circuit with eight tamper pins and nine internal tampers. The external tamper pins
can be configured for edge detection, or level detection with or without filtering, or active
tamper that increases the security level by auto checking that the tamper pins are not
externally opened or shorted.
TAMP main features:
• A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches
and cryptographic peripherals.
• 32 32-bit backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the Backup domain that
remains powered-on by VBAT when the VDD power is switched off.
• Up to 8 tamper pins for 8 external tamper detection events:
– Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks
– Flexible active tamper I/O management: from 4 meshes (each input associated to
its own exclusive output) to 7 meshes (single output shared for up to 7 tamper
inputs)
– Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management
– Configurable digital filter
Note: As input, only PC13, PI8, PA0, PA1, and PA2 are functional in Standby and VBAT modes.
As output, only PC13 and PA1, and PI8 are functional in Standby and VBAT modes.
• Internal tamper events to protect against transient or environmental perturbation
attacks
• Each tamper can be configured in two modes:
– Hardware mode: immediate erase of secrets on tamper detection, including
backup registers erase
– Software mode: erase of secrets following a tamper detection launched by
software
• Any tamper detection can generate an RTC time stamp event.
• TrustZone support:
– Tamper secure or nonsecure configuration.
– Backup registers configuration in three configurable-size areas:
- 1 read/write secure area
- 1 write secure/read nonsecure area
- 1 read/write nonsecure area
– Secret key, stored in backup registers, protected against read and write access
• Tamper configuration and backup registers privilege protection
• Monotonic counter

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3.35 Inter-integrated circuit interface (I2C)

The devices embed four I2Cs. Refer to Table 7 for the implemented features.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Target and controller modes, multicontroller capability
– Standard-mode (Sm), with a bit rate up to 100 Kbit/s
– Fast-mode (Fm), with a bit rate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
– 7- and 10-bit addressing modes, multiple 7-bit target addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBus) specification rev 1.3 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
commun.ication speed to be independent from the PCLK reprogramming
• Wake-up from Stop capability
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 7. I2C implementation

Feature(1) I2C1 I2C2 I2C3 I2C4

Standard-mode (up to 100 Kbit/s) X X X X

Fast-mode (up to 400 Kbit/s) X X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X
Programmable analog and digital noise filters X X X X
SMBus/PMBus hardware support X X X X
Independent clock X X X X
Wake-up capability X X X X
1. X: supported

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3.36 Improved inter-integrated circuit (I3C)

The I3C interface handles communication between the MCU and others, like sensors and
host processor(s), all connected on an I3C bus.
The peripheral implements the required features of the MIPI I3C specification v1.1. It can
control I3C bus-specific sequencing, protocol, arbitration and timing, and can act as
controller (formerly known as master) or as target (formerly known as slave). When acting
as controller the peripheral improves the features of the I2C interface, preserving some
backward compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C
fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that the latter does not
perform clock stretching.
The I3C peripheral can be used with DMA to off-load the CPU.

Table 8. I3C peripheral controller/target features versus MIPI v1.1

MIPI When When
Feature Comments
v1.1 controller target

I3C SDR message X X X -

Mandatory when controller, and the I3C bus is
Legacy I2C message (Fm/Fm+) X X - mixed with (external) legacy I2C target(s).
Optional in MIPI v1.1 when target.
HDR DDR message X - -
Optional in MIPI v1.1
HDR-TSL/TSP, HDR-BT X - -
Dynamic address assignment X X X -
No (intended) support of I3C peripheral as a
Static address X X -
target on an I2C bus.
Grouped addressing X X - Optional in MIPI v1.1
CCCs X X X Mandatory and some optional CCCs supported.
Error detection and recovery X X X -
In-band interrupt (with MDB) X X X -
Secondary controller X X X -
Hot-join mechanism X X X -
Target reset X X X -
Synchronous timing control X X -
Asynchronous timing control 0 X X -
Asynchronous timing control 1, 2, 3 X - -
Optional in MIPI v1.1
Device to device tunneling X X -
Multi-lane data transfer X X -
Monitoring device early termination X - -

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3.37 Universal synchronous/asynchronous receiver transmitter

(USART/UART) and low-power universal asynchronous
receiver transmitter (LPUART)
The devices have six embedded universal synchronous receiver transmitters
(USART1/USART2/USART3/USART6/USART10/USART11), six universal asynchronous
receiver transmitters (UART4/UART5/UART7/UART8/UART9/UART12), and one low-power
universal asynchronous receiver transmitter (LPUART1).

Table 9. USART, UART and LPUART features

USART UART LPUART
Mode/feature(1)
1/2/3/6/10/11 4/5/7/8/9/12 1

Hardware flow control for modem X X X

Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous mode (master/slave) X - -
Smartcard mode X - -
Single-wire half-duplex communication X X X
IrDA SIR ENDEC block X X -
LIN mode X X -
(2)
Dual-clock domain and wake-up from Stop mode X X(2) X(2)
Receiver timeout interrupt X X -
Modbus communication X X -
Auto-baud rate detection X X -
Driver enable X X X
USART data length 7, 8, and 9 bits
Tx/Rx FIFO X X X
Tx/Rx FIFO size 8 bytes
1. X = supported.
2. Wake-up supported from Stop mode.

3.37.1 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
The USART offers a flexible means to perform full-duplex data exchange with external
equipments requiring an industry standard NRZ asynchronous serial data format. A very
wide range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.
High-speed data communication (up to 20 Mbauds) is possible by using the DMA (direct
memory access) for multibuffer configuration.

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The USART main features are:

• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or by 8, to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Auto baud rate detection
• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous Master/Slave mode and clock output/input for synchronous
communications
• SPI slave transmission underrun error flag
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wake-up from stop capability
• LIN master synchronous break send capability and LIN slave break detection capability
– 13-bit break generation and 10/11-bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16 bit duration for Normal mode
• Smartcard mode
– Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for Smartcard operation
• Support for Modbus communication
– Timeout feature
– CR/LF character recognition

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3.37.2 Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum
power consumption. It also supports half-duplex single-wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher-speed clock can be used to
reach higher baud-rates.
The LPUART interface can be served by the DMA controller.
The LPUART main features are:
• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 to 9600 bauds using a 32.768 kHz clock source
• Higher baud rates can be achieved by using a higher frequency clock source
• Two internal FIFOs to transmit and receive data
Each FIFO can be enabled/disabled by software and come with status flags for FIFOs
states.
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Programmable data word length (7 or 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– Busy and end of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Four error detection flags:
– Overrun error
– Noise detection
– Frame error
– Parity error
• Interrupt sources with flags

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• Multiprocessor communications: wake-up from Mute mode by idle line detection or

address mark detection
• Wake-up from Stop capability

3.38 Serial peripheral interface (SPI) / inter-integrated sound

interfaces (I2S)
The devices embed six serial peripheral interfaces (SPI) that can be used to communicate
with external devices while using the specific synchronous protocol. The SPI protocol
supports half-duplex, full-duplex and simplex synchronous, serial communication with
external devices.
The interface can be configured as master or slave, and can operate in multi-slave or multi-
master configurations. The device configured as master provides communication clock
(SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied
optionally just to set up communication with concrete slave and to assure it handles the data
flow properly. The Motorola data format is used by default, but some other specific modes
are supported as well.
The SPI main features are:
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only
• Multi master or multi slave mode capability
• Dual-clock domain, separated clock for the peripheral kernel that can be independent
of PCLK
• Baud rate prescaler up to kernel frequency divided by 2 or bypass from RCC in Master
mode
• Protection of configuration and setting
• Hardware or software management of SS for both master and slave
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO x MOSI swap capability
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• SPI Motorola and TI formats support
• Hardware CRC feature can secure communication at the end of transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode
• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun at slave, mode fault at master
• Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability
• Programmable number of data in transaction
• Configurable FIFO thresholds (data packing)

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• Configurable behavior at slave underrun condition (support of cascaded circular

buffers)
• Wake-up from Stop capability
• Optional status pin RDY signalizing the slave device ready to handle the data flow.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in full-duplex communication modes, and can be
configured to operate with configurable resolution as input or output channel.
I2S main features:
• Full duplex communication
• Simplex communication (only transmitter or receiver)
• Master or slave operations
• 8-bit programmable linear prescaler
• Data length may be 16, 24 or 32 bits
• Channel length can be 16 or 32 in master, any value in slave
• Programmable clock polarity
• Error flags signaling for improved reliability: Underrun, Overrun, and Frame Error
• Embedded Rx and TxFIFOs
• Supported I2S protocols:
– I2S Philips standard
– MSB-Justified standard (left-justified)
– LSB-Justified standard (right-justified)
– PCM standard (with short and long frame synchronization)
• Data ordering programmable (LSb or MSb first)
• DMA capability for transmission and reception
• Master clock can be output to drive an external audio component. The ratio is fixed at
256 x FWS (where FWS is the audio sampling frequency)

Table 10. SPI features

SPI1, SPI2, SPI3 SPI4, SPI5, SPI6
Feature
(full feature set instances) (full feature set instances)

Data size Configurable from 4- to 32-bit Configurable from 4- to 16-bit

CRC polynomial length CRC polynomial length
CRC computation
configurable from 5- to 33-bit configurable from 5- to 17-bit
Size of FIFOs 16x 8-bit 8x 8-bit
Number of transfered data Up to 65535
I2S feature Yes No

3.39 Serial audio interface (SAI)

The devices embed two SAIs. Refer to Table 11 for the features implementation. The SAI
bus interface handles communications between the MCU and the serial audio protocol.

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The SAI peripheral supports:

• Two independent audio sub-blocks that can be transmitters or receivers with their
respective FIFO
• 8-word integrated FIFOs for each audio sub-block
• Synchronous or Asynchronous mode between the audio sub-blocks
• Master or slave configuration independent for both audio sub-blocks
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
• Peripheral with large configurability and flexibility, allowing to target the following audio
protocols: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame
• Number of bits by frame may be configurable
• Frame synchronization active level configurable (offset, bit length, level)
• First active bit position in the slot is configurable
• LSB first or MSB first for data transfer
• Mute mode
• Stereo/mono audio frame capability
• Communication clock strobing edge configurable (SCK)
• Error flags with associated interrupts if enabled respectively
– Overrun and underrun detection
– Anticipated frame synchronization signal detection in Slave mode
– Late frame synchronization signal detection in Slave mode
– Codec not ready for the AC’97 mode in reception
• Interruption sources when enabled:
– Errors
– FIFO requests
• DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.

Table 11. SAI implementation

Feature(1) SAI1 SAI2

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X

Mute mode X X
Stereo/mono audio frame capability. X X
16 slots X X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X
FIFO size X (8 words) X (8 words)
SPDIF X X
PDM X -
1. X: supported

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3.40 Secure digital input/output and MultiMediaCards interface

(SDMMC)
The SD/SDIO, embedded MultiMediaCard (eMMC™) host interface (SDMMC) provides an
interface between the AHB bus and SD memory cards, SDIO cards, and eMMC devices.
The MultiMediaCard system specifications are available through the MultiMediaCard
association website at www.mmca.org, published by the MMCA technical committee.
SD memory card and SD I/O card system specifications are available through the SD card
association website at www.sdcard.org.
The SDMMC features include the following:
• Compliance with Embedded MultiMediaCard System Specification Version 5.1
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit (HS200
SDMMC_CK speed limited to maximum allowed I/O speed, HS400 is not supported).
• Full compatibility with previous versions of MultiMediaCards (backward compatibility).
• Full compliance with SD memory card specifications version 6.0
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Full compliance with SDIO card specification version 4.0
Card support for two different databus modes: 1-bit (default) and 4-bit (SDR104
SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and UHS-II
mode not supported).
• Data transfer up to 208 Mbyte/s for the 8-bit mode, depending maximum allowed I/O
speed.
• Data and command output enable signals to control external bidirectional drivers
• IDMA linked list support
The MultiMediaCard/SD bus connects cards to the host.
The current version of the SDMMC supports only one SD/SDIO/eMMC card at any one time
and a stack of eMMC.

Table 12. SDMMC features

(1)
Mode/feature SDMMC1 SDMMC2

Variable delay (SDR104, HS200) X X

SDMMC_CKIN X X
SDMMC_CDIR, SDMMC_D0DIR X -
SDMMC_D123DIR X -
1. X = supported.

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Functional overview STM32H562xx and STM32H563xx

When SDMMC peripherals are used simultaneously:

• Only one can be used in eMMC with 8-bit bus width.
• Usage of SDMMC1 SDIO voltage switch use is mutually exclusive with SDMMC2
eMMC with 8-bit bus width.
• If SDMMC1 must support SDIO UHS-I modes (SDR12, SDR25, SDR50, SDR104, or
DDR50), SDMMC2 cannot support eMMC with 8-bit bus width.
• If SDMMC2 must support eMMC with 8-bit bus width, SDMMC1 can only support SDIO
Default mode and High-speed mode.

3.41 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN module, a shared
message RAM memory and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and
transmits FIFOs.
The FDCAN main features are:
• Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4
• CAN FD with maximum 64 data bytes supported
• CAN error logging
• AUTOSAR and J1939 support
• Improved acceptance filtering
• Two receive FIFOs of three payloads each (up to 64 bytes per payload)
• Separate signaling on reception of high priority messages
• Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload)
• Configurable transmit Event FIFO
• Programmable loop-back test mode
• Maskable module interrupts
• Two clock domains: APB bus interface and CAN core kernel clock
• Power-down support

3.42 USB full speed (USB)

USB main features:
• USB specification version 2.0 full-speed compliant
• Host and device functions
• 2048 bytes of dedicated SRAM data buffer memory with 32-bit access
• USB clock recovery
• Configurable number of endpoints from 1 to 8
• Cyclic redundancy check (CRC) generation/checking, non-return-to-zero inverted
(NRZI) encoding/decoding and bit-stuffing
• Isochronous transfers support

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• Double-buffered bulk/isochronous endpoint support

• USB suspend/resume operations
• Frame-locked clock pulse generation
• USB 2.0 Link power management support
• Battery charging specification revision 1.2 support in device

3.43 USB Type-C/USB Power Delivery controller (UCPD)

The devices embed one controller (UCPD) compliant with USB Type-C Cable and
Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB power delivery
requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB power delivery message transmission and reception
• FRS (fast role swap) support
The digital controller handles:
• USB Type-C level detection with debounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB power delivery payload, generating interrupts (DMA
compatible)
• USB power delivery timing dividers (including a clock pre-scaler)
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB power delivery messages and FRS signaling.

3.44 Ethernet MAC interface with dedicated DMA controller (ETH)

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
Ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
• Support of 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation

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• MAC control sublayer (control frames) support

• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and
group addresses)
• 32-bit status code for each transmitted or received frame
• Internal 2-Kbyte FIFOs to buffer transmit and receive frames
• Support of hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Trigger of interrupt when system time becomes greater than target time

3.45 High-definition multimedia interface (HDMI) - consumer

electronics control (CEC)
The devices embed an HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wake up the MCU from Stop mode on data reception.

3.46 Development support

3.46.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.

3.46.2 Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device.
Real-time instruction and data flow activity be recorded and then formatted for display on
the host computer that runs the debugger software. TPA hardware is commercially available
from common development tool vendors.
The ETM operates with third party debugger software tools.

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4 Pinout, pin description, and alternate functions

4.1 Pinout/ballout schematics

Figure 5. LQFP64 pinout

BOOT0
VCAP

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDD
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12

MSv67303V4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD

PC4
PC5
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3

PA4
PA5
PA6
PA7

1. The above figure shows the package top view.

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Pinout, pin description, and alternate functions STM32H562xx and STM32H563xx

Figure 6. VFQFPN68 pinout

BOOT0
VCAP

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
VBAT 1 51
VDD
PC13 2 50
VSS
PC14-OSC32_IN 3 49
PA13
PC15-OSC32_OUT 4 48
PA12
PH0-OSC_IN 5 47
PA11
PH1-OSC_OUT 6 46
PA10
NRST 7 45
PA9
PC0 8 44
PA8
PC1 9 VFQFPN68 43
PC9
PC2 10 42
PC8
PC3 11 41
PC7
VSSA 12 40
PC6
VDDA 13 39
PD12
PA0 14 38
PD11
PA1 15 37
PB15
PA2 16 36
Exposed pad PB14
PA3 17 35
PB13
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VSS
VDD

PC4
PC5
PB0
PB1
PB2
PB10

VCAP
VSS
VDD
PB12
PA4
PA5
PA6
PA7

PB11
VSS
MS56628V1

1. The above figure shows the package top view.

2. VSS pads are connected to the exposed pad.

Figure 7. WLCSP80 SMPS ballout

1 2 3 4 5 6 7 8 9 10

A VDD PD0 PD2 VDD VCAP

B VDDUSB PD1 PB4 VSS VBAT

C PA12 PC10 PB3 PB7 PC13

PC14-
D VSS PA15 PB5 BOOT0 OSC32_I
N
E PA11 PA14 PC11 PB6 PB8
PC15-
F PC9 PA13 PC12 NRST OSC32_
OUT
G VDD PA8 PA10 PC1 VSS

H VSS PA9 PA6 PC0 VDD

PH1-
J PD15 PC6 PC8 PA1 OSC_OU
T
PH0-
K PD14 PC7 PA7 PA0
OSC_IN

L PB15 PB12 PB2 PA5 PC3

M PB13 PE10 PC4 PA2 PC2

VSSSMP
N PB14
S
PE8 PC5 VSSA

P VSS PB10 PB1 VSS VDDA

VDDSMP
R VDD
S
PE9 PB0 PA4

VLXSMP
T VCAP
S
PE7 VDD PA3

MSv73080V1

1. The above figure shows the package top view.

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Figure 8. LQFP100 pinout

BOOT0
VCAP

PC10
PC12
PC11

PA14
PA15
VDD
VSS

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD
VCAP
PE15
PB10
PE12
PE13
PE14
PE8
PE9
PE10
PB1
PB2
PE7
PC4
PC5
PB0
VSS
VDD

PE11
PA4
PA5
PA6
PA7
PA3

MSv67304V3

1. The above figure shows the package top view.

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Figure 9. LQFP100 SMPS pinout

BOOT0
VCAP

PC10
PC12
PC11

PA14
PA15
VDD
VSS

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VCAP
VSSSMPS
VDDSMPS
VLXSMPS
PB10
PE15
PE14
PE13
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PB0
VDD
VSS

PB11
PE11
PA7
PA6
PA5
PA4

MSv64012V3

1. The above figure shows the package top view.

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Figure 10. LQFP144 pinout

VDDIO2
BOOT0
VCAP

PG15

PG14
PG13
PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
VDD

VDD
VSS

VSS

PG9

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS

PG0
PG1
VDD

PC4
PC5
PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15

PE7
PE8
PE9
VSS

VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10
VCAP

VDD
PA3

PA4
PA5
PA6
PA7

PF11

PE11

MSv67305V3

1. The above figure shows the package top view.

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Figure 11. LQFP144 SMPS pinout

VDDIO2
BOOT0
VCAP

PG15

PG14
PG13
PG12
PG10

PC12

PC10
PC11

PA15
PA14
VDD

VDD
VSS

VSS

PG9

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA 30 79 PD10
VREF+ 31 78 PD9
VDDA 32 77 PD8
PA0 33 76 PB15
PA1 34 75 PB14
PA2 35 74 PB13
PA3 36 73 VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS

VSS
VDD

PB0
PB1
PB2

PF12

PF13

PE8

VSS
VDD

PF14
PF15
PG0
PG1
PE7

PE9

VLXSMPS
VDD
PE10

PE12
PE13
PE14
PE15
PB10

VDDSMPS
VSSSMPS
VCAP
VSS
PA4
PA5
PA6
PA7

PF11

PE11

PB11

MSv64013V3

1. The above figure shows the package top view.

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Figure 12. UFBGA169 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13

A PE2 PI7 VDD PB9 PB6 PB4 VDDIO2 PG10 PD3 VDD PC11 PA14 PI2

PC14-
B OSC32 PE3 VSS VCAP BOOT0 PG15 VSS PD7 PC12 VSS PA15 PI1 PI0
_IN

PC15-
C OSC32 PE5 PI6 PI4 PE0 PB5 PG14 PG12 PD2 PC10 PI3 VSS VDD
_OUT

VDDUS
D VDD VSS PE6 PE4 PE1 PB7 PG13 PD5 PD0 PH14 PH15 PH13
B

E PF1 VBAT PI8 PC13 PB8 PB3 PG11 PD6 PD1 PA10 PA9 PA13 PA12

F PF4 PF2 PF0 PI11 PF3 PF5 PG9 PD4 PC6 PC7 PG8 PA8 PA11

G VDD VSS PF7 PF6 PF8 PF10 PE8 PG7 PG3 PG5 PG6 PC8 PC9

PH1-
PH0-
H OSC_IN
OSC_O PF9 NRST PC3 PC5 PF13 PE10 PD15 PD11 PD14 VSS VDD
UT

J PC0 PC1 PC2 PA0 PA1 PF11 PF15 PE14 PD9 PB15 PD10 PG2 PG4

K VREF- VSSA PH2 PA5 PA7 PB1 PG1 PE12 PB10 PH6 PB12 PD12 PD13

L VDDA VREF+ PA2 PA4 PB0 PB2 PG0 PE9 PE13 PH7 PB13 PD8 VDD

M VDD VSS PH5 VSS PA6 PF14 VSS PE11 PB11 PH8 PH10 VSS PB14

N PH4 PH3 PA3 VDD PC4 PF12 VDD PE7 PE15 VCAP VDD PH11 PH12

MSv68827V2

1. The above figure shows the package top view.

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Figure 13. UFBGA169 SMPS ballout

1 2 3 4 5 6 7 8 9 10 11 12 13

A PI7 PI6 VDD VCAP PB4 VDDIO2 PD5 VDD PC11 PC10 VDD PI3 PH15

B VDD VSS PI5 VSS BOOT0 PG15 PD7 VSS PD1 PA15 VSS PI0 PA12

C VBAT PE5 PE2 PI4 PE1 PB6 PG10 PD3 PD0 PA14 PI1 PH13 PA11

PC14-
D OSC32 PE6 PE4 PE3 PE0 PB7 PG12 PD4 PC12 PI2 PH14 PA13 VDD
_IN

PC15-
VDDUS
E OSC32 PF0 PC13 PI8 PB9 PB5 PG9 PD2 PC8 PA8 PA10 VSS
B
_OUT

F PF7 VSS PF1 PF2 PB8 PB3 PD6 PG5 PG7 PC6 PC7 PC9 PA9

G VDD PF9 PF5 PF8 PF4 PF3 PF6 PD13 PG3 PD15 PG4 PG6 PG8

PH0-
H OSC_IN
VSS NRST PF10 PA1 PB1 PF13 PD11 PD9 PB15 PD12 PD14 PG2

PH1-
J OSC_O PC0 PC1 PH2 PA5 PF11 PF15 PE8 PE14 PB14 PD8 VSS VDD
UT

K PC2 PC3 PA0 PA3 PA7 PF12 PG1 PE13 PB10 PH10 PB12 PB13 PD10

L VSSA VREF- PA2 PH5 PC4 PF14 PE7 PE10 PE15 PB11 PH7 PH12 PH11

VSSSM
M VDDA VREF+ VSS PA4 PC5 PG0 VSS PE11 PE12
PS
VSS PH8 PH9

VLXSM VDDSM
N PH4 PH3 VDD PA6 PB0 PB2 VDD PE9
PS PS
VCAP VDD PH6

MSv64014V3

1. The above figure shows the package top view.

70/270 DS14258 Rev 5

STM32H562xx and STM32H563xx Pinout, pin description, and alternate functions

Figure 14. LQFP176 pinout

VDDIO2
BOOT0
VCAP

PG13
PG12

PG10
PG11
PG15

PG14

PC12

PC10
PC11

PA15
PA14
VDD

VDD

VDD
PG9

VSS
PD7
PD6

PD5
PD4
PD3
VSS

VSS
PE1
PE0

PD2
PD1
PD0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
PI7
PI6
PI5
PI4

PI3
PI2
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VDDUSB
PC14-OSC32_IN 9 124 PA13
PC15-OSC32_OUT 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDD
PF4 20 113 VSS
PF5 21 112 PG8
VSS 22 111 PG7
VDD 23 LQFP176 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PF10 28 105 PD15
PH0-OSC_IN 29 104 PD14
PH1-OSC_OUT 30 103 VDD
NRST 31 102 VSS
PC0 32 101 PD13
PC1 33 100 PD12
PC2 34 99 PD11
PC3 35 98 PD10
VDD 36 97 PD9
VSSA 37 96 PD8
VREF+ 38 95 PB15
VDDA 39 94 PB14
PA0 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 PH12
PH3 44 89 PH11
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PH4
PH5

VSS
VDD

PC4
PC5
PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10

VCAP
VSS
VDD
PH6
PH7
PH8
PH9
PH10
PA3

PA4
PA5
PA6
PA7

PF11

PE11

PB11

MSv67307V3

1. The above figure shows the package top view.

DS14258 Rev 5 71/270

75
Pinout, pin description, and alternate functions STM32H562xx and STM32H563xx

Figure 15. LQFP176 SMPS pinout

VDDIO2
BOOT0
VCAP

PG13
PG12

PG10
PG11
PG15

PG14

PC12

PC10
PC11

PA15
PA14
VDD

VDD

VDD
PG9

VSS
PD7
PD6

PD5
PD4
PD3
VSS

VSS
PE1
PE0

PD2
PD1
PD0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
PI7
PI6
PI5
PI4

PI3
PI2
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VDDUSB
PC14-OSC32_IN 9 124 PA13
PC15-OSC32_OUT 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDD
PF4 20 113 VSS
PF5 21 112 PG8
VSS 22 111 PG7
VDD 23 LQFP176 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PH0-OSC_IN 28 105 PD15
PH1-OSC_OUT 29 104 PD14
NRST 30 103 VDD
PC0 31 102 VSS
PC1 32 101 PD13
PC2 33 100 PD12
PC3 34 99 PD11
VDD 35 98 PD10
VSSA 36 97 PD9
VREF+ 37 96 PD8
VDDA 38 95 PB15
PA0 39 94 PB14
PA1 40 93 PB13
PA2 41 92 PB12
PH2 42 91 VDD
PH3 43 90 VSS
PA3 44 89 PH12
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS
VDD

PC4
PC5
PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10

PE12

PE14

PB10

VLXSMPS
PE13

PE15

VDDSMPS
VSSSMPS
VCAP
VSS
VDD
PH6
PH7
PH9
PH10
PA4
PA5
PA6
PA7

PF11

PE11

PB11

PH11

MSv67301V3

1. The above figure shows the package top view.

72/270 DS14258 Rev 5

STM32H562xx and STM32H563xx Pinout, pin description, and alternate functions

Figure 16. UFBGA176+25 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13

B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12

C VBAT PI7 PI6 PI5 VDD VCAP VDD VDDIO2 VDD PG9 PD5 PD1 PI3 PI2 PA11

D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10

PC14-
E OSC32_ PF0 PI10 PI11 PH13 PH14 PI0 PA9
IN

PC15-
F OSC32_ VSS VDD PH2 VSS VSS VSS VSS VSS VSS VDD PC9 PA8
OUT

PH0-
G OSC_IN
VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7

PH1-
VDDUS
H OSC_O PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS
B
PG8 PC6
UT

J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6

K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3

L PF10 PF9 PF8 VSS PH11 PH10 PD15 PG2

M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP PH6 PH8 PH9 PD14 PD13

N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10

P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8

R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15

MSv67306V3

1. The above figure shows the package top view.

DS14258 Rev 5 73/270

75
Pinout, pin description, and alternate functions STM32H562xx and STM32H563xx

Figure 17. UFBGA176+25 SMPS ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A PI7 PI5 VCAP PB9 BOOT0 PB5 PG15 PG14 PG10 PD7 PD5 PD3 PD1 PI3 PI1

B VBAT PE3 PI4 PE1 PB8 PB6 PB3 PG12 PG9 PD6 PD4 PD0 PA14 PI2 PH13

C VSS PE6 PE4 PI6 PE0 PB7 PB4 PG13 PG11 PD2 PC12 PC11 PA15 PH15 PA12

PC15- PC14-
D OSC32_ OSC32_ PE5 PE2 VDD VSS VDDIO2 VDD VSS VDD VSS PC10 PH14 VSS PA11
OUT IN

E PI9 PI8 PC13 VDD VDD PA13 PA10 PA9

VDD33U
F PF1 PF0 PI11 PI10 VSS VSS VSS VSS VSS
SB
PC9 PC8 PA8

G PF4 PF3 PF2 VSS VSS VSS VSS VSS VSS VSS PC7 PC6 PG8

H PF6 PF8 PF5 VDD VSS VSS VSS VSS VSS VSS PG7 PG3 PG5

PH1-
PH0-
J OSC_IN
OSC_O PF9 PF10 VSS VSS VSS VSS VSS VDD PD15 PG6 PG4
UT

K VSS PF7 NRST PC2 VSS VSS VSS VSS VSS PD10 PD14 PD12 PG2

L PC0 PC1 PA1 VDD PB12 PD9 PD11 PD13

M VDDA VSSA PA2 VSS PA4 VDD VSS VDD VSS PB10 VDD PH9 PH12 PB15 PD8

N VREF+ VREF- PC3 PC4 PA3 PB1 PF12 PF15 PE9 PE14 PE15 PB11 PH8 PH10 PB14

VSSSM
P PH5 PA0 PH3 PC5 PA6 PB2 PF13 PG1 PE8 PE11 PE13
PS
PH6 PH7 PH11

VLXSM VDDSM
R PH4 PH2 PA5 PA7 PB0 PF11 PF14 PG0 PE7 PE10 PE12
PS PS
VCAP PB13

MSv67300V3

1. The above figure shows the package top view.

74/270 DS14258 Rev 5

STM32H562xx and STM32H563xx Pinout, pin description, and alternate functions

4.2 Pin description

Table 13. Legend/abbreviations used in the pinout table
Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/output pin
FT 5 V-tolerant I/O
TT 3.6 V-tolerant I/O
RST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os(1)
_a I/O, with analog switch function supplied by VDDA
_c I/O with USB Type-C power delivery function
I/O structure
_d I/O with USB Type-C power delivery dead battery function
_f I/O, Fm+ capable
_h I/O with high-speed low-voltage mode
_s I/O supplied only by VDDIO2
_t I/O with tamper function functional in VBAT mode
_u I/O, with USB function supplied by VDDUSB
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in the following table are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u,
TT_a.

DS14258 Rev 5 75/270

75
76/270
Table 14. STM32H562xx and STM32H563xx pin/ball definition
Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TRACECLK, LPTIM1_IN2,
SAI1_CK1, SPI4_SCK,
SAI1_MCLK_A, USART10_RX,
- 1 1 C3 1 D4 - 1 1 A1 1 A2 - PE2 I/O FT_h - -
UART8_TX, OCTOSPI1_IO2,
ETH_MII_TXD3, FMC_A23,
DCMI_D3/PSSI_D3, EVENTOUT
DS14258 Rev 5

TRACED0, TIM15_BKIN,
- 2 2 D4 2 B2 - 2 2 B2 2 A1 - PE3 I/O FT_h - SAI1_SD_B, USART10_TX, TAMP_IN6/TAMP_OUT3
FMC_A19, EVENTOUT

TRACED1, SAI1_D2,
TIM15_CH1N, SPI4_NSS,
- 3 3 D3 3 C3 - 3 3 D4 3 B1 - PE4 I/O FT_h - TAMP_IN7/TAMP_OUT8
SAI1_FS_A, FMC_A20,
DCMI_D4/PSSI_D4, EVENTOUT

TRACED2, SAI1_CK2,
TIM15_CH1, SPI4_MISO,
- 4 4 C2 4 D3 - 4 4 C2 4 B2 - PE5 I/O FT_h - TAMP_IN8/TAMP_OUT7
SAI1_SCK_A, FMC_A21,

STM32H562xx and STM32H563xx

DCMI_D6/PSSI_D6, EVENTOUT

TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
- 5 5 D2 5 C2 - 5 5 D3 5 B3 - PE6 I/O FT_h - SPI4_MOSI, SAI1_SD_A, TAMP_IN3/TAMP_OUT6
SAI2_MCLK_B, FMC_A22,
DCMI_D7/PSSI_D7, EVENTOUT

A1 - - - - - - - - - - - - VDD S - - - -

B8 - - - - - - - - - - - - VSS S - - - -

B10 6 6 C1 6 B1 1 6 6 E2 6 C1 1 VBAT S - - - -

D2 - - - - - - - - - - - - VSS S - - - -
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

(5) TAMP_IN2/TAMP_OUT3,
- - - E4 7 E2 - - - E3 7 D2 - PI8 I/O FT_t EVENTOUT
RTC_OUT2, WKUP3

TAMP_IN1/TAMP_OUT2/
(5)
C9 7 7 E3 8 E3 2 7 7 E4 8 D1 2 PC13 I/O FT_t EVENTOUT TAMP_OUT3, RTC_OUT1/
RTC_TS, WKUP4

G9 - - - - - - - - - - - - VSS S - - - -
DS14258 Rev 5

PC14-
D10 8 8 D1 9 D2 3 8 8 B1 9 E1 3 OSC32_IN I/O FT - EVENTOUT OSC32_IN
(OSC32_IN)

PC15-
F10 9 9 E1 10 D1 4 9 9 C1 10 F1 4 OSC32_OUT I/O FT - EVENTOUT OSC32_OUT
(OSC32_OUT)

UART4_RX, FDCAN1_RX,
- - - - 11 E1 - - - - 11 D3 - PI9 I/O FT_h - -
EVENTOUT

FDCAN1_RX, ETH_MII_RX_ER,
- - - - 12 F4 - - - - 12 E3 - PI10 I/O FT_h - -
PSSI_D14, EVENTOUT

- - - - 13 F3 - - - F4 13 E4 - PI11 I/O FT - PSSI_D15, EVENTOUT TAMP_IN4/TAMP_OUT5

- - - B2 14 C1 - - - D2 14 D5 - VSS S - - - -

- - - B1 15 D5 - - - D1 15 C5 - VDD S - - - -

I2C2_SDA, FMC_A0,
- - 10 E2 16 F2 - - 10 F3 16 E2 - PF0 I/O FT_f - -
LPTIM5_CH1, EVENTOUT

I2C2_SCL, FMC_A1,
- - 11 F3 17 F1 - - 11 E1 17 H3 - PF1 I/O FT_f - -
LPTIM5_CH2, EVENTOUT
77/270
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
78/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

LPTIM3_CH2, LPTIM3_IN2,
I2C2_SMBA, UART12_TX,
- - 12 F4 18 G3 - - 12 F2 18 H2 - PF2 I/O FT_h - -
USART11_CK, FMC_A2,
LPTIM5_IN1, EVENTOUT

LPTIM3_IN1, USART11_TX,
- - 13 G6 19 G2 - - 13 F5 19 J2 - PF3 I/O FT_h - FMC_A3, LPTIM5_IN2, -
EVENTOUT
DS14258 Rev 5

LPTIM3_ETR, USART11_RX,
- - 14 G5 20 G1 - - 14 F1 20 J3 - PF4 I/O FT_h - -
FMC_A4, EVENTOUT

LPTIM3_CH1, I2C4_SCL,
I3C1_SCL, UART12_RX,
- - 15 G3 21 H3 - - 15 F6 21 K3 - PF5 I/O FT_fh - USART11_CTS/USART11_NSS, -
FMC_A5, LPTIM3_IN1,
EVENTOUT

H2 10 16 F2 22 G4 - 10 16 G2 22 F2 - VSS S - - - -

STM32H562xx and STM32H563xx

A7 11 17 G1 23 E4 - 11 17 G1 23 F3 - VDD S - - - -

TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
- - 18 G7 24 H1 - - 18 G4 24 K2 - PF6 I/O FT_h - -
OCTOSPI1_IO3, LPTIM5_CH1,
EVENTOUT

TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
- - 19 F1 25 K2 - - 19 G3 25 K1 - PF7 I/O FT_h - -
OCTOSPI1_IO2, LPTIM5_CH2,
EVENTOUT

TIM16_CH1N, SPI5_MISO,
SAI1_SCK_B,
- - 20 G4 26 H2 - - 20 G5 26 L3 - PF8 I/O FT_h - UART7_RTS/UART7_DE, -
TIM13_CH1, OCTOSPI1_IO0,
LPTIM5_IN1, EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS,
- - 21 G2 27 J3 - - 21 H3 27 L2 - PF9 I/O FT_h - -
TIM14_CH1, OCTOSPI1_IO1,
LPTIM5_IN2, EVENTOUT

TIM16_BKIN, SAI1_D3,
PSSI_D15, OCTOSPI1_CLK,
- - 22 H4 - J4 - - 22 G6 28 L1 - PF10 I/O FT_h - -
DCMI_D11/PSSI_D11,
DS14258 Rev 5

EVENTOUT

PH0-
K10 12 23 H1 28 J1 5 12 23 H1 29 G1 5 I/O FT - EVENTOUT OSC_IN
OSC_IN(PH0)

PH1-
J9 13 24 J1 29 J2 6 13 24 H2 30 H1 6 I/O FT - EVENTOUT OSC_OUT
OSC_OUT(PH1)

F8 14 25 H3 30 K3 7 14 25 H4 31 J1 7 NRST I/O RST - - -

TIM16_BKIN, SAI1_MCLK_A,
SPI2_RDY, SAI2_FS_B,
H8 15 26 J2 31 L1 8 15 26 J1 32 M2 8 PC0 I/O FT_a - ADC12_INP10
FMC_A25, OCTOSPI1_IO7,
FMC_SDNWE, EVENTOUT

TRACED0, SAI1_D1,
SPI2_MOSI/I2S2_SDO,
ADC12_INP11,
SAI1_SD_A,
ADC12_INN10,
G7 16 27 J3 32 L2 9 16 27 J2 33 M3 9 PC1 I/O FT_ah - USART11_RTS/USART11_DE,
TAMP_IN3/TAMP_OUT5,
SAI2_SD_A, SDMMC2_CK,
WKUP6
OCTOSPI1_IO4, ETH_MDC,
EVENTOUT

PWR_CSLEEP, TIM17_CH1,
TIM4_CH4, SPI2_MISO/I2S2_SDI,
ADC12_INP12,
M10 17 28 K1 33 K4 10 17 28 J3 34 M4 10 PC2 I/O FT_a - OCTOSPI1_IO5, OCTOSPI1_IO2,
ADC12_INN11
ETH_MII_TXD2, FMC_SDNE0,
79/270

EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
80/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

PWR_CSTOP, SAI1_D3,
LPTIM3_CH1,
SPI2_MOSI/I2S2_SDO, ADC12_INP13,
L9 18 29 K2 34 N3 11 18 29 H5 35 M5 11 PC3 I/O FT_a -
OCTOSPI1_IO6, OCTOSPI1_IO0, ADC12_INN12
ETH_MII_TX_CLK,
FMC_SDCKE0, EVENTOUT

G1 - - - 35 H4 - - 30 M1 36 G3 - VDD S - - - -
DS14258 Rev 5

P2 - - H2 - K1 - - - M2 - G2 - VSS S - - - -

N9 19 30 L1 36 M2 12 19 31 K2 37 M1 12 VSSA S - - - -

- - - L2 - N2 - 20 - K1 - N1 - VREF- S - - - -

- 20 31 M2 37 N1 - 21 32 L2 38 P1 - VREF+ S - - - -

P10 21 32 M1 38 M1 13 22 33 L1 39 R1 13 VDDA S - - - -

TIM2_CH1, TIM5_CH1,
TIM8_ETR, TIM15_BKIN,

STM32H562xx and STM32H563xx

SPI6_NSS, SPI3_RDY, ADC12_INP0, ADC12_INN1,
K8 22 33 K3 39 P2 14 23 34 J4 40 N3 14 PA0 I/O FT_at (5) USART2_CTS/USART2_NSS, TAMP_IN2/TAMP_OUT1,
UART4_TX, SDMMC2_CMD, WKUP1
SAI2_SD_B, ETH_MII_CRS,
TIM2_ETR, EVENTOUT

TIM2_CH2, TIM5_CH2,
TIM15_CH1N, LPTIM1_IN1,
OCTOSPI1_DQS,
(5) USART2_RTS/USART2_DE, ADC12_INP1,
J7 23 34 H5 40 L3 15 24 35 J5 41 N2 15 PA1 I/O FT_aht
UART4_RX, OCTOSPI1_IO3, TAMP_IN5/TAMP_OUT4
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_RMII_RE
F_CLK, EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM2_CH3, TIM5_CH3,
ADC12_INP14,
(5) TIM15_CH1, LPTIM1_IN2,
M8 24 35 L3 41 M3 16 25 36 L3 42 P2 16 PA2 I/O FT_hat TAMP_IN4/TAMP_OUT3,
USART2_TX, SAI2_SCK_B,
WKUP2
ETH_MDIO, EVENTOUT

LPTIM1_IN2, OCTOSPI1_IO4,
- - - J4 42 R2 - - - K3 43 F4 - PH2 I/O FT_h - SAI2_SCK_B, ETH_MII_CRS, -
FMC_SDCKE0, EVENTOUT
DS14258 Rev 5

H10 - - - - L4 - - - - - K4 - VDD S - - - -

P8 - - - - M4 - - - - - L4 - VSS S - - - -

OCTOSPI1_IO5, SAI2_MCLK_B,
- - - N2 43 P3 - - - N2 44 G4 - PH3 I/O FT_ah - ETH_MII_COL, FMC_SDNE0, -
EVENTOUT

I2C2_SCL, SPI5_RDY, SPI6_RDY,

- - - N1 - R1 - - - N1 45 H4 - PH4 I/O FT_fa - -
PSSI_D14, EVENTOUT

I2C2_SDA, SPI5_NSS,
- - - L4 - P1 - - - M3 46 J4 - PH5 I/O FT_fa - SPI6_RDY, FMC_SDNWE, -
EVENTOUT

TIM2_CH4, TIM5_CH4,
OCTOSPI1_CLK, TIM15_CH2,
T10 25 36 K4 44 N5 17 26 37 N3 47 R2 17 PA3 I/O FT_ah - SPI2_NSS/I2S2_WS, SAI1_SD_B, ADC12_INP15
USART2_RX, ETH_MII_COL,
EVENTOUT

- 26 37 M3 45 M7 18 27 38 M4 48 M8 18 VSS S - - - -

R1 27 38 N3 46 M6 19 28 39 N4 49 N8 19 VDD S - - - -
81/270
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
82/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM5_ETR, LPTIM2_CH1,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
R9 28 39 M4 47 M5 20 29 40 L4 50 N4 20 PA4 I/O TT_a - ADC12_INP18, DAC1_OUT1
USART2_CK, SPI6_NSS,
DCMI_HSYNC/PSSI_DE,
EVENTOUT

TIM2_CH1, TIM8_CH1N,
DS14258 Rev 5

SPI1_SCK/I2S1_CK, SPI6_SCK, ADC12_INP19,

L7 29 40 J5 48 R3 21 30 41 K4 51 P4 21 PA5 I/O TT_ah - ETH_MII_TX_EN/ETH_RMII_TX_ ADC12_INN18,
EN, PSSI_D14, TIM2_ETR, DAC1_OUT2
EVENTOUT

TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
H6 30 41 N4 49 P5 22 31 42 M5 52 P3 22 PA6 I/O FT_ah - OCTOSPI1_IO3, USART11_TX, ADC12_INP3
SPI6_MISO, TIM13_CH1,
DCMI_PIXCLK/PSSI_PDCK,

STM32H562xx and STM32H563xx

EVENTOUT

TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
USART11_RX, SPI6_MOSI,
K6 31 42 K5 50 R4 23 32 43 K5 53 R3 23 PA7 I/O FT_ah - ADC12_INP7, ADC12_INN3
TIM14_CH1, OCTOSPI1_IO2,
ETH_MII_RX_DV/ETH_RMII_CRS
_DV, FMC_SDNWE, FMC_NWE,
EVENTOUT

TIM2_CH4, SAI1_CK1,
LPTIM2_ETR, I2S1_MCK,
M6 - - L5 51 N4 24 33 44 N5 54 N5 24 PC4 I/O FT_a - USART3_RX, ADC12_INP4
ETH_MII_RXD0/ETH_RMII_RXD0
, FMC_SDNE0, EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM1_CH4N, SAI1_D3,
PSSI_D15, SAI1_FS_A,
UART12_RTS/UART12_DE,
N7 - - M5 52 P4 25 34 45 H6 55 P5 25 PC5 I/O FT_ah - ADC12_INP8, ADC12_INN4
OCTOSPI1_DQS,
ETH_MII_RXD1/ETH_RMII_RXD1
, FMC_SDCKE0, EVENTOUT

T8 - - - - M8 - - - - - - - VDD S - - - -
DS14258 Rev 5

TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, OCTOSPI1_IO1,
R7 32 43 N5 53 R5 26 35 46 L5 56 R5 26 PB0 I/O FT_ah - USART11_CK, UART4_CTS, ADC12_INP9, ADC12_INN5
ETH_MII_RXD2, LPTIM3_CH1,
EVENTOUT

TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, OCTOSPI1_IO0,
P6 33 44 H6 54 N6 27 36 47 K6 57 R4 27 PB1 I/O FT_ah - ADC12_INP5
ETH_MII_RXD3, LPTIM3_CH2,
EVENTOUT

RTC_OUT2, SAI1_D1,
TIM8_CH4N, SPI1_RDY,
LPTIM1_CH1, SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
L5 34 45 N6 55 P6 28 37 48 L6 58 M6 28 PB2 I/O FT_ah - LSCO
OCTOSPI1_CLK,
OCTOSPI1_DQS,
SDMMC1_CMD, LPTIM5_ETR,
EVENTOUT

SPI5_MOSI, OCTOSPI1_NCLK,
SAI2_SD_B, FMC_NRAS,
- - 46 J6 56 R6 - - 49 J6 59 R6 - PF11 I/O FT_ah - ADC1_INP2
DCMI_D12/PSSI_D12,
LPTIM6_CH1, EVENTOUT
83/270

FMC_A6, LPTIM6_CH2,
- - 47 K6 57 N7 - - 50 N6 60 P6 - PF12 I/O FT_ah - ADC1_INP6, ADC1_INN2
EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
84/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

- - 48 M7 58 - - - 51 M7 61 - - VSS S - - - -

- - 49 N7 59 - - - 52 N7 62 N9 - VDD S - - - -

I2C4_SMBA, FMC_A7,
- - 50 H7 60 P7 - - 53 H7 63 N6 - PF13 I/O FT_ah - ADC2_INP2
LPTIM6_IN1, EVENTOUT

FMC_A8, LPTIM6_IN2,
- - 51 L6 61 R7 - - 54 M6 64 R7 - PF14 I/O FT_fah - ADC2_INP6, ADC2_INN2
EVENTOUT
DS14258 Rev 5

I2C4_SDA, I3C1_SDA, FMC_A9,

- - 52 J7 62 N8 - - 55 J7 65 P7 - PF15 I/O FT_fh - -
EVENTOUT

UART9_RX, FMC_A10,
- - 53 M6 63 R8 - - 56 L7 66 N7 - PG0 I/O FT_h - -
LPTIM4_IN1, EVENTOUT

SPI2_MOSI/I2S2_SDO,
- - 54 K7 64 P8 - - 57 K7 67 M7 - PG1 I/O FT_h - UART9_TX, FMC_A11, -
EVENTOUT

TIM1_ETR,

STM32H562xx and STM32H563xx

UART12_RTS/UART12_DE,
T6 35 55 L7 65 R9 - 38 58 N8 68 R8 - PE7 I/O FT_ah - -
UART7_RX, OCTOSPI1_IO4,
FMC_D4/FMC_AD4, EVENTOUT

TIM1_CH1N,
UART12_CTS/UART12_NSS,
N5 36 56 J8 66 P9 - 39 59 G7 69 P8 - PE8 I/O FT_ah - -
UART7_TX, OCTOSPI1_IO5,
FMC_D5/FMC_AD5, EVENTOUT

TIM1_CH1, UART12_RX,
UART7_RTS/UART7_DE,
R5 37 57 N8 67 N9 - 40 60 L8 70 P9 - PE9 I/O FT_ah - -
OCTOSPI1_IO6,
FMC_D6/FMC_AD6, EVENTOUT

- - 58 - 68 - - - 61 - 71 - - VSS S - - - -

- - 59 - 69 - - - 62 - 72 - - VDD S - - - -
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM1_CH2N, UART12_TX,
M4 38 60 L8 70 R10 - 41 63 H8 73 R9 - PE10 I/O FT_ah - UART7_CTS, OCTOSPI1_IO7, -
FMC_D7/FMC_AD7, EVENTOUT

TIM1_CH2, SPI1_RDY,
SPI4_NSS, OCTOSPI1_NCS,
- 39 61 M8 71 P10 - 42 64 M8 74 P10 - PE11 I/O FT_ah - -
SAI2_SD_B, FMC_D8/FMC_AD8,
EVENTOUT
DS14258 Rev 5

TIM1_CH3N, SPI4_SCK,
- 40 62 M9 72 R11 - 43 65 K8 75 R10 - PE12 I/O FT_h - SAI2_SCK_B, -
FMC_D9/FMC_AD9, EVENTOUT

TIM1_CH3, SPI4_MISO,
SAI2_FS_B,
- 41 63 K8 73 P11 - 44 66 L9 76 N11 - PE13 I/O FT_h - -
FMC_D10/FMC_AD10,
EVENTOUT

TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
- 42 64 J9 74 N10 - 45 67 J8 77 P11 - PE14 I/O FT_h - -
FMC_D11/FMC_AD11,
EVENTOUT

TIM1_BKIN, TIM1_CH4N,
USART10_CK,
- 43 65 L9 75 N11 - 46 68 N9 78 R11 - PE15 I/O FT_h - -
FMC_D12/FMC_AD12,
EVENTOUT

TIM2_CH3, LPTIM3_CH1,
LPTIM2_IN1, I2C2_SCL,
P4 44 66 K9 76 M10 29 47 69 K9 79 R12 29 PB10 I/O FT_f - SPI2_SCK/I2S2_CK, -
USART3_TX, OCTOSPI1_NCS,
ETH_MII_RX_ER, EVENTOUT
85/270
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
86/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM2_CH4, LPTIM2_ETR,
I2C2_SDA, SPI2_RDY, SPI4_RDY,
- 45 67 L10 77 N12 - - - M9 80 R13 30 PB11 I/O FT_f - USART3_RX, -
ETH_MII_TX_EN/ETH_RMII_TX_
EN, FMC_NBL1, EVENTOUT

T4 46 68 N9 78 R12 - - - - - - - VLXSMPS S - - - -
DS14258 Rev 5

R3 47 69 N10 79 R13 - - - - - - - VDDSMPS S - - - -

N3 48 70 M10 80 P12 - - - - - - - VSSSMPS S - - - -

T2 49 71 N11 81 R14 30 48 70 N10 81 M10 31 VCAP S - - - -

- 50 72 M11 82 M9 31 49 71 M12 82 M9 32 VSS S - - - -

- 51 73 N12 83 M11 32 50 72 N11 83 N10 33 VDD S - - - -

TIM1_CH3N, TIM12_CH1,
TIM8_CH1, I2C2_SMBA,
- - - N13 84 P13 - - - K10 84 M11 - PH6 I/O FT - SPI5_SCK, ETH_MII_RXD2, -

STM32H562xx and STM32H563xx

FMC_SDNE1,
DCMI_D8/PSSI_D8, EVENTOUT

TIM1_CH3, TIM8_CH1N,
I2C3_SCL, SPI5_MISO,
- - - L11 85 P14 - - - L10 85 N12 - PH7 I/O FT_f - -
ETH_MII_RXD3, FMC_SDCKE1,
DCMI_D9/PSSI_D9, EVENTOUT

TIM1_CH2N, TIM5_ETR,
TIM8_CH2, I2C3_SDA,
- - - M12 - N13 - - - M10 86 M12 - PH8 I/O FT_fh - SPI5_MOSI, -
DCMI_HSYNC/PSSI_DE,
EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM1_CH2, TIM12_CH2,
TIM8_CH2N, I2C3_SMBA,
- - - M13 86 M12 - - - - 87 M13 - PH9 I/O FT_h - -
SPI5_NSS, DCMI_D0/PSSI_D0,
EVENTOUT

TIM1_CH1N, TIM5_CH1,
TIM8_CH3, I2C4_SMBA,
- - - K10 87 N14 - - - M11 88 L13 - PH10 I/O FT_h - -
SPI5_RDY, DCMI_D1/PSSI_D1,
DS14258 Rev 5

EVENTOUT

TIM1_CH1, TIM5_CH2,
TIM8_CH3N, I2C4_SCL,
- - - L13 88 P15 - - - N12 89 L12 - PH11 I/O FT_fh - -
I3C1_SCL, DCMI_D2/PSSI_D2,
EVENTOUT

TIM1_BKIN, TIM5_CH3,
TIM8_BKIN, I2C4_SDA,
- - - L12 89 M13 - - - N13 90 K12 - PH12 I/O FT_fh - -
I3C1_SDA, TIM8_CH4N,
DCMI_D3/PSSI_D3, EVENTOUT

- - - - 90 H12 - - - - - - - VSS S - - - -

- - - - 91 J12 - - - L13 91 J12 - VDD S - - - -

TIM1_BKIN, OCTOSPI1_NCLK,
I2C2_SDA, SPI2_NSS/I2S2_WS,
UCPD1_FRSTX, USART3_CK,
L3 - - K11 92 L12 33 51 73 K11 92 P12 34 PB12 I/O FT_fh - -
FDCAN2_RX,
ETH_MII_TXD0/ETH_RMII_TXD0,
UART5_RX, EVENTOUT
87/270
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
88/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM1_CH1N, LPTIM3_IN1,
LPTIM2_CH1, I2C2_SMBA,
(6) SPI2_SCK/I2S2_CK,
M2 52 74 K12 93 R15 34 52 74 L11 93 P13 35 PB13 I/O FT_c UCPD1_CC1
USART3_CTS/USART3_NSS,
FDCAN2_TX, SDMMC1_D0,
UART5_TX, EVENTOUT

TIM1_CH2N, TIM12_CH1,
DS14258 Rev 5

TIM8_CH2N, USART1_TX,
SPI2_MISO/I2S2_SDI,
(6)
N1 53 75 J10 94 N15 35 53 75 M13 94 R14 36 PB14 I/O FT_c USART3_RTS/USART3_DE, UCPD1_CC2
UART4_RTS/UART4_DE,
SDMMC2_D0, LPTIM3_ETR,
EVENTOUT

RTC_REFIN, TIM1_CH3N,
TIM12_CH2, TIM8_CH3N,
USART1_RX,
SPI2_MOSI/I2S2_SDO,

STM32H562xx and STM32H563xx

USART11_CTS/USART11_NSS,
L1 54 76 H10 95 M14 36 54 76 J10 95 R15 37 PB15 I/O FT_h - PVD_IN
UART4_CTS, SDMMC2_D1,
OCTOSPI1_CLK,
ETH_MII_TXD1/ETH_RMII_TXD1,
DCMI_D2/PSSI_D2, UART5_RX,
EVENTOUT

USART3_TX,
- 55 77 J11 96 M15 - 55 77 L12 96 P15 - PD8 I/O FT_h - FMC_D13/FMC_AD13, -
EVENTOUT

- - - - - G12 - - - - - - - VSS S - - - -

USART3_RX, FDCAN2_RX,
- 56 78 H9 97 L13 - 56 78 J9 97 P14 - PD9 I/O FT_h - FMC_D14/FMC_AD14, -
EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

LPTIM2_CH2, USART3_CK,
- 57 79 K13 98 K12 - 57 79 J11 98 N15 - PD10 I/O FT_h - FMC_D15/FMC_AD15, -
EVENTOUT

SAI1_CK1, LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3_NSS,
- 58 80 H8 99 L14 - 58 80 H10 99 N14 38 PD11 I/O FT_h - -
UART4_RX, OCTOSPI1_IO0,
DS14258 Rev 5

SAI2_SD_A,
FMC_A16/FMC_CLE, EVENTOUT

LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
I3C1_SCL, SAI1_D1,
USART3_RTS/USART3_DE,
- 59 81 H11 100 K14 - 59 81 K12 100 N13 39 PD12 I/O FT_fh - -
UART4_TX, OCTOSPI1_IO1,
SAI2_FS_A, FMC_A17/FMC_ALE,
DCMI_D12/PSSI_D12,
EVENTOUT

LPTIM1_CH1, TIM4_CH2,
LPTIM2_CH1, I2C4_SDA,
I3C1_SDA, OCTOSPI1_IO3,
- 60 82 G8 101 L15 - 60 82 K13 101 M15 - PD13 I/O FT_fh - SAI2_SCK_A, -
UART9_RTS/UART9_DE,
FMC_A18, DCMI_D13/PSSI_D13,
LPTIM4_IN1, EVENTOUT

- - 83 J12 102 - - - 83 H12 102 H12 - VSS S - - - -

- - 84 J13 103 - - - 84 H13 103 J13 - VDD S - - - -

TIM4_CH3, UART8_CTS,
K2 61 85 H12 104 K13 - 61 85 H11 104 M14 - PD14 I/O FT_h - UART9_RX, FMC_D0/FMC_AD0, -
89/270

EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
90/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM4_CH4,
UART8_RTS/UART8_DE,
J1 62 86 G10 105 J13 - 62 86 H9 105 L14 - PD15 I/O FT_h - -
UART9_TX, FMC_D1/FMC_AD1,
EVENTOUT

- - - - - - - - - - - - - VDD S - - - -

- - - - - - - - - - - - - VSS S - - - -
DS14258 Rev 5

TIM8_BKIN, UART12_RX,
- - 87 H13 106 K15 - - 87 J12 106 L15 - PG2 I/O FT_h - FMC_A12, LPTIM6_ETR, -
EVENTOUT

TIM8_BKIN2, UART12_TX,
- - 88 G9 107 H14 - - 88 G9 107 K15 - PG3 I/O FT_h - FMC_A13, LPTIM5_ETR, -
EVENTOUT

TIM1_BKIN2,
- - 89 G11 108 J15 - - 89 J13 108 K14 - PG4 I/O FT_h - FMC_A14/FMC_BA0, -
LPTIM4_ETR, EVENTOUT

STM32H562xx and STM32H563xx

TIM1_ETR, FMC_A15/FMC_BA1,
- - 90 F8 109 H15 - - 90 G10 109 K13 - PG5 I/O FT_h - -
EVENTOUT

TIM17_BKIN, I3C1_SDA,
I2C4_SDA, SPI1_RDY,
OCTOSPI1_NCS,
- - 91 G12 110 J14 - - 91 G11 110 J15 - PG6 I/O FT_fh - -
UCPD1_FRSTX, FMC_NE3,
DCMI_D12/PSSI_D12,
EVENTOUT

SAI1_CK2, I3C1_SCL, I2C4_SCL,

SAI1_MCLK_A, USART6_CK,
- - 92 F9 111 H13 - - 92 G8 111 J14 - PG7 I/O FT_fh - UCPD1_FRSTX, FMC_INT, -
DCMI_D13/PSSI_D13,
EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_DE,
- - 93 G13 112 G15 - - 93 F11 112 H14 - PG8 I/O FT_h - -
ETH_PPS_OUT, FMC_SDCLK,
EVENTOUT

- - 94 - 113 - - - 94 - 113 - - VSS S - - - -

- - 95 - 114 - - - 95 - 114 - - VDD S - - - -

DS14258 Rev 5

TIM3_CH1, TIM8_CH1,
I2S2_MCK, SAI1_SCK_A,
USART6_TX, SDMMC1_D0DIR,
J3 63 96 F10 115 G14 37 63 96 F9 115 H15 40 PC6 I/O FT_h - -
FMC_NWAIT, SDMMC2_D6,
OCTOSPI1_IO5, SDMMC1_D6,
DCMI_D0/PSSI_D0, EVENTOUT

TRGIO, TIM3_CH2, TIM8_CH2,

I2S3_MCK, USART6_RX,
SDMMC1_D123DIR, FMC_NE1,
K4 64 97 F11 116 G13 38 64 97 F10 116 G15 41 PC7 I/O FT_h - -
SDMMC2_D7, OCTOSPI1_IO6,
SDMMC1_D7,
DCMI_D1/PSSI_D1, EVENTOUT

TRACED1, TIM3_CH3,
TIM8_CH3, USART6_CK,
UART5_RTS/UART5_DE,
J5 65 98 E9 117 F14 39 65 98 G12 117 G14 42 PC8 I/O FT_h - -
FMC_NE2/FMC_NCE, FMC_INT,
FMC_ALE, SDMMC1_D0,
DCMI_D2/PSSI_D2, EVENTOUT

MCO2, TIM3_CH4, TIM8_CH4,

I2C3_SDA, AUDIOCLK,
F2 66 99 F12 118 F13 40 66 99 G13 118 F14 43 PC9 I/O FT_fh - UART5_CTS, OCTOSPI1_IO0, UCPD1_DB2
FMC_CLE, SDMMC1_D1,
91/270

DCMI_D3/PSSI_D3, EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
92/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

- - - - - - - - - - - G12 - VSS S - - - -

- - - - - - - - - - - G13 - VDD S - - - -

MCO1, TIM1_CH1, TIM8_BKIN2,

I2C3_SCL, SPI1_RDY,
G3 67 100 E10 119 F15 41 67 100 F12 119 F15 44 PA8 I/O FT_fh - USART1_CK, USB_SOF, -
UART7_RX, FMC_NOE,
DS14258 Rev 5

DCMI_D3/PSSI_D3, EVENTOUT

TIM1_CH2, LPUART1_TX,
I2C3_SMBA, SPI2_SCK/I2S2_CK,
H4 68 101 F13 120 E15 42 68 101 E11 120 E15 45 PA9 I/O FT_d - USART1_TX, ETH_MII_TX_ER, UCPD1_DB1
FMC_NWE, DCMI_D0/PSSI_D0,
EVENTOUT

TIM1_CH3, LPUART1_RX,
LPTIM2_IN2, UCPD1_FRSTX,
G5 69 102 E11 121 E14 43 69 102 E10 121 D15 46 PA10 I/O FT_h - USART1_RX, FDCAN2_TX, -
SDMMC1_D0,

STM32H562xx and STM32H563xx

DCMI_D1/PSSI_D1, EVENTOUT

TIM1_CH4, LPUART1_CTS,
SPI2_NSS/I2S2_WS, UART4_RX,
E1 70 103 C13 122 D15 44 70 103 F13 122 C15 47 PA11 I/O FT_u - USART1_CTS/USART1_NSS, -
FDCAN1_RX, USB_DM,
EVENTOUT

TIM1_ETR,
LPUART1_RTS/LPUART1_DE,
SPI2_SCK/I2S2_CK, UART4_TX,
C1 71 104 B13 123 C15 45 71 104 E13 123 B15 48 PA12 I/O FT_u - -
USART1_RTS/USART1_DE,
SAI2_FS_B, FDCAN1_TX,
USB_DP, EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

PA13 (7)
F4 72 105 D12 124 E13 46 72 105 E12 124 A15 49 I/O FT JTMS/SWDIO, EVENTOUT -
(JTMS/SWDIO)

- 74 107 E12 126 D14 47 74 107 C12 126 F12 50 VSS S - - - -

- 75 108 D13 127 E12 48 75 108 C13 127 F13 51 VDD S - - - -

B2 73 106 E13 125 F12 - 73 106 D13 125 H13 - VDDUSB S - - - -

DS14258 Rev 5

LPTIM1_IN2, TIM8_CH1N,
UART8_TX, UART4_TX,
- - - C12 128 B15 - - - D12 128 E12 - PH13 I/O FT_h - -
FDCAN1_TX, DCMI_D3/PSSI_D3,
EVENTOUT

TIM8_CH2N, UART4_RX,
- - - D11 129 D13 - - - D10 129 E13 - PH14 I/O FT_h - FDCAN1_RX, -
DCMI_D4/PSSI_D4, EVENTOUT

TIM8_CH3N,
- - - A13 130 C14 - - - D11 130 D13 - PH15 I/O FT_h - DCMI_D11/PSSI_D11, -
EVENTOUT

TIM5_CH4, SPI2_NSS/I2S2_WS,
- - - B12 131 - - - - B13 131 E14 - PI0 I/O FT_h - DCMI_D13/PSSI_D13, -
EVENTOUT

TIM8_BKIN2,
- - - C11 132 A15 - - - B12 132 D14 - PI1 I/O FT_h - SPI2_SCK/I2S2_CK, -
DCMI_D8/PSSI_D8, EVENTOUT

TIM8_CH4, SPI2_MISO/I2S2_SDI,
- - - D10 133 B14 - - - A13 133 C14 - PI2 I/O FT_h - -
DCMI_D9/PSSI_D9, EVENTOUT

TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
- - - A12 134 A14 - - - C11 134 C13 - PI3 I/O FT_h - -
DCMI_D10/PSSI_D10,
93/270

EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
94/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

- - - B8 135 D9 - - - B10 135 D9 - VSS S - - - -

- - - A8 136 D8 - - - A10 136 C9 - VDD S - - - -

PA14 (7)
E3 76 109 C10 137 B13 49 76 109 A12 137 A14 52 I/O FT JTCK/SWCLK, EVENTOUT -
(JTCK/SWCLK)

JTDI, TIM2_CH1, LPTIM3_IN2,

HDMI_CEC, SPI1_NSS/I2S1_WS,
DS14258 Rev 5

SPI3_NSS/I2S3_WS, SPI6_NSS,
(7)
D4 77 110 B10 138 C13 50 77 110 B11 138 A13 53 PA15(JTDI) I/O FT UART4_RTS/UART4_DE, -
UART7_TX, FMC_NBL1,
DCMI_D11/PSSI_D11, TIM2_ETR,
EVENTOUT

LPTIM3_ETR,
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
C3 78 111 A10 139 D12 51 78 111 C10 139 B14 54 PC10 I/O FT_h - OCTOSPI1_IO1, -
ETH_MII_TXD0/ETH_RMII_TXD0,

STM32H562xx and STM32H563xx

SDMMC1_D2,
DCMI_D8/PSSI_D8, EVENTOUT

LPTIM3_IN1,
SPI3_MISO/I2S3_SDI,
E5 79 112 A9 140 C12 52 79 112 A11 140 B13 55 PC11 I/O FT_h - USART3_RX, UART4_RX, -
OCTOSPI1_NCS, SDMMC1_D3,
DCMI_D4/PSSI_D4, EVENTOUT

TRACED3, TIM15_CH1,
SPI6_SCK,
SPI3_MOSI/I2S3_SDO,
F6 80 113 D9 141 C11 53 80 113 B9 141 A12 56 PC12 I/O FT_h - -
USART3_CK, UART5_TX,
SDMMC1_CK,
DCMI_D9/PSSI_D9, EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

- - - B11 - D11 - - - - - - - VSS S - - - -

- - - A11 - D10 - - - - - - - VDD S - - - -

TIM8_CH4N, UART4_RX,
A3 81 114 C9 142 B12 - 81 114 D9 142 B12 - PD0 I/O FT_h - FDCAN1_RX, UART9_CTS, -
FMC_D2/FMC_AD2, EVENTOUT

UART4_TX, FDCAN1_TX,
DS14258 Rev 5

B4 82 115 B9 143 A13 - 82 115 E9 143 C12 - PD1 I/O FT_h - -

FMC_D3/FMC_AD3, EVENTOUT

TRACED2, TIM3_ETR,
TIM15_BKIN, UART5_RX,
A5 83 116 E8 144 C10 54 83 116 C9 144 D12 - PD2 I/O FT_h - SDMMC1_CMD, WKUP7
DCMI_D11/PSSI_D11,
LPTIM4_ETR, EVENTOUT

SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_NSS,
- 84 117 C8 145 A12 - 84 117 A9 145 D11 - PD3 I/O FT_h - WKUP8
FMC_CLK, DCMI_D5/PSSI_D5,
EVENTOUT

USART2_RTS/USART2_DE,
- 85 118 D8 146 B11 - 85 118 F8 146 D10 - PD4 I/O FT_h - OCTOSPI1_IO4, FMC_NOE, -
EVENTOUT

TIM1_CH4N, SPI2_RDY,
USART2_TX, FDCAN1_TX,
- 86 119 A7 147 A11 - 86 119 D8 147 C11 - PD5 I/O FT_h - -
OCTOSPI1_IO5, FMC_NWE,
EVENTOUT

- - 120 - 148 - - - 120 B7 148 D8 - VSS S - - - -

- - 121 A6 149 D7 - - 121 A7 149 C8 - VDDIO2 S - - - -

95/270
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
96/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

SAI1_D1, SPI3_MOSI/I2S3_SDO,
SAI1_SD_A, USART2_RX,
OCTOSPI1_IO6, SDMMC2_CK,
- 87 122 F7 150 B10 - 87 122 E8 150 B11 - PD6 I/O FT_sh - -
FMC_NWAIT,
DCMI_D10/PSSI_D10,
EVENTOUT

SPI1_MOSI/I2S1_SDO,
DS14258 Rev 5

USART2_CK, OCTOSPI1_IO7,
- 88 123 B7 151 A10 - 88 123 B8 151 A11 - PD7 I/O FT_sh - SDMMC2_CMD, -
FMC_NE1/FMC_NCE,
LPTIM4_OUT, EVENTOUT

- - - - - D6 - - - - - - - VSS S - - - -

SPI1_MISO/I2S1_SDI,
USART6_RX, OCTOSPI1_IO6,
SAI2_FS_B, SDMMC2_D0,
- - 124 E7 152 B9 - - 124 F7 152 C10 - PG9 I/O FT_sh - -
FMC_NE2/FMC_NCE,
DCMI_VSYNC/PSSI_RDY,

STM32H562xx and STM32H563xx

EVENTOUT

SPI1_NSS/I2S1_WS, SAI2_SD_B,
- - 125 C7 153 A9 - - 125 A8 153 B10 - PG10 I/O FT_sh - SDMMC2_D1, FMC_NE3, -
DCMI_D2/PSSI_D2, EVENTOUT

LPTIM1_IN2, SPI1_SCK/I2S1_CK,
USART10_RX,
USART11_RTS/USART11_DE,
- - - - 154 C9 - - 126 E7 154 B9 - PG11 I/O FT_sh - SDMMC2_D2, -
ETH_MII_TX_EN/ETH_RMII_TX_
EN, DCMI_D3/PSSI_D3,
EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

LPTIM1_IN1, PSSI_D15,
SPI6_MISO, USART10_TX,
USART6_RTS/USART6_DE,
- - 126 D7 155 B8 - - 127 C8 155 B8 - PG12 I/O FT_sh - SDMMC2_D3, -
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_NE4, DCMI_D11/PSSI_D11,
LPTIM5_CH1, EVENTOUT
DS14258 Rev 5

TRACED0, LPTIM1_CH1,
SPI6_SCK,
USART10_CTS/USART10_NSS,
USART6_CTS/USART6_NSS,
- - 127 - 156 C8 - - 128 D7 156 A8 - PG13 I/O FT_sh - -
SDMMC2_D6,
ETH_MII_TXD0/ETH_RMII_TXD0,
FMC_A24, LPTIM5_CH2,
EVENTOUT

TRACED1, LPTIM1_ETR,
LPTIM1_CH2, SPI6_MOSI,
USART10_RTS/USART10_DE,
USART6_TX, OCTOSPI1_IO7,
- - 128 - 157 A8 - - 129 C7 157 A7 - PG14 I/O FT_sh - -
SDMMC2_D7,
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_A25, LPTIM5_IN1,
EVENTOUT

- - 129 B4 158 - - - 130 - 158 D7 - VSS S - - - -

- - 130 A3 159 - - - 131 - 159 C7 - VDD S - - - -

SPI4_RDY, USART10_CK,
USART6_CTS/USART6_NSS,
- - 131 B6 160 A7 - - 132 B6 160 B7 - PG15 I/O FT_h - FMC_NCAS, -
DCMI_D13/PSSI_D13,
97/270

EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
98/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

JTDO/TRACESWO, TIM2_CH2,
I2C2_SDA, SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
PB3(JTDO/TRA
C5 89 132 F6 161 B7 55 89 133 E6 161 A10 57 I/O FT_fh - UART12_CTS/UART12_NSS, -
CESWO)
SPI6_SCK, SDMMC2_D2,
CRS_SYNC, UART7_RX,
LPTIM6_ETR, EVENTOUT
DS14258 Rev 5

NJTRST, TIM16_BKIN,
TIM3_CH1, OCTOSPI1_CLK,
LPTIM1_CH2,
SPI1_MISO/I2S1_SDI,
B6 90 133 A5 162 C7 56 90 134 A6 162 A9 58 PB4(NJTRST) I/O FT_h - -
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS, SPI6_MISO,
SDMMC2_D3, UART7_TX,
DCMI_D7/PSSI_D7, EVENTOUT

TIM17_BKIN, TIM3_CH2,
OCTOSPI1_NCLK, I2C1_SMBA,

STM32H562xx and STM32H563xx

SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
D6 91 134 E6 163 A6 57 91 135 C6 163 A6 59 PB5 I/O FT_h - SPI3_MOSI/I2S3_SDO, -
SPI6_MOSI, FDCAN2_RX,
ETH_PPS_OUT, FMC_SDCKE1,
DCMI_D10/PSSI_D10,
UART5_RX, EVENTOUT

TIM16_CH1N, TIM4_CH1,
I3C1_SCL, I2C1_SCL,
HDMI_CEC, I2C4_SCL,
USART1_TX, LPUART1_TX,
E7 92 135 C6 164 B6 58 92 136 A5 164 B6 60 PB6 I/O FT_f - -
FDCAN2_TX, OCTOSPI1_NCS,
FMC_SDNE1,
DCMI_D5/PSSI_D5, UART5_TX,
EVENTOUT
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

TIM17_CH1N, TIM4_CH2,
I3C1_SDA, I2C1_SDA,
I2C4_SDA, USART1_RX,
LPUART1_RX, FDCAN1_TX,
C7 93 136 D6 165 C6 59 93 137 D6 165 B5 61 PB7 I/O FT_fa - WKUP5
SDMMC2_D5, SDMMC2_CKIN,
FMC_NL,
DCMI_VSYNC/PSSI_RDY,
EVENTOUT
DS14258 Rev 5

D8 94 137 B5 166 A5 60 94 138 B5 166 D6 62 BOOT0 I B - - -

TIM16_CH1, TIM4_CH3,
I3C1_SCL, I2C1_SCL, SPI4_RDY,
I2C4_SCL, SDMMC1_CKIN,
E9 95 138 F5 167 B5 61 95 139 E5 167 A5 63 PB8 I/O FT_fhs - UART4_RX, FDCAN1_RX, -
SDMMC2_D4, ETH_MII_TXD3,
SDMMC1_D4,
DCMI_D6/PSSI_D6, EVENTOUT

TIM17_CH1, TIM4_CH4,
I3C1_SDA, I2C1_SDA,
SPI2_NSS/I2S2_WS, I2C4_SDA,
- 96 139 E5 168 A4 - 96 140 A4 168 B4 64 PB9 I/O FT_fhs - SDMMC1_CDIR, UART4_TX, -
FDCAN1_TX, SDMMC2_D5,
SDMMC2_CKIN, SDMMC1_D5,
DCMI_D7/PSSI_D7, EVENTOUT

LPTIM1_ETR, TIM4_ETR,
LPTIM2_CH2, LPTIM2_ETR,
SPI3_RDY, UART8_RX,
- 97 140 D5 169 C5 - 97 141 C5 169 A4 65 PE0 I/O FT_h - -
FDCAN1_RX, SAI2_MCLK_A,
FMC_NBL0, DCMI_D2/PSSI_D2,
EVENTOUT
99/270
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
100/270 Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

LPTIM1_IN2, UART8_TX,
- - 141 C5 170 B4 - - - D5 170 A3 - PE1 I/O FT_h - FDCAN1_TX, FMC_NBL1, -
DCMI_D3/PSSI_D3, EVENTOUT

A9 98 142 A4 171 A3 62 98 142 B4 171 C6 66 VCAP S - - - -

- 99 143 - - - 63 99 143 B3 - - 67 VSS S - - - -

- 100 144 - 172 - 64 100 144 A3 172 - 68 VDD S - - - -

DS14258 Rev 5

TIM8_BKIN, SPI2_RDY,
- - - C4 173 B3 - - - C4 173 D4 - PI4 I/O FT_h - SAI2_MCLK_A, -
DCMI_D5/PSSI_D5, EVENTOUT

TIM8_CH1, SAI2_SCK_A,
- - - B3 174 A2 - - - - 174 C4 - PI5 I/O FT_h - DCMI_VSYNC/PSSI_RDY, -
EVENTOUT

TIM8_CH2, SAI2_SD_A,
- - - A2 175 C4 - - - C3 175 C3 - PI6 I/O FT_h - -
DCMI_D6/PSSI_D6, EVENTOUT

STM32H562xx and STM32H563xx

TIM8_CH3, SAI2_FS_A,
- - - A1 176 A1 - - - A2 176 C2 - PI7 I/O FT_h - -
DCMI_D7/PSSI_D7, EVENTOUT

- - - - - F6 - - - - - F6 - VSS S - - - -

- - - - - F7 - - - - - F7 - VSS S - - - -

- - - - - F8 - - - - - F8 - VSS S - - - -

- - - - - F9 - - - - - F9 - VSS S - - - -

- - - - - F10 - - - - - F10 - VSS S - - - -

- - - - - G6 - - - - - G6 - VSS S - - - -

- - - - - G7 - - - - - G7 - VSS S - - - -

- - - - - G8 - - - - - G8 - VSS S - - - -
 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

STM32H562xx and STM32H563xx

Pin number(1)(2)

UFBGA176+25 SMPS
UFBGA169 SMPS

I/O structure
WLCSP80 SMPS

LQFP100 SMPS

LQFP144 SMPS

LQFP176 SMPS
Pin name

UFBGA176+25

Pin type
UFBGA169

VFQFPN68

Notes
(function

LQFP100

LQFP144

LQFP176
LQFP64
Alternate functions Additional functions
after
reset)(3)(4)

- - - - - G9 - - - - - G9 - VSS S - - - -

- - - - - G10 - - - - - G10 - VSS S - - - -

- - - - - H6 - - - - - H6 - VSS S - - - -

- - - - - H7 - - - - - H7 - VSS S - - - -

- - - - - H8 - - - - - H8 - VSS S - - - -
DS14258 Rev 5

- - - - - H9 - - - - - H9 - VSS S - - - -

- - - - - H10 - - - - - H10 - VSS S - - - -

- - - - - J6 - - - - - J6 - VSS S - - - -

- - - - - J7 - - - - - J7 - VSS S - - - -

- - - - - J8 - - - - - J8 - VSS S - - - -

- - - - - J9 - - - - - J9 - VSS S - - - -

- - - - - J10 - - - - - J10 - VSS S - - - -

- - - - - K6 - - - - - K6 - VSS S - - - -

-
- - - - K7 - - - - - K7 - VSS S - - - -

- - - - - K8 - - - - - K8 - VSS S - - - -

- - - - - K9 - - - - - K9 - VSS S - - - -

- - - - - K10 - - - - - K10 - VSS S - - - -

1. The devices with SMPS correspond to commercial code STM32H563xIxxQ.

2. A non-connected I/O in a given package is configured as an output tied to VSS. When VREF+ pad is not available on a package, the internal voltage reference buffer
(VREFBUF) is not available and must be kept disabled.
101/270

3. PC13, PC14 and PC15 are supplied through the power switch (by VSW). This switch sinks a limited amount of current, hence the use of PC13 to PC15 GPIOs in output mode
is limited: The speed must not exceed 2 MHz with a maximum load of 30 pF. These GPIOs must not be used as current sources (for example to drive a LED).
102/270
4. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends upon the content of the RTC registers that are not reset by the system
reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
5. As a tamper input, only PC13, PI8, PA0, PA1, and PA2 are functional in Standby and VBAT mode. As a tamper output, only PC13, PA1, and PI8 are functional in Standby and
VBAT mode.
6. For the output timing characteristics refer to Table 67.
7. After reset, these pins are configured as JTAG/SW debug alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated too.
DS14258 Rev 5

STM32H562xx and STM32H563xx

 4.3 Alternate functions

STM32H562xx and STM32H563xx

Table 15. Alternate functions AF0 to AF7(1)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/ I2C4/OCTOSPI/ SDMMC1/SPI2/

Port LPTIM3/ I3C1/LPTIM2/3/ I2C1/2/3/4/ CEC/I3C1/LPTIM1/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/
LPTIM1/
SYS PDM_SAI1/ LPUART1/ LPTIM1/2/SPI1/ SPI1/I2S1/SPI2/I2S2/ SPI4/UART4/12/ SPI6/UART7/8/12
TIM1/2/16/17
TIM3/4/5/12/15 OCTOSPI/TIM1/8 I2S1/TIM15/ SPI3/I2S3/SPI4/5/6 USART10/ /USART1/2/3/6/
USART1 USB_PD 10/11

USART2_CTS/
PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR TIM15_BKIN SPI6_NSS SPI3_RDY
USART2_NSS
USART2_RTS/
PA1 - TIM2_CH2 TIM5_CH2 - TIM15_CH1N LPTIM1_IN1 OCTOSPI1_DQS
USART2_DE
PA2 - TIM2_CH3 TIM5_CH3 - TIM15_CH1 LPTIM1_IN2 - USART2_TX
DS14258 Rev 5

PA3 - TIM2_CH4 TIM5_CH4 OCTOSPI1_CLK TIM15_CH2 SPI2_NSS/I2S2_WS SAI1_SD_B USART2_RX

SPI3_NSS/
PA4 - - TIM5_ETR LPTIM2_CH1 - SPI1_NSS/I2S1_WS USART2_CK
I2S3_WS
PA5 - TIM2_CH1 - TIM8_CH1N - SPI1_SCK/I2S1_CK - -
PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO/I2S1_SDI OCTOSPI1_IO3 USART11_TX
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI/I2S1_SDO - USART11_RX
A
PA8 MCO1 TIM1_CH1 - TIM8_BKIN2 I2C3_SCL SPI1_RDY - USART1_CK
PA9 - TIM1_CH2 - LPUART1_TX I2C3_SMBA SPI2_SCK/I2S2_CK - USART1_TX
PA10 - TIM1_CH3 - LPUART1_RX LPTIM2_IN2 - UCPD1_FRSTX USART1_RX
USART1_CTS/
PA11 - TIM1_CH4 - LPUART1_CTS - SPI2_NSS/I2S2_WS UART4_RX
USART1_NSS
LPUART1_RTS/ USART1_RTS/
PA12 - TIM1_ETR - - SPI2_SCK/I2S2_CK UART4_TX
LPUART1_DE USART1_DE
PA13 JTMS/SWDIO - - - - - - -
PA14 JTCK/SWCLK - - - - - - -
103/270

SPI3_NSS/I2S3_
PA15 JTDI TIM2_CH1 LPTIM3_IN2 - HDMI_CEC SPI1_NSS/I2S1_WS SPI6_NSS
WS
 Table 15. Alternate functions AF0 to AF7(1) (continued)
104/270 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/ I2C4/OCTOSPI/ SDMMC1/SPI2/

Port LPTIM3/ I3C1/LPTIM2/3/ I2C1/2/3/4/ CEC/I3C1/LPTIM1/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/
LPTIM1/
SYS PDM_SAI1/ LPUART1/ LPTIM1/2/SPI1/ SPI1/I2S1/SPI2/I2S2/ SPI4/UART4/12/ SPI6/UART7/8/12
TIM1/2/16/17
TIM3/4/5/12/15 OCTOSPI/TIM1/8 I2S1/TIM15/ SPI3/I2S3/SPI4/5/6 USART10/ /USART1/2/3/6/
USART1 USB_PD 10/11

PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - OCTOSPI1_IO1 USART11_CK

PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - OCTOSPI1_IO0 -
SPI3_MOSI/
PB2 RTC_OUT2 - SAI1_D1 TIM8_CH4N SPI1_RDY LPTIM1_CH1 SAI1_SD_A
I2S3_SDO
JTDO/TRACE SPI3_SCK/I2S3_ UART12_CTS/
PB3 TIM2_CH2 - - I2C2_SDA SPI1_SCK/I2S1_CK
SWO CK UART12_NSS
SPI3_MISO/I2S3 SPI2_NSS/
PB4 NJTRST TIM16_BKIN TIM3_CH1 OCTOSPI1_CLK LPTIM1_CH2 SPI1_MISO/I2S1_SDI
_SDI I2S2_WS
DS14258 Rev 5

SPI3_MOSI/
PB5 - TIM17_BKIN TIM3_CH2 OCTOSPI1_NCLK I2C1_SMBA SPI1_MOSI/I2S1_SDO I2C4_SMBA
I2S3_SDO
PB6 - TIM16_CH1N TIM4_CH1 I3C1_SCL I2C1_SCL HDMI_CEC I2C4_SCL USART1_TX

B PB7 - TIM17_CH1N TIM4_CH2 I3C1_SDA I2C1_SDA - I2C4_SDA USART1_RX

PB8 - TIM16_CH1 TIM4_CH3 I3C1_SCL I2C1_SCL SPI4_RDY I2C4_SCL SDMMC1_CKIN
PB9 - TIM17_CH1 TIM4_CH4 I3C1_SDA I2C1_SDA SPI2_NSS/I2S2_WS I2C4_SDA SDMMC1_CDIR

STM32H562xx and STM32H563xx

PB10 - TIM2_CH3 LPTIM3_CH1 LPTIM2_IN1 I2C2_SCL SPI2_SCK/I2S2_CK - USART3_TX
PB11 - TIM2_CH4 - LPTIM2_ETR I2C2_SDA SPI2_RDY SPI4_RDY USART3_RX
PB12 - TIM1_BKIN - OCTOSPI1_NCLK I2C2_SDA SPI2_NSS/I2S2_WS UCPD1_FRSTX USART3_CK
USART3_CTS/
PB13 - TIM1_CH1N LPTIM3_IN1 LPTIM2_CH1 I2C2_SMBA SPI2_SCK/I2S2_CK -
USART3_NSS
USART3_RTS/
PB14 - TIM1_CH2N TIM12_CH1 TIM8_CH2N USART1_TX SPI2_MISO/I2S2_SDI -
USART3_DE
USART11_CTS/
PB15 RTC_REFIN TIM1_CH3N TIM12_CH2 TIM8_CH3N USART1_RX SPI2_MOSI/I2S2_SDO -
USART11_NSS
 Table 15. Alternate functions AF0 to AF7(1) (continued)

STM32H562xx and STM32H563xx

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/ I2C4/OCTOSPI/ SDMMC1/SPI2/

Port LPTIM3/ I3C1/LPTIM2/3/ I2C1/2/3/4/ CEC/I3C1/LPTIM1/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/
LPTIM1/
SYS PDM_SAI1/ LPUART1/ LPTIM1/2/SPI1/ SPI1/I2S1/SPI2/I2S2/ SPI4/UART4/12/ SPI6/UART7/8/12
TIM1/2/16/17
TIM3/4/5/12/15 OCTOSPI/TIM1/8 I2S1/TIM15/ SPI3/I2S3/SPI4/5/6 USART10/ /USART1/2/3/6/
USART1 USB_PD 10/11

PC0 - TIM16_BKIN - - - - SAI1_MCLK_A SPI2_RDY

USART11_RTS/
PC1 TRACED0 - SAI1_D1 - - SPI2_MOSI/I2S2_SDO SAI1_SD_A
USART11_DE
PC2 PWR_CSLEEP TIM17_CH1 TIM4_CH4 - - SPI2_MISO/I2S2_SDI OCTOSPI1_IO5 -
PC3 PWR_CSTOP - SAI1_D3 LPTIM3_CH1 - SPI2_MOSI/I2S2_SDO OCTOSPI1_IO6 -
PC4 - TIM2_CH4 SAI1_CK1 LPTIM2_ETR - I2S1_MCK - USART3_RX
UART12_RTS/
PC5 - TIM1_CH4N SAI1_D3 - PSSI_D15 - SAI1_FS_A
DS14258 Rev 5

UART12_DE
PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK SAI1_SCK_A USART6_TX
PC7 TRGIO - TIM3_CH2 TIM8_CH2 - - I2S3_MCK USART6_RX
C PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - USART6_CK
PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA AUDIOCLK - -
SPI3_SCK/
PC10 - - LPTIM3_ETR - - - USART3_TX
I2S3_CK
SPI3_MISO/
PC11 - - LPTIM3_IN1 - - - USART3_RX
I2S3_SDI
SPI3_MOSI/
PC12 TRACED3 - TIM15_CH1 - - SPI6_SCK USART3_CK
I2S3_SDO
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -
105/270
 Table 15. Alternate functions AF0 to AF7(1) (continued)
106/270 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/ I2C4/OCTOSPI/ SDMMC1/SPI2/

Port LPTIM3/ I3C1/LPTIM2/3/ I2C1/2/3/4/ CEC/I3C1/LPTIM1/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/
LPTIM1/
SYS PDM_SAI1/ LPUART1/ LPTIM1/2/SPI1/ SPI1/I2S1/SPI2/I2S2/ SPI4/UART4/12/ SPI6/UART7/8/12
TIM1/2/16/17
TIM3/4/5/12/15 OCTOSPI/TIM1/8 I2S1/TIM15/ SPI3/I2S3/SPI4/5/6 USART10/ /USART1/2/3/6/
USART1 USB_PD 10/11

PD0 - - - TIM8_CH4N - - - -
PD1 - - - - - - - -
PD2 TRACED2 - TIM3_ETR - TIM15_BKIN - - -
USART2_CTS/
PD3 - - - - - SPI2_SCK/I2S2_CK -
USART2_NSS
USART2_RTS/
PD4 - - - - - - -
USART2_DE
DS14258 Rev 5

PD5 - TIM1_CH4N - - - SPI2_RDY - USART2_TX

PD6 - - SAI1_D1 - - SPI3_MOSI/I2S3_SDO SAI1_SD_A USART2_RX
PD7 - - - - - SPI1_MOSI/I2S1_SDO - USART2_CK
D
PD8 - - - - - - - USART3_TX
PD9 - - - - - - - USART3_RX
PD10 - - - LPTIM2_CH2 - - - USART3_CK
USART3_CTS/

STM32H562xx and STM32H563xx

PD11 - - SAI1_CK1 LPTIM2_IN2 I2C4_SMBA - -
USART3_NSS
USART3_RTS/
PD12 - LPTIM1_IN1 TIM4_CH1 LPTIM2_IN1 I2C4_SCL I3C1_SCL SAI1_D1
USART3_DE
PD13 - LPTIM1_CH1 TIM4_CH2 LPTIM2_CH1 I2C4_SDA I3C1_SDA - -
PD14 - - TIM4_CH3 - - - - -
PD15 - - TIM4_CH4 - - - - -
 Table 15. Alternate functions AF0 to AF7(1) (continued)

STM32H562xx and STM32H563xx

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/ I2C4/OCTOSPI/ SDMMC1/SPI2/

Port LPTIM3/ I3C1/LPTIM2/3/ I2C1/2/3/4/ CEC/I3C1/LPTIM1/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/
LPTIM1/
SYS PDM_SAI1/ LPUART1/ LPTIM1/2/SPI1/ SPI1/I2S1/SPI2/I2S2/ SPI4/UART4/12/ SPI6/UART7/8/12
TIM1/2/16/17
TIM3/4/5/12/15 OCTOSPI/TIM1/8 I2S1/TIM15/ SPI3/I2S3/SPI4/5/6 USART10/ /USART1/2/3/6/
USART1 USB_PD 10/11

PE0 - LPTIM1_ETR TIM4_ETR LPTIM2_CH2 LPTIM2_ETR - SPI3_RDY -

PE1 - LPTIM1_IN2 - - - - - -
PE2 TRACECLK LPTIM1_IN2 SAI1_CK1 - - SPI4_SCK SAI1_MCLK_A USART10_RX
PE3 TRACED0 - - - TIM15_BKIN - SAI1_SD_B USART10_TX
PE4 TRACED1 - SAI1_D2 - TIM15_CH1N SPI4_NSS SAI1_FS_A -
PE5 TRACED2 - SAI1_CK2 - TIM15_CH1 SPI4_MISO SAI1_SCK_A -
PE6 TRACED3 TIM1_BKIN2 SAI1_D1 - TIM15_CH2 SPI4_MOSI SAI1_SD_A -
DS14258 Rev 5

UART12_RTS/
PE7 - TIM1_ETR - - - - UART7_RX
UART12_DE
E UART12_CTS/
PE8 - TIM1_CH1N - - - - UART7_TX
UART12_NSS
UART7_RTS/
PE9 - TIM1_CH1 - - - - UART12_RX
UART7_DE
PE10 - TIM1_CH2N - - - - UART12_TX UART7_CTS
PE11 - TIM1_CH2 - - SPI1_RDY SPI4_NSS OCTOSPI1_NCS -
PE12 - TIM1_CH3N - - - SPI4_SCK - -
PE13 - TIM1_CH3 - - - SPI4_MISO - -
PE14 - TIM1_CH4 - - - SPI4_MOSI - -
PE15 - TIM1_BKIN - TIM1_CH4N - - - USART10_CK
107/270
 Table 15. Alternate functions AF0 to AF7(1) (continued)
108/270 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/ I2C4/OCTOSPI/ SDMMC1/SPI2/

Port LPTIM3/ I3C1/LPTIM2/3/ I2C1/2/3/4/ CEC/I3C1/LPTIM1/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/
LPTIM1/
SYS PDM_SAI1/ LPUART1/ LPTIM1/2/SPI1/ SPI1/I2S1/SPI2/I2S2/ SPI4/UART4/12/ SPI6/UART7/8/12
TIM1/2/16/17
TIM3/4/5/12/15 OCTOSPI/TIM1/8 I2S1/TIM15/ SPI3/I2S3/SPI4/5/6 USART10/ /USART1/2/3/6/
USART1 USB_PD 10/11

PF0 - - - - I2C2_SDA - - -
PF1 - - - - I2C2_SCL - - -
PF2 - - LPTIM3_CH2 LPTIM3_IN2 I2C2_SMBA - UART12_TX USART11_CK
PF3 - - LPTIM3_IN1 - - - - USART11_TX
PF4 - - LPTIM3_ETR - - - - USART11_RX
USART11_CTS/
PF5 - - LPTIM3_CH1 - I2C4_SCL I3C1_SCL UART12_RX
USART11_NSS
DS14258 Rev 5

PF6 - TIM16_CH1 - - - SPI5_NSS SAI1_SD_B UART7_RX

PF7 - TIM17_CH1 - - - SPI5_SCK SAI1_MCLK_B UART7_TX
F
UART7_RTS/
PF8 - TIM16_CH1N - - - SPI5_MISO SAI1_SCK_B
UART7_DE
PF9 - TIM17_CH1N - - - SPI5_MOSI SAI1_FS_B UART7_CTS
PF10 - TIM16_BKIN SAI1_D3 - PSSI_D15 - - -
PF11 - - - - - SPI5_MOSI - -

STM32H562xx and STM32H563xx

PF12 - - - - - - - -
PF13 - - - - I2C4_SMBA - - -
PF14 - - - - - - - -
PF15 - - - - I2C4_SDA I3C1_SDA - -
 Table 15. Alternate functions AF0 to AF7(1) (continued)

STM32H562xx and STM32H563xx

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/ I2C4/OCTOSPI/ SDMMC1/SPI2/

Port LPTIM3/ I3C1/LPTIM2/3/ I2C1/2/3/4/ CEC/I3C1/LPTIM1/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/
LPTIM1/
SYS PDM_SAI1/ LPUART1/ LPTIM1/2/SPI1/ SPI1/I2S1/SPI2/I2S2/ SPI4/UART4/12/ SPI6/UART7/8/12
TIM1/2/16/17
TIM3/4/5/12/15 OCTOSPI/TIM1/8 I2S1/TIM15/ SPI3/I2S3/SPI4/5/6 USART10/ /USART1/2/3/6/
USART1 USB_PD 10/11

PG0 - - - - - - - -
SPI2_MOSI/
PG1 - - - - - - -
I2S2_SDO
PG2 - - - TIM8_BKIN - - - UART12_RX
PG3 - - - TIM8_BKIN2 - - - UART12_TX
PG4 - TIM1_BKIN2 - - - - - -
PG5 - TIM1_ETR - - - - - -
DS14258 Rev 5

PG6 - TIM17_BKIN - I3C1_SDA I2C4_SDA SPI1_RDY - -

PG7 - - SAI1_CK2 I3C1_SCL I2C4_SCL - SAI1_MCLK_A USART6_CK
USART6_RTS/
PG8 - - - TIM8_ETR - SPI6_NSS -
USART6_DE
G
PG9 - - - - - SPI1_MISO/I2S1_SDI - USART6_RX
PG10 - - - - - SPI1_NSS/I2S1_WS - -
USART11_RTS/
PG11 - LPTIM1_IN2 - - - SPI1_SCK/I2S1_CK USART10_RX
USART11_DE
USART6_RTS/
PG12 - LPTIM1_IN1 - - PSSI_D15 SPI6_MISO USART10_TX
USART6_DE
USART10_CTS/ USART6_CTS/
PG13 TRACED0 LPTIM1_CH1 - - - SPI6_SCK
USART10_NSS USART6_NSS
USART10_RTS/
PG14 TRACED1 LPTIM1_ETR - - LPTIM1_CH2 SPI6_MOSI USART6_TX
USART10_DE
USART6_CTS/
PG15 - - - - - SPI4_RDY USART10_CK
USART6_NSS
109/270
 Table 15. Alternate functions AF0 to AF7(1) (continued)
110/270 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/ I2C4/OCTOSPI/ SDMMC1/SPI2/

Port LPTIM3/ I3C1/LPTIM2/3/ I2C1/2/3/4/ CEC/I3C1/LPTIM1/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/
LPTIM1/
SYS PDM_SAI1/ LPUART1/ LPTIM1/2/SPI1/ SPI1/I2S1/SPI2/I2S2/ SPI4/UART4/12/ SPI6/UART7/8/12
TIM1/2/16/17
TIM3/4/5/12/15 OCTOSPI/TIM1/8 I2S1/TIM15/ SPI3/I2S3/SPI4/5/6 USART10/ /USART1/2/3/6/
USART1 USB_PD 10/11

PH0 - - - - - - - -
PH1 - - - - - - - -
PH2 - LPTIM1_IN2 - - - - - -
PH3 - - - - - - - -
PH4 - - - - I2C2_SCL SPI5_RDY - SPI6_RDY
PH5 - - - - I2C2_SDA SPI5_NSS - SPI6_RDY
PH6 - TIM1_CH3N TIM12_CH1 TIM8_CH1 I2C2_SMBA SPI5_SCK - -
DS14258 Rev 5

PH7 - TIM1_CH3 - TIM8_CH1N I2C3_SCL SPI5_MISO - -

H
PH8 - TIM1_CH2N TIM5_ETR TIM8_CH2 I2C3_SDA SPI5_MOSI - -
PH9 - TIM1_CH2 TIM12_CH2 TIM8_CH2N I2C3_SMBA SPI5_NSS - -
PH10 - TIM1_CH1N TIM5_CH1 TIM8_CH3 I2C4_SMBA SPI5_RDY - -
PH11 - TIM1_CH1 TIM5_CH2 TIM8_CH3N I2C4_SCL I3C1_SCL - -
PH12 - TIM1_BKIN TIM5_CH3 TIM8_BKIN I2C4_SDA I3C1_SDA - -

STM32H562xx and STM32H563xx

PH13 - LPTIM1_IN2 - TIM8_CH1N - - - UART8_TX
PH14 - - - TIM8_CH2N - - - -
PH15 - - - TIM8_CH3N - - - -
 Table 15. Alternate functions AF0 to AF7(1) (continued)

STM32H562xx and STM32H563xx

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/ I2C4/OCTOSPI/ SDMMC1/SPI2/

Port LPTIM3/ I3C1/LPTIM2/3/ I2C1/2/3/4/ CEC/I3C1/LPTIM1/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/
LPTIM1/
SYS PDM_SAI1/ LPUART1/ LPTIM1/2/SPI1/ SPI1/I2S1/SPI2/I2S2/ SPI4/UART4/12/ SPI6/UART7/8/12
TIM1/2/16/17
TIM3/4/5/12/15 OCTOSPI/TIM1/8 I2S1/TIM15/ SPI3/I2S3/SPI4/5/6 USART10/ /USART1/2/3/6/
USART1 USB_PD 10/11

PI0 - - TIM5_CH4 - - SPI2_NSS/I2S2_WS - -

PI1 - - - TIM8_BKIN2 - SPI2_SCK/I2S2_CK - -
PI2 - - - TIM8_CH4 - SPI2_MISO/I2S2_SDI - -
PI3 - - - TIM8_ETR - SPI2_MOSI/I2S2_SDO - -
PI4 - - - TIM8_BKIN - - - SPI2_RDY
PI5 - - - TIM8_CH1 - - - -
I
PI6 - - - TIM8_CH2 - - - -
DS14258 Rev 5

PI7 - - - TIM8_CH3 - - - -
PI8 - - - - - - - -
PI9 - - - - - - - -
PI10 - - - - - - - -
PI11 - - - - - - - -
1. Refer to the next table for AF8 to AF15.
111/270
 Table 16. Alternate functions AF8 to AF15(1)
112/270 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

FDCAN1/2/FMC
ETH[MII/RMII)/ FMC[NAND16)/
[NAND16)/FMC CRS/FMC[NAND DCMI/FMC[NAND16)/
Port LPUART1/SAI2 FMC[NAND16)/ FMC[NORmux)/
[NORmux)/FMC 16)/OCTOSPI/S FMC[NORmux)/ LPTIM3/4/5/6/
/SDMMC1/SPI6 OCTOSPI/ FMC[NOR_RAM)/ SYS
[NOR_RAM)/ AI2/SDMMC2/ FMC[NOR_RAM)/ TIM2/UART5
/UART4/5/8 SDMMC2/ FMC[SDRAM_16bit)
OCTOSPI/ TIM8/USB_PD LPTIM5
UART7/9/USB_PD /SDMMC1
SDMMC2/TIM13/14

PA0 UART4_TX SDMMC2_CMD SAI2_SD_B ETH_MII_CRS - - TIM2_ETR EVENTOUT

ETH_MII_RX_CLK
PA1 UART4_RX OCTOSPI1_IO3 SAI2_MCLK_B /ETH_RMII_REF_ - - - EVENTOUT
CLK
PA2 SAI2_SCK_B - - ETH_MDIO - - - EVENTOUT
PA3 - - - ETH_MII_COL - - - EVENTOUT
DCMI_HSYNC/
DS14258 Rev 5

PA4 SPI6_NSS - - - - - EVENTOUT

PSSI_DE
ETH_MII_TX_EN/
PA5 SPI6_SCK - - - PSSI_D14 TIM2_ETR EVENTOUT
ETH_RMII_TX_EN
DCMI_PIXCLK/
PA6 SPI6_MISO TIM13_CH1 - - - - EVENTOUT
PSSI_PDCK
A ETH_MII_RX_DV/
PA7 SPI6_MOSI TIM14_CH1 OCTOSPI1_IO2 ETH_RMII_CRS_ FMC_SDNWE FMC_NWE - EVENTOUT
DV

STM32H562xx and STM32H563xx

PA8 - - USB_SOF UART7_RX FMC_NOE DCMI_D3/PSSI_D3 - EVENTOUT
PA9 - - - ETH_MII_TX_ER FMC_NWE DCMI_D0/PSSI_D0 - EVENTOUT
PA10 - FDCAN2_TX - - SDMMC1_D0 DCMI_D1/PSSI_D1 - EVENTOUT
PA11 - FDCAN1_RX USB_DM - - - - EVENTOUT
PA12 SAI2_FS_B FDCAN1_TX USB_DP - - - - EVENTOUT
PA13 - - - - - - - EVENTOUT
PA14 - - - - - - - EVENTOUT
UART4_RTS/
PA15 - - UART7_TX FMC_NBL1 DCMI_D11/PSSI_D11 TIM2_ETR EVENTOUT
UART4_DE
 Table 16. Alternate functions AF8 to AF15(1) (continued)

STM32H562xx and STM32H563xx

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

FDCAN1/2/FMC
ETH[MII/RMII)/ FMC[NAND16)/
[NAND16)/FMC CRS/FMC[NAND DCMI/FMC[NAND16)/
Port LPUART1/SAI2 FMC[NAND16)/ FMC[NORmux)/
[NORmux)/FMC 16)/OCTOSPI/S FMC[NORmux)/ LPTIM3/4/5/6/
/SDMMC1/SPI6 OCTOSPI/ FMC[NOR_RAM)/ SYS
[NOR_RAM)/ AI2/SDMMC2/ FMC[NOR_RAM)/ TIM2/UART5
/UART4/5/8 SDMMC2/ FMC[SDRAM_16bit)
OCTOSPI/ TIM8/USB_PD LPTIM5
UART7/9/USB_PD /SDMMC1
SDMMC2/TIM13/14

PB0 UART4_CTS - - ETH_MII_RXD2 - - LPTIM3_CH1 EVENTOUT

PB1 - - - ETH_MII_RXD3 - - LPTIM3_CH2 EVENTOUT
PB2 - OCTOSPI1_CLK OCTOSPI1_DQS - SDMMC1_CMD LPTIM5_ETR - EVENTOUT
PB3 SPI6_SCK SDMMC2_D2 CRS_SYNC UART7_RX - - LPTIM6_ETR EVENTOUT
PB4 SPI6_MISO SDMMC2_D3 - UART7_TX - DCMI_D7/PSSI_D7 - EVENTOUT
PB5 SPI6_MOSI FDCAN2_RX - ETH_PPS_OUT FMC_SDCKE1 DCMI_D10/PSSI_D10 UART5_RX EVENTOUT
DS14258 Rev 5

PB6 LPUART1_TX FDCAN2_TX OCTOSPI1_NCS - FMC_SDNE1 DCMI_D5/PSSI_D5 UART5_TX EVENTOUT

DCMI_VSYNC/
PB7 LPUART1_RX FDCAN1_TX SDMMC2_D5 SDMMC2_CKIN FMC_NL - EVENTOUT
PSSI_RDY
PB8 UART4_RX FDCAN1_RX SDMMC2_D4 ETH_MII_TXD3 SDMMC1_D4 DCMI_D6/PSSI_D6 - EVENTOUT
B
PB9 UART4_TX FDCAN1_TX SDMMC2_D5 SDMMC2_CKIN SDMMC1_D5 DCMI_D7/PSSI_D7 - EVENTOUT
PB10 - OCTOSPI1_NCS - ETH_MII_RX_ER - - - EVENTOUT
ETH_MII_TX_EN/
PB11 - - - FMC_NBL1 - - EVENTOUT
ETH_RMII_TX_EN
ETH_MII_TXD0/
PB12 - FDCAN2_RX - - - UART5_RX EVENTOUT
ETH_RMII_TXD0
PB13 - FDCAN2_TX - - SDMMC1_D0 - UART5_TX EVENTOUT
UART4_RTS/
PB14 SDMMC2_D0 - - - - LPTIM3_ETR EVENTOUT
UART4_DE
ETH_MII_TXD1/
PB15 UART4_CTS SDMMC2_D1 OCTOSPI1_CLK - DCMI_D2/PSSI_D2 UART5_RX EVENTOUT
ETH_RMII_TXD1
113/270
 Table 16. Alternate functions AF8 to AF15(1) (continued)
114/270 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

FDCAN1/2/FMC
ETH[MII/RMII)/ FMC[NAND16)/
[NAND16)/FMC CRS/FMC[NAND DCMI/FMC[NAND16)/
Port LPUART1/SAI2 FMC[NAND16)/ FMC[NORmux)/
[NORmux)/FMC 16)/OCTOSPI/S FMC[NORmux)/ LPTIM3/4/5/6/
/SDMMC1/SPI6 OCTOSPI/ FMC[NOR_RAM)/ SYS
[NOR_RAM)/ AI2/SDMMC2/ FMC[NOR_RAM)/ TIM2/UART5
/UART4/5/8 SDMMC2/ FMC[SDRAM_16bit)
OCTOSPI/ TIM8/USB_PD LPTIM5
UART7/9/USB_PD /SDMMC1
SDMMC2/TIM13/14

PC0 SAI2_FS_B FMC_A25 OCTOSPI1_IO7 - FMC_SDNWE - - EVENTOUT

PC1 SAI2_SD_A SDMMC2_CK OCTOSPI1_IO4 ETH_MDC - - - EVENTOUT
PC2 - OCTOSPI1_IO2 - ETH_MII_TXD2 FMC_SDNE0 - - EVENTOUT
PC3 - OCTOSPI1_IO0 - ETH_MII_TX_CLK FMC_SDCKE0 - - EVENTOUT
ETH_MII_RXD0/
PC4 - - - FMC_SDNE0 - - EVENTOUT
ETH_RMII_RXD0
DS14258 Rev 5

ETH_MII_RXD1/
PC5 - - OCTOSPI1_DQS FMC_SDCKE0 - - EVENTOUT
ETH_RMII_RXD1
SDMMC1_D0D
PC6 FMC_NWAIT SDMMC2_D6 OCTOSPI1_IO5 SDMMC1_D6 DCMI_D0/PSSI_D0 - EVENTOUT
IR
SDMMC1_D12
C PC7 FMC_NE1 SDMMC2_D7 OCTOSPI1_IO6 SDMMC1_D7 DCMI_D1/PSSI_D1 - EVENTOUT
3DIR
UART5_RTS/ FMC_NE2/
PC8 FMC_INT FMC_ALE SDMMC1_D0 DCMI_D2/PSSI_D2 - EVENTOUT
UART5_DE FMC_NCE

STM32H562xx and STM32H563xx

PC9 UART5_CTS OCTOSPI1_IO0 - FMC_CLE SDMMC1_D1 DCMI_D3/PSSI_D3 - EVENTOUT
ETH_MII_TXD0/
PC10 UART4_TX OCTOSPI1_IO1 - SDMMC1_D2 DCMI_D8/PSSI_D8 - EVENTOUT
ETH_RMII_TXD0
PC11 UART4_RX OCTOSPI1_NCS - - SDMMC1_D3 DCMI_D4/PSSI_D4 - EVENTOUT
PC12 UART5_TX - - - SDMMC1_CK DCMI_D9/PSSI_D9 - EVENTOUT
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT
 Table 16. Alternate functions AF8 to AF15(1) (continued)

STM32H562xx and STM32H563xx

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

FDCAN1/2/FMC
ETH[MII/RMII)/ FMC[NAND16)/
[NAND16)/FMC CRS/FMC[NAND DCMI/FMC[NAND16)/
Port LPUART1/SAI2 FMC[NAND16)/ FMC[NORmux)/
[NORmux)/FMC 16)/OCTOSPI/S FMC[NORmux)/ LPTIM3/4/5/6/
/SDMMC1/SPI6 OCTOSPI/ FMC[NOR_RAM)/ SYS
[NOR_RAM)/ AI2/SDMMC2/ FMC[NOR_RAM)/ TIM2/UART5
/UART4/5/8 SDMMC2/ FMC[SDRAM_16bit)
OCTOSPI/ TIM8/USB_PD LPTIM5
UART7/9/USB_PD /SDMMC1
SDMMC2/TIM13/14

PD0 UART4_RX FDCAN1_RX - UART9_CTS FMC_D2/FMC_AD2 - - EVENTOUT

PD1 UART4_TX FDCAN1_TX - - FMC_D3/FMC_AD3 - - EVENTOUT
PD2 UART5_RX - - - SDMMC1_CMD DCMI_D11/PSSI_D11 LPTIM4_ETR EVENTOUT
PD3 - - - - FMC_CLK DCMI_D5/PSSI_D5 - EVENTOUT
PD4 - - OCTOSPI1_IO4 - FMC_NOE - - EVENTOUT
PD5 - FDCAN1_TX OCTOSPI1_IO5 - FMC_NWE - - EVENTOUT
DS14258 Rev 5

PD6 - - OCTOSPI1_IO6 SDMMC2_CK FMC_NWAIT DCMI_D10/PSSI_D10 - EVENTOUT

FMC_NE1/
PD7 - - OCTOSPI1_IO7 SDMMC2_CMD - LPTIM4_OUT EVENTOUT
FMC_NCE
FMC_D13/
PD8 - - - - - - EVENTOUT
D FMC_AD13
FMC_D14/
PD9 - FDCAN2_RX - - - - EVENTOUT
FMC_AD14
FMC_D15/
PD10 - - - - - - EVENTOUT
FMC_AD15
PD11 UART4_RX OCTOSPI1_IO0 SAI2_SD_A - FMC_A16/FMC_CLE - - EVENTOUT
PD12 UART4_TX OCTOSPI1_IO1 SAI2_FS_A - FMC_A17/FMC_ALE DCMI_D12/PSSI_D12 - EVENTOUT
UART9_RTS/
PD13 - OCTOSPI1_IO3 SAI2_SCK_A FMC_A18 DCMI_D13/PSSI_D13 LPTIM4_IN1 EVENTOUT
UART9_DE
PD14 UART8_CTS - - UART9_RX FMC_D0/FMC_AD0 - - EVENTOUT
UART8_RTS/
PD15 - - UART9_TX FMC_D1/FMC_AD1 - - EVENTOUT
UART8_DE
115/270
 Table 16. Alternate functions AF8 to AF15(1) (continued)
116/270 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

FDCAN1/2/FMC
ETH[MII/RMII)/ FMC[NAND16)/
[NAND16)/FMC CRS/FMC[NAND DCMI/FMC[NAND16)/
Port LPUART1/SAI2 FMC[NAND16)/ FMC[NORmux)/
[NORmux)/FMC 16)/OCTOSPI/S FMC[NORmux)/ LPTIM3/4/5/6/
/SDMMC1/SPI6 OCTOSPI/ FMC[NOR_RAM)/ SYS
[NOR_RAM)/ AI2/SDMMC2/ FMC[NOR_RAM)/ TIM2/UART5
/UART4/5/8 SDMMC2/ FMC[SDRAM_16bit)
OCTOSPI/ TIM8/USB_PD LPTIM5
UART7/9/USB_PD /SDMMC1
SDMMC2/TIM13/14

PE0 UART8_RX FDCAN1_RX SAI2_MCLK_A - FMC_NBL0 DCMI_D2/PSSI_D2 - EVENTOUT

PE1 UART8_TX FDCAN1_TX - - FMC_NBL1 DCMI_D3/PSSI_D3 - EVENTOUT
PE2 UART8_TX OCTOSPI1_IO2 - ETH_MII_TXD3 FMC_A23 DCMI_D3/PSSI_D3 - EVENTOUT
PE3 - - - - FMC_A19 - - EVENTOUT
PE4 - - - - FMC_A20 DCMI_D4/PSSI_D4 - EVENTOUT
PE5 - - - - FMC_A21 DCMI_D6/PSSI_D6 - EVENTOUT
DS14258 Rev 5

PE6 - - SAI2_MCLK_B - FMC_A22 DCMI_D7/PSSI_D7 - EVENTOUT

PE7 - - OCTOSPI1_IO4 - FMC_D4/FMC_AD4 - - EVENTOUT
PE8 - - OCTOSPI1_IO5 - FMC_D5/FMC_AD5 - - EVENTOUT
E
PE9 - - OCTOSPI1_IO6 - FMC_D6/FMC_AD6 - - EVENTOUT
PE10 - - OCTOSPI1_IO7 - FMC_D7/FMC_AD7 - - EVENTOUT
PE11 - - SAI2_SD_B - FMC_D8/FMC_AD8 - - EVENTOUT

STM32H562xx and STM32H563xx

PE12 - - SAI2_SCK_B - FMC_D9/FMC_AD9 - - EVENTOUT
FMC_D10/
PE13 - - SAI2_FS_B - - - EVENTOUT
FMC_AD10
FMC_D11/
PE14 - - SAI2_MCLK_B - - - EVENTOUT
FMC_AD11
FMC_D12/
PE15 - - - - - - EVENTOUT
FMC_AD12
 Table 16. Alternate functions AF8 to AF15(1) (continued)

STM32H562xx and STM32H563xx

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

FDCAN1/2/FMC
ETH[MII/RMII)/ FMC[NAND16)/
[NAND16)/FMC CRS/FMC[NAND DCMI/FMC[NAND16)/
Port LPUART1/SAI2 FMC[NAND16)/ FMC[NORmux)/
[NORmux)/FMC 16)/OCTOSPI/S FMC[NORmux)/ LPTIM3/4/5/6/
/SDMMC1/SPI6 OCTOSPI/ FMC[NOR_RAM)/ SYS
[NOR_RAM)/ AI2/SDMMC2/ FMC[NOR_RAM)/ TIM2/UART5
/UART4/5/8 SDMMC2/ FMC[SDRAM_16bit)
OCTOSPI/ TIM8/USB_PD LPTIM5
UART7/9/USB_PD /SDMMC1
SDMMC2/TIM13/14

PF0 - - - - FMC_A0 LPTIM5_CH1 - EVENTOUT

PF1 - - - - FMC_A1 LPTIM5_CH2 - EVENTOUT
PF2 - - - - FMC_A2 LPTIM5_IN1 - EVENTOUT
PF3 - - - - FMC_A3 LPTIM5_IN2 - EVENTOUT
PF4 - - - - FMC_A4 - - EVENTOUT
PF5 - - - - FMC_A5 - LPTIM3_IN1 EVENTOUT
DS14258 Rev 5

PF6 - - OCTOSPI1_IO3 - - LPTIM5_CH1 - EVENTOUT

PF7 - - OCTOSPI1_IO2 - - LPTIM5_CH2 - EVENTOUT
F
PF8 - TIM13_CH1 OCTOSPI1_IO0 - - LPTIM5_IN1 - EVENTOUT
PF9 - TIM14_CH1 OCTOSPI1_IO1 - - LPTIM5_IN2 - EVENTOUT
PF10 - OCTOSPI1_CLK - - - DCMI_D11/PSSI_D11 - EVENTOUT
PF11 - OCTOSPI1_NCLK SAI2_SD_B - FMC_NRAS DCMI_D12/PSSI_D12 LPTIM6_CH1 EVENTOUT
PF12 - - - - FMC_A6 - LPTIM6_CH2 EVENTOUT
PF13 - - - - FMC_A7 - LPTIM6_IN1 EVENTOUT
PF14 - - - - FMC_A8 - LPTIM6_IN2 EVENTOUT
PF15 - - - - FMC_A9 - - EVENTOUT
117/270
 Table 16. Alternate functions AF8 to AF15(1) (continued)
118/270 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

FDCAN1/2/FMC
ETH[MII/RMII)/ FMC[NAND16)/
[NAND16)/FMC CRS/FMC[NAND DCMI/FMC[NAND16)/
Port LPUART1/SAI2 FMC[NAND16)/ FMC[NORmux)/
[NORmux)/FMC 16)/OCTOSPI/S FMC[NORmux)/ LPTIM3/4/5/6/
/SDMMC1/SPI6 OCTOSPI/ FMC[NOR_RAM)/ SYS
[NOR_RAM)/ AI2/SDMMC2/ FMC[NOR_RAM)/ TIM2/UART5
/UART4/5/8 SDMMC2/ FMC[SDRAM_16bit)
OCTOSPI/ TIM8/USB_PD LPTIM5
UART7/9/USB_PD /SDMMC1
SDMMC2/TIM13/14

PG0 - - - UART9_RX FMC_A10 - LPTIM4_IN1 EVENTOUT

PG1 - - - UART9_TX FMC_A11 - - EVENTOUT
PG2 - - - - FMC_A12 - LPTIM6_ETR EVENTOUT
PG3 - - - - FMC_A13 LPTIM5_ETR - EVENTOUT
PG4 - - - - FMC_A14/FMC_BA0 - LPTIM4_ETR EVENTOUT
PG5 - - - - FMC_A15/FMC_BA1 - - EVENTOUT
DS14258 Rev 5

PG6 - - OCTOSPI1_NCS UCPD1_FRSTX FMC_NE3 DCMI_D12/PSSI_D12 - EVENTOUT

PG7 - - - UCPD1_FRSTX FMC_INT DCMI_D13/PSSI_D13 - EVENTOUT
PG8 - - - ETH_PPS_OUT FMC_SDCLK - - EVENTOUT

G FMC_NE2/ DCMI_VSYNC/
PG9 - OCTOSPI1_IO6 SAI2_FS_B SDMMC2_D0 - EVENTOUT
FMC_NCE PSSI_RDY
PG10 - - SAI2_SD_B SDMMC2_D1 FMC_NE3 DCMI_D2/PSSI_D2 - EVENTOUT
ETH_MII_TX_EN/

STM32H562xx and STM32H563xx

PG11 - - SDMMC2_D2 - DCMI_D3/PSSI_D3 - EVENTOUT
ETH_RMII_TX_EN
ETH_MII_TXD1/
PG12 - - SDMMC2_D3 FMC_NE4 DCMI_D11/PSSI_D11 LPTIM5_CH1 EVENTOUT
ETH_RMII_TXD1
ETH_MII_TXD0/
PG13 - - SDMMC2_D6 FMC_A24 LPTIM5_CH2 - EVENTOUT
ETH_RMII_TXD0
ETH_MII_TXD1/
PG14 - OCTOSPI1_IO7 SDMMC2_D7 FMC_A25 LPTIM5_IN1 - EVENTOUT
ETH_RMII_TXD1
PG15 - - - - FMC_NCAS DCMI_D13/PSSI_D13 - EVENTOUT
 Table 16. Alternate functions AF8 to AF15(1) (continued)

STM32H562xx and STM32H563xx

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

FDCAN1/2/FMC
ETH[MII/RMII)/ FMC[NAND16)/
[NAND16)/FMC CRS/FMC[NAND DCMI/FMC[NAND16)/
Port LPUART1/SAI2 FMC[NAND16)/ FMC[NORmux)/
[NORmux)/FMC 16)/OCTOSPI/S FMC[NORmux)/ LPTIM3/4/5/6/
/SDMMC1/SPI6 OCTOSPI/ FMC[NOR_RAM)/ SYS
[NOR_RAM)/ AI2/SDMMC2/ FMC[NOR_RAM)/ TIM2/UART5
/UART4/5/8 SDMMC2/ FMC[SDRAM_16bit)
OCTOSPI/ TIM8/USB_PD LPTIM5
UART7/9/USB_PD /SDMMC1
SDMMC2/TIM13/14

PH0 - - - - - - - EVENTOUT
PH1 - - - - - - - EVENTOUT
PH2 - OCTOSPI1_IO4 SAI2_SCK_B ETH_MII_CRS FMC_SDCKE0 - - EVENTOUT
PH3 - OCTOSPI1_IO5 SAI2_MCLK_B ETH_MII_COL FMC_SDNE0 - - EVENTOUT
PH4 - - - - - PSSI_D14 - EVENTOUT
PH5 - - - - FMC_SDNWE - - EVENTOUT
DS14258 Rev 5

PH6 - - - ETH_MII_RXD2 FMC_SDNE1 DCMI_D8/PSSI_D8 - EVENTOUT

PH7 - - - ETH_MII_RXD3 FMC_SDCKE1 DCMI_D9/PSSI_D9 - EVENTOUT
H DCMI_HSYNC/
PH8 - - - - - - EVENTOUT
PSSI_DE
PH9 - - - - - DCMI_D0/PSSI_D0 - EVENTOUT
PH10 - - - - - DCMI_D1/PSSI_D1 - EVENTOUT
PH11 - - - - - DCMI_D2/PSSI_D2 - EVENTOUT
PH12 - - TIM8_CH4N - - DCMI_D3/PSSI_D3 - EVENTOUT
PH13 UART4_TX FDCAN1_TX - - - DCMI_D3/PSSI_D3 - EVENTOUT
PH14 UART4_RX FDCAN1_RX - - - DCMI_D4/PSSI_D4 - EVENTOUT
PH15 - - - - - DCMI_D11/PSSI_D11 - EVENTOUT
119/270
 Table 16. Alternate functions AF8 to AF15(1) (continued)
120/270 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

FDCAN1/2/FMC
ETH[MII/RMII)/ FMC[NAND16)/
[NAND16)/FMC CRS/FMC[NAND DCMI/FMC[NAND16)/
Port LPUART1/SAI2 FMC[NAND16)/ FMC[NORmux)/
[NORmux)/FMC 16)/OCTOSPI/S FMC[NORmux)/ LPTIM3/4/5/6/
/SDMMC1/SPI6 OCTOSPI/ FMC[NOR_RAM)/ SYS
[NOR_RAM)/ AI2/SDMMC2/ FMC[NOR_RAM)/ TIM2/UART5
/UART4/5/8 SDMMC2/ FMC[SDRAM_16bit)
OCTOSPI/ TIM8/USB_PD LPTIM5
UART7/9/USB_PD /SDMMC1
SDMMC2/TIM13/14

PI0 - - - - - DCMI_D13/PSSI_D13 - EVENTOUT

PI1 - - - - - DCMI_D8/PSSI_D8 - EVENTOUT
PI2 - - - - - DCMI_D9/PSSI_D9 - EVENTOUT
PI3 - - - - - DCMI_D10/PSSI_D10 - EVENTOUT
PI4 - - SAI2_MCLK_A - - DCMI_D5/PSSI_D5 - EVENTOUT
DCMI_VSYNC/
PI5 - - SAI2_SCK_A - - - EVENTOUT
DS14258 Rev 5

I PSSI_RDY
PI6 - - SAI2_SD_A - - DCMI_D6/PSSI_D6 - EVENTOUT
PI7 - - SAI2_FS_A - - DCMI_D7/PSSI_D7 - EVENTOUT
PI8 - - - - - - - EVENTOUT
PI9 UART4_RX FDCAN1_RX - - - - - EVENTOUT
PI10 - FDCAN1_RX - ETH_MII_RX_ER - PSSI_D14 - EVENTOUT
PI11 - - - - - PSSI_D15 - EVENTOUT

STM32H562xx and STM32H563xx

1. Refer to the previous table for AF0 to AF7.
STM32H562xx and STM32H563xx Electrical characteristics

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes, and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = VDDA = 3.3 V (for
the 1.71 ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 18.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 19.

Figure 18. Pin loading conditions Figure 19. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19210V MS19211V

DS14258 Rev 5 121/270

238
Electrical characteristics STM32H562xx and STM32H563xx

5.1.6 Power supply scheme

Figure 20. Power supply scheme with SMPS

STM32H5
SMPS disabled
SMPS packages
VDDSMPS VDDSMPS
SMPS
ȝ) 4.7 ȝ) ȝ+
VLXSMPS Switched Mode
floating 100 pF or 200 pF
Power Supply
ȝ) ȝ) step down
converter
VSSSMPS
VCAP1/2
Core domain
100 nF
SMPS enabled LDO
Voltage VDDLDO

VDDIO2 VDDIO2 regulator

ȝ)
100 nF VDDIO2
IOs

Two different possible use cases VDD

100 nF VDD
IOs
VDD
VDD
ȝ)
100 nF VDD
domain
VSS Power switch

Two different possible use cases

Backup
VBAT domain
Battery ȝ) 100 nF

BKUP
IOs
VDD
Two different possible use cases

VDDUSB VDDUSB

ȝ) 100 nF USB FS

IOs

VDDA VDDA
Analog domain
ȝ) 100 nF
Ÿ
VREF+
VREF+ 100 nF VREF-
ȝ)
VSSA

Three different possible use cases ȝ) Defines different use case options

Internal VREFBUF
enabled Define power domaines
MSv71967V3

122/270 DS14258 Rev 5

STM32H562xx and STM32H563xx Electrical characteristics

Figure 21. Power supply scheme with LDO

STM32H5
LDO packages
VDDSMPS
SMPS
VLXSMPS Switched Mode
Power Supply
step down
VSSSMPS converter

VCAP1/2
[ȝ) 100 nF
Core domain
LDO enabled LDO disabled LDO
Voltage
VDDLDO
regulator
VDDIO2 VDDIO2

ȝ) 100 nF
VDDIO2
IOs

Two different possible use cases VDD

100 nF
VDD
IOs
VDD
VDD
ȝ) 100 nF
VDD
domain
VSS Power switch

Two different possible use cases

Backup
VBAT
domain
ȝ) 100 nF
Battery

BKUP
IOs
VDD
Two different possible use cases

VDDUSB VDDUSB
ȝ) 100 nF
USB FS
IOs

VDDA VDDA
ȝ) 100 nF

Ÿ
VREF+ Analog domain
100 nF
VREF+ VREF-
ȝ) VSSA
ȝ)
Three different possible use cases
Defines different use case options
Internal VREFBUF
enabled
Define power domaines
MSv71966V3

Note: Refer to “Getting started with STM32H5 Series hardware development” (AN5711) for more
details.

DS14258 Rev 5 123/270

238
Electrical characteristics STM32H562xx and STM32H563xx

Caution: Each power supply pair must be decoupled with filtering ceramic capacitors as shown
above. These capacitors must be placed as close as possible to or below the appropriate
pins on the underside of the PCB to ensure the good functionality of the device. It is not
recommended to remove filtering capacitors to reduce PCB size or cost. This might cause
incorrect operation of the device.

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 17, Table 18, and Table 19
may cause permanent damage to the device. These are stress ratings only and the
functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability. Device mission profile
(application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended
mission profiles are available on demand.

Table 17. Voltage characteristics(1)

Symbol Ratings Min Max Unit

External main supply voltage (including

VDDx - VSS VDDSMPS(2), VDDA, VDDUSB, VDDIO2(2)(3)(4), -0.3 4.0 V
VBAT, and VREF+)

VDDIOx(4) - I/O supply when HSLV(2) = 0 -0.3 4.0

V
VSS I/O supply when HSLV (2)
=1 -0.3 2.75
min (min(VDD, VDDA, VDDUSB,
Input voltage on FT_xxx pins except FT_c pins VSS - 0.3 V
VDDIO2) + 4.0, 6.0 V)(6)(7)
min (min(VBAT, VDDA, VDDUSB,
Input voltage on FT_t in VBAT mode VSS - 0.3
VDDIO2) + 4.0V, 6.0 V)

VIN(5) Input voltage on TT_xx pins VSS - 0.3 4.0

min (min(VDD, VDDA, VDDUSB,
Input voltage on BOOT0 pin VSS V
VDDIO2) + 4.0, 6.0 V)(6)
Input voltage on FT_c pins VSS - 0.3 5.5
Input voltage on any other pins VSS - 0.3 4.0
VREF+-VDDA Allowed voltage difference for VREF+ > VDDA - 0.4
Variations between different VDDX power pins
|∆VDDx| - 50.0
of the same domain mV
|VSSx-VSS| Variations between all the different ground pins - 50.0
1. All main power (VDD, VDDA, VDDUSB, VDDIO2, VREF+, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always
be connected to the external power supply, in the permitted range.
2. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481.
3. If HSLV = 0.
4. VDDIO1 or VDDIO2. VDDIO1 = VDD.
5. VIN maximum must always be respected. Refer to the maximum allowed injected current values.
6. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
7. This formula must be applied on power supplies related to the I/O structure described by the pin definition table.

124/270 DS14258 Rev 5

STM32H562xx and STM32H563xx Electrical characteristics

Table 18. Current characteristics

Symbol Ratings Max Unit

∑IVDD Total current into sum of all VDD power lines (source)(1) 350
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 350
IVDD Maximum current into each VDD power pin (source)(1) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
IIO(PIN) Output current sunk/sourced by any I/O and control pin 20 mA
(2)
Total output current sunk by sum of all I/Os and control pins 140
∑IIO(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 140
IINJ(PIN)(3)(4) Injected current on FT_xxx, TT_xx, NRST pins -5 / 0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDDIO2, and VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supplies, in the allowed range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os, and does not occur for input voltages
lower than the specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 17 for the
minimum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).

Table 19. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150 °C

TJ Maximum junction temperature 130(1) °C
1. The junction temperature is limited to 105 °C in the VOS0 voltage range.

5.3 Operating conditions

5.3.1 General operating conditions

Table 20. General operating conditions
Symbol Parameter Operating conditions Min Typ Max Unit

Standard operating HSLV(1) = 0 1.71(2) - 3.6

VDD V
voltage HSLV (1)
=1 1.71 (2)
- 2.7
Supply voltage for the
VDDSMPS internal SMPS VDD VDD - VDD V
step-down converter

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Table 20. General operating conditions (continued)

Symbol Parameter Operating conditions Min Typ Max Unit

At least one I/O in PB8, PB9, PD6, PD7,

1.08 - 3.6
PG[9:14] is used, HSLV(1) = 0
PB8, PB9, PD6, PD7,
VDDIO2 PG[9:14] I/Os supply At least one I/O in PB8, PB9, PD6, PD7, V
1.08 - 2.7
voltage PG[9:14] is used, HSLV(1) = 1
PB8, PB9, PD6, PD7, PG[9:14] are not used 0 3.6
USB is used 3.0 - 3.6
VDDUSB USB supply voltage V
USB is not used 0 - 3.6
ADC is used 1.62 -
DAC is used 1.8 -
VDDA Analog supply voltage 3.6 V
VREFBUF is used 2.1 -
ADC, DAC, and VREFBUF are not used 0 -
Backup domain
VBAT - 1.2 - 3.6 V
supply voltage
min (min
(VDD,
VDDA,
VDDUSB,
All I/Os except FT_c and TT_xx -0.3 -
VDDIO2)
+ 3.6V,
5.5 V)
(3)(4)

min (min
VIN I/O input voltage (VBAT, V
VDDA,
VDDUSB,
Input voltage on FT_t in VBAT mode -0.3 -
VDDIO2)
+ 3.6 V,
5.5 V)
(3)(4)

FT_c I/O -0.3 - 5.0

VDDIOx +
TT_xx I/O -0.3 -
0.3

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Table 20. General operating conditions (continued)

Symbol Parameter Operating conditions Min Typ Max Unit
(5)
VOS0
1.30 1.35 1.40
(max frequency for AHB and APB: 250 MHz)
VOS1
1.15 1.20 1.26
(max frequency for AHB and APB: 200 MHz)
Internal regulator ON V
VOS2
1.05 1.10 1.15
(max frequency for AHB and APB: 150 MHz)
VOS3
0.95 1.00 1.05
(max frequency for AHB and APB: 100 MHz)
VCORE
Regulator OFF: VOS0(5) 1.32 1.35 1.40
external VCORE voltage VOS1 1.17 1.20 1.26
must be supplied from V
external regulator on VOS2 1.07 1.10 1.15
VCAP pins VOS3 0.97 1.00 1.05
SVOS3 - 1.0 -
Stop mode SVOS4 - 0.9 - V
SVOS5 - 0.74 -
(5)
VOS0 - - 250
VOS1 - - 200
fHCLK AHB clock frequency MHz
VOS2 - - 150
VOS3 - - 100
VOS0(5) - - 250

fPCLKx APB1, APB2, APB3 VOS1 - - 200

MHz
(x=1,2,3) clock frequency VOS2 - - 150
VOS3 - - 100
LQFP64 See Table 140 for
appropriate thermal
LQFP100
resistance and package.
LQFP144 Power dissipation is
Power dissipation at calculated according to
TA = 85 or 105 °C LQFP176 ambient temperature
PD mW
for suffix 6 or 7 UFBGA169 (TA), maximum junction
versions(6) temperature (TJ), and
UFBGA176 selected thermal
VFQFPN68 resistance.

WLCSP80

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Table 20. General operating conditions (continued)

Symbol Parameter Operating conditions Min Typ Max Unit

LQFP100 See Table 140 for

appropriate thermal
LQFP144 resistance and package.
Power dissipation is
Power dissipation at LQFP176 calculated according to
PD TA = 125 °C mW
ambient temperature
for suffix 3 version(6) UFBGA169
(TA), maximum junction
UFBGA176 temperature (TJ), and
selected thermal
WLCSP80 resistance.

Ambient temperature
Maximum power dissipation -40 - 125
for the suffix 3 version

Ambient temperature Maximum power dissipation -40 - 85

TA for the suffix 6 version °C
In LDO bypass mode -40 - 125

Ambient temperature Maximum power dissipation -40 - 105

for the suffix 7 version In LDO bypass mode -40 - 125

Junction temperature VOS0 -40 - 105

TJ °C
range VOS1, VOS2, and VOS3 -40 - 130
1. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481.
2. When RESET is released functionality is guaranteed down to BOR level 0 minimum voltage.
3. This formula must be applied on power supplies related to the I/O structure described by the pin definition table. Maximum
I/O input voltage is the smallest value between min (VDD, VDDA, VDDIO2) + 3.6 V and 5.5 V.
4. For operation with voltages higher than min (VDD, VDDA, VDDIO2) + 0.3V, the internal pull-up and pull-down resistors must
be disabled.
5. In VOS0 mode the max TJ is 105 °C.
6. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 19).

Table 21. Maximum allowed clock frequencies

Symbol(1)(2) Parameter VOS0 VOS1 VOS2 VOS3 Unit

fCPU CPU 250 200 150 100

fHCLK AHB 250 200 150 100
fPCLK APB 250 200 150 100
- FMC 250 200 150 100
foctospi_ker_ck OCTOSPI[1:2] 250 200 150 100
fsdmmc_ker_ck SDMMC[1:2] 250 200 150 100 MHz
- HDMI_CEC 4 4 4 4
ffdcan_ker_ck FDCAN 250 200 150 100
fI2C_ker_ck I2C[1:4] 250 200 150 100
fI3C_ker_ck I3C 250 200 150 100
flptim_ker_ck LPTIM[1:6] 250 200 150 100

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Table 21. Maximum allowed clock frequencies (continued)

Symbol(1)(2) Parameter VOS0 VOS1 VOS2 VOS3 Unit

TIM[1:8], TIM[12:17] 250 200 150 100

ftim_ker_ck
TIM6/17 64 64 64 64
frng_clk RNG 50 50 50 50
fsai_a_ker_ck
SAI1/2 250 200 150 100
fsai_b_ker_ck
SPI(I2S)1,2,3 125 100 75 50
fspi_ker_ck
SPI4,5,6 125 100 75 50
flpuart_ker_ck LPUART1 250 200 150 100
fusart_ker_ck USART/UART 250 200 150 100 MHz
fusb_ker_ck USB FS 50 50 50 50
fadc_ker_ck_input ADC 250 200 150 100
fadc_ker_ck(3) ADC 125 100 75 50
fdac_ker_ck DAC 250 200 150 100
fucpd_ker_ck USBPD 64 64 64 64
frtc_ker_ck RTC 1 1 1 1
- DCMI 250 200 150 100
1. Specified by design - Not tested in production.
2. The maximum kernel clock frequencies can be limited by the maximum peripheral clock frequency
(refer to each peripheral electrical characteristics).
3. This maximum kernel clock frequency does not consider the maximum ADC clock frequency (refer to
Table 95).

5.3.2 VCAP external capacitor

The stabilization for the embedded LDO regulator is achieved by connecting an external
capacitor CEXT (whose value is specified in Table 22) to the VCAPx (one or two pins,
depending upon the package). Two external capacitors must be connected to VCAP pins
(refer to AN5711 “STM32H5 Series hardware development”).

Figure 22. External capacitor CEXT

C

ESR

R Leak
MS19044V2

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Table 22. Supply voltage and maximum frequency configuration

Symbol Parameter Conditions

CEXT External capacitor for LDO enabled 2.2 μF(1)

ESR Equivalent series resistance of the external capacitor < 100 mΩ
1. This value corresponds to CEXT typical value. A variation of ±20% is tolerated

5.3.3 SMPS step-down converter

The devices embed a high power efficiency SMPS step-down converter requiring external
components.

Table 23. Characteristics of SMPS step-down converter external components

Symbol Parameter Conditions Min Typ Max Unit

Capacitance of external capacitor on VDDSMPS pins - - 4.7(1) - µF

Cin
ESR of external capacitor 2.4 MHz - - 10 mΩ
Cfilt Capacitance of external capacitor on VLXSMPS pin - - 220 - pF
Capacitance of external capacitor on VCAP pin - - 10(1) - µF
COUT
ESR of external capacitor 2.4 MHz - 20 mΩ
Inductance of external inductor on VLXSMPS pin - - 2.2(1) - µH
All packages - - 150
L
Series DC resistance WLCSP80 package, mΩ
- - 300
VDDSMPS > 3 V
DC current at which the inductance drops 30% from the
ISAT - 1 - -
value without current
A
Average current for which the temperature of the
IRMS - 1 - -
inductor is raised 40 °C by the DC current
1. Tolerance: -50% and + 30% for all conditions.

The SMPS current consumption can be determined using the following formula based on
the maximum LDO current consumption provided in Section 5.3.7:
IDDSMPS = IDDLDO × VCORE / (VDD × efficiency)
IDDLDO is the current in LDO configuration given in the following tables, VCORE is the digital
core supply (VCAP), and efficiency is defined in the following curves.

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Figure 23. SMPS efficiency versus load current in Run, Sleep, and Stop modes
with SVOS3 mode, TJ = 30 °C
Efficiency (%)

100

90

VDDSMPS = 1.8V, VOS0

VDDSMPS = 3.3V, VOS0
80 VDDSMPS = 1.8V, VOS1
VDDSMPS = 3.3V, VOS1
VDDSMPS = 1.8V, VOS2
70 VDDSMPS = 3.3V, VOS2
VDDSMPS = 1.8V, VOS3
VDDSMPS = 3.3V, VOS3
60

50

40

30
Current (mA)
1 10 100 1000
MSv71968V1

Note: SVOS3 is equivalent to VOS3 in Run and Sleep modes.

Figure 24. SMPS efficiency versus load current in Run, Sleep, and Stop modes
with SVOS3 mode, TJ = 130 °C
Efficiency (%)
100

90

VDDSMPS = 1.8V, VOS0

80 VDDSMPS = 3.3V, VOS0
VDDSMPS = 1.8V, VOS0
VDDSMPS = 3.3V, VOS0
70 VDDSMPS = 1.8V, VOS1
VDDSMPS = 3.3V, VOS1
VDDSMPS = 1.8V, VOS2
60
VDDSMPS = 3.3V, VOS2
VDDSMPS = 1.8V, VOS3
VDDSMPS = 3.3V, VOS3
50

40

30 Current (mA)
1 10 100 1000 MSv71969V1

Note: SVOS3 is equivalent to VOS3 in Run and Sleep modes.

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Figure 25. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 30 °C

Figure 26. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 130 °C

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5.3.4 Operating conditions at power-up/down

Subject to general operating conditions for TA.
v

Table 24. Operating conditions at power-up/down (regulator ON)

Symbol Parameter Min Max Unit

VDD rise time rate 0 ∞

TVDD
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
TVDDA
VDDA fall time rate 10 ∞
TVDDUSB rise time rate 0 ∞
TVDDUSB μs/V
TVDDUSB fall time rate 10 ∞
TVDDIO2 rise time rate 0 ∞
TVDDIO2
TVDDIO2 fall time rate 10 ∞
TVBAT rise time rate 0 ∞
TVBAT
TVBAT fall time rate 10 ∞

5.3.5 Embedded reset and power control block characteristics

The parameters given in Table 25 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 20.

Table 25. Embedded reset and power control block characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

tRSTTEMPO(2) Reset temporization after BOR0 detection VDD rising - 377 550 μs

Power-on/down reset threshold Rising edge 1.62 1.67 1.71

VPOR/PDR V
(BORH_EN =0) Falling edge 1.58 1.62 1.68

Brownout reset threshold 1 Rising edge 2.04 2.10 2.15

VBOR1
(BORH_EN =1) Falling edge 1.95 2.00 2.06

Brownout reset threshold 2 Rising edge 2.34 2.41 2.47

VBOR2 V
(BORH_EN =1) Falling edge 2.25 2.31 2.37

Brownout reset threshold 3 Rising edge 2.63 2.70 2.78

VBOR3
(BORH_EN =1) Falling edge 2.54 2.61 2.68

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Table 25. Embedded reset and power control block characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

Rising edge 1.90 1.96 2.01

VPVD0 PVD threshold 0
Falling edge 1.81 1.86 1.91
Rising edge 2.05 2.10 2.16
VPVD1 PVD threshold 1
Falling edge 1.96 2.01 2.06
Rising edge 2.19 2.26 2.32
VPVD2 PVD threshold 2
Falling edge 2.10 2.15 2.21
Rising edge 2.35 2.41 2.47
VPVD3 PVD threshold 3 V
Falling edge 2.25 2.31 2.37
Rising edge 2.49 2.56 2.62
VPVD4 PVD threshold 4
Falling edge 2.39 2.45 2.51
Rising edge 2.64 2.71 2.78
VPVD5 PVD threshold 5
Falling edge 2.55 2.61 2.68
Rising edge 2.78 2.86 2.94
VPVD6 PVD threshold 6
Falling edge 2.69 2.76 2.83
VPOR/PDR Hysteresis for power-on/down reset Hysteresis in Run mode - 43 -
Hysteresis voltage of BOR (unless mV
Vhyst_BOR_PVD - - 100 -
BORH_EN = 0) and PVD
IDD_BOR_PVD(2) BOR and PVD consumption from VDD - - - 0.630
µA
IDD_POR_PDR POR and PDR consumption from VDD - 0.8 - 1.2
Rising edge 1.66 1.71 1.76
VAVD0 VDDA voltage monitor 0 threshold
Falling edge 1.56 1.61 1.66
Rising edge 2.06 2.12 2.19
VAVD1 VDDA voltage monitor 1threshold
Falling edge 1.96 2.02 2.08
V
Rising edge 2.42 2.50 2.58
VAVD2 VDDA voltage monitor 2 threshold
Falling edge 2.35 2.42 2.49
Rising edge 2.74 2.83 2.91
VAVD3 VDDA voltage monitor 3 threshold
Falling edge 2.64 2.72 2.80
VIO2VM VDDIO2 voltage monitor threshold - - 0.9 - V
Vhyst_AVD Hysteresis of VDDA voltage monitor - - 100 - mV
Power voltage detector consumption
IDD_AVD_IO2VM(2) - - - 0.25
from VDD (AVD, IO2VM)
µA
Analog voltage detector consumption
IDD_AVD_A(2) - - - 0.25
from VDDA (resistor bridge)
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Specified by design - Not tested in production

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5.3.6 Embedded reference voltage

The parameters given in Table 26 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 20.

Table 26. Embedded reference voltage

Symbol Parameter Conditions Min Typ Max Unit

VREFINT(1) Internal reference voltage -40 °C < TJ < +130 °C 1.180 1.216 1.255 V
ADC sampling time when reading the
tS_vrefint(2)(3) - 4.3 - -
internal reference voltage
VBAT sampling time when reading the
tS_vbat 9 - - µs
internal VBAT voltage
Start time of reference voltage buffer
tstart_vrefint(3) - - - 4.4
when the ADC is enabled
Irefbuf(3) Reference buffer consumption for ADC VDD = 3.3 V 9 13.5 23 µA
Internal reference voltage spread over
∆VREFINT(3) -40 °C < TJ < +130 °C - 5 15 mV
the temperature range
Average temperature
TCoeff Average temperature coefficient - 20 70 ppm/°C
coefficient
VDDcoeff Average voltage coefficient 3.0 V < VDD < 3.6 V - 10 1370 ppm/V
(3)
VREFINT_DIV1 1/4 reference voltage - 25 -
VREFINT_DIV2(3) 1/2 reference voltage - - 50 - %VREFINT
VREFINT_DIV3 (3) 3/4 reference voltage - 75 -
1. VREFINT does not take into account package and soldering effects.
2. The shortest sampling time for the application can be determined by multiple iterations.
3. Specified by design - Not tested in production.

Table 27. Internal reference voltage calibration value

Symbol Parameter Memory address

VREFINT_CAL Raw data acquired at 30 °C, VDDA = 3.3 V 0x08FF F810 - 0x08FF F811

5.3.7 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.

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• All peripherals are disabled except when explicitly mentioned.

• The flash memory access time is adjusted with the minimum wait-state number,
depending on the fHCLK frequency (refer to the tables “FLASH recommended number
of wait states and programming delay” available in the reference manual).
• When the peripherals are enabled, the AHB clock frequency is the CPU frequency and
the APB clock frequency is AHB frequency.
The parameters given in the following tables are derived from tests performed under supply
voltage conditions summarized in Table 20, and, unless otherwise specified, at ambient
temperature.
The maximum current consumption is given for LDO regulator ON.

Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory, 2-way instruction cache ON, PREFETCH ON

Max(1)(2)
fHCLK Typ Typ
Symbol Parameter Conditions Unit
(MHz) LDO SMPS TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 130 °C

250 32.1 17.5 37 65 87 -

VOS0 215 27.9 15.0 32 60 82 -
200 25.7 13.8 30 59 81 -
200 22.1 11.0 25 45 62 93
180 20.3 10.1 23 43 59 90
VOS1
All peripherals 168 18.8 9.3 21 42 58 89
disabled 150 16.9 8.5 20 40 56 88
150 15.4 7.4 17 33 47 73
VOS2
100 10.8 5.2 13 28 41 68
100 9.8 4.5 11 23 34 55
VOS3 60 6.4 3.0 8.0 20 30 52
Supply current
IDD(Run) 25 3.2 1.7 5.0 17 27 49 mA
in Run mode
250 86.8 49.8 90 118 140 -
VOS0 215 75.0 43.2 78 107 128 -
200 69.5 40.1 72 102 123 -
200 60.7 31.7 62 82 99 130
VOS1 180 55.1 28.5 56 76 92 124
All peripherals
150 45.8 23.4 47 68 84 116
enabled
150 41.9 20.0 43 59 72 98
VOS2
100 28.5 13.8 30 45 58 85
100 25.9 11.7 27 39 49 71
VOS3 60 16.2 7.5 17 29 40 61
25 7.5 3.8 9.0 21 31 53

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1. Evaluated by characterization - Not tested in production.

2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption.

Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory, 1-way instruction cache ON, PREFETCH ON
Max(1)(2)
fHCLK Typ Typ
Symbol Parameter Conditions Unit
(MHz) LDO SMPS TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 130 °C

250 29.2 15.9 34 62 84 -

VOS0
200 23.3 12.5 28 56 78 -
200 20.1 10.0 23 43 59 91
VOS1 180 18.5 9.2 21 41 57 89
Supply current All peripherals
IDD(Run) 150 15.4 7.8 18 38 54 86 mA
in Run mode disabled
150 14.0 6.7 16 32 45 71
VOS2
100 9.8 4.8 12 27 40 67
100 8.9 4.2 10 22 33 54
VOS3
25 3.0 1.6 4.0 17 27 49
1. Evaluated by characterization - Not tested in production.
2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption.

Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from SRAM with cache 1-way
Max(1)(2)
Symbol

fHCLK Typ Typ

Parameter Conditions Unit
(MHz) LDO SMPS TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 130 °C

250 27.8 15.5 32 61 82 -

VOS0 215 24.1 13.4 29 57 79 -
200 22.1 12.3 27 55 77 -
200 19.1 9.9 22 42 58 90
VOS1 180 17.6 9.1 20 40 56 88
IDD Supply current All peripherals
150 14.6 7.6 22 42 58 90 mA
(Run) in Run mode disabled
150 13.3 6.6 17 37 53 85
VOS2
100 9.4 4.7 11 27 40 66
100 8.5 4.1 10 22 33 54
VOS3 60 5.6 2.8 7 19 30 51
25 2.9 1.6 4 16 27 48
1. Evaluated by characterization - Not tested in production.
2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption.

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Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from SRAM with cache 2-way
Max(1)(2)
fHCLK Typ Typ
Symbol Parameter Conditions Unit
(MHz) LDO SMPS TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 130 °C

250 30.8 17.2 35 64 86 -

VOS0 215 26.7 14.4 31 60 81 -
200 24.6 13.3 29 58 80 -
200 21.2 10.5 24 44 61 93
180 19.5 9.7 22 42 58 90
VOS1
Supply current All peripherals 168 18.0 9.0 21 41 57 89
IDD(Run) mA
in Run mode disabled 150 16.2 8.4 19 39 55 87
150 14.8 7.2 17 33 46 72
VOS2
100 10.3 5.1 12 28 41 67
100 9.4 4.5 11 23 33 55
VOS3 60 6.1 2.9 8.0 20 30 52
25 3.2 1.7 5.0 17 27 49
1. Evaluated by characterization - Not tested in production.
2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption.

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Table 32. Typical consumption in Run mode with CoreMark running

from flash memory and SRAM(1)
Conditions
fHCLK Typ Typ Typ Typ
Symbol Parameter Unit Unit
(MHz) LDO SMPS LDO SMPS
Peripheral Code

250 32.1 17.5 128.6 70.1

All peripherals
200 22.1 10.97 110.7 54.8
disabled,
instruction cache FLASH 168 18.8 9.3 111.8 55.6
2-way,
150 15.4 8.5 102.7 56.9
prefetch ON
100 9.8 4.5 97.9 45.3

All peripherals 250 29.2 15.9 116.6 63.8

disabled, 200 20.1 12.5 100.4 62.7
instruction cache FLASH
1-way, 150 14.0 10.0 93.3 66.4
prefetch ON 100 8.9 4.2 88.9 41.7
Supply current
IDD(Run) mA μA/MHz
in Run mode 250 30.8 17.2 123.3 68.7
All peripherals 200 21.2 10.5 106.2 52.6
disabled,
SRAM 168 18.0 9.0 107.3 53.4
instruction cache
2-way 150 14.8 7.2 98.5 48.2
100 9.4 4.5 94.1 44.6
250 27.8 15.5 111.1 61.9
All peripherals
disabled, 200 19.1 9.9 95.4 49.3
SRAM
instruction cache 150 13.3 6.6 88.9 43.8
1-way
100 8.5 4.1 84.9 40.7
1. Evaluated by characterization - Not tested in production.

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Table 33. Typical consumption in Run mode with SecureMark running from
flash memory and SRAM(1)
Conditions
fHCLK Typ Typ Typ Typ
Symbol Parameter Unit Unit
(MHz) LDO SMPS LDO SMPS
Peripheral Code

250 34.1 17.9 136.3 71.8

180 21.8 10.6 120.9 58.8
All peripherals disabled,
instruction cache 2-way, FLASH 168 20.1 9.8 119.7 58.5
prefetch ON
150 24.9 7.7 166.2 51.2
Supply 100 10.6 4.8 106.0 47.6
IDD(Run) current in mA μA/MHz
Run mode 250 31.3 16.6 125.2 66.3
180 20.1 9.8 111.6 54.5
All peripherals disabled,
instruction cache 1-way, FLASH 168 18.5 9.1 110.4 54.2
prefetch ON
150 18.8 7.2 125.1 47.7
100 9.8 4.5 98.3 44.5
1. Evaluated by characterization - Not tested in production.

Table 34. Typical and maximum current consumption in Sleep mode

Max(1) (2)
fHCLK Typ Typ
Symbol Parameter Conditions Unit
(MHz) LDO SMPS TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C

250 7.3 4.2 12 40 61 -

VOS0
200 5.8 3.3 10 38 60 -
200 4.8 2.6 8 27 43 75
180 4.8 2.6 8 27 43 75
VOS1
Supply current All peripherals 168 4.3 2.3 7 26 42 74
IDD(sleep) mA
in sleep mode disabled 150 3.9 2.2 7 26 42 74
150 3.5 1.9 6 21 34 60
VOS2
100 2.8 1.6 5 20 33 59
100 2.5 1.4 4 16 26 48
VOS3
60 2.0 1.2 4 15 26 47
1. Evaluated by characterization - Not tested in production.
2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption.

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Table 35. Typical and maximum current consumption in Stop mode

Max(1) (2)
Typ Typ
Symbol Parameter Conditions Unit
LDO SMPS TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 130 °C

SVOS3 0.37 0.09 2.00 13.98 24.00 44.39

Flash memory in
low power mode, SVOS4 0.27 0.07 1.40 10.48 18.37 34.76
SRAMs ON
SVOS5 0.19 0.06 0.86 7.08 12.88 25.31
Flash memory in SVOS3 0.38 0.10 2.02 14.01 24.06 44.55
normal mode,
SRAMs ON SVOS4 0.29 0.09 1.42 10.52 18.46 34.88
Supply current
IDD(stop) Flash memory in SVOS3 0.34 0.09 1.93 13.28 22.75 41.99 mA
in Stop
low power mode,
SVOS4 0.25 0.07 1.35 9.87 17.33 32.65
SRAMs OFF except
SRAM2 16 Kbytes ON SVOS5 0.17 0.05 0.81 6.46 11.68 22.86
Flash memory in SVOS3 0.35 0.10 1.95 13.45 23.02 42.52
low power mode,
SVOS4 0.26 0.08 1.36 10.01 17.52 33.10
SRAMs OFF except
SRAM2 ON SVOS5 0.17 0.08 0.82 6.59 11.92 23.37
1. Evaluated by characterization - Not tested in production.
2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption.

Table 36. Typical and maximum current consumption in Standby mode

Conditions Typ(1) Max(1)

Symbol Parameter Unit
Backup RTC and TJ = TJ = TJ = TJ =
1.8 V 2.4 V 3V 3.3 V
RAM LSE(2) 25 °C 85 °C 105 °C 130 °C

Supply OFF OFF 2.58 2.78 3.01 3.19 5.9 11.7 21.2 53
current in ON OFF 3.79 4.05 4.38 4.63 8.2 21.0 37.0 90
IDD(standby) standby μA
mode, OFF ON 2.91 3.15 3.47 3.67 6.9 12.9 22.5 55
IWDG OFF ON ON 4.16 4.46 4.85 5.12 9.2 22.2 38.3 92
1. Evaluated by characterization - Not tested in production.
2. LSE is in medium-low drive mode.

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Table 37. Typical and maximum current consumption in VBAT mode(1)

v

Conditions Typ Max

Symbol Parameter Unit
Backup RTC and TJ = TJ = TJ = TJ =
1.8 V 2.4 V 3V 3.3 V
RAM LSE(2) 25 °C 85 °C 105 °C 130 °C

OFF OFF 0.01 0.01 0.02 0.02 0.2 2.45 6.2 19.0

Supply current ON OFF 1.11 1.14 1.17 1.29 4.5 16.05 30.0 72.2
IDD(VBAT) μA
in VBAT mode OFF ON 0.45 0.46 0.48 0.59 1.2 3.65 7.5 21.0
ON ON 1.56 1.57 1.62 1.84 5.5 17.25 31.3 74.2
1. Evaluated by characterization - Not tested in production.
2. LSE is in medium-low drive mode.

I/O system current consumption

All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 58.
To estimate the current consumption for the output pins, consider also external pull-downs
or loads.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the Schmitt trigger
circuits used to discriminate the input value. Unless this specific configuration is required by
the application, this current consumption can be avoided by configuring the I/Os in analog
mode. This is notably the case of ADC input pins, to be configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done by using pull-up/down resistors, or by configuring the pins in
output mode.
In addition to the internal peripheral current consumption, the I/Os used by an application
also contribute to the current consumption. When an I/O pin switches, it uses the current
from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the
capacitive load (internal or external) connected to the pin:

I SW = V DDx × f SW × C L

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

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On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration
• All peripherals are disabled unless otherwise mentioned
• The I/O compensation cell is enabled
• fHCLK is the CPU clock, fPCLK = frcc_cpu_ck, and fHCLK = frcc_cpu_ck.
The given value is calculated by measuring the difference of current consumption:
• with all peripherals clocked off
• with only one peripheral clocked on
• frcc_cpu_ck = 250 MHz (Scale 0), frcc_cpu_ck = 200 MHz (Scale 1), frcc_cpu_ck = 150 MHz
(Scale 2), frcc_cpu_ck= 100 MHz (Scale 3)
• the ambient operating temperature is 25 °C and VDD = 3.0 V

Table 38. Peripheral current consumption in Sleep mode

IDD (typ)
Bus Peripheral Unit
VOS0 VOS1 VOS2 VOS3

SRAM1 0.9 0.85 0.78 0.7

BKPRAM 0.95 0.89 0.82 0.74
CORDIC 0.5 0.45 0.42 0.4
CRC 0.22 0.21 0.18 0.18
DCACHE 0.66 0.59 0.55 0.51
ETH 11.33 10 9.13 8.32
FLASH 10.19 8.87 8.09 7.35
AHB1 μA/MHz
FMAC 2.07 1.84 1.68 1.56
GPDMA1 0.62 0.55 0.51 0.45
GPDMA2 0.45 0.43 0.38 0.35
GTZC1 1.19 1.05 0.97 0.9
ICACHE 0.86 0.81 0.75 0.67
RAMCFG 0.88 0.79 0.71 0.67
AHB1 1.09 0.94 0.86 0.79

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Table 38. Peripheral current consumption in Sleep mode (continued)

IDD (typ)
Bus Peripheral Unit
VOS0 VOS1 VOS2 VOS3

ADC12 2.35 2.1 1.9 1.74

DAC1 1.35 1.19 1.07 0.98
DCMI 3.49 3.09 2.83 2.55
GPIOA 0.1 0.08 0.07 0.08
GPIOB 0.07 0.06 0.05 0.05
GPIOC 0.08 0.05 0.04 0.04
GPIOD 0.09 0.06 0.05 0.04
GPIOE 0.09 0.09 0.08 0.05
GPIOF 0.06 0.08 0.08 0.05
AHB2 μA/MHz
GPIOG 0.07 0.07 0.06 0.04
GPIOH 0.07 0.07 0.05 0.06
GPIOI 0.07 0.07 0.06 0.04
HASH1 1.37 1.2 1.1 1
PKA 5.43 4.78 4.37 3.98
RNG1 1.12 0.99 0.9 0.82
SRAM2 1.33 1.18 1.06 0.96
SRAM3 1.5 1.33 1.22 1.1
AHB2 1.59 1.39 1.29 1.16
FMC 9.73 8.48 7.69 6.95
OSPI1 2.88 2.54 2.29 2.08
AHB4 SDMMC1 8.71 7.64 6.98 6.36 uA/MHz
SDMMC2 8.46 7.45 6.82 6.2
AHB4 0.36 0.32 0.32 0.28

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Table 38. Peripheral current consumption in Sleep mode (continued)

IDD (typ)
Bus Peripheral Unit
VOS0 VOS1 VOS2 VOS3

CEC 0.15 0.15 0.14 0.11

CRS 0.22 0.23 0.20 0.19
FDCAN1 6.37 5.63 5.14 4.70
I2C1 0.57 0.5 0.49 0.42
I2C2 0.57 0.52 0.5 0.46
I3C1 0.28 0.27 0.28 0.25
LPTIM2 0.91 0.81 0.75 0.69
SPI2 1.04 0.93 0.89 0.78
SPI3 1.00 0.92 0.85 0.76
TIM12 1.41 1.26 1.18 1.06
TIM13 0.92 0.82 0.77 0.70
TIM14 0.89 0.78 0.75 0.66
TIM2 2.86 2.51 2.30 2.11
TIM3 2.52 2.21 2.03 1.87
TIM4 2.43 2.15 1.96 1.79
TIM5 2.79 2.48 2.26 2.06
APB1 μA/MHz
TIM6 0.54 0.49 0.45 0.42
TIM7 0.56 0.5 0.48 0.43
UART12 1.17 1.06 0.95 0.88
UART4 1.12 0.98 0.93 0.83
UART5 1.09 0.99 0.93 0.84
UART7 1.28 1.14 1.05 0.93
UART8 1.17 1.06 0.94 0.86
UART9 1.12 1.00 0.90 0.84
UCPD1 1.1 1.00 0.90 0.84
USART10 1.35 1.22 1.14 1.02
USART11 1.24 1.11 1.04 0.94
USART2 1.42 1.29 1.19 1.07
USART3 1.35 1.24 1.14 1.02
USART6 1.19 1.08 1.02 0.92
WWDG1 0.39 0.35 0.35 0.30
APB1 1.85 1.61 1.49 1.34

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Table 38. Peripheral current consumption in Sleep mode (continued)

IDD (typ)
Bus Peripheral Unit
VOS0 VOS1 VOS2 VOS3

SAI1 1.13 0.99 0.93 0.82

SAI2 1.06 0.9 0.85 0.75
SPI1 1.03 0.91 0.85 0.75
SPI4 1.03 0.89 0.83 0.73
SPI6 1.03 0.9 0.85 0.74
TIM1 4.35 3.86 3.52 3.2
APB2 TIM15 2.08 1.84 1.69 1.54 μA/MHz
TIM16 1.43 1.26 1.16 1.05
TIM17 1.44 1.25 1.17 1.05
TIM8 4.33 3.82 3.5 3.18
USART1 1.24 1.11 1.02 0.91
USBFS 2.53 2.22 2.04 1.84
APB2 1.04 0.92 0.84 0.77
I2C3 2.43 2.14 1.93 1.76
I2C4 2.37 2.08 1.89 1.73
LPTIM1 0.92 0.82 0.75 0.67
LPTIM3 0.88 0.77 0.71 0.65
LPTIM4 0.49 0.45 0.41 0.37
LPTIM5 0.84 0.76 0.69 0.63
APB3 LPTIM6 0.93 0.82 0.76 0.70 uA/MHz
LPUART1 0.84 0.74 0.66 0.63
RTCAPB 1.93 1.70 1.54 1.38
SBS 0.45 0.41 0.38 0.34
SPI5 1.05 0.93 0.84 0.75
VREFBUF 0.08 0.08 0.07 0.05
APB3 0.64 0.57 0.53 0.48

Wake-up time from low-power modes

The times given in Table 39 are measured starting from the wake-up event trigger up to the
first instruction executed by the CPU:
• for Stop or Sleep modes: the wake-up event is WFE.
• WKUP (PA0) pin is used to wake-up from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD = 3.0 V.

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Table 39. Low-power mode wake-up timings(1)

Symbol Parameter Conditions Typ Max Unit

Instruction cache enabled 15 16 CPU

Wake-up time from
tWUSLEEP clock
Sleep mode Instruction cache disabled 15 16 cycles
SVOS3, HSI 64 MHz, flash memory in normal mode 4.0 4.8
SVOS3, HSI 64 MHz, flash memory in low-power mode 7.9 11.5
SVOS4, HSI 64 MHz, flash memory in normal mode 13.8 16.0
SVOS4, HSI 64 MHz, flash memory in low-power mode 17.7 21.9

Wake-up time from SVOS5, HSI 64 MHz, flash memory in low-power mode 31.4 36.8
tWUSTOP
Stop mode SVOS3, CSI 4 MHz, flash memory in normal mode 25.5 31.0 µs
SVOS3, CSI 4 MHz, flash memory in low power mode 27.7 34.2
SVOS4, CSI 4 MHz, flash memory in normal mode 35.3 40.8
SVOS4, CSI 4 MHz, flash memory in low-power mode 37.5 44.0
SVOS5, CSI 4 MHz, flash memory in low-power mode 51.2 58.9
Wake-up time from
tWUSTBY VCAP capacitors discharged 506.0 653.6
Standby mode
1. Evaluated by characterization - Not tested in production.

5.3.8 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal must respect the Table 40 in addition to Table 58. The external
clock can be low-swing (analog) or digital. In case of a low-swing analog input clock, the
clock squarer must be activated (refer to RM0481).

Table 40. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock External digital/analog

fHSE_ext 4 25 50 MHz
source frequency clock
Digital OSC_IN input
VHSEH 0.7 VDD - VDD
high-level voltage
External digital clock V
Digital OSC_IN input
VHSEL VSS - 0.3 VDD
low-level voltage
Digital OSC_IN input
tw(HSEH) / tw(HSEL)(2) External digital clock 7 - - ns
high or low time

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Table 40. High-speed external user clock characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Analog low-swing
Visw(HSEH)
OSC_IN peak-to-peak 0.2 - 2/3 VDD V
(VHSEH -VHSEL)(3) External analog low
amplitude
swing clock
Analog low-swing
DuCyHSE 45 50 55 %
OSC_IN duty cycle
Analog low-swing
External analog low
tr(HSE) / tf(HSE) OSC_IN rise and fall 0.05 / fHSE_ext - 0.3 / fHSE_ext ns
swing clock, 10% to 90%
times
1. Specified by design - Not tested in production..
2. The rise and fall times for a digital input signal are not specified, but the VHSEH and VHSEL conditions must be fulfilled
anyway.
3. The DC component of the signal must ensure that the signal peaks are located between VDD and VSS.

Figure 27. High-speed external clock source AC timing diagram

VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t

THSE

External fHSE_ext
IL
clock source OSC_IN
STM32

ai17528b

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal must respect the Table 41 in addition to Table 58. The external
clock can be low-swing (analog) or digital. In case of a low-swing analog input clock, the
clock squarer must be activated (refer to RM0481).

Table 41. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fLSE_ext External digital/analog clock - 32.768 1000 kHz
frequency
Digital OSC32_IN input
VLSEH 0.7 VDD - VDD
high-level voltage
External digital clock V
Digital OSC32_IN input
VLSEL VSS - 0.3 VDD
low-level voltage

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Table 41. Low-speed external user clock characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Digital OSC_IN input high

tw(LSEH)/tw(LSEL) External digital clock 250 - - ns
or low time
Analog low-swing OSC_IN
Visw_H 0.6 - 1.225
high-level voltage
Analog low-swing OSC_IN
Visw_L 0.35 - 0.8 V
low-level voltage External analog low swing
ViswLSE Analog low-swing OSC_IN clock
0.5 - 0.875
(VLSEH -VLSEL) peak-to-peak amplitude
Analog low-swing OSC_IN
DuCyLSE 45 50 55 %
duty cycle
Analog low-swing OSC_IN External analog low swing
tr(LSE)/tf(LSE) - 100 200 ns
rise and fall times clock, 10% to 90%
1. Specified by design - Not tested in production.

Note: For information on selecting the crystal, refer to AN2867 “Guidelines for oscillator design on
STM8AF/AL/S and STM32 MCUs/MPUs” available from www.st.com.

Figure 28. Low-speed external clock source AC timing diagram

VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t

TLSE

External fLSE_ext
OSC32_IN IL
clock source
STM32

ai17529b

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic
resonator oscillator.
All the information given in this paragraph are based on characterization results obtained
with typical external components specified in Table 42. In the application, the resonator and
the load capacitors must be placed as close as possible to the oscillator pins to minimize
output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).

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Table 42. 4-50 MHz HSE oscillator characteristics(1)

Symbol Parameter Operating conditions(2) Min Typ Max Unit

F Oscillator frequency - 4 - 50 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 10
VDD = 3 V, Rm = 20 Ω,
- 0.44 -
CL = 10 pF at 4 MHz
VDD = 3 V, Rm = 20 Ω,
- 0.44 -
CL = 10 pF at 8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, Rm = 20 Ω, mA
- 0.55 -
CL = 10 pF at 16 MHz
VDD = 3 V, Rm = 20 Ω,
- 0.67 -
CL = 10 pF at 32 MHz
VDD = 3 V, Rm = 20 Ω,
- 1.17 -
CL = 10 pF at 48 MHz
Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V
tSU(HSE) (4) Startup time VDD is stabilized - 2 - ms
1. Evaluated by design - Not tested in production.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

Note: For information on selecting the crystal, refer to AN2867 “Guidelines for oscillator design on
STM8AF/AL/S and STM32 MCUs/MPUs”, available from www.st.com.

Figure 29. Typical application with an 8 MHz crystal

Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain

REXT(1) OSC_OU T STM32

CL2
ai17530b

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph is based on design simulation results
obtained with typical external components specified in Table 43. In the application, the
resonator and the load capacitors must be placed as close as possible to the oscillator pins
to minimize output distortion and startup stabilization time. Refer to the crystal resonator

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manufacturer for more details on the resonator characteristics (frequency, package,

accuracy).

Table 43. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

F Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 00
- 246 -
Low drive capability
LSEDRV[1:0] = 01
- 333 -
Medium low drive capability
IDD LSE current consumption nA
LSEDRV[1:0] = 10
- 462 -
Medium high drive capability
LSEDRV[1:0] = 11
- 747 -
High drive capability
LSEDRV[1:0] = 00
- - 0.5
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Maximum critical crystal Medium low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Specified by design - Not tested in production.
2. Refer to the note and caution paragraphs below the table, and to AN2867 “Guidelines for oscillator design
on STM8AF/AL/S and STM32 MCUs/MPUs”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to when a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and can vary significantly
with the crystal manufacturer

Note: For information on selecting the crystal, refer to AN2867 “Guidelines for oscillator design on
STM8AF/AL/S and STM32 MCUs/MPUs”, available from www.st.com.

Figure 30. Typical application with a 32.768 kHz crystal

Resonator with
integrated CL1
capacitors OSC32_IN fLSE

Bias
32.768 kHz
RF controlled
resonator
gain

OSC32_OUT STM32
CL2
ai17531d

Note: An external resistor is not required between OSC32_IN and OSC32_OUT, and it is
forbidden to add one.

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5.3.9 Internal clock source characteristics

The parameters given in Table 44 to Table 47 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 20.

48 MHz high-speed internal RC oscillator (HSI48)

Table 44. HSI48 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 (1) (1)

HSI48 frequency VDD = 3.3 V, TJ= 30 °C 47.5 48 48.5 MHz
TRIM(3) User trimming step - - 0.175 0.250
USER TRIM %
User trimming coverage ±32 steps ±4.70 ±5.6 -
COVERAGE(2)
DuCy(HSI48)(3) Duty cycle - 45 - 55 %
Accuracy of the HSI48 oscillator over
ACCHSI48_REL(3) TJ = -40 to 130 °C -4.5 - 4 %
temperature (reference is 30 °C)

HSI48 oscillator frequency drift with VDD = 3.0 to 3.6 V - 0.025 0.05
∆VDD(HSI48) %
VDD (reference is 3.3 V) VDD = 1.71 to 3.6 V - 0.05 0.1
tsu(HSI48)(3) HSI48 oscillator start-up time - - 2.1 4.0 μs
IDD(HSI48)(3) HSI48 oscillator power consumption - - 350 400 μA
Next transition jitter accumulated
NT jitter(3) - - ±0.15 -
jitter on 28 cycles
ns
Paired transition jitter accumulated
PT jitter(3) - - ±0.25 -
jitter on 56 cycles(4)
1. Calibrated during manufacturing tests.
2. Evaluated by characterization - Not tested in production.
3. Specified by design - Not tested in production.
4. Jitter measurements are performed without clock sources activated in parallel.

64 MHz high-speed internal RC oscillator (HSI)

Table 45. HSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency VDD = 3.3 V, TJ = 30 °C 63.7(2) 64.0(2) 64.3(2) MHz

Trimming is not a multiple of 32(3) - 0.24 0.32
Trimming is 128, 256, and 384(3) -5.2 -1.8 -
TRIM User trimming step Trimming is 64, 192, 320, and 488(3) -1.4 -0.8 - %

Other trimmings are multiples of 32 (not

-0.6 -0.25 -
including multiples of 64 and 128)(3)
DuCy(HSI) Duty cycle - 45 - 55 %

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Table 45. HSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Frequency drift with VDD

∆VDD(HSI) VDD= 1.71 to 3.6 V -0.12 - 0.03
(reference is 3.3 V)
%
Frequency drift with VDD TJ= -20 to 105 °C -1(4) - 1(4)
∆TEMP(HSI)
(reference is 64 MHz) TJ= -40 to 130 °C -2(4) - 1(4)
tsu(HSI) Start-up time - - 1.4 2.0 μs
At 1% of target frequency - 4 8
tstab(HSI) Stabilization time μs
At 1% of target frequency - - 4
IDD(HSI) Power consumption - - 300 450 μA
1. Specified by design - Not tested in production, unless otherwise specified.
2. Calibrated during manufacturing tests.
3. Trimming value of HSICAL[8:0].
4. Guaranteed by characterization - Not tested in production.

4 MHz low-power internal RC oscillator (CSI)

Table 46. CSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fCSI Frequency VDD = 3.3 V, TJ = 30 °C 3.96(2) 4 4.04(2) MHz

Trimming is not a multiple of 16 - 0.40 0.75
Trimming is not a multiple of 32 -4.75 -2.75 0.75
TRIM User trimming step %
Other trimmings are a multiple of 32
-0.43 0.00 0.75
(not including multiples of 64 and 128)
DuCy(CSI) Duty cycle - 45 - 55 %

Frequency drift over TJ= 0 to 85 °C -3.7(3) - 4.5(3) %

∆TEMP(CSI)
temperature TJ= -40 to TJ = 130 °C -11(3) - 7.5(3) %
∆VDD(CSI) Frequency drift over VDD VDD= 1.71 to 3.6 V -0.06 - 0.06 %
tsu(CSI) Start-up time - - 1 2 μs
Stabilization time
tstab(CSI) - - - 4 cycle
(to reach ± 3% of fCSI)
IDD(CSI) Power consumption - - 23 30 μA
1. Specified by design - Not tested in production, unless otherwise specified.
2. Calibrated during manufacturing tests.
3. Evaluated by characterization - Not tested in production.

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Low-speed internal (LSI) RC oscillator

Table 47. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.3 V, TJ = 25 °C 31.4(1) 32 32.6(1)

fLSI Frequency TJ = -40 to 110 °C, VDD =1.71 to 3.6 V 29.76(2) - 33.6(2) kHz
(2) (2)
TJ = -40 to 130 °C, VDD =1.71 to 3.6 V 29.4 - 33.6
(3)
tsu(LSI) Start-up time - - 80 130
Stabilization time μs
tstab(LSI)(3) - - 120 170
(5% of final value)
IDD(LSI)(3) Power consumption - - 130 280 nA
1. Calibrated during manufacturing tests.
2. Evaluated by characterization - Not tested in production.
3. Specified by design - Not tested in production.

5.3.10 PLL characteristics

The parameters given in Table 48 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 20.

Table 48. PLL characteristics (wide VCO frequency range)(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock - 2 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1 - 250(2)

PLL multiplier output clock VOS1 1 - 200(2)

fPLL_P_OUT
P, Q, R VOS2 1 - 150(2) MHz
VOS3 1 - 100(2)
fVCO_OUT PLL VCO output - 128 - 560(2)
Normal mode - 45 100(3) μs
tLOCK PLL lock time
Sigma-delta mode (fPLL_IN ≥ 8 MHz) - 60 120(3)

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Table 48. PLL characteristics (wide VCO frequency range)(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

fVCO_OUT = 128 MHz - 60 -

fVCO_OUT = 200 MHz - 50 -
Cycle-to-cycle jitter ±ps
fVCO_OUT = 400 MHz - 20 -
fVCO_OUT = 560 MHz - 15 -
Normal mode (f PLL_IN = 2 MHz),
- ±0.2 -
Jitter fVCO_OUT = 560 MHz
Normal mode (f PLL_IN = 16 MHz),
- ±0.8 -
fVCO_OUT = 560 MHz
Long term jitter %
Sigma-delta mode (f PLL_IN = 2 MHz),
- ±0.2 -
fVCO_OUT = 560 MHz
Sigma-delta mode (f PLL_IN = 16 MHz),
- ±0.8 -
fVCO_OUT = 560 MHz
VDD - 330 420
fVCO_OUT = 560 MHz
PLL power consumption on VCORE - 630 -
IDD(PLL) μA
VDD VDD - 155 230
fVCO_OUT = 128 MHz
VCORE - 170 -
1. Specified by design - Not tested in production, unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation.
3. Evaluated by characterization - Not tested in production.

Table 49. PLL characteristics (medium VCO frequency range)

Symbol Parameter Conditions Min(1) Typ(1) Max(1) Unit

PLL input clock - 1 - 2 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1.17 - 210

PLL multiplier output clock VOS1 1.17 - 210

fPLL_OUT
P, Q, R VOS2 1.17 - 160(2) MHz
(2)
VOS3 1.17 - 88
fVCO_OUT PLL VCO output - 150 - 420
Normal mode - 45 80(3)
tLOCK PLL lock time μs
Sigma-delta mode Forbidden

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Table 49. PLL characteristics (medium VCO frequency range) (continued)

Symbol Parameter Conditions Min(1) Typ(1) Max(1) Unit

fVCO_OUT = 150 MHz - - 60 -

fVCO_OUT = 200 MHz - - 40 -
Cycle-to-cycle jitter
fVCO_OUT = 400 MHz - - 18 -
±ps
Jitter fVCO_OUT = 420 MHz - - 15 -
fVCO_OUT = 150 MHz fPLL_OUT = - 75 -
Period jitter
fVCO_OUT = 400 MHz 50 MHz - 25 -
Long term jitter Normal mode fVCO_OUT = 400 MHz - ±0.2 - %
VDD - 275 360
fVCO_OUT = 420 MHz
PLL power consumption on VCORE - 450 -
IDD(PLL) μA
VDD VDD - 160 240
fVCO_OUT = 150 MHz
VCORE - 165 -
1. Specified by design - Not tested in production, unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation.
3. Evaluated by characterization - Not tested in production.

5.3.11 Memory characteristics

Flash memory
The characteristics are given at TJ = -40 to 130 °C unless otherwise specified.
The devices are shipped to customers with the flash memory erased.

Table 50. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

Word program(2) - 2.5 3.6

IDD Supply current Sector erase - 1.8 4 mA
Mass erase - 2.0 4
1. Specified by design - Not tested in production
2. Data are evaluated with a write of 50% of the programmed bits equal to 0.

Table 51. Flash memory programming(1)

Symbol Parameter Conditions Min(2) Typ Max(1) Unit

128 bits (user area) - 31 100

tprog Word program time µs
16 bits (OTP area) - 31 100
tERASE Sector erase time (8 Kbytes) - 2 10 ms
tME Mass erase time - 0.512 2.6
s
tBE Bank erase time - 0.256 1.3
Vprog Programming voltage 1.71 - 3.6 V

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1. Data are valid for program memory and high-cycling data memory.
2. Specified by design - Not tested in production.

Table 52. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NPEND Endurance program memory TJ = -40 to +130 °C 10

kcycles
NDEND Endurance data memory TJ = -40 to +130 °C 100
1 kcycle at TA = 125 °C 10
tPRET Program memory, data retention 1 kcycles at TA = 85 °C 30
10 kcycles at TA = 55 °C 30
Years
100 kcycle at TA = 125 °C 1
tDRET Data retention for data memory 100 kcycles at TA = 85 °C 10
100 kcycles at TA = 55 °C 10
1. Evaluated by characterization - Not tested in production, unless otherwise specified.

5.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed (toggling two LEDs through I/O ports), the device is
stressed by two electromagnetic events until a failure occurs. The failure is indicated by the
LEDs:
• Electrostatic discharge (ESD), positive and negative, is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows to resume normal operation.
The test results are given in Table 53. They are based on the EMS levels and classes
defined in AN1709 “EMC design guide for STM8, STM32 and legacy MCUs”.

Table 53. EMS characteristics

Symbol Parameter Conditions Level/Class

Voltage limits to apply on any I/O pin to

VFESD VDD = 3.3 V, TA = 25 °C, 2B
induce a functional disturbance
LQFP176-SMPS,
Fast transient voltage burst limits to apply frcc_cpu_ck = 250 MHz,
VFTB through 100 pF on VDD and VSS pins to conform to IEC 61000-4-2 5A
induce a functional disturbance

As a consequence, it is recommended to add a serial resistor (1 kΩ), located as close as

possible to the MCU, to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).

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Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. Note that good EMC performance is
highly dependent upon the user application, and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for its application.
Software recommendations
The software flow must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (such as control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST or on the oscillator pins for 1 s.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015 “Software
techniques for improving microcontrollers EMC performance”).

Electromagnetic interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard, which specifies the test board and the pin loading.

Table 54. EMI characteristics

Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
25/250 MHz

0.1 to 30 MHz 21
30 to 130 MHz 22
VDD = 3.6 V, TA = 25 °C, dBµV
Peak
SEMI LQFP176-SMPS package, 130 MHz to 1 GHz 29
level(1)
conforming to IEC61967-2
1 GHz to 2 GHz 21
EMI level 4 -
1. Refer to the EMI radiated test chapter of application note AN1709 “EMC design guide for STM8, STM32 and legacy MCUs”
available from the ST website www.st.com.

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5.3.13 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive pulse followed by a negative one) are applied to the pins
of each sample according to each pin combination. This test conforms to the
ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards.

Table 55. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)

Packages
1C 1000(2)
Electrostatic discharge TA = 25 °C, conforming to with SMPS
VESD(HBM) V
voltage (human body model) ANSI/ESDA/JEDEC JS-001 Packages
2 2000
without SMPS
Electrostatic discharge TA = 25 °C, conforming to
VESD(CDM) All packages C2a 500 V
voltage (charge device model) ANSI/ESDA/JEDEC JS-002
1. Evaluated by characterization - Not tested in production.
2. The electrostatic discharge is 2000 V for all pins, except VFBSMPS, for which the test fails at 2000 V and passes at 1600 V.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with the JESD78 IC latch-up standard.

Table 56. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TJ = 130 °C, conforming to JESD78 II level A

5.3.14 I/O current injection characteristics

As a general rule, avoid current injection to the I/O pins, due to external voltage below VSS
or above VDD (for standard, 3.3 V-capable I/O pins) during the normal product operation. To
give an indication of the device robustness when an abnormal injection accidentally
happens, susceptibility tests are performed on a sample basis during the characterization.

Functional susceptibility to I/O current injection

While a simple application is executed, the device is stressed by injecting current into the
I/O pins (one at the time) programmed in floating input mode, and checked for functional
failures. The failure is indicated by an out of range parameter: ADC error above a certain

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limit (higher than 5 LSB TUE), out of conventional limits (-5 / +0 µA range) of induced
leakage current on adjacent pins, or other functional failures (such as reset, oscillator
frequency deviation).
The following table shows I/Os current injection susceptibility data. Negative/positive
induced leakage currents are caused, respectively, by negative/positive injection.

Table 57. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on pins PA4, PA5, PB2, PB12,

0 0
IINJ PC14, PC15, PD8, and PH2 mA
Injected current on all other pins 5 N/A
1. Evaluated by characterization - Not tested in production.

5.3.15 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under the conditions summarized in Table 20. All I/Os are CMOS and TTL
compliant (except for BOOT0).
Note: For information on GPIO configuration, refer to AN4899 “STM32 GPIO configuration for
hardware settings and low-power consumption”, available on www.st.com.

Table 58. I/O static characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

I/O input low level voltage

- - 0.3 VDDIOx(2)
except BOOT0
I/O input low level voltage
VIL 1.08 V < VDD < 3.6 V - - 0.4 VDDIOx - 0.1(3) V
except BOOT0
BOOT0 I/O input low level
- - 0.19 VDDIOx + 0.1(3)
voltage
I/O input high level
0.7 VDDIOx(2) - -
voltage except BOOT0
I/O input high level 0.52 VDDIOx +
VIH 1.08 V < VDD < 3.6 V - - V
voltage except BOOT0 0.18(3)
BOOT0 I/O input high 0.17 VDDIOx +
- -
level voltage 0.6(3)
TT_xx, FT_xxx and NRST
1.08 V < VDD < 3.6 V - 250 -
I/O input hysteresis
VHYS(3) mV
BOOT0 I/O input
1.71 V < VDD < 3.6 V - 200 -
hysteresis

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Table 58. I/O static characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

0 < VIN ≤
- - ±200
Max(VDDXXX)(7)
Max(VDDXXX) <
FT_xx input leakage
VIN ≤ Max(VDDXXX) + - - 2500
current(3)
1 V) (5)(7)
Ileak(4) nA
Max(VDDXXX) < VIN ≤
- - 750
5.5 V (5)(7)
TT_xx input leakage 0 < VIN ≤ Max(VDDXXX)
(7) - - ±200
current
BOOT0 0 < VIN ≤ VDDOX - - 15
Weak pull-up
RPU VIN = VSS 30 40 50
equivalent resistor(6)
kΩ
Weak pull-down (7)
RPD VIN = VDD 30 40 50
equivalent resistor(6)
CIO I/O pin capacitance - - 5 - pF
1. VDDIOx represents VDD or VDDIO2.
2. Compliant with CMOS requirements.
3. Specified by design - Not tested in production.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ieak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. VIN must be lower than Max(VDDXXX) + 3.6 V.
6. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10%).
7. Max(VDDXXX) is the maximum value of all the I/O supplies.

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in the following figure.

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Figure 31. VIL/VIH for all I/Os except BOOT0

3

2.5
Minimum required
logic level 1 zone
TTL standard requirement VIHmin = 2V
2
xV DDIO
min
= 0.7
nt) V IH
ireme
VIN (V) ard requ
OS stand
1.5 n (CM
roductio
d in p VDDIO +
0.18
Teste = 0.52
ulation
VIHmin Undefined input range
on sim
Based
1
VDDIO - 0.1
VILmax = 0.4
simulation = 0.3 VDDIO TTL standard requirement VILmax = 0.8V
Based on ment) VILmax
S stan dard require
tion (CMO
0.5 Test ed in produc
Minimum required
logic level 0 zone
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

Device characteristics VDDIO (V)

Tested thresholds MSv47925V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins that can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 18).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 18).

Output voltage levels

Unless otherwise specified, the parameters given in Table 59 and Table 61 are derived from
tests performed under ambient temperature and VDD supply voltage conditions summarized
in Table 20. All I/Os are CMOS and TTL compliant.

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Table 59. Output voltage characteristics for all I/Os except PC13, PC14, PC15, and PI8
Symbol Parameter Conditions(1) Min Max Unit

CMOS port(2), IIO = 8 mA

VOL Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2), IIO = -8 mA
VOH Output high level voltage VDD− 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = 8 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = -8 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 20 mA
VOL(3) Output low level voltage - 1.3
2.7 V ≤ VDD ≤ 3.6 V
IIO = -20 mA
VOH(3) Output high level voltage VDD - 1.3 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 4 mA
VOL(3) Output low level voltage - 0.4 V
1.71 V ≤ VDD ≤ 3.6 V
IIO = -4 mA
VOH (3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD <3.6 V
IIO = 2 mA
VOL(3) Output low level voltage - 0.3 VDDIO2
1.08 V ≤ VDD ≤ 1.32 V
IIO = -2 mA
VOH (3) Output high level voltage 0.7 VDDIO2 -
1.71 V ≤ VDD < 1.32 V
IIO = 20 mA
- 0.4
2.3 V≤ VDD ≤3.6 V
Output low level voltage for IIO = 10 mA
VOLFM+(3) an FTf I/O pin in (FT I/O with - 0.4
1.71 V ≤ VDD ≤ 3.6 V
“f” option)
IIO = 4.5 mA
- 0.4
1.08 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17, and
the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute
maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design - Not tested in production.

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Table 60. Output voltage characteristics for FT_c I/Os

Symbol Parameter Conditions(1) Min Max Unit

CMOS port(2), IIO = 2 mA

VOL Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2), IIO = -2 mA
VOH Output high level voltage VDD− 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = 2 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = -2 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
V
IIO = 1 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
IIO = -1 mA
VOH(3) Output high level voltage VDD - 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 0.1 mA
VOL(3) Output low level voltage - 0.4
1.71 V ≤ VDD ≤ 3.6 V
IIO = -0.1 mA
VOH (3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD < 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 17, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must
always respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design - Not tested in production.

Table 61. Output voltage characteristics for PC13 and PI8(1)

Symbol Parameter Conditions(3) Min Max Unit

CMOS port(2), IIO = 3 mA

VOL Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2), IIO = -3 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = 3 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
V
TTL port(2), IIO = -3 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 1.5 mA
VOL(3) Output low level voltage - 0.4
1.71 V ≤ VDD ≤ 3.6 V
IIO = −1.5 mA
VOH(3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 17, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must
always respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design - Not tested in production.

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Table 62. Output voltage characteristics for PC14 and PC15(1)

Symbol Parameter Conditions(3) Min Max Unit

CMOS port(2), IIO = 0.5 mA

VOL Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2), IIO = -0.5 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = 0.5 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
V
TTL port(2), IIO = -0.5 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 0.25 mA
VOL(3) Output low level voltage - 0.4
1.71 V ≤ VDD ≤ 3.6 V
IIO = -0.25 mA
VOH(3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 17, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must
always respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design - Not tested in production.

Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of GPIOx_HSLVR register can be used to optimize the I/O speed when the
voltage is below 2.7 V.

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Table 63. Output timing characteristics (HSLV OFF)(1)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 8

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 10
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 14
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 16
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 5
00
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 18.0
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 36.0
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 17.0
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 34.0
Output high to low level C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 15.5
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 32.0
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 14.2
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 30.0
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12.2
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 27

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Table 63. Output timing characteristics (HSLV OFF)(1) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V 40

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 12
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 45
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 14
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 16
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 55
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 18
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 60
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 20
01
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 6.2
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 11.4
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.7
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 10.5
Output high to low level C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.1
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 9.5
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.5
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V 8.4
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V 3.7
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V 7.0

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Table 63. Output timing characteristics (HSLV OFF)(1) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 80

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 30
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 90
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 35
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 40
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 110
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 45
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 133
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 50
10
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.8
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 7.5
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.4
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 6.6
Output high to low level C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.9
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 5.7
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.5
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 4.7
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.9
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 3.7

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Table 63. Output timing characteristics (HSLV OFF)(1) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 40
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 120
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 50
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 140
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 60
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 166
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 70
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 200
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 80
11
C = 50 pF, 2.7 V≤ VDD ≤ 3.6 V - 3.3
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 6.3
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.8
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 5.5
Output high to low level C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.3
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 4.6
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.9
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 3.7
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.4
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 3
1. Specified by design - Not tested in production.
2. The maximum frequency is defined with the conditions (tr + tf) ≤ 2/3 T, Skew ≤ 1/20 T, and 45% < Duty cycle < 55%.
3. When 2 V < VDD < 2.7 V the maximum frequency is between values given for VDD = 1.98 V and VDD = 2.7 V.
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. When 2 V < VDD < 2.7 V the maximum trise/tfall is between values given for VDD = 1.98 V and VDD = 2.7 V.

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Output buffer timing characteristics (HSLV option enabled)

Table 64. Output timing characteristics (HSLV ON)(1)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 8

C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 10
Fmax(2) Maximum frequency C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 12 MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 14
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 16
00
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 17.8
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 15.8
Output high to low level
tr/tf(3) fall time and output low C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 14.4 ns
to high level rise time
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 13.1
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 11.4
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 40
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 45
Fmax(2) Maximum frequency C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 50 MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 55
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 60
01
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 7.2
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 6.5
Output high to low level
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 5.6 ns
to high level rise time
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 4.8
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 3.8
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 60
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 70
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 90 MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 110
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 140
10
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 5.3
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 4.6
Output high to low level
(3)(4)
tr/tf fall time and output low C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 3.8 ns
to high level rise time
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 3.0
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 2.2

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Table 64. Output timing characteristics (HSLV ON)(1) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 67

C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 100
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 120 MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 155
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 200
11
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 5.0
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 4.1
Output high to low level
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 3.3 ns
to high level rise time
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 2.5
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 1.8
1. Specified by design - Not tested in production.
2. The maximum frequency is defined with the conditions: (tr+tf) ≤ 2/3 T, Skew ≤ 1/20 T, 45% < Duty cycle < 55%.
3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform.
4. Compensation system enabled.

Table 65. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF)(1)
Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1

C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1
00
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 83.0
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 79.0
Output high to low level fall
tr/tf(3) time and output low to high C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 46.0 ns
level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 72.0
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 68.0

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Table 65. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF)(1) (continued)
Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5

C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
01
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 24.5
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 22.2
Output high to low level fall
tr/tf(3) time and output low to high C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 20.0 ns
level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 17.8
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 15.0
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10
10
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 16.2
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 14.3
Output high to low level fall
tr/tf(3) time and output low to high C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 12.2 ns
level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10.0
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 7.9
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 20
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 23
Fmax(2)
(4) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 25 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 28
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 30
11
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 14.0
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 12.0
Output high to low level fall
tr/tf(3)(4) time and output low to high C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10.0 ns
level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 8.0
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 6.0
1. Specified by design - Not tested in production.
2. The maximum frequency is defined with the conditions (tr + tf) ≤ 2/3 T, Skew ≤ 1/20 T, 45% < Duty cycle < 55%.
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.

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Table 66. Output timing characteristics VDDIO2 1.2 V (HSLV ON)(1)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5

C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
00
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 32.5
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 30.0
Output high to low level
tr/tf(3) fall time and output low C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 27.5 ns
to high level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 25.0
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 22.5
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 15.0
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 17.5
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 20.0 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 22.5
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 25.0
01
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 14.6
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 12.9
Output high to low level
tr/tf(3) fall time and output low C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 11.2 ns
to high level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 9.3
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 7.3
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 25
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 30
Fmax (2)(4)
Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 33 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 44
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 55
10
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 11.6
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 9.7
Output high to low level
tr/tf(3)(4) fall time and output low C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 7.8 ns
to high level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 6.1
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 4.3

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Table 66. Output timing characteristics VDDIO2 1.2 V (HSLV ON)(1) (continued)
Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 30

C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 35
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 44 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 55
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 77
11
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 11.1
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 9.2
Output high to low level
tr/tf(3)(4) fall time and output low C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 7.2 ns
to high level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5.4
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 3.6
1. Specified by design - Not tested in production.
2. The maximum frequency is defined with the conditions (tr + tf) ≤ 2/3 T, Skew ≤ 1/20 T, 45%< Duty cycle < 55%.
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.

Table 67. Output timing characteristics for FT_c I/Os (PB13/PB14)(1)(2)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDDIO ≤ 3.6 V - 2

Fmax Maximum frequency MHz
C = 50 pF, 1.71 V ≤ VDDIO < 2.7 V - 1
00
C = 50 pF, 2.7 V ≤ VDDIO < 3.6 V - 166
tr/tf Output rise and fall time ns
C = 50 pF, 1.71 V ≤ VDDIO < 2.7 V - 330
C = 30 pF, 2.7 V ≤ VDDIO < 3.6 V - 10
Frmax Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDDIO < 2.7 V - 4
01
C = 30 pF, 2.7 V ≤ VDDIO < 3.6 V - 33
tr/tf Output rise and fall time ns
C = 30 pF, 1.71 V ≤ VDDIO < 2.7 V - 65
1. Specified by design - Not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of
GPIO port configuration register.

5.3.16 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 58).
Unless otherwise specified, the parameters in Table 68 are derived from tests performed
under the ambient temperature and VDD supply voltage conditions summarized in Table 20.

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Table 68. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

RPU(2) Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ

(2)
VF(NRST) NRST input filtered pulse 1.71 V < VDD < 3.6 V - - 50
ns
(2)
VNF(NRST) NRST input not filtered pulse 1.71 V < VDD < 3.6 V 350 - -
1. The pull-up is designed with a true resistance in series with a switchable PMOS. The PMOS contribution to
the series resistance is minimum (~10 % order).
2. Specified by design - Not tested in production.

Figure 32. Recommended NRST pin protection

VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter

0.1 μF

STM32

ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 58, otherwise the reset is not taken into account by the device.

5.3.17 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length to ensure its detection by the
event controller.

Table 69. EXTI input characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLEC Pulse length to event controller - 20 - - ns

1. Specified by design - Not tested in production.

5.3.18 FMC characteristics

Unless otherwise specified, the parameters given in tables 70 to 83 are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0

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Refer to Section 5.3.15 for more details on the input/output alternate function
characteristics.

Asynchronous waveforms and timings

Figures 33 through 35 represent asynchronous waveforms, tables 70 through 77 provide
the corresponding timings. The results shown in these tables are obtained with the following
FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, the Tfmc_ker_ck is the fHCLK clock period.

Figure 33. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)

FMC_NE

tv(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

tv(A_NE) t h(A_NOE)

FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)

FMC_NBL[1:0]

t h(Data_NE)

t su(Data_NOE) th(Data_NOE)

t su(Data_NE)

FMC_D[15:0] Data

t v(NADV_NE)

tw(NADV)

FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32753V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

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Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 Tfmc_ker_ck - 1 3 Tfmc_ker_ck + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2 Tfmc_ker_ck - 1 2 Tfmc_ker_ck + 1
FMC_NOE high to FMC_NE high hold
th(NE_NOE) Tfmc_ker_ck - 0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 1
th(A_NOE) Address hold time after FMC_NOE high 2 Tfmc_ker_ck - 1.5 - ns
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck + 10 -
tsu(Data_NOE) Data to FMC_NOEx high setup time 9 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1
1. Evaluated by characterization - Not tested in production.

Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT

timings(1)(2)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 Tfmc_ker_ck - 1 8 Tfmc_ker_ck + 1

tw(NOE) FMC_NOE low time 7 Tfmc_ker_ck - 1 7 Tfmc_ker_ck + 1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck - 0.5 -
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 Tfmc_ker_ck + 10 -
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4 Tfmc_ker_ck +10 -
invalid
1. Evaluated by characterization - Not tested in production.
2. NWAIT pulse width is equal to one fmc_ker_ck cycle.

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Figure 34. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)

FMC_NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)

FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)

FMC_D[15:0] Data
t v(NADV_NE)

tw(NADV)
FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32754V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 Tfmc_ker_ck - 1 3 Tfmc_ker_ck + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 1 Tfmc_ker_ck+ 0.5
tw(NWE) FMC_NWE low time Tfmc_ker_ck - 1 Tfmc_ker_ck +1
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck - 1 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck -1 -
ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck -1 -
tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck + 1
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1
1. Evaluated by characterization - Not tested in production.

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Table 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT

timings(1)(2)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 Tfmc_ker_ck - 1 8 Tfmc_ker_ck+ 1

tw(NWE) FMC_NWE low time 6 Tfmc_ker_ck - 1 6 Tfmc_ker_ck+ 1
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 Tfmc_ker_ck + 10 - ns

FMC_NEx hold time after FMC_NWAIT

th(NE_NWAIT) 4 Tfmc_ker_ck + 10 -
invalid
1. Evaluated by characterization - Not tested in production.
2. NWAIT pulse width is equal to one fmc_ker_ck cycle.

Figure 35. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)

FMC_ NE
tv(NOE_NE) t h(NE_NOE)

FMC_NOE

t w(NOE)

FMC_NWE

tv(A_NE) th(A_NOE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)
tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32755V1

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Table 74. Asynchronous multiplexed PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4 Tfmc_ker_ck - 1 4 Tfmc_ker_ck + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2 Tfmc_ker_ck - 1 2 Tfmc_ker_ck +0.5
ttw(NOE) FMC_NOE low time Tfmc_ker_ck - 1 Tfmc_ker_ck+ 1
FMC_NOE high to FMC_NE high hold
th(NE_NOE) Tfmc_ker_ck - 0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 1
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 0.5 Tfmc_ker_ck + 1 ns
FMC_AD(address) valid hold time after
th(AD_NADV) Tfmc_ker_ck + 0.5 -
FMC_NADV high
th(A_NOE) Address hold time after FMC_NOE high 2 Tfmc_ker_ck - 0.5 -
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck +10 -
tsu(Data_NOE) Data to FMC_NOE high setup time 9 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. Evaluated by characterization - Not tested in production.

Table 75. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) (2)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9 Tfmc_ker_ck - 1 9 Tfmc_ker_ck + 1

tw(NOE) FMC_NOE low time 7 Tfmc_ker_ck - 1 7 Tfmc_ker_ck + 1
FMC_NWAIT valid before FMC_NEx ns
tsu(NWAIT_NE) 4 Tfmc_ker_ck +10 -
high
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 3 Tfmc_ker_ck +10 -
invalid
1. Evaluated by characterization - Not tested in production.
2. NWAIT pulse width is equal to one fmc_ker_ck cycle.

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Figure 36. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)

FMC_ NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)

FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)

tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32756V1

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Table 76. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4 Tfmc_ker_ck -1 4 Tfmc_ker_ck +1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 1 Tfmc_ker_ck +0.5
tw(NWE) FMC_NWE low time 2 Tfmc_ker_ck - 1 2 Tfmc_ker_ck + 1
FMC_NWE high to FMC_NE high hold
th(NE_NWE) Tfmc_ker_ck - 0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 1 Tfmc_ker_ck + 1 ns
FMC_AD(adress) valid hold time after
th(AD_NADV) Tfmc_ker_ck - 1 -
FMC_NADV high
th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck - 1 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck - 1 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck + 0.5
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck - 0.5 -
1. Evaluated by characterization - Not tested in production.

Table 77. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9 Tfmc_ker_ck - 1 9 Tfmc_ker_ck + 1

tw(NWE) FMC_NWE low time 7 Tfmc_ker_ck -1 7 Tfmc_ker_ck + 1
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 Tfmc_ker_ck + 10 - ns

FMC_NEx hold time after FMC_NWAIT

th(NE_NWAIT) 4 Tfmc_ker_ck + 10 -
invalid
1. Evaluated by characterization - Not tested in production.
2. NWAIT pulse width is equal to one fmc_ker_ck cycle.

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Synchronous waveforms and timings

Figures 37 through 40 represent synchronous waveforms, tables 78 through 81 provide the
corresponding timings. The results shown in these tables are obtained with the following
FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash, DataLatency = 0 for PSRAM.
• With capacity load CL = 30 pF
In all the timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK
maximum values:
• For 2.7 V < VDD < 3.6 V: maximum FMC_CLK = 100 MHz at CL = 20 pF
• For 1.71 V < VDD < 1.8 V: maximum FMC_CLK = 95 MHz at CL = 20 pF
• For 1.71 V < VDD < 1.8 V: maximum FMC_CLK = 100 MHz at CL = 15 pF

Figure 37. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)

FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32757V1

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Table 78. Synchronous multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2Tfmc_ker_ck - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 1
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x = 0…2) Tfmc_ker_ck - 1 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16…25) Tfmc_ker_ck- 1 -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1 ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck + 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0.5 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3.5 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 1.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
1. Evaluated by characterization - Not tested in production.

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Figure 38. Synchronous multiplexed PSRAM write timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)

FMC_AD[15:0] AD[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

td(CLKH-NBLH)

FMC_NBL

MS32758V1

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Table 79. Synchronous multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period, VDD = 2.7 to 3.6 V 2Tfmc_ker_ck - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 1
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0…2) Tfmc_ker_ck - 1 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16…25) Tfmc_ker_ck - 1 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1
ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck + 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 1 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 1
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 1
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
1. Evaluated by characterization - Not tested in production.

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Figure 39. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK)

FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)

FMC_D[15:0] D1 D2

tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

Table 80. Synchronous non-multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 -

t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0…2) - 1
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0…2) Tfmc_ker_ck- 1 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16…25) Tfmc_ker_ck- 1 - ns
td(CLKL-NOEL) FMC_CLK ow to FMC_NOE low - 1
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck + 0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 3.5 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1.5 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
1. Evaluated by characterization - Not tested in production.

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Figure 40. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)

FMC_CLK

td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx

td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE

td(CLKL-Data) td(CLKL-Data)

FMC_D[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL

MS32760V1

Table 81. Synchronous non-multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

t(CLK) FMC_CLK period 2Tfmc_ker_ck - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0…2) - 1
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0…2) Tfmc_ker_ck - 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16…25) Tfmc_ker_ck + 0.5 -
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck+ 0.5 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 1.5
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck - 0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -

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1. Evaluated by characterization - Not tested in production.

NAND controller waveforms and timings

Figures 41 through 44 represent synchronous waveforms, tables 82 and 83 provide the
corresponding timings. The results are obtained with the following FMC configuration and a
capacitive load (CL) of 30 pF:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
• Capacitive load CL = 30 pF
In all timing tables, Tfmc_ker_ck is the HCLK clock period.

Figure 41. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)

FMC_NOE (NRE)

tsu(D-NOE) th(NOE-D)

FMC_D[y:0]

MSv73150V1

1. y = 7 or 15, depending upon the NAND flash memory interface.

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Figure 42. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) tw(NWE) th(NWE-ALE)

FMC_NWE

FMC_NOE (NRE)

td(D-NWE)

tv(NWE-D) th(NWE-D)

FMC_D[y:0]

MSv73151V1

1. y = 7 or 15, depending upon the NAND flash memory interface.

Figure 43. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)
FMC_NOE

tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32769V1

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Figure 44. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)

FMC_NWE

FMC_N OE

td(D-NWE)

tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32770V1

Table 82. Switching characteristics for NAND flash read cycles(1)

Symbol Parameter Min Max Unit

tw(N0E) FMC_NOE low width 4Tfmc_ker_ck - 0.5 4Tfmc_ker_ck+ 0.5

FMC_D[15-0] valid data before
tsu(D-NOE) 11 -
FMC_NOE high
FMC_D[15-0] valid data after ns
th(NOE-D) 0 -
FMC_NOE high
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck + 0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Tfmc_ker_ck - 1.5 -
1. Evaluated by characterization - Not tested in production.

Table 83. Switching characteristics for NAND flash write cycles(1)

Symbol Parameter Min Max Unit

tw(NWE) FMC_NWE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck + 0.5

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2Tfmc_ker_ck + 0.5 -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5Tfmc_ker_ck - 2.5 -
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3Tfmc_ker_ck + 0.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2Tfmc_ker_ck - 1 -
1. Evaluated by characterization - Not tested in production.

SDRAM waveforms and timings

In all timing tables, the tfmc_ker_ck is the fHCLK clock period, with the following FMC_SDCLK
maximum values:

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• For 2.7 V< VDD< 3.6 V: maximum FMC_SDCLK = 95 MHz at 20 pF (100 MHz for
VDD > 3.0V)
• For 1.71 V < VDD < 1.8 V: maximum FMC_SDCLK = 95 MHz at 15 pF
• For 1.71 V < VDD < 1.8 V: maximum FMC_SDCLK = 90 MHz at 20 pF

Figure 45. SDRAM read access waveforms (CL = 1)

FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)

FMC_A[12:0] Row n Col1 Col2 Coli Coln

th(SDCLKL_AddC)

td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)

FMC_SDNRAS

td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS

FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)

FMC_D[31:0] Data1 Data2 Datai Datan

MS32751V2

Table 84. SDRAM read timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck + 0.5

tsu(SDCLKH _Data) Data input setup time 3 -
th(SDCLKH_Data) Data input hold time 0.5 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 1.5
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
1. Evaluated by characterization - Not tested in production.

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Table 85. LPSDR SDRAM read timings(1)

Symbol Parameter Min Max Unit

tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck + 0.5

tsu(SDCLKH_Data) Data input setup time 3 -
th(SDCLKH_Data) Data input hold time 0.5 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL_SDNE) Chip select valid time - 1.5
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 1.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
1. Evaluated by characterization - Not tested in production.

Figure 46. SDRAM write access waveforms

FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)

FMC_A[12:0] Row n Col1 Col2 Coli Coln

th(SDCLKL_AddC)

td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)

FMC_SDNRAS

td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)

FMC_SDNWE
td(SDCLKL_Data)

FMC_D[31:0] Data1 Data2 Datai Datan

td(SDCLKL_NBL) th(SDCLKL_Data)

FMC_NBL[3:0]
MS32752V2

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Table 86. SDRAM write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 1
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 2
td(SDCLKL_SDNWE) SDNWE valid time - 1
th(SDCLKL_SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL_ SDNE) Chip select valid time - 1
th(SDCLKL-_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
td(SDCLKL_SDNCAS) SDNCAS hold time 0 -
1. Evaluated by characterization - Not tested in production.

Table 87. LPSDR SDRAM write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 1
th(SDCLKL _Data) Data output hold time 0. -
td(SDCLKL_Add) Address valid time - 2
td(SDCLKL-SDNWE) SDNWE valid time - 1
th(SDCLKL-SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL- SDNE) Chip select valid time - 1.5
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
1. Evaluated by characterization - Not tested in production.

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5.3.19 Octo-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 88 and Table 89 are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0
Refer to Section 5.3.15 for more details on the input/output alternate function
characteristics.

Table 88. OCTOSPI characteristics in SDR mode(1)(2)

Symbol Parameter Conditions Min Typ Max(3) Unit

1.71 V < VDD < 1.9 V,

- - 110
CL = 15 pF
F(CLK) Clock frequency MHz
1.71 V < VDD < 3.6 V,
- - 150
CL =15 pF
tw(CLKH) Clock high and low time, PRESCALER[7:0] = n t(CLK) / 2 - 0.5 - t(CLK) / 2 + 0.5
t even division (= 0, 1, 3, 5,..., 255) t(CLK) / 2 - 0.5 - t(CK) / 2 + 0.5
w(CLKL)

(n / 2) * t(CLK) / (n / 2) * t(CLK) /
tw(CLKH) -
Clock high and low time, PRESCALER[7:0] = n (n + 1) - 0.5 (n + 1) + 0.5
odd division (= 2, 4, 6, ..., 254) (n / 2 + 1) * t(CLK) / (n / 2 + 1) * t(CLK) /
tw(CLKL) - ns
(n + 1) - 0.5 (n + 1) + 0.5
ts(IN) Data input setup time - 4 - -
th(IN) Data input hold time - 1 - -
tv(OUT) Data output valid time - - 0.5 1
th(OUT) Data output hold time - 0 - -
1. All values apply to Octal- and Quad-SPI mode.
2. Evaluated by characterization - Not tested in production.
3. At VOS1 these values are degraded by up to 5%.

Figure 47. OCTOSPI SDR read/write timing diagram

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V3

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Table 89. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V < VDD < 1.9 V,

- - 100(4)
OCTOSPI clock CL = 15 pF
FCLK MHz
frequency 2.7 V < VDD < 3.6 V,
- - 125(4)
CL = 15 pF
tw(CLKH) OCTOSPI clock PRESCALER[7:0] = n t(CLK) / 2 - 0.5 - t(CLK) / 2 + 0.5
t high and low time (= 0, 1, 3, 5, .., 255) t(CLK) / 2 - 0.5 - t(CLK) / 2 + 0.5
w(CLKL)

(n / 2) * t(CLK)/ (n / 2) * t(CLK)/ ns
tw(CLKH) -
OCTOSPI clock PRESCALER[7:0] = n (n + 1) - 0.5 (n + 1) + 0.5
high and low time (= 2, 4, 6, 8, ..., 254) (n / 2 + 1) * t
tw(CLKL) (CLK)/ -
(n / 2 + 1) * t(CLK)/
(n + 1) - 0.5 (n + 1) + 0.5
tv(CLK) Clock valid time - - - t(CLK) +0.5 ns
tsr(IN),
Data input setup time - 4 - -
tsf(IN)
thr(IN),
Data input hold time - 1.5 - -
thf(IN)
DHQC = 0 - 2.5 3.5
tvr(OUT) ns
Data output valid time DHQC = 1, t(CLK) / 4
tvf(OUT) - t(CLK) / 4 + 1
Prescaler [7:0] = 1, 2... + 0.5
DHQC = 0 1.5 - -
thr(OUT)
Data output hold time DHQC = 1,
thf(OUT) t(CLK) / 4 - 1 - -
Prescaler [7:0] = 1, 2...
1. All values apply to Octal and Quad-SPI mode.
2. Evaluated by characterization - Not tested in production.
3. Delay block bypassed.
4. DHQC must be set to reach the mentioned frequency.

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Table 90. OCTOSPI characteristics in DTR mode (with DQS) / HyperBus(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V < VDD < 1.9 V,

- - 125(3)(4)
CL = 15 pF
FCLK OCTOSPI clock frequency MHz
2.7 V < VDD < 3.6 V,
- - 125(3)(5)
CL = 15 pF
tw(CLKH) OCTOSPI clock PRESCALER[7:0] = n t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
tw(CLKL) high and low time = (0, 1, 3, 5, …, 255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) -
OCTOSPI clock PRESCALER[7:0] = n (n+1) - 0.5 (n+1) + 0.5
ns
high and low time = (2, 4, 6, 8, …, 254) (n/2+1)*t(CLK)/ (n/2+1)*t(CLK)/
tw(CLKL) -
(n+1) - 0.5 (n+1) + 0.5
tv(CLK) Clock valid time - - - t(CLK) + 2
th(CLK) Clock hold time - t(CLK)/2 - 1 - -
CLK, NCLK crossing level
tODr(CLK)(5) VDD = 1.8 V 890 - 1300
on CLK rising edge
mV
CLK, NCLK crossing level
tODf(CLK)(5) VDD = 1.8 V 790 - 1080
on CLK falling edge
tw(CS) Chip select high time - 3 * t(CLK) - -
tv(DQ) Data input valid time - 3 - -
tv(DS) Data strobe input valid time - 1 - - ns
th(DS) Data strobe input hold time - 0 - -
tv(RWDS) Data strobe output valid time - - - 3 * t(CLK)
tsr(DQ),
Data input setup time - -0.5 - -
tsf(DQ)
thr(DQ),
Data input hold time - 2 - -
thf(DQ)
DHQC = 0 - 2.5 3.5
tvr(OUT) DHQC = 1, all
Data output valid time t(CLK)/4 ns
tvf(OUT) prescaler values - t(CLK)/4 + 1
+ 0.5
except 0
DHQC = 0 1.5 - -
thr(OUT) DHQC = 1, all
Data output hold time
thf(OUT) prescaler values t(CLK)/4 - 1 - -
except 0
1. Evaluated by characterization - Not tested in production.
2. Delay block activated.
3. Maximum frequency value are given for a maximum RWDS to DQ skew of ± 1.0 ns.
4. DHQC must be set to reach the mentioned frequency.
5. It is recommended that PF10/PB5, PB4/PB5 and PA3/PB5 are in line with crossing specification.

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Figure 48. OCTOSPI timing diagram - DTR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output D0 D1 D2 D3 D4 D5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input D0 D1 D2 D3 D4 D5

MSv36879V4

Figure 49. OCTOSPI HyperBus clock

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

tf(NCLK) t(NCLK) tw(NCLKL) tw(NCLKH) tr(NCLK)

NCLK

VOD(CLK)
CLK
MSv47732V3

Figure 50. OCTOSPI HyperBus read

tw(CS)

NCS

tv(CLK) t ACC= Initial access th(CLK)

CLK, NCLK

tv(RWDS) tv(DS) th(DS)

RWDS

tv(OUT) th(OUT) Latency count tv(DQ) ts(DQ) th(DQ)

47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

DQ[7:0] A B A B

Command address
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS. MSv47733V3

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Figure 51. OCTOSPI HyperBus write

tw(CS)

NCS

Read write recovery Access latency

tv(CLK) th(CLK)

CLK, NCLK

tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

Low = 1x latency count
RWDS

Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)

Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B

Command address Host drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS.
MSv47734V3

5.3.20 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 91 are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 20, with the following configuration:

Table 91. Delay block characteristics

Symbol Parameter Conditions Min Typ Max Unit

tinit Initial delay - 750 1100 1700 ps

t∆ Unit delay - 38 44 54 ps

5.3.21 DCMI interface characteristics

Unless otherwise specified, the parameters given in Table 92 are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 20, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load CL = 30 pF
• Measurement points done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling VOS0 selected

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Table 92. DCMI characteristics(1)

Symbol Parameter Min Max Unit

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel clock input - 100 MHz
DPIXEL Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 2.5 -
th(DATA) Data hold time 2 -
ns
tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC and DCMI_VSYNC input setup times 2.5 -
th(HSYNC), th(VSYNC) DCMI_HSYNC and DCMI_VSYNC input hold times 1.5 -
1. Evaluated by characterization - Not tested in production.

Figure 52. DCMI timing diagrams

1/DCMI_PIXCLK

DCMI_PIXCLK

tsu(HSYNC) th(HSYNC)

DCMI_HSYNC

tsu(VSYNC) th(HSYNC)

DCMI_VSYNC
tsu(DATA) th(DATA)

DATA[0:13]

MS32414V2

5.3.22 PSSI interface characteristics

Unless otherwise specified, the parameters given in Table 92 and Table 93 are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 20 and Section 5.3.1, with the following configuration:
• PSSI_PDCK polarity: falling
• PSSI_RDY and PSSI_DE polarity: low
• Bus width: 16 lines
• DATA width: 32 bits
• Capacitive load CL= 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling VOS0 selected

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Table 93. PSSI transmit characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio PSSI_PDCK/fHCLK - - 0.4 -

2.7 V ≤ VDD ≤ 3.6 V (2)
- 90
PSSI_PDCK PSSI clock input MHz
1.71 V ≤ VDD ≤ 3.6 V - 86
Dpixel PSSI clock input duty cycle 30 70 %
2.7 V ≤ VDD ≤ 3.6 V - 11
tov(DATA) Data output valid time
1.71 V ≤ VDD ≤ 3.6 V - 11.5
toh(DATA) Data output hold time 5.5 -
tov((DE) DE output valid time - 11.5 ns
toh(DE) DE output hold time 1.71 V ≤ VDD ≤ 3.6 V 5.5 -
tsu(RDY) RDY input setup time 0.5 -
th(RDY) RDY input hold time 0.5 -
1. Evaluated by characterization - Not tested in production.
2. This maximal frequency does not consider receiver setup and hold timings.

Table 94. PSSI receive characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio PSSI_PDCK/fHCLK - 0.4 -

PSSI_PDCK PSSI clock input 1.71 V ≤ VDD ≤ 3.6 V - 100 MHz
Dpixel PSSI clock input duty cycle - 30 70 %
tsu(DATA) Data input setup time 2 -
th(DATA) Data input hold time 2.5 -
tsu((DE) DE input setup time 1.5 -
1.71 V ≤ VDD ≤ 3.6 V ns
th(DE) DE input hold time 2 -
tov(RDY) RDY output valid time - 16.5
toh(RDY) RDY output hold time 5.5 -
1. Evaluated by characterization - Not tested in production.

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Figure 53. PSSI transmit timing diagram

tc(PDCK)
tw(PDCKH) tw(PDCKL)
tf(PDCK) tr(PDCK)
PSSI_PDCK
(input) CKPOL = 0

CKPOL = 1

tov(DATA) toh(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)
PSSI_DE
(output)

DEPOL = 0
tov(DE) toh(DE)

DEPOL = 1
PSSI_RDY

RDYPOL = 0
(input)

tsu(RDY) th(RDY)

RDYPOL = 1
MSv65388V1

Figure 54. PSSI receive timing diagram

tc(PDCK)
tw(PDCKH) tw(PDCKL)
tf(PDCK) tr(PDCK)
PSSI_PDCK

CKPOL = 0
(input)

CKPOL = 1

tsu(DATA)
thDATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
tsu(DE)
th(DE)
PSSI_DE

DEPOL = 0
(output)

DEPOL = 1
tov(RDY) toh(RDY)
PSSI_RDY

RDYPOL = 0
(input)

RDYPOL = 1
MSv65389V1

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5.3.23 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 95 are derived from tests
performed under the ambient temperature, fHCLK frequency, and VDDA supply voltage
conditions summarized in Table 20.

Table 95. 12-bit ADC characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply
VDDA voltage for - 1.62 - 3.6
ADC ON

Positive
VREF+ reference - 1.62 - VDDA V
voltage

Negative
VREF- reference - VSSA
voltage

Clock
fadc_ker_ck(3) 1.62 V ≤ VDDA ≤ 3.6 V 1.5 - 75 MHz
frequency

fadc_ker_ck
1.8V ≤ VDDA ≤ 3.6V - 5.00 -
= 75 MHz
Continuous
mode
fadc_ker_ck
1.6V ≤ VDDA ≤ 3.6V - 4.66 -
= 70 MHz
Resolution
= 12 bits
fadc_ker_ck
2.4V ≤ VDDA ≤ 3.6V - 4.00 -
Single or = 60 MHz
Discontinuous
mode fadc_ker_ck
1.6V ≤ VDDA ≤ 3.6V - 3.33 -
= 50 MHz
Sampling rate
for fast Continuous
1.6V ≤ VDDA ≤ 3.6V - 5.77 -
channels mode
(VIN[0:5]) fadc_ker_ck
= 75 MHz
Resolution
2.4V ≤ VDDA ≤ 3.6V - 5.77 -
= 10 bits Single or
fS(4) with Discontinuous
RAIN = 47 Ω mode fadc_ker_ck SMP
1.6V ≤ VDDA ≤ 3.6V -40°C ≤ TJ ≤ 130°C - 5.00 - MSPS
and = 65 MHz =2.5
CPCB = 22 pF
Resolution
- 6.82 -
= 8 bits
fadc_ker_ck
All modes 1.6V ≤ VDDA ≤ 3.6V
= 75 MHz
Resolution
- 8.33 -
= 6 bits

Resolution
- 2.30 -
= 12 bits
fadc_ker_ck
= 35 MHz
Resolution
- 2.70 -
Sampling rate = 10 bits
for slow All modes(5) 1.6V ≤ VDDA ≤ 3.6V
channels Resolution fadc_ker_ck
- 4.50 -
= 8 bits = 50 MHz

Resolution fadc_ker_ck
- 5.50 -
= 6 bits = 50 MHz

External trigger
tTRIG Resolution = 12 bits - - 15 1/fadc_ker_ck
period

Conversion
VAIN(2) - 0 - VREF+
voltage range
V
Common
VREF / 2 VREF / 2
VCMIV mode input - VREF / 2
− 10% + 10%
voltage

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Table 95. 12-bit ADC characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Resolution = 12 bits, TJ = 130°C (tolerance 4 LSBs) - - 321

Resolution = 12 bits, TJ = 125°C - - 220

Resolution = 10 bits, TJ = 130°C - - 1039

Resolution = 10 bits, TJ = 125°C - - 2100

External input
RAIN(6) Ω
impedance
Resolution = 8 bits, TJ = 130°C - - 6327

Resolution = 8 bits, TJ = 125°C - - 12000

Resolution = 6 bits, TJ = 130°C - - 47620

Resolution = 6 bits, TJ = 125°C - - 80000

Internal
CADC sample and - - 3 - pF
hold capacitor

tADCVREG_ LDO startup

- - 5 10 µs
STUP time

Conversion
tSTAB Power-up time LDO already started 1 - -
cycle

Offset
tOFF_CAL - 1335
calibration time

Trigger CKMODE = 00 1.5 2 2.5

conversion
latency for
regular and CKMODE = 01 - - 2.5
tLATR injected
channels CKMODE = 10 - - 2.5
without
aborting the
conversion CKMODE = 11 - - 2.25

Trigger CKMODE = 00 2.5 3 3.5

conversion 1/fadc_ker_ck
latency for
regular and CKMODE = 01 - - 3.5
tLATRINJ injected
channels when CKMODE = 10 - - 3.5
a regular
conversion is
aborted CKMODE = 11 - - 3.25

tS Sampling time - 2.5 - 640.5

Total
conversion tS + 0.5
tCONV N-bits resolution - -
time (including +N
sampling)

Consumption fs = 5 MSPS - 600 -

on VDDA and
IDDA_D(ADC) VREF, fs = 1 MSPS - 190 -
differential
mode fs = 0.1 MSPS - 50 -

fs = 5 MSPS - 500 -
Consumption
on VDDA and
IDDA_SE(ADC) fs = 1 MSPS - 150 -
VREF, single-
ended mode
fs = 0.1 MSPS - 50 -
µA
fadc_ker_ck = 75 MHz - 265 -

fadc_ker_ck = 50 MHz 175 -

fadc_ker_ck = 25 MHz - 90 -
Consumption
IDD(ADC)
on VDD
fadc_ker_ck = 12.5 MHz - 45 -

fadc_ker_ck = 6.25 MHz - 22 -

fadc_ker_ck = 3.125 MHz - 11 -

1. Specified by design - Not tested in production.

2. The voltage booster on ADC switches must be used for VDDA < 2.7 V (embedded I/O switches).

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3. This frequency is the analog ADC specification, it must respect the value in Table 21.
4. These values are valid on BGA packages.
5. Depending upon the package, VREF+ can be internally connected to VDDA, and VREF- to VSSA.
6. The tolerance is two LSBs for 12-bit, 10-bit and 8-bit resolutions, otherwise specified.

Table 96. Minimum sampling time versus RAIN(1)(2)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channel Slow channel(3)

47 3.75E-08 6.12E-08
68 3.94E-08 6.25E-08
100 4.36E-08 6.51E-08
150 5.11E-08 7.00E-08
12 bits
220 6.54E-08 7.86E-08
330 8.80E-08 9.57E-08
470 1.17E-07 1.23E-07
680 1.60E-07 1.65E-07
47 3.19E-08 5.17E-08
68 3.35E-08 5.28E-08
100 3.66E-08 5.45E-08
150 4.35E-08 5.83E-08
220 5.43E-08 6.50E-08
330 7.18E-08 7.89E-08
10 bits
470 9.46E-08 1.00E-07
680 1.28E-07 1.33E-07
1000 1.81E-07 1.83E-07
1500 2.63E-07 2.63E-07
2200 3.79E-07 3.76E-07
3300 5.57E-07 5.52E-07

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Table 96. Minimum sampling time versus RAIN(1)(2) (continued)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channel Slow channel(3)

47 2.64E-08 4.17E-08
68 2.76E-08 4.24E-08
100 3.02E-08 4.39E-08
150 3.51E-08 4.66E-08
220 4.27E-08 5.13E-08
330 5.52E-08 6.19E-08
470 7.17E-08 7.72E-08
680 9.68E-08 1.00E-07
8 bits
1000 1.34E-07 1.37E-07
1500 1.93E-07 1.94E-07
2200 2.76E-07 2.74E-07
3300 4.06E-07 4.01E-07
4700 5.73E-07 5.62E-07
6800 8.21E-07 7.99E-07
10000 1.20E-06 1.17E-06
15000 1.79E-06 1.74E-06
47 2.14E-08 3.16E-08
68 2.23E-08 3.21E-08
100 2.40E-08 3.31E-08
150 2.68E-08 3.52E-08
220 3.13E-08 3.87E-08
330 3.89E-08 4.51E-08
470 4.88E-08 5.39E-08
680 6.38E-08 6.79E-08
6 bits
1000 8.70E-08 8.97E-08
1500 1.23E-07 1.24E-07
2200 1.73E-07 1.73E-07
3300 2.53E-07 2.49E-07
4700 3.53E-07 3.45E-07
6800 5.04E-07 4.90E-07
10000 7.34E-07 7.11E-07
15000 1.09E-06 1.05E-06
1. Specified by design - Not tested in production.
2. Data valid up to 130 °C, with a 22 pF PCB capacitor, and VDDA = 1.6 V.

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3. Slow channels correspond to all ADC inputs except for the fast channels.

Figure 55. ADC conversion timing diagram

CLK

Mux Sampling(1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1/2 SMP Number of CLK clock cycles = ADC resolution / 2

Total conversion time: 0.5 +Tsamp + N/2

1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details).

Table 97. ADC accuracy(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Fast and slow Single ended - ±3.5 ±12

ET Total unadjusted error
channels Differential - ±2.5 ±7.5
- Single ended - ±3 ±5.5
EO Offset error
- Differential - ±2 ±3.5
- Single ended - ±3.5 ±11
EG Gain error LSB
- Differential ±2.5 ±7
- Single ended - ±0.75 +2/-1
ED Differential linearity error
- Differential - ±0.75 +2/-1

Fast and slow Single ended - ±2 ±6.5

EL Integral linearity error
channels Differential - ±1 ±4
Single ended - 10.8 -
ENOB Effective number of bits Bits
Differential - 11.5 -

Signal-to-noise and Single ended - 68 -

SINAD
distortion ratio Differential - 71 -
Single ended - 70 -
SNR Signal-to-noise ratio dB
Differential - 72 -
Single ended - -70 -
THD Total harmonic distortion
Differential - -80 -
1. Evaluated by characterization for BGA packages. The values for LQFP package can differ. Not tested in production.
2. ADC DC accuracy values are measured after internal calibration in continuous mode.

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Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins, which may potentially inject negative currents.

Figure 56. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

1. Example of an actual transfer curve.

2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
5. EO = Offset error: deviation between the first actual transition and the first ideal one.
6. EG = Gain error: deviation between the last ideal transition and the last actual one.
7. ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
8. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.

Figure 57. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter

Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 95 for the values of RAIN, and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

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pad capacitance (refer to Table 58). A high Cparasitic value downgrades conversion accuracy. To remedy
this, fADC should be reduced.
3. Refer to Table 58 for the value of Ilkg.
4. Refer to Figure 20.

General PCB design guidelines

It is recommended to perform power supply decoupling as shown in Figure 58 or Figure 59,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors must be
ceramic (good quality), and placed as close as possible to the chip.

Figure 58. Power supply and reference decoupling (VREF+ not connected to VDDA)

STM32

VREF+(1)

1 μF // 100 nF
VDDA

1 μF // 100 nF

VSSA/VREF-(1)

MSv50648V2

1. VREF+ input is not available on all packages (refer to Table 14), VREF- is available only on UFBGA176+25,
UFBGA169 with SMPS, LQFP100, UFBGA169, and UFBGA176+25 packages. When VREF+ is not
available, it is internally connected to VSSA.

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Figure 59. Power supply and reference decoupling (VREF+ connected to VDDA)

STM32

VREF+/VDDA(1)

1 μF // 100 nF

VREF-/VSSA(1)

MSv50649V1

1. VREF+ input is not available on all packages (refer to Table 14), VREF- is available only on UFBGA176+25,
UFBGA169 with SMPS, LQFP100, UFBGA169, and UFBGA176+25 packages. When VREF- is not
available, it is internally connected to VSSA. If VREF- is available and connected to VDDA, refer to Figure 20
for more detailsIf.

5.3.24 DAC characteristics

Table 98. DAC characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.8 3.3 3.6

VREF+ Positive reference voltage - 1.8 - VDDA V
VREF- Negative reference voltage - - VSSA -
Connected
5 - -
DAC output buffer to VSSA
RL Resistive load
ON Connected kΩ
25 - -
to VDDA
RO Output impedance DAC output buffer OFF 10.3 13 16
Output impedance sample VDD = 2.7 V - - 1.6
DAC output buffer
RBON and hold mode, output kΩ
ON VDD = 2.0 V - - 2.6
buffer ON
Output impedance sample VDD = 2.7 V - - 17.8
DAC output buffer
RBOFF and hold mode, output kΩ
OFF VDD = 2.0 V - - 18.7
buffer OFF
CL DAC output buffer OFF - - 50 pF
Capacitive load
CSH Sample and Hold mode - 0.1 1 µF
VDDA
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT −0.2 V
output
DAC output buffer OFF 0 - VREF+

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Table 98. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

±0.5 LSB - 2.05 3

Settling time (full scale: for a Normal mode, DAC ±1 LSB - 1.97 2.87
12-bit code transition output buffer ON,
between the lowest and the ±2 LSB - 1.67 2.84
CL ≤ 50 pF,
tSETTLING highest input codes when RL ≥ 5 kΩ ±4 LSB - 1.66 2.78 µs
DAC_OUT reaches the final
value of ±0.5LSB, ±1LSB, ±8 LSB - 1.65 2.7
±2LSB, ±4LSB, ±8LSB) Normal mode, DAC output buffer
- 1.7 2
OFF, ±1LSB CL= 10 pF
Wake-up time from off state Normal mode, DAC output buffer
- 5 7.5
(setting the ENx bit in the ON, CL ≤ 50 pF, RL = 5 kΩ
tWAKEUP
(2) DAC control register) until µs
the final value of ±1LSB is Normal mode, DAC output buffer
- 2 5
reached OFF, CL ≤ 10 pF

DC VDDA supply rejection Normal mode, DAC output buffer

PSRR - -80 -28 dB
ratio ON, CL ≤ 50 pF, RL = 5 kΩ
Sampling time in Sample MODE<2:0>_V12 = 100/101
- 0.7 2.6
and Hold mode, CL= 100 nF (BUFFER ON)
(code transition between the ms
MODE<2:0>_V12 = 110
tSAMP lowest and the highest input - 11.5 18.7
(BUFFER OFF)
code when DAC_OUT
reaches the ±1LSB final MODE<2:0>_V12=111(3)
- 0.3 0.6 µs
value) (INTERNAL BUFFER OFF)
(4)
Ileak Output leakage current - - - nA
Internal sample and hold
CIint - 1.8 2.2 2.6 pF
capacitor
tTRIM Middle code offset trim time Minimum time to verify each code 50 - - µs

Middle code offset for VREF+ = 3.6 V - 850 -

Voffset µV
1 trim code step VREF+ = 1.8 V - 425 -
No load,
middle
- 360 -
code
DAC output buffer (0x800)
ON
No load,
worst code - 490 -
DAC quiescent consumption (0xF1C)
IDDA(DAC) µA
from VDDA
No load,
DAC output buffer middle/
- 20 -
OFF worst code
(0x800)
Sample and Hold mode, 360*TON/
- -
CSH = 100 nF (TON+TOFF)(5)

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Table 98. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

No load,
middle
- 170 -
code
DAC output buffer (0x800)
ON
No load,
worst code - 170 -
(0xF1C)
DAC consumption from
IDDV(DAC) No load, µA
VREF+
DAC output buffer middle/
- 160 -
OFF worst code
(0x800)
Sample and Hold mode, buffer ON, 170*TON/
- -
CSH = 100 nF (worst code) (TON+TOFF)(5)
Sample and Hold mode, buffer 160*TON/
- -
OFF, CSH = 100 nF (worst code) (TON+TOFF)(5)
1. Specified by design - Not tested in production, unless otherwise specified.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
3. DACx_OUT pin is not connected externally (internal connection only).
4. Refer to Table 58.
5. TON is the refresh phase duration, TOFF is the hold phase duration. Refer to the reference manual for more details.

Table 99. DAC accuracy(1)

Symbol Parameter Conditions Min Typ Max Unit

Differential non DAC output buffer ON −2 - 2

DNL LSB
linearity(2) DAC output buffer OFF −2 - 2
- Monotonicity 10 bits - - - -
DAC output buffer ON,
−4 - 4
CL≤50 pF, RL≥5 kΩ
INL Integral non linearity(3)
DAC output buffer OFF,
−4 - 4
CL ≤ 50 pF, no RL

DAC output buffer ON, VREF+ = 3.6 V - - ±12

Offset error at code CL≤50 pF, RL ≥5 kΩ VREF+ = 1.8 V - - ±25
Offset
0x800 (3) LSB
DAC output buffer OFF,
- - ±8
CL ≤ 50 pF, no RL
Offset error at code DAC output buffer OFF,
Offset1 - - ±5
0x001(4) CL ≤ 50 pF, no RL
Offset error at code VREF+ = 3.6 V - - ±5
DAC output buffer ON,
OffsetCal 0x800 after factory
CL≤50 pF, RL ≥5 kΩ VREF+ = 1.8 V - - ±7
calibration

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Table 99. DAC accuracy(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit
DAC output buffer ON,
- - ±1
CL≤50 pF, RL ≥5 kΩ
Gain Gain error(5) %
DAC output buffer OFF,
- - ±1
CL ≤ 50 pF, no RL
DAC output buffer ON,
- - ±30
CL≤50 pF, RL ≥5 kΩ
TUE Total unadjusted error
DAC output buffer OFF,
±12 LSB
CL≤50 pF, no RL
Total unadjusted error DAC output buffer ON,
TUECal - - ±23
after calibration CL≤50 pF, RL ≥5 kΩ
DAC output buffer ON, CL≤50 pF,
- 67.8 -
RL ≥5 kΩ, 1 kHz, BW = 500 kHz
SNR Signal-to-noise ratio(6)
DAC output buffer OFF, CL ≤ 50 pF,
- 67.8 -
no RL,1 kHz, BW = 500 kHz
DAC output buffer ON,
- −78.6 -
Total harmonic CL≤50 pF, RL ≥5 kΩ, 1 kHz
THD dB
distortion(6) DAC output buffer OFF,
- −78.6 -
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON,
- 67.5 -
Signal-to-noise and CL≤50 pF, RL ≥5 kΩ, 1 kHz
SINAD
distortion ratio(6) DAC output buffer OFF,
- 67.5 -
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON,
- 10.9 -
Effective number of CL≤50 pF, RL ≥ 5 kΩ, 1 kHz
ENOB bits
bits DAC output buffer OFF,
- 10.9 -
CL ≤ 50 pF, no RL, 1 kHz
1. Evaluated by characterization - Not tested in production.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5 dBFS with Fsampling = 1 MHz.

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Figure 60. 12-bit buffered/non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)
RL

12-bit DAC_OUTx
digital to
analog
converter
CL

ai17157V3

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly, without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.

5.3.25 Analog temperature sensor characteristics

Table 100. Analog temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

VSENSE linearity with temperature (from VSENSOR voltage) - - 3

TL(1) °C
VSENSE linearity with temperature (from ADC counter) - - 3
Average slope (from VSENSOR voltage) - 2 -
Avg_Slope(2) mV/°C
Average slope (from ADC counter) - 2 -
V30(3) Voltage at 30 °C ± 5 °C - 0.62 - V
tstart_run Startup time in Run mode (buffer startup) - - 25.2
µs
(1)
tS_temp ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5
1. Specified by design - Not tested in production.
2. Evaluated by characterization - Not tested in production.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 bytes.

Table 101. Temperature sensor calibration values

Symbol Parameter Memory address

Temperature sensor raw data acquired value at 30 °C,

TS_CAL1 0x08FF F814 -0x08FF F815
VDDA = 3.3 V
Temperature sensor raw data acquired value at 130 °C,
TS_CAL2 0x08FF F818 - 0x08FF F819
VDDA = 3.3 V

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5.3.26 Digital temperature sensor characteristics

Table 102. Digital temperature sensor characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fDTS(2) Output clock frequency - 500 750 1150 kHz

TLC(2) Temperature linearity coefficient VOS2 1660 2100 2750 Hz/°C

Temperature offset TJ = −40 to 30 °C -13 - 4

TTOTAL_ERROR(2) °C
measurement, all VOS TJ = 30 °C to TJmax -7 - 2
VOS2 0 - 0
Additional error due to supply
TVDD_CORE VOS0, VOS1, °C
variation -1 - 1
VOS3
tTRIM Calibration time - - - 2 ms
Wake-up time from off state
tWAKE_UP - - 67 116 μs
until DTS ready bit is set
IDDCORE_DTS DTS consumption on VDD_CORE - 8.5 30 70 μA
1. Specified by design - Not tested in production, unless otherwise specified.
2. Evaluated by characterization - Not tested in production.

5.3.27 VCORE monitoring characteristics

Table 103. VCORE monitoring characteristics(1)

Symbol Parameter Min Typ Max Unit

TS_VCORE ADC sampling time when reading the VCORE voltage 1 - - μs

1. Specified by design - Not tested in production.

5.3.28 Temperature and VBAT monitoring

Table 104. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 4 x 26 - kΩ

Q Ratio on VBAT measurement - 4 - -
(1)
Er Error on Q -10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring 3.50 3.575 3.63
V
VBATlow Low supply monitoring - 1.36 -
IVBATbuf Sensor buffer consumption - 3.8 6.5 µA
1. Specified by design - Not tested in production.

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Table 105. VBAT charging characteristics

Symbol Parameter Conditions Min Typ Max Unit

VBRS in PWR_CR3 = 0 - 5 -
RBC Battery charging resistor kΩ
VBRS in PWR_CR3 = 1 - 1.5 -

Table 106. Temperature monitoring characteristics

Symbol Parameter Min Typ Max Unit

TEMPhigh High temperature monitoring - 126 -

°C
TEMPlow Low temperature monitoring - -37 -

5.3.29 Voltage booster for analog switch

Table 107. Voltage booster for analog switch characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDD Supply voltage - 1.71 2.6 3.6 V

tSU(BOOST) Booster startup time - - - 50 µs
1.71 V ≤ VDD ≤ 2.7 V - - 125
IDD(BOOST) Booster consumption µA
2.7 V < VDD < 3.6 V - - 250
1. Evaluated by characterization - Not tested in production.

5.3.30 VREFBUF characteristics

Table 108. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VRS = 000 2.8 3.3 3.6

Normal mode at
VRS = 001 2.4 - 3.6
VDDA = 3.3 V
Analog supply VRS = 010 2.1 - 3.6
VDDA V
voltage VRS = 000 1.62 - 2.80
Degraded mode(2) VRS = 001 1.62 - 2.40
VRS = 010 1.62 - 2.10
VRS = 000 2.498(3) 2.5000 2.5035(3)
Normal mode at
VRS = 001 2.0460 2.0490 2.0520
30 °C, ILOAD = 100 µA
VREFBUF_ Voltage reference VRS = 010 1.8010 1.8040 1.8060
V
OUT buffer output VRS = 000 VDDA − 150 mV - 2.5035
Degraded mode(2) VRS = 001 VDDA − 150 mV - 2.0520
VRS = 010 VDDA − 150 mV - 1.8060
Trim step
TRIM - - - ±0.05 ±0.1 %
resolution

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Table 108. VREFBUF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

CL Load capacitor - - 0.5 1 1.50 μF

Equivalent serial
esr - - - - 2 Ω
resistor of CL
Iload Static load current - - - - 4 mA
Iload = 500 µA - 200 - ppm/
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V
Iload = 4 mA - 100 - V

ppm/
Iload_reg Load regulation 500 µA ≤ Iload ≤ 4 mA Normal mode - 50 -
mA
Temperature ppm/
Tcoeff -40 °C < TJ < +130 °C - - - 100
coefficient °C

Power supply DC - - 60 -
PSRR dB
rejection 100 kHz - - 40 -
CL= 0.5 µF - - 300 -
tSTART Start-up time CL= 1 µF - - 500 - µs
CL= 1.5 µF - - 650 -
Control of
maximum DC
IINRUSH current drive on - - 8 - mA
VREFBUF_OUT
during startup(4)
ILOAD = 0 µA - - 15 25
IDDA(VREF Consumption
ILOAD = 500 µA - - 16 30 µA
BUF) from VDDA
ILOAD = 4 mA - - 32 50
1. Specified by design - Not tested in production, unless otherwise specified.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. Evaluated by characterization - Not tested in production.
4. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage must be in
the range of 2.1 V - 3.6 V, 2.4 V -3.6 V, and 2.8 V - 3.6 V, respectively, for VRS = 010, 001, and 000.

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5.3.31 Timer characteristics

The parameters given in Table 109 are guaranteed by design.
Refer to Section 5.3.15 for details on the input/output alternate function characteristics
(output compare, input capture, external clock, PWM output).

Table 109. TIMx characteristics(1)(2)

Symbol Parameter Conditions(3) Min Max Unit

AHB/APBx prescaler = 1, 2, or 4,
1 - tTIMxCLK
fTIMxCLK = 250 MHz
tres(TIM) Timer resolution time
AHB/APBx prescaler > 4,
1 - tTIMxCLK
fTIMxCLK = 125 MHz

Timer external clock

fEXT 0 fTIMxCLK / 2 MHz
frequency on CH1 to CH4 fTIMxCLK = 250 MHz
ResTIM Timer resolution - 16 / 32 bit
Maximum possible count
tMAX_COUNT - - 65536 × 65536 tTIMxCLK
with 32-bit counter
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Specified by design - Not tested in production.
3. The maximum timer frequency on APB1 or APB2 is up to 250 MHz, by setting the TIMPRE bit in the RCC_CFGR register,
if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4 x Frcc_pclkx1 or
TIMxCLK = 4 x Frcc_pclkx2.

5.3.32 Low-power timer characteristics

Table 110. LPTIMx characteristics(1)(2)

Symbol Parameter Min Max Unit

tres(TIM) Timer resolution time 1 - tlptim_ker_ck

flptim_ker_ck Timer kernel clock 0 250

MHz
fEXT Timer external clock frequency on Input1 and Input2 0 flptim_ker_ck / 3

ResTIM Timer resolution - 16 bit

tMAX_COUNT Maximum possible count - 65535 tlptim_ker_ck

1. LPTIMx is used as a general term for LPTIM1 to LPTIM6 timers.

2. Specified by design - Not tested in production.

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5.3.33 Communication interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are specified by design, not tested in production, when the I2C
peripheral is properly configured (refer to the product reference manual)
The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but still present. Only
FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to
Section 5.3.15 for the I2C I/Os characteristics
All I2C SDA and SCL I/Os embed an analog filter, refer to Table 111 for its characteristics.

Table 111. I2C analog filter characteristics(1)(2)

Symbol Parameter Min Max Unit

tAF Maximum pulse width of spikes suppressed by analog filter 50(3) 160(4) ns
1. Evaluated by characterization - Not tested in production.
2. Measurement points are done at 50% VDD.
3. Spikes with widths below tAF(min) are filtered.
4. Spikes with widths above tAF(max) are not filtered.

USART interface characteristics

Unless otherwise specified, the parameters given in Table 112 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• VOS level set to VOS0
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.15 for more details on the input/output alternate function characteristics
(NSS, CK, TX, RX for USART).

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Table 112. USART characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master receiver
31
1.71 V < VDD < 3.6 V
Master transmitter
31/6(2)
1.71 V < VDD < 3.6 V
Master transmitter
31/6(2)
2.7 V < VDD < 3.6 V
fCK USART clock frequency - - MHz
Slave receiver
83
1.71 V < VDD < 3.6 V
Slave transmitter
32/6(2)
1.71 V < VDD < 3.6 V
Slave transmitter
35/6(2)
2.7 V < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode tker(3) + 3.5 - -
th(NSS) NSS hold time Slave mode 2.5 - -
tw(SCKH)
CK high and low time Master mode 1/fck/2 -1 1/fck/2 1/fck/2 +1
tw(SCKL)
Master mode 13 - -
tsu(RX) Data input setup time
Slave mode 3.5 - -
Master mode 0.5 - -
th(RX) Data input hold time
Slave mode 1.5 - - ns
Slave mode,
- 15.5/71(2)
1.71 V < VDD < 3.6 V
11.5
Slave mode,
- 14/35(2)
2.7 V < VDD < 3.6 V
tv(TX) Data output valid time
Slave mode,
- 3/52(2)
1.71 V < VDD < 3.6 V
2.5
Slave mode,
- 3/22(2)
2.7 V < VDD < 3.6 V
Slave mode 7.5 - -
th(TX) Data output hold time ns
Master mode 0 - -
1. Evaluated by characterization - Not tested in production.
2. For PB14 with OSPEEDRy[1:0] = 01.
3. Tker is the usart_ker_ck_pres clock period.

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Figure 61. USART timing diagram in Master mode

1/fCK

CK output
CPHA = 0
CPOL = 0
CPHA = 0
CK output CPOL = 1

CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(CKH)
tsu(RX) tw(CKL)
RX
INPUT MSB IN BIT6 IN LSB IN
th(RX)
TX
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX)
MSv65386V4

1. Measurement points are done at 0.5VDD and with external CL = 30 pF.

Figure 62. USART timing diagram in Slave mode

NSS
input
1/fCK th(NSS)
tsu(NSS) tw(CKH)

CPHA = 0
CK input

CPOL = 0
CPHA = 0
CPOL = 1

tw(CKL) tv(TX) th(TX)

TX output First bit OUT Next bits OUT Last bit OUT

th(RX)
tsu(RX)

RX input First bit IN Next bits IN Last bit IN

MSv65387V4

I3C interface characteristics

The I3C interface meets the timings requirements of the MIPI® I3C specification v1.1.
The I3C peripheral supports:
• I3C SDR-only as controller
• I3C SDR-only as target
• I3C SCL bus clock frequency up to 12.5 MHz

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The parameters given in Table 113 are obtained with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0
The timings are in line with MIPI specification, except for the ones given in Table 113 and
Table 114. For tSU_OD and tSU_PP this can be mitigated by increasing the corresponding
SCL low duration in the I3C_TIMINGR0 register. For tSCO this can be mitigated by enabling
and adjusting the clock stall time both on the address ACK phase and on the data read Tbit
phase in the I3C_TIMINGR2 register. This can also be mitigated by increasing the SCL low
duration in the I3C_TIMINGR0 register. For further details refer to AN5879.

Table 113. I3C open-drain measured timing

I3C open drain mode
(specification) Timing
Symbol Parameter Conditions Unit
measurements
Min Max

SDA data setup time Controller

tSU_OD 3 - 16.5 ns
during open drain mode 1.71 V < VDD < 3.6 V

Table 114. I3C push-pull measured timing

I3C open drain mode
(specification) Timing
Symbol Parameter Conditions Unit
measurements
Min Max

SDA signal data setup in Controller

tSU_PP 3 - 12 ns
push-pull mode 1.71 V < VDD < 3.6 V

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 115 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0
Refer to Section 5.3.15 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).

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Table 115. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master receiver mode

- - 135/3(2)
2.7 V < VDD < 3.6 V
Master receiver mode
- - 120/3(2)
1.71 V < VDD < 2.7 V
Master transmitter mode
135/3(2)
2.7 V < VDD < 3.6 V
fSCK Master transmitter mode
SPI clock frequency - - 120/3(2) MHz
1/tSCK 1.71 V < VDD < 3.6 V
Slave receiver mode
- - 120
1.71 V < VDD < 3.6 V
Slave transmitter mode
- - 43/6(3)
2.7 V < VDD < 3.6 V
Slave transmitter mode
- - 41/6(3)
1.71 V < VDD < 2.7 V
tsu(NSS) NSS setup time Slave mode 3.5 - - ns
th(NSS) NSS hold time Slave mode 4.5 - - ns
tw(SCKH)
SCK high and low time Master mode (tSCK/2) - 1 (tSCK/2) (tSCK/2) + 1 ns
tw(SCKL)
tsu(MI) Master mode 3.5 - -
Data input setup time ns
tsu(SI) Slave mode 2 - -
th(MI) Master mode 1 - -
Data input hold time ns
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 6.5 - 15 ns
tdis(SO) Data output disable time Slave mode 7.5 - 18 ns
Slave mode,
- 8.5/25(3) 11.5/33(3)
2.7 V < VDD < 3.6 V
tv(SO)
Data output valid time Slave mode, ns
- 10/59(3) 12/76(3)
1.71 V < VDD < 3.6 V
tv(MO) Master mode - 1.5 2
Slave mode,
th(SO) 6.5/20.5(3) - -
Data output hold time 1.71 V < VDD < 3.6 V ns
th(MO) Master mode 0 - -
1. Evaluated by characterization - Not tested in production.
2. When using PB13.
3. When using PB14.

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Figure 63. SPI timing diagram - Master mode

High
(1)
SS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output

CPOL=0

CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output

CPOL=0

CPHA=1
CPOL=1
tsu(MI) th(MI)

MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT

tv(MO) th(MO)
MSv69586V2

1. The SS input can be configured to active low or active high.

Figure 64. SPI timing diagram - Slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

th(SI)
tsu(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

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Figure 65. SPI timing diagram - Slave mode and CPHA = 1

SS input(1)

tc(SCK) th(SS)
tsu(SS) tw(SCKH)
CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv69585V2

1. The SS input can be configured to active low or active high.

I2S interface characteristics

Unless otherwise specified, the parameters given in Table 116 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0
Refer to Section 5.3.15 for more details on the input/output alternate function characteristics
(CK,SD,WS).

Table 116. I2S dynamic characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK I2S main clock output - - 50

Master transmitter - 50
MHz
fCK I2S clock output Slave transmitter (TX) - 21
Slave receiver (RX) - 50

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Table 116. I2S dynamic characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

tv(WS) WS valid time - 2

Master mode
th(WS) WS hold time 0.5 -
tsu(WS) WS setup time 3 -
Slave mode
th(WS) WS hold time 1.5 -
tsu(SD_MR) Master receiver 4 -
Data input setup time
tsu(SD_SR) Slave receiver 2 -
ns
th(SD_MR) Master receiver 1 -
Data input hold time
th(SD_SR) Slave receiver 1.5 -
tv(SD_ST) Slave transmitter (after enable edge) - 14
Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 1
th(SD_ST) Slave transmitter (after enable edge) 5.5 -
Data output hold time
th(SD_MT) Master transmitter (after enable edge) 0 -
1. Evaluated by characterization - Not tested in production.

Figure 66. I2S slave timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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Figure 67. I2S master timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

USB full speed (FS) characteristics

The USB interface is fully compliant with the USB specification version 2.0.

Table 117. USB DC electrical characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

VDD USB full speed transceiver operating voltage - 3.0(2) - 3.6 V

VDI(3) Differential input sensitivity Over VCM range 0.2 - -
VCM(3) Differential input common mode range Includes VDI range 0.8 - 2.5 V
VSE(3) Single ended receiver input threshold - 0.8 - 2.0
VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
V
VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
Pull down resistor on PA11, PA12
RPD(3) VIN = VDD 14.25 - 24.8
(USB_DP/DM)
kΩ
Pull-up resistor on PA12 (USB_DP) VIN = VSS, during idle 0.9 1.25 1.575
RPU(3)
Pull-up resistor on PA12 (USB_DP) VIN = VSS during reception 1.425 2.25 3.09
1. All the voltages are measured from the local ground potential.
2. The USB full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical
characteristics, which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Specified by design - Not tested in production.

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4. RL is the load connected on the USB full speed drivers.

Figure 68. USB timings - definition of data signal rise and fall time

Cross over
points
Differential
data lines

VCRS

VSS

tf tr
ai14137b

Table 118. USB startup time

Symbol Parameter Max Unit

tSTARTUP(1) USB transceiver startup time 1 μs

1. Specified by design - Not tested in production.

Table 119. USB electrical characteristics(1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit

trLS Rise time in LS(2) CL = 200 to 600 pF 75 300 ns

tfLS Fall time in LS(2) CL = 200 to 600 pF 75 300 ns
trfmLS Rise/fall time matching in LS tr/tf 80 125 %
trFS Rise time in FS(2) CL = 50 pF 4 20 ns
tfFS Fall time in FS(2) CL = 50 pF 4 20 ns
trfmFS Rise/fall time matching in FS tr/tf 90 111 %
VCRS Output signal crossover voltage (LS/FS) - 1.3 2.0 V
ZDRV Output driver impedance(3) Driving high or low 28 44 Ω
1. Specified by design - Not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed information, refer to USB specification -
chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.

Table 120. USB BCD DC electrical characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Primary detection mode consumption - - - 300

IDD(USBBCD) μA
Secondary detection mode consumption - - - 300
RDAT_LKG Data line leakage resistance - 300 - - kΩ
VDAT_LKG Data line leakage voltage - 0.0 - 3.6 V

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Table 120. USB BCD DC electrical characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Dedicated charging port resistance

RDCP_DAT - - - 200 Ω
across D+/D-
VLGC_HI Logic high - 2.0 - 3.6
VLGC_LOW Logic low - - - 0.8
VLGC Logic threshold - 0.8 - 2.0
V
VDAT_REF Data detect voltage - 0.25 - 0.4
VDP_SRC D+ source voltage - 0.5 - 0.7
VDM_SRC D- source voltage - 0.5 - 0.7
IDP_SINK D+ sink current - 25 - 175
μA
IDM_SINK D- sink current - 25 - 175
1. Specified by design - Not tested in production.

SAI characteristics
Unless otherwise specified, the parameters given in Table 121 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• I/O compensation cell activated
• Measurement points are done at CMOS levels: 0.5 VDD
• VOS level set to VOS0
Refer to Section 5.3.15 for more details on the input/output alternate function characteristics
(SCK, SD, WS).

Table 121. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK SAI main clock output - - 50

Master transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 38
Master transmitter, 1.71 V ≤ VDD ≤ 3.6 V - 38
Master receiver, 1.71 V ≤ VDD ≤ 3.6 V - 38 MHz
fCK SAI clock frequency
Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 34
Slave transmitter, 1.71 V ≤ VDD ≤ 3.6 V - 33
Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V - 50

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Table 121. SAI characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

Master mode, 2.7 V ≤ VDD ≤ 3.6 V - 13

tv(FS) FS valid time
Master mode, 1.71 V ≤ VDD ≤ 3.6 V - 13
tsu(FS) FS setup time Slave mode 3 -
Master mode 5 -
th(FS) FS hold time
Slave mode 2 -
tsu(SD_A_MR) Master receiver 4 -
Data input setup time
tsu(SD_B_SR) Slave receiver 3.5 -
th(SD_A_MR) Master receiver 1.5 -
Data input hold time
th(SD_B_SR) Slave receiver 0.5 -
ns
Slave transmitter (after enable edge),
- 14.5
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge),
- 15
1.71 V ≤ VDD ≤ 3.6 V
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 7 -
Master transmitter (after enable edge),
- 13
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge),
- 13
1.71 V ≤ VDD ≤ 3.6 V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 5.5 -
1. Evaluated by characterization - Not tested in production.

Figure 69. SAI master timing waveforms

1/fSCK

SAI_SCK_X
(CKSTR = 0)

SAI_SCK_X
(CKSTR = 1)
th(FS)

SAI_FS_X
(output)
tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
(transmit) Slot n Slot n+2

tsu(SD_MR) th(SD_MR)

SAI_SD_X
(receive) Slot n

MS32771V2

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Figure 70. SAI slave timing waveforms

1/fSCK

SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)

tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input)
tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X Slot n Slot n+2

(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X
Slot n
(receive)
MS32772V2

SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 122 and Table 123 are derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD supply
voltage summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL= 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.15 for more details on the input/output characteristics.

Table 122. Dynamic characteristics: SD/MMC, VDD = 2.7 to 3.6 V(1)

Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 130(2)/6(3) MHz

tW(CKL) Clock low time 8.5 9.5 -
fPP = 52 MHz ns
tW(CKH) Clock high time 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) mode

tISU Input setup time HS - 3 - -

tIH Input hold time HS - 1 - - ns
tIDW(5) Input valid window (variable window) - 4.5 - -

CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) mode

tOV Output valid time HS - - 5 5.5/38(3)

ns
tOH Output hold time HS - 3 - -

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Table 122. Dynamic characteristics: SD/MMC, VDD = 2.7 to 3.6 V(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

CMD, D inputs (referenced to CK) in SD default mode

tISUD Input setup time SD - 2.5 -

ns
tIHD Input hold time SD - 1.5 -

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD - - 0.5 1/33(3)

ns
tOHD Output hold default time SD - 0 - -
1. Evaluated by characterization - Not tested in production.
2. CL applied is 20 pF.
3. When using PB13 and PB14.
4. For SD 1.8 V support, an external voltage converter is needed.
5. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Table 123. Dynamic characteristics: eMMC, VDD = 1.71 to 1.9 V(1)

Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 110(2)/6(3) MHz

tW(CKL) Clock low time 8.5 9.5 -
fPP =52 MHz ns
tW(CKH) Clock high time 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC mode

tISU Input setup time HS - 1.5 - -

tIH Input hold time HS - 1.5 - - ns
tIDW(4) Input valid window (variable window) - 4 - -

CMD, D outputs (referenced to CK) in eMMC mode

tOV Output valid time HS - - 5.5 6/75(3)

ns
tOH Output hold time HS - 3 - -
1. Evaluated by characterization - Not tested in production.
2. CL = 20 pF.
3. When using PB13 and PB14.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

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Figure 71. SDIO high-speed/eMMC timing

MSv72345V1

Figure 72. SD default speed timings

CK
tOV tOH

D, CMD output MSv69710V1

Figure 73. DDR mode timings

D input Valid data Valid data

tISU tIH tISU tIH

tW(CKH)

CK

tW(CKL)
tOV tOV
tOH tOH

D output Valid data Valid data

MSv69158V1

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Ethernet interface characteristics

Unless otherwise specified, the parameters given in Table 124, Table 125, and Table 126
are derived from tests performed under the ambient temperature, frcc_c_ck frequency and
VDD supply voltage conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL= 20 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.5 V
Refer to Section 5.3.15 for more details on the input/output characteristics.

Table 124. Dynamic characteristics: Ethernet MAC signals for SMI (1)
Symbol Parameter Min Typ Max Unit

tMDC MDC cycle time (2.5 MHz) 400 400 403

Td(MDIO) Write data valid time 0 0.5 1
ns
tsu(MDIO) Read data setup time 12.5 - -
th(MDIO) Read data hold time 0 - -
1. Evaluated by characterization - Not tested in production.

Table 125. Dynamic characteristics: Ethernet MAC signals for RMII (1)
Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 3 - -

tih(RXD) Receive data hold time 1 - -
tsu(CRS) Carrier sense setup time 2 - -
ns
tih(CRS) Carrier sense hold time 1 - -
td(TXEN) Transmit enable valid delay time 7.5 9.5 15
td(TXD) Transmit data valid delay time 7.5 10 15.5
1. Evaluated by characterization - Not tested in production.

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Table 126. Dynamic characteristics: Ethernet MAC signals for MII (1)
Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 3 - -

tih(RXD) Receive data hold time 1.5 - -
tsu(DV) Data valid setup time 2 - -
tih(DV) Data valid hold time 1 - -
ns
tsu(ER) Error setup time 3 - -
tih(ER) Error hold time 1 - -
td(TXEN) Transmit enable valid delay time 7.5 10 16
td(TXD) Transmit data valid delay time 8 10.5 16.5
1. Evaluated by characterization - Not tested in production.

Figure 74. Ethernet RMII timing diagram

RMII_REF_CLK

td(TXEN)
td(TXD)

RMII_TX_EN
RMII_TXD[1:0]

tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)

RMII_RXD[1:0]
RMII_CRS_DV

ai15667b

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Figure 75. Ethernet MII timing diagram

MII_RX_CLK

tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)

MII_RXD[3:0]
MII_RX_DV
MII_RX_ER

MII_TX_CLK

td(TXEN)
td(TXD)

MII_TX_EN
MII_TXD[3:0]

ai15668b

Figure 76. Ethernet SMI timing diagram

tMDC

ETH_MDC

td(MDIO)

ETH_MDIO(O)

tsu(MDIO) th(MDIO)

ETH_MDIO(I)

MS31384V1

JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 127 and Table 128 for
JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck
frequency and VDD supply voltage summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL= 30 pF
• HSLV activated when VDD ≤ 2.7 V
• Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.15 for more details on the input/output characteristics:

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Table 127. Dynamic JTAG characteristics

Symbol Parameter Conditions Min Typ Max Unit

FTCK 2.7 V < VDD < 3.6 V - - 50

TCK clock frequency MHz
1/tc(TCK) 1.71 V < VDD < 3.6 V - - 45
tisu(TMS) TMS input setup time - 2 - -
tih(TMS) TMS input hold time - 1.5 - -
tisu(TDI) TDI input setup time - 1.5 - -
tih(TDI) TDI input hold time - 1.5 - - ns
2.7V < VDD < 3.6 V - 8 10
tov(TDO) TDO output valid time
1.71 < VDD < 3.6 V - 8 11
toh(TDO) TDO output hold time - 6.5 - -

Table 128. Dynamic SWD characteristics

Symbol Parameter Conditions Min Typ Max Unit

FSWCLK 2.7 V < VDD < 3.6 V - - 80

SWCLK clock frequency MHz
1/tc(SWCLK) 1.71 V < VDD < 3.6 V - - 71
tisu(SWDIO) SWDIO input setup time - 1.5 - -
tih(SWDIO) SWDIO input hold time - 1.5 - -
2.7 V < VDD < 3.6 V - 10.5 12.5 ns
tov(SWDIO) SWDIO output valid time
1.71 V < VDD < 3.6 V - 10.5 14.0
toh(SWDIO) SWDIO output hold time - 8.5 - -

Figure 77. JTAG timing diagram

tc(TCK)

TCK

tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS

tov(TDO) toh(TDO)

TDO

MSv40458V1

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Figure 78. SWD timing diagram

tc(SWCLK)

SWCLK

tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)

tov(SWDIO) toh(SWDIO)

SWDIO
(transmit)

MSv40459V1

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6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

6.1 Device marking

Refer to “Reference device marking schematics for STM32 microcontrollers and
microprocessors” (TN1433), available on www.st.com, for the location of pin 1 / ball A1 as
well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.

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6.2 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 79. LQFP64 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4

0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A

(13) (N – 4)x e

C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C

D (4)

(5) (2) D1 (9) (11)

(10)
D (3) b WITH PLATING
N (4)

1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)

A A SECTION B-B
(Section A-A)

TOP VIEW 5W_LQFP64_ME_V1

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Table 129. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 80. LQFP64 - Footprint example

48 33

0.30
49 0.5 32

12.70

10.30

10.30
64 17

1.20
1 16

7.80

12.70
5W_LQFP64_FP_V2

1. Dimensions are expressed in millimeters.

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6.3 VFQFPN68 package information (B029)

This VFQFPN is a 68 pins, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat package.

Figure 81. VFQFPN68 - Outline

PIN 1 IDENTIFIER
LASER MARKING ddd C
D
A
A1
68 67 A2
1
2

E E

(2X) 0.10 C
SEATING
C PLANE

TOP VIEW SIDE VIEW

L
D2

E2

2
1

PIN 1 ID
C 0.30 X 45'
68 67 b
e
EXPOSED PAD AREA
BOTTOM VIEW B029_VFQFPN68_ME_V1

1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Packages No lead. Sawed
version. Very thin profile: 0.80 < A ≤ 1.00mm.
2. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other
feature of package body. Exact shape and size of this feature is optional.

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Table 130. VFQFPN68 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0 0.02 0.05 0 0.0008 0.0020
A3 - 0.20 - - 0.0008 -
b 0.15 0.20 0.25 0.0059 0.0079 0.0098
D 7.85 8.00 8.15 0.3091 0.3150 0.3209
D2 6.30 6.40 6.50 0.2480 0.2520 0.2559
E 7.85 8.00 8.15 0.3091 0.3150 0.3209
E2 6.30 6.40 6.50 0.2480 0.2520 0.2559
e - 0.40 - - 0.0157 -
L 0.40 0.50 0.60 0.0157 0.0197 0.0236
ddd - - 0.08 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 82. VFQFPN68 - Footprint example

8.30
7.00
6.65

0.15 6.40
6.65
7.00
8.30
6.40

0.25

0.82
0.65
0.40
B029_VFQFPN68_FP_V2

1. Dimensions are expressed in millimeters.

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6.4 WLCSP80 package information (B0D4)

This WLCSP is a 80 ball, 3.50 x 3.27 mm, 0.35 mm pitch, wafer level chip scale package.

Figure 83. WLCSP80 - Outline

F e1
G (DETAIL A)
(DETAIL B)

K e e

e
e2
DETAIL B

BACKSIDE CODE
BOTTOM VIEW
A

bbb C
A3 A2 SIDE VIEW

SIDE VIEW

DETAIL A
BUMP
D

A1
eee Z

E
b (80x)
ccc Z X Y
ddd Z
A1 Orientation SEATING
ref DETAIL A PLANE
4x aaa C ROTATED 90

TOP VIEW
B0D4_WLCSP80_ME_V1

1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.

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Table 131. WLCSP80 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 0.58 - - 0.228

A1 - 0.17 - - 0.0067 -
A2 - 0.38 - - 0.0150 -
(3)
A3 - 0.025 - - 0.0098 -
b 0.22 0.24 0.27 0.0087 0.0094 0.0106
D 3.47 3.50 3.52 0.1366 0.1378 0.1386
E 3.25 3.27 3.30 0.1279 0.1287 0.1299
e - 0.35 - - 0.138 -
e1 - 2.73 - - 0.1075 -
e2 - 2.45 - - 0.0964 -
F(4) - 0.384 - - 0.0151 -
G(4) - 0.484 - - 0.0190 -
H - 0.1025 - - 0.0040 -
aaa - - 0.10 - - 0.0039
bbb - - 0.10 - - 0.0039
(5)
ccc - - 0.10 - - 0.0039
(6)
ddd - - 0.05 - - 0.0020
eee - - 0.05 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place
5. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
6. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true
position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of
each ball must lie simultaneously in both tolerance zones.

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Figure 84. WLCSP80 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 132. WLCSP80 - Example of PCB design rules

Dimension Values

Pitch 0.35 mm
Dpad 0.225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.235 mm
Stencil thickness 0.080 mm

Example of device marking for WLCSP80

The following figure gives an example of the locations and orientation of the marking areas
versus ball A1, and allows engineering samples to be identified.
With the device text markings oriented as in the figure, ball A1 is always located at top left.

Figure 85. WLCSP80 marking example (package top view)

Ball 1 identifier

Product
identification

Date code
Y ww
Revision
code
MS56506V1

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6.5 LQFP100 package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 86. LQFP100 - Outline(15)

ș2 ș
(2)
R1

H
R2

B
B-
N
O
(6)

TI
C
SE
D1/4 B GAUGE PLANE

S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)

BOTTOM VIEW SECTION A-A

(N-4) x e (13)

C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)

SIDE VIEW

D (4)
(11) c
(2) (5) D1 c1 (11)

D (3)
(10) (4)
N

b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B

D1/4 (6) (2)

A B
(5)

E1 E

SECTION A-A

A A

TOP VIEW 1L_LQFP100_ME_V3

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Table 133. LQFP100 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - 1.50 1.60 - 0.0590 0.0630

(12)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
E(4) 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
N(13) 100
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
(1)
bbb 0.20 0.0079
ccc(1) 0.08 0.0031
(1)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 87. LQFP100 - Footprint example

75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

1L_LQFP100_FP_V1

1. Dimensions are expressed in millimeters.

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6.6 LQFP144 package information (1A)

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 88. LQFP144 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
(6) B GAUGE PLANE

0.25
D 1/4
S
B
L
3
E 1/4 (L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D SECTION A-A
bbb H A-B D 4x

(N-4)x e
C
A
0.05 (12) ddd C A-B D
A2 A1 b ccc C

D (4)
D1 (2) (5)
(10) (3) D (9) (11)
N (4)
b WITH PLATING

1
2
3 E 1/4

(11) (11)
c c1
(6)
D 1/4 (2)
(3) A B (3) (5)

E1 E b1 BASE METAL
(11)

SECTION B-B

A A
(Section A-A)

TOP VIEW
1A_LQFP144_ME_V2

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Table 134. LQFP144 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 22.00 BSC 0.8661 BSC
(2)(5)
D1 20.00 BSC 0.7874 BSC
E(4) 22.00 BSC 0.8661 BSC
E1(2)(5) 20.00 BSC 0.7874 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 144
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

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Figure 89. LQFP144 - Footprint example

108 73
1.35

109 0.35 72

0.50

19.90 17.85
22.60

144 37

1 36

19.90
22.60
1A_LQFP144_FP

1. Dimensions are expressed in millimeters.

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6.7 UFBGA169 package information (A0YV)

This UFBGA is a 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.

Figure 90. UFBGA169 - Outline

E1
e SE

N
M
L
K e
J
H
G D1
SD F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13
Øb (169 balls)
A1 ball pad
Ø eee M C A B
corner Ø fff M C

BOTTOM VIEW
Detail A
A3 ccc C
A Mold resin A2

Seating plane
C Solder balls A1 A5
2 ddd C Substrate
SIDE VIEW C
DETAIL A
B E
A

A1 ball pad
3 corner (DATUM A)

(DATUM B)

aaa C
(4x)
TOP VIEW A0YV_UFBGA169_ME_V2

1. Drawing is not to scale.

2. Primary datum C is defined by the plane established by the contact points of three or more solder balls that
support the device when it is placed on top of a planar surface.
3. The terminal (ball) A1 corner must be identified on the top surface of the package by using a corner
chamfer, ink or metallized markings, or other feature of package body or integral heat slug. A distinguish
feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of
each corner is optional.

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Table 135. UFBGA169 - Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A(2) - - 0.60 - - 0.0236

(3)
A1 0.05 - - 0.0020 - -
A2 - 0.43 - - 0.0169 -
(4)
b 0.23 0.28 0.33 0.0091 0.0110 0.0130
(5)
D 7.00 BSC 0.2756 BSC
(5)
D1 6.00 BSC 0.2362 BSC
E(5) 7.00 BSC 0.2756 BSC
(5)
E1 6.00 BSC 0.2362 BSC
(5)(6)
e 0.50 BSC 0.0197 BSC
N(7) 169
SD(5)(8) 0.50 BSC 0.0197 BSC
SE(5)(8) 0.50 BSC 0.0197 BSC
(9)
aaa 0.15 0.0059
(9)
ccc 0.20 0.0079
ddd(9) 0.08 0.0031
(9)
eee 0.15 0.0059
(9)
fff 0.05 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The profile height, A, is the distance from the seating plane to the highest point on the package. It is
measured perpendicular to the seating plane.
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to primary
datum C.
5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For
tolerances refer to form and position table.
6. e represents the solder ball grid pitch.
7. N represents the total number of balls on the BGA.
8. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the position of the
centre ball(s) in the outer row or column of a fully populated matrix.
9. Tolerance of form and position drawing

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Figure 91. UFBGA169 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 136. UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values

Pitch 0.5 mm
Dpad 0.27 mm
0.35 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Solder paste 0.27 mm aperture diameter.

Note: Non-solder mask defined (NSMD) pads are recommended.

Note: 4 to 6 mils solder paste screen printing process.

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6.8 LQFP176 package information (1T)

This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package.
Note: See list of notes in the notes section.

Figure 92. LQFP176 - Outline(15)

ș2 ș1

(2) R1

H R2

B(See SECTION B-B)

(6) GAUGE PLANE
0.25
D1/4
S
B ș
L
E1/4 ș
4x N/4 TIPS 4x (L1)
(1) (11)
bbb H A-B D
aaa C A-B D

BOTTOM VIEW SECTION A-A

A2 0.05
(N-4) x e 
C
A
A1 (12) ddd C A-BD ccc C
b

SIDE VIEW

D (4)
(2) (5) D1
D  (9) (11)
(10) N
(4) b WITH PLATING

E1/4

(11) c c1 (11)
D1/4 (6) (5)

A B (2)
E1 E b1 BASE METAL
(11)

SECTION A-A
A A
SECTION B-B

TOP VIEW 1T_LQFP176_ME_V2

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Table 137. LQFP176 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1(12) 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
(9)(11)
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
(11)
b1 0.170 0.200 0.230 0.0067 0.0079 0.0091
c(11) 0.090 - 0.200 0.0035 - 0.0079
(11)
c1 0.090 - 0.160 0.0035 - 0.063
(4)
D 26.000 1.0236
(2)(5)
D1 24.000 0.9449
E(4) 26.000 0.0197
(2)(5)
E1 24.000 0.9449
e 0.500 0.1970
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1(1)(11) 1 0.0394 REF
N(13) 176
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.080 - - 0.0031 - -
R2 0.080 - 0.200 0.0031 - 0.0079
S 0.200 - - 0.0079 - -
(1)
aaa 0.200 0.0079
(1)
bbb 0.200 0.0079
(1)
ccc 0.080 0.0031
ddd(1) 0.080 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

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Figure 93. LQFP176 - Footprint example

1.2
176 133
1 0.5 132

0.3
26.7

21.8

44 89
45 88
1.2

21.8

26.7

1T_FP_V1

1. Dimensions are expressed in millimeters.

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6.9 UFBGA(176+25) package information (A0E7)

This UFBGA is a 176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package.

Figure 94. UFBGA(176+25) - Outline

Seating plane
C A4
ddd C

A
A2 A3 b A1
A1 ball A
A1 ball index E
identifier area
E1
e F
A
F

D1 D

e
B
R
15 1
Øb (176 + 25 balls)
BOTTOM VIEW TOP VIEW
Ø eee M C A B
Ø fff M C

A0E7_ME_V10

1. Drawing is not to scale.

Table 138. UFBGA(176+25) - Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 0.600 - - 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 9.850 10.000 10.150 0.3878 0.3937 0.3996
D1 - 9.100 - - 0.3583 -
E 9.850 10.000 10.150 0.3878 0.3937 0.3996
E1 - 9.100 - - 0.3583 -
e - 0.650 - - 0.0256 -
F - 0.450 - - 0.0177 -
ddd - - 0.080 - - 0.0031

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Table 138. UFBGA(176+25) - Mechanical data (continued)

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

eee - - 0.150 - - 0.0059

fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 95. UFBGA(176+25) - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 139. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA)
Dimension Values

Pitch 0.65 mm
Dpad 0.300 mm
0.400 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.300 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm

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6.10 Package thermal characteristics

The maximum chip-junction temperature, TJmax in degrees Celsius, can be calculated using
the following equation:
TJmax = TAmax + (PDmax × ΘJA)
Where:
• TAmax is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax),
• PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/Omax represents the maximum power dissipation on output pins:
PI/Omax = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 140. Package thermal characteristics

Symbol Definition Parameter Value Unit

LQFP64 (10 x 10 mm) 48.1

VFQFPN68 (8 x 8 mm) 24.2
WLCSP80 (3.50 x 3.27 mm) 47.3

Thermal resistance LQFP100 (14 x 14 mm) 35.9

ΘJA °C/W
junction-ambient LQFP144 (20 x 20 mm) 37.5
LQFP176 (24 x 24 mm) 38.3
UFBGA169 (7 x 7 mm) 40.6
UFBGA176 (10 x 10 mm) 39.1
LQFP64 (10 x 10 mm) 24.1
VFQFPN68 (8 x 8 mm) 9.4
WLCSP80 (3.50 x 3.27 mm) 23.0

Thermal resistance LQFP100 (14 x 14 mm) 21.9

ΘJB °C/W
junction-board LQFP144 (20 x 20 mm) 26.3
LQFP176 (24 x 24 mm) 28.3
UFBGA169 (7 x 7 mm) 26.4
UFBGA176 (10 x 10 mm) 27.0

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Table 140. Package thermal characteristics (continued)

Symbol Definition Parameter Value Unit

LQFP64 (10 x 10 mm) 10.3

VFQFPN68 (8 x 8 mm) 10.8
WLCSP80 (3.50 x 3.27 mm) 2.3

Thermal resistance LQFP100 (14 x 14 mm) 8.5

ΘJC °C/W
junction-case LQFP144 (20 x 20 mm) 8.6
LQFP176 (24 x 24 mm) 9.1
UFBGA169 (7 x 7 mm) 11.2
UFBGA176 (10 x 10 mm) 10.9

6.10.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
• For information on thermal management, refer to AN5036 “Guidelines for thermal
management on STM32 applications”, available from www.st.com.

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7 Ordering information

Example: STM32 H 563 V I T 6 Q TR

Device family

STM32 = Arm based 32-bit microcontroller

Product type

H = high performance

Device subfamily

562 = STM32H562xx devices without Ethernet

563 = STM32H563xx devices

Pin count

R = 64 pins / 68 pins
M = 80 pins
V = 100 pins
Z = 144 pins
A = 169 balls
I = 176 pins

Flash memory size

G = 1 Mbyte
I = 2 Mbytes

Package

V = VFQFPN
T = LQFP
I = UFBGA (7 x 7 mm)
K = UFBGA (10 x 10)
Y = WLCSP

Temperature range

6 = Industrial, -40 to 85 °C (130 °C junction), available only in LDO option

7 = Industrial, -40 to 105 °C (130 °C junction), available only in LDO option
3 = Industrial, -40 to 125 °C (130 °C junction), available only in SMPS option

Dedicated pinout

Q = Dedicated pinout supporting SMPS step-down converter

Packing

TR = tape and reel

xxx = programmed parts

For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.

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STM32H562xx and STM32H563xx Important security notice

8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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Revision history STM32H562xx and STM32H563xx

9 Revision history

Table 141. Document revision history

Date Revision Changes

06-Mar-2023 1 Initial release.

Updated Features and Section 3.10.1: Power supply schemes.
Updated Table 2: STM32H56xxx features and peripheral counts,
Table 18: Current characteristics, Table 20: General operating
conditions, tables 30 to 32, tables 34 to 35, Table 58: I/O static
characteristics, and Table 64: Output timing characteristics (HSLV ON).
Updated Figure 7: WLCSP80 SMPS ballout, Figure 41: NAND
controller waveforms for read access, Figure 42: NAND controller
20-Oct-2023 2
waveforms for write access, Figure 63: SPI timing diagram - Master
mode, Figure 65: SPI timing diagram - Slave mode and CPHA = 1,
Figure 69: SAI master timing waveforms, and Figure 70: SAI slave
timing waveforms.
Added Section 3.32: Public key accelerator (PKA), Section 6.1: Device
marking, and Example of device marking for WLCSP80.
Minor text edits across the whole document.
Updated Figure 1: STM32H562xx and STM32H563xx block diagram,
Figure 6: VFQFPN68 pinout, Figure 17: UFBGA176+25 SMPS ballout,
Figure 31: VIL/VIH for all I/Os except BOOT0, and Figure 63: SPI
timing diagram - Master mode.
Updated Table 14: STM32H562xx and STM32H563xx pin/ball
definition, Table 15: Alternate functions AF0 to AF7, Table 21:
Maximum allowed clock frequencies, Table 23: Characteristics of
SMPS step-down converter external components, Table 30: Typical
and maximum current consumption in Run mode, code with data
processing running from SRAM with cache 1-way, Table 45: HSI
oscillator characteristics, tables 53 to 55, Table 122: Dynamic
28-May-2024 3 characteristics: SD/MMC, VDD = 2.7 to 3.6 V, and Table 123: Dynamic
characteristics: eMMC, VDD = 1.71 to 1.9 V.
Updated Section 3.24.1: Analog temperature sensor.
Added Section 3.25: Digital temperature sensor (DTS), Section 5.3.14:
I/O current injection characteristics, and USB full speed (FS)
characteristics.
Added Table 60: Output voltage characteristics for FT_c I/Os and
Table 67: Output timing characteristics for FT_c I/Os (PB13/PB14).
Added Figure 36: Asynchronous multiplexed PSRAM/NOR write
waveforms.
Minor text edits across the whole document.

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Table 141. Document revision history

Date Revision Changes

Updated Features, Section 3.28: Digital camera interface (DCMI),

Wake-up time from low-power modes, and Section 7: Ordering
information.
Updated Table 2: STM32H56xxx features and peripheral counts,
Table 10: SPI features, Table 20: General operating conditions,
Table 21: Maximum allowed clock frequencies, Table 36: Typical and
maximum current consumption in Standby mode, Table 37: Typical and
13-Dec-2024 4 maximum current consumption in VBAT mode, Table 40: High-speed
external user clock characteristics, Table 51: Flash memory
programming, Table 89: OCTOSPI characteristics in DTR mode (no
DQS), Table 90: OCTOSPI characteristics in DTR mode (with DQS) /
HyperBus, Table 95: 12-bit ADC characteristics, Table 110: LPTIMx
characteristics, and Table 135: UFBGA169 - Mechanical data.
Updated Figure 5: LQFP64 pinout and Figure 90: UFBGA169 - Outline.
Minor text edits across the whole document.
Updated Table 36: Typical and maximum current consumption in
02-Jan-2025 5
Standby mode.

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