PROFET® BTS 736 L2

Smart High-Side Power Switch

Two Channels: 2 x 40mΩ
Status Feedback
Product Summary Package

Operating Voltage Vbb(on) 4.75...41V P-DSO-20-9

Active channels one two parallel
On-state Resistance RON 40mΩ 20mΩ
Nominal load current IL(NOM) 4.8A 7.3A
Current limitation IL(SCr) 30A 30A

General Description
• N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input and

diagnostic feedback, monolithically integrated in Smart SIPMOS technology.
• Fully protected by embedded protection functions

Applications
• µC compatible high-side power switch with diagnostic feedback for 5V, 12V and 24V grounded loads
• All types of resistive, inductive and capacitve loads
• Most suitable for loads with high inrush currents, so as lamps
• Replaces electromechanical relays, fuses and discrete circuits

Basic Functions
• Very low standby current
• CMOS compatible input
• Fast demagnetization of inductive loads
• Stable behaviour at undervoltage
• Wide operating voltage range
• Logic ground independent from load ground

Protection Functions Block Diagram

• Short circuit protection
Vbb
• Overload protection
• Current limitation
• Thermal shutdown
• Overvoltage protection (including load dump) with external IN1 Logic
resistor Channel
ST1
• Reverse battery protection with external resistor 1 OUT 1
• Loss of ground and loss of Vbb protection
• Electrostatic discharge protection (ESD) IN2 Logic Load 1
ST2 Channel
Diagnostic Function 2 OUT 2
• Diagnostic feedback with open drain output PROFET
• Open load detection in ON-state GND Load 2
• Feedback of thermal shutdown in ON-state

Semiconductor Group Page 1 of 14 1999-Mar-23

 BTS 736 L2

Functional diagram

overvoltage gate current limit VBB

protection control
+
internal charge
logic pump clamp for
voltage supply inductive load
OUT1

IN1 temperature
sensor
ESD
LOAD
Open load
ST1 detection

GND1
Channel 1

IN2 Control and protection circuit

of
ST2 channel 2
GND2 OUT2
PROFET

Pin Definitions and Functions Pin configuration

Pin Symbol Function (top view)

1,10, Vbb Positive power supply voltage. Design the
11,12, wiring for the simultaneous max. short circuit Vbb 1 • 20 Vbb
15,16, currents from channel 1 to 2 and also for low GND1 2 19 Vbb
19,20 thermal resistance IN1 3 18 OUT1
3 IN1 Input 1,2, activates channel 1,2 in case of ST1 4 17 OUT1
7 IN2 logic high signal N.C. 5 16 Vbb
17,18 OUT1 Output 1,2, protected high-side power output GND2 6 15 Vbb
13,14 OUT2 of channel 1,2. Design the wiring for the max. IN2 7 14 OUT2
short circuit current
ST2 8 13 OUT2
4 ST1 Diagnostic feedback 1,2 of channel 1,2,
N.C. 9 12 Vbb
8 ST2 open drain, low on failure
Vbb 10 11 Vbb
2 GND1 Ground 1 of chip 1 (channel 1)
6 GND2 Ground 2 of chip 2 (channel 2)
5,9 N.C. Not Connected

Semiconductor Group Page 2 1999-Mar-23

 BTS 736 L2

Maximum Ratings at Tj = 25°C unless otherwise specified

Parameter Symbol Values Unit
Supply voltage (overvoltage protection see page 4) Vbb 43 V
Supply voltage for full short circuit protection Vbb 24 V
Tj,start = -40 ...+150°C
Load current (Short-circuit current, see page 5) IL self-limited A
Load dump protection1) VLoadDump = VA + Vs, VA = 13.5 V VLoad dump3) 60 V
RI2) = 2 Ω, td = 200 ms; IN = low or high,
each channel loaded with RL = 9.0 Ω,
Operating temperature range Tj -40 ...+150 °C
Storage temperature range Tstg -55 ...+150
Power dissipation (DC)4) Ta = 25°C: Ptot 3.8 W
(all channels active) Ta = 85°C: 2.0
Maximal switchable inductance, single pulse
Vbb = 12V, Tj,start = 150°C4),
IL = 4.0 A, EAS = 296 mJ, 0 Ω one channel: ZL 19.0 mH
IL = 6.0 A, EAS = 631 mJ, 0 Ω two parallel channels: 17.5
see diagrams on page 9
Electrostatic discharge capability (ESD) IN: VESD 1.0 kV
(Human Body Model) ST: 4.0
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
8.0
R=1.5kΩ; C=100pF
Input voltage (DC) VIN -10 ... +16 V
Current through input pin (DC) IIN ±2.0 mA
Current through status pin (DC) IST ±5.0
see internal circuit diagram page 8

Thermal Characteristics
Parameter and Conditions Symbol Values Unit
min typ Max
Thermal resistance
junction - soldering point4),5) each channel: Rthjs -- -- 12 K/W
junction - ambient4) one channel active: Rthja -- 40 --
all channels active: -- 33 --

1) Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150Ω
resistor for the GND connection is recommended.
2) RI = internal resistance of the load dump test pulse generator
3) VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
4) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
5) Soldering point: upper side of solder edge of device pin 15. See page 14
Semiconductor Group Page 3 1999-Mar-23
 BTS 736 L2

Electrical Characteristics
Parameter and Conditions, each of the two channels Symbol Values Unit
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified min typ Max
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT); IL = 2 A, Vbb ≥ 7V
each channel, Tj = 25°C: RON -- 36 40 mΩ
Tj = 150°C: 67 75

two parallel channels, Tj = 25°C: 18 20

see diagram, page 10
Nominal load current one channel active: IL(NOM) 4.4 4.8 -- A
two parallel channels active: 6.7 7.3
Device on PCB6), Ta = 85°C, Tj ≤ 150°C
Output current while GND disconnected or pulled up; IL(GNDhigh) -- -- 2 mA
Vbb = 30 V, VIN = 0,
see diagram page 8; (not tested specified by design)
Turn-on time7) IN to 90% VOUT: ton 50 100 200 µs
Turn-off time IN to 10% VOUT: toff 50 120 250
RL = 12 Ω
Slew rate on 7) dV/dton 0.1 -- 1 V/µs
10 to 30% VOUT, RL = 12 Ω:
Slew rate off 7) -dV/dtoff 0.1 -- 1 V/µs
70 to 40% VOUT, RL = 12 Ω:

Operating Parameters
Operating voltage Tj=-40 Vbb(on) 4.75 -- 41 V
Tj=25...150°C: -- 43
Overvoltage protection8) Tj =-40°C: Vbb(AZ) 41 -- -- V
I bb = 40 mA Tj =25...150°C: 43 47 52
µA
)
Standby current 9 Tj =-40°C...25°C: Ibb(off) -- 10 16
VIN = 0; see diagram page 10 Tj =150°C: -- -- 50
Leakage output current (included in Ibb(off)) IL(off) -- 1 10 µA
VIN = 0
Operating current 10), VIN = 5V,
IGND = IGND1 + IGND2, one channel on: IGND -- 0.8 1.4 mA
two channels on: -- 1.6 2.8

6) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
7) See timing diagram on page 11.
8) Supply voltages higher than V
bb(AZ) require an external current limit for the GND and status pins (a 150Ω
resistor for the GND connection is recommended). See also VON(CL) in table of protection functions and
circuit diagram on page 8.
9) Measured with load; for the whole device; all channels off
10) Add I , if I
ST ST > 0

Semiconductor Group Page 4 1999-Mar-23

 BTS 736 L2
Parameter and Conditions, each of the two channels Symbol Values Unit
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified min typ Max

Protection Functions
Current limit, (see timing diagrams, page 12)
Tj =-40°C: IL(lim) 40 49 60 A
Tj =25°C: 33 41 48
Tj =+150°C: 23 29 35
Repetitive short circuit current limit,
Tj = Tjt each channel IL(SCr) -- 30 -- A
two parallel channels -- 30 --
(see timing diagrams, page 12)
Initial short circuit shutdown time Tj,start =25°C: toff(SC) -- 1.7 -- ms
(see timing diagrams on page 12)
Output clamp (inductive load switch off)11) V
at VON(CL) = Vbb - VOUT, IL= 40 mA Tj =-40°C: VON(CL) 41 -- --
Tj =25°C...150°C: 43 47 52
Thermal overload trip temperature Tjt 150 -- -- °C
Thermal hysteresis ∆Tjt -- 10 -- K

Reverse Battery
Reverse battery voltage 12) -Vbb -- -- 32 V
Drain-source diode voltage (Vout > Vbb) -VON -- 600 -- mV
IL = - 4.0 A, Tj = +150°C

11) If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
VON(CL)
12) Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Power dissipation is higher compared to normal operating
conditions due to the voltage drop across the drain-source diode. The temperature protection is not active
during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and
circuit page 8).
Semiconductor Group Page 5 1999-Mar-23
 BTS 736 L2
Parameter and Conditions, each of the two channels Symbol Values Unit
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified min typ Max

Diagnostic Characteristics
Open load detection current, (on-condition)
each channel I L (OL) 1
100 -- 900 mA

Input and Status Feedback13)

Input resistance RI 2.5 3.5 6 kΩ
(see circuit page 8)
Input turn-on threshold voltage VIN(T+) 1.7 -- 3.2 V
Input turn-off threshold voltage VIN(T-) 1.5 -- -- V
Input threshold hysteresis ∆ VIN(T) -- 0.5 -- V
Off state input current VIN = 0.4 V: IIN(off) 1 -- 50 µA
On state input current VIN = 5 V: IIN(on) 20 50 90 µA
Delay time for status with open load after switch td(ST OL4) 100 520 900 µs
off; (see diagram on page 13)
Status output (open drain)
Zener limit voltage IST = +1.6 mA: VST(high) 5.4 6.1 -- V
ST low voltage IST = +1.6 mA: VST(low) -- -- 0.4

13) If ground resistors RGND are used, add the voltage drop across these resistors.

Semiconductor Group Page 6 1999-Mar-23

 BTS 736 L2

Truth Table
Channel 1 Input 1 Output 1 Status 1

Channel 2 Input 2 Output 2 Status 2

level level BTS 736L2
Normal L L H
operation H H H
Open load L Z H
H H L
Overtem- L L H
perature H L L
L = "Low" Level X = don’t care Z = high impedance, potential depends on external circuit
H = "High" Level Status signal valid after the time delay shown in the timing diagrams

Parallel switching of channel 1 and 2 is easily possible by connecting the inputs and outputs in parallel. The
status outputs ST1 and ST2 have to be configured as a ’Wired OR’ function with a single pull-up resistor.

Terms
Ibb
V Leadframe Leadframe
bb I IN1 I IN2
Vbb Vbb
IN1 IN2
3 I L1 VON1 7 I L2 VON2
PROFET OUT1 PROFET OUT2
I ST1 17,18 I ST2 13,14
Chip 1 Chip 2
ST1 ST2
4 8
V V
IN1 V ST1 GND1
IN2
V ST2 GND2
2 6
IGND1 V OUT1 IGND2 V OUT2
R R
GND1 GND2

Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20

External RGND optional; two resistors RGND1, RGND2 = 150 Ω or a single resistor RGND = 75 Ω for reverse
battery protection up to the max. operating voltage.

Semiconductor Group Page 7 1999-Mar-23

 BTS 736 L2
Input circuit (ESD protection), IN1 or IN2 Overvolt. and reverse batt. protection
+ 5V
+ Vbb
R
I R ST
IN
V
Z2
RI
IN
ESD-ZD I
I Logic
I

GND R ST ST OUT

V
Z1 PROFET
The use of ESD zener diodes as voltage clamp at DC GND
R Load
conditions is not recommended. R GND

Signal GND Load GND

Status output, ST1 or ST2

VZ1 = 6.1 V typ., VZ2 = 47 V typ., RGND = 150 Ω,
+5V RST= 15 kΩ, RI= 3.5 kΩ typ.
In case of reverse battery the load current has to be
limited by the load. Temperature protection is not active
R ST(ON)
ST

Open-load detection OUT1 or OUT2

ON-state diagnostic
ESD-
ZD
Open load, if VON < RON·IL(OL); IN high
GND
+ V bb
ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 375 Ω
at 1.6 mA. The use of ESD zener diodes as voltage clamp at
DC conditions is not recommended.
VON
ON

Inductive and overvoltage output clamp,

OUT1 or OUT2 OUT

Logic Open load

+Vbb unit detection

VZ

V ON

OUT GND disconnect

Vbb
Power GND IN

VON clamped to VON(CL) = 47 V typ. OUT

PROFET

ST
GND
V V V V
bb IN ST GND

Any kind of load. In case of IN = high is VOUT ≈ VIN - VIN(T+).

Due to VGND > 0, no VST = low signal available.

Semiconductor Group Page 8 1999-Mar-23

 BTS 736 L2
GND disconnect with GND pull up Inductive load switch-off energy
dissipation
E bb

Vbb
IN E AS

OUT ELoad
PROFET
Vbb
IN
ST
GND
PROFET OUT
= L
ST EL

{
V V V
V IN ST GND
GND
bb ZL

ER
R
Any kind of load. If VGND > VIN - VIN(T+) device stays off L
Due to VGND > 0, no VST = low signal available.
Energy stored in load inductance:
2
Vbb disconnect with energized inductive EL = 1/2·L·I L
load While demagnetizing load inductance, the energy
dissipated in PROFET is
EAS= Ebb + EL - ER= ∫ VON(CL)·iL(t) dt,
high Vbb
IN
with an approximate solution for RL > 0 Ω:
OUT
PROFET IL· L IL·RL
EAS= (V + |VOUT(CL)|)
2·RL bb
ln (1+ |V )
ST OUT(CL)|
GND

Maximum allowable load inductance for

V
bb a single switch off (one channel)4)
L = f (IL ); Tj,start = 150°C, Vbb = 12 V, RL = 0 Ω
For inductive load currents up to the limits defined by ZL
(max. ratings and diagram on page 9) each switch is ZL [mH]
protected against loss of Vbb.
1000
Consider at your PCB layout that in the case of Vbb dis-
connection with energized inductive load all the load current
flows through the GND connection.

100

10

1
2 3 4 5 6 7 8 9 10 11 12

IL [A]

Semiconductor Group Page 9 1999-Mar-23

 BTS 736 L2
Typ. on-state resistance
RON = f (Vbb,Tj ); IL = 2 A, IN = high

RON [mOhm]

80

70
Tj = 150°C

60

50

40
25°C

30
-40°C

20

10
3 5 7 9 30 40
Vbb [V]

Typ. standby current

Ibb(off) = f (Tj ); Vbb = 9...34 V, IN1,2 = low

Ibb(off) [µA]
45

40

35

30

25

20

15

10

0
-50 0 50 100 150 200

Tj [°C]

Semiconductor Group Page 10 1999-Mar-23

 BTS 736 L2
Timing diagrams
Both channels are symmetric and consequently the diagrams are valid for channel 1 and
channel 2

Figure 1a: Vbb turn on:

IN1 Figure 2b: Switching a lamp:

IN2 IN

V bb
ST
V
OUT1

V V
OUT
OUT2

ST1 open drain

I
L

ST2 open drain

t
t

The initial peak current should be limited by the lamp and not by the
current limit of the device.
Figure 2a: Switching a resistive load,
turn-on/off time and slew rate definition: Figure 2c: Switching an inductive load
IN
IN

VOUT
ST
90%
t on dV/dtoff

V
dV/dton t OUT
off
10%

IL
I
L
I L(OL)
t t

*) if the time constant of load is too large, open-load-status may

occur

Semiconductor Group Page 11 1999-Mar-23

 BTS 736 L2
Figure 3a: Turn on into short circuit: Figure 4a: Overtemperature:
shut down by overtemperature, restart by cooling Reset if Tj <Tjt

IN1 other channel: normal operation

IN

ST
I
L1

I
L(lim)
V
I OUT
L(SCr)

t
off(SC) T
ST J

t t

Heating up of the chip may require several milliseconds, depending

on external conditions

Figure 3b: Turn on into short circuit: Figure 5a: Open load: detection in ON-state, open
shut down by overtemperature, restart by cooling load occurs in on-state
(two parallel switched channels 1 and 2)

IN1/2 IN

t t
I +I d(ST OL) d(ST OL)
L1 L2
ST
2xIL(lim)

V
OUT

I
L(SCr)

normal open normal

t I
off(SC) L
ST1/2
t
t
td(ST OL) = 10 µs typ.
ST1 and ST2 have to be configured as a ’Wired OR’ function
ST1/2 with a single pull-up resistor.

Semiconductor Group Page 12 1999-Mar-23

 BTS 736 L2
Figure 5b: Open load: turn on/off to open load
IN

t
ST d(STOL4)

I
L

Semiconductor Group Page 13 1999-Mar-23

 BTS 736 L2
Package and Ordering Code
Standard: P-DSO-20-9 Published by Siemens AG, Bereich Bauelemente, Vertrieb,
Produkt-Information, Balanstraße 73, D-81541 München
Sales Code BTS 728 L2  Siemens AG 1999. All Rights Reserved
Ordering Code Q67060-S7011-A2 As far as patents or other rights of third parties are concerned,
liability is only assumed for components per se, not for applications,
processes and circuits implemented within components or assem-
All dimensions in millimetres blies. The information describes a type of component and shall not
be considered as warranted characteristics. The characteristics for
which SIEMENS grants a warranty will only be specified in the
purchase contract. Terms of delivery and rights to change design
reserved. For questions on technology, delivery and prices please
contact the Offices of Semiconductor Group in Germany or the
Siemens Companies and Representatives woldwide (see address
list). Due to technical requirements components may contain dan-
gerous substances. For information on the type in question please
contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing: Please use the recycling operators known to you. We can
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have to invoice you for any costs incurred.
Components used in life-support devices or systems must be
expressly authorised for such purpose! Critical components14) of
the Semiconductor Group of Siemens AG, may only be used in life
supporting devices or systems15) with the express written approval
of the Semiconductor Group of Siemens AG.
Definition of soldering point with temperature Ts:
upper side of solder edge of device pin 15.

Pin 15

Printed circuit board (FR4, 1.5mm thick, one layer

70µm, 6cm2 active heatsink area) as a reference for
max. power dissipation Ptot, nominal load current
IL(NOM) and thermal resistance Rthja

14) A critical component is a component used in a life-support

device or system whose failure can reasonably be expected to
cause the failure of that life-support device or system, or to
affect its safety or effectiveness of that device or system.
15) Life support devices or systems are intended (a) to be
implanted in the human body or (b) support and/or maintain
and sustain and/or protect human life. If they fail, it is
reasonably to assume that the health of the user or other
persons may be endangered.

Semiconductor Group Page 14 1999-Mar-23

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