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MEMORY INTERFACING:

8086 Memory Banks

8086 has a 20 bit address bus and hence it can address 220 or 1,048,576 addresses. In each location a byte is
stored. So when a word is stored in the memory, it is stored in two consecutive memory locations. Strictly
speaking, both memory read and memory write operations require more than one memory cycle. If we want
8086 to complete memory read and memory write operations to be completed with one machine cycle, the
memory is to be organized in the form of two banks. Each bank will have 524,288 bytes each.

One memory bank contains all the even addressed locations like 00000, 00002 and 00004. The data lines of
this bank are connected to the lower eight data lines, D0 through D7 of the 8086. The other memory bank has
all the odd addressed locations like 00001, 00003 and 00005. The data lines of this bank are connected to the
upper eight data lines, D8 through D15 of the 8086. Address line A0 is used as part of the enabling for memory
in the lower bank. Address lines A1 through A19 are used to select the desired memory device in the bank to
address the desired byte in the service. These address lines from A1 through A19 are also used to access a
particular location in the upper bank. An additional signal called Bus High Enable (BHE – Active Low) is used to
enable the upper memory bank. An external latch, strobed by ALE, grabs the BHE (Active Low) signal that
holds it stable for the rest of the machine cycle. The following table shows the required logic levels on the BHE
(Active Low) and A0 signals for various types of memory accesses.

Address Data type Bhe (active low) A0 Bus cycles Data lines used

0000 BYTE 1 0 ONE D0-D7

0000 WORD 0 0 ONE D0-D15

0001 BYTE 0 1 ONE D7-D15

0001 WORD 0 1 FIRST D0-D7

1 0 SECOND D7-D15

Case 1

Read/Write a byte form/to an even address – A0 will be low and BHE (Active Low) will be high – Byte is
transferred to/from low bank through D0-D7

Example – MOV AH, DS: BYTE PTR [0000]

Case 2

Similar to case 1 except the word access instead of the byte access – Both A0 and BHE (Active Low) will be
asserted low – Low byte of the word through D0-D7 and high byte of the word through D8-D15

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Example – MOV AX,DS:WORD PTR[0000]

Case 3

Read/Wrire a byte from/to an odd address – A0 will be high and BHE (Active Low) will be asserted low – Low
bank is disabled and high bank is enabled – Byte is transferred through D0-D7

Example – MOV AL,DS:BYTE PTR[0001]

Case 4

Read/Write a word from/to an odd address – 8086 requires two bus cycles – During the first machine cycle
assert BHE (Active Low) as low and A0 as high – First byte is transferred through D0-D7 and the second byte is
transferred through D8-D15

Example – MOV AX,DS:WORD PTR[0001H]

The memory is made up of semiconductor material used to store the programs and data. Three types of
memory is,

 Process memory
 Primary or main memory
 Secondary memory

Typical EPROM and static RAM:

 A typical semiconductor memory IC will have n address pins, m data pins (or output pins).

 Having two power supply pins (one for connecting required supply voltage (V and the other for
connecting ground).

 The control signals needed for static RAM are chip select (chip enable), read control (output enable)
and write control (write enable).

 The control signals needed for read operation in EPROM are chip select (chip enable) and read control
(output enable).

Pin connections common to all memory devices are: The address input, data output or input/outputs,
selection input and control input used to select a read or write operation.
• Address connections: All memory devices have address inputs that select a memory location within the
memory device. Address inputs are labeled from A0 to An.
• Data connections: All memory devices have a set of data outputs or input/outputs. Today many of them
have bi-directional common I/O pins.
• Selection connections: Each memory device has an input, that selects or enables the memory device.
This kind of input is most often called a chip select ( ), chip enable ( ) or simply select ( ) input.

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Memory component illustrating the address, data and, Control connections

RAM memory generally has at least one or input and ROM at least one . A RAM memory device
has either one or two control inputs. If there is one control input it is often called R/W. This pin selects a
read operation or a write operation only if the device is selected by the selection input ( ). If the RAM
has two control inputs, they are usually labeled or and or G.

The ROM read only memory permanently stores programs and data and data was always present, even
when power is disconnected. It is also called as nonvolatile memory.
• EPROM (erasable programmable read only memory) is also erasable if exposed to high intensity
ultraviolet light for about 20 minutes or less, depending upon the type of EPROM.
• We have PROM (programmable read only memory)
• RMM (read mostly memory) is also called the flash memory.
• The flash memory is also called as an EEPROM (electrically erasable programmable ROM), EAROM
(electrically alterable ROM), or a NOVROM (nonvolatile ROM).
• These memory devices are electrically erasable in the system, but require more time to erase than a
normal RAM.

. EPROM contains the series of 27XXX contains the following part numbers: 2704(512 * 8), 2708(1K * 8),
2716(2K * 8), 2732(4K * 8), 2764(8K * 8), 27128(16K * 8) etc.
• Each of these parts contains address pins, eight data connections, one or more chip selection inputs ( )
and an output enable pin ( ). This device contains 11 address inputs and 8 data outputs. If both the
pin connection and are at logic 0, data will appear on the output connection. If both the pins
are not at logic 0, the data output connections remain at their high impedance or off state.
• To read data from the EPROM Vpp pin must be placed at logic 1.

 Static RAM memory device retain data for as long as DC power is applied. Because no special action
is required to retain stored data, these devices are called as static memory. They are also called
volatile memory because they will not retain data without power.
 The main difference between a ROM and RAM is that a RAM is written under normal operation,
while ROM is programmed outside the computer and is only normally read.

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 The SRAM stores temporary data and is used when the size of read/write memory is relatively
small.

Table - Number of Address Pins and Data Pins in Memory ICs

Decoder:
It is used to select the memory chip of processor during the execution of a program. No of IC's used for
decoder is,

 2-4 decoder (74LS139)

 3-8 decoder (74LS138)

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Fig - Block diagram and Truth table of 3-8 decoder

Static RAM Interfacing

• The semiconductor RAM is broadly two types – Static RAM and Dynamic RAM.
• The semiconductor memories are organized as two dimensional arrays of memory locations.
• For example 4K * 8 or 4K byte memory contains 4096 locations, where each locations contains 8-bit data
and only one of the 4096 locations can be selected at a time. Once a location is selected all the bits in it
are accessible using a group of conductors called Data bus.
• For addressing the 4K bytes of memory, 12 address lines are required.
• In general to address a memory location out of N memory locations, we will require at least n bits of
address, i.e. n address lines where n = Log2 N.
• Thus if the microprocessor has n address lines, then it is able to address at the most N locations of
memory, where 2n=N. If out of N locations only P memory locations are to be interfaced, then the least
significant p address lines out of the available n lines can be directly connected from the
microprocessor to the memory chip while the remaining (n-p) higher order address lines may be used
for address decoding as inputs to the chip selection logic.
• The memory address depends upon the hardware circuit used for decoding the chip select ( ). The
output of the decoding circuit is connected with the pin of the memory chip.

• The general procedure of static memory interfacing with 8086 is briefly described as follows:
1. Arrange the available memory chip so as to obtain 16- bit data bus width. The upper 8-bit bank is called
as odd address memory bank and the lower 8-bit bank is called as even address memory bank.
2. Connect available memory address lines of memory chip with those of the microprocessor and also
connect the memory and inputs to the corresponding processor control signals. Connect the
16-bit data bus of the memory bank with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, and A0 are used for decoding the required chip
select signals for the odd and even memory banks. The of memory is derived from the o/p of the
decoding circuit.

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• As a good and efficient interfacing practice, the address map of the system should be continuous as far
as possible, i.e. there should not be no windows in the map and no fold back space should be allowed.
• A memory location should have a single address corresponding to it, i.e. absolute decoding should be
preferred and minimum hardware should be used for decoding.

Example: Interface 8K*8 EPROM and 4K*8 SRAM chips with 8086 microprocessor. Select suitable map.
Memory map:

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
FFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

EPROM
FE000 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

FDFFF 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1

SRAM
FC000 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Memory chip selection:

Input Data transfer Memory chips selection

C B A

0 0 0 Word transfer through D15-D0 Both even & odd banks in SRAM
0 0 1 Lower byte transfer through D7-D0 Even bank in SRAM
0 1 0 Higher byte through D15-D8 Odd bank in SRAM
1 0 0 Word transfer through D15-D0 Both even & odd banks in EPROM
1 0 1 Lower byte transfer through D7-D0 Even bank in EPROM
1 1 0 Higher byte through D15-D8 Odd bank in EPROM

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Interfacing:

DIRECT MEMORY ACCESS

Need for DMA & DMA Transfer method

An important aspect governing the Computer System performance is the transfer of data between
memory and I/O devices. The operation involves loading programs or data files from disk into memory,
saving file on disk, and accessing virtual memory pages on any secondary storage medium. Consider a
typical system consisting of a CPU, memory and one or more input/output devices as shown in fig.
Assume one of the I/O devices is a disk drive and that the computer must load a program from this
drive into memory. The CPU would read the first byte of the program and then write that byte to
memory. Then it would do the same for the second byte, until it had loaded the entire program into
memory. This process proves to be inefficient. Loading data into, and then writing data out of the CPU
significantly slows down the transfer. The CPU does not modify the data at all, so it only serves as an
additional stop for data on the way to it’s final destination. The process would be much quicker if we
could bypass the CPU & transfer data directly from the I/O device to memory. Direct Memory Access
does exactly that.

A DMA controller implements direct memory access in a computer system.

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It connects directly to the I/O device at one end and to the system buses at the other end. It also
interacts with the CPU, both via the system buses and two new direct connections. It is sometimes
referred to as a channel. In an alternate configuration, the DMA controller may be incorporated
directly into the I/O device.
Direct Memory Access--the ability of an I/O subsystem to transfer data to and from a memory subsystem
without processor intervention
DMA Controller--a device that can control data transfers between an I/O subsystem and a memory subsystem
in the same manner that a processor can control such transfers.

The DMA controller can issue commands to the memory that behave exactly like the commands issued
by the microprocessor. The DMA controller in a sense is a second processor in the system but is dedicated to
an I/O function. The DMA controller as shown below connects one or more I/O ports directly to memory,
where the I/O data stream passes through the DMA controller faster and more efficiently than through the
processor as the DMA channel is specialised to the data transfer task.

8257 DMA CONTROLLER

The Intel 8257 is a 4-channel direct memory access (DMA) controller. It is specifically designed to simplify the transfer of
data at high speeds for the Intel® microcomputer systems. Its primary function is to generate, upon a peripheral request,
a sequential memory address which will allow the peripheral to read or write data directly to or from memory. The 8257
has priority logic that resolves the peripherals requests and issues a composite hold request to the microprocessor. It
maintains the DMA cycle count for each channel and outputs a control signal to notify the peripheral that the
programmed number of DMA cycles is complete.
Features:
o Compatible with 8085, 8086/88
o It is a 4-Channel DMA Controller. So 4- I/O devices can be interfaced to DMA.
o Each channel has 16-bit address and 14 bit counter.
o It provides chip priority resolver that resolves priority of channels in fixed or rotating mode.
o Provides Terminal Count and Modulo 128 Outputs
o It requires Single TTL Clock
o It requires Single + 5V power Supply
o Available in Standard Temperature Range

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Architecture:

Block Diagram Description

DMA Channels
The 8257 provides four separate DMA channels (labelled CH-0 to CH-3). Each channel includes two sixteen-bit registers:
(1) a DMA address register, and (2) a terminal count register. Both registers must be initialized before a channel is
enabled. The DMA address register is loaded with the address of the first memory location to be accessed. The value
loaded into the low-order 14-bits of the terminal count register specifies the number of DMA cycles minus one before
the Terminal Count (TC) output is activated. For instance, a terminal count of 0 would cause the TC output to be active in
the first DMA cycle for that channel. In general, if N = the number of desired DMA cycles, load the value N-1 into the
low-order 14-bits of the terminal count register. The most significant two bits of the terminal count register specify the
type of DMA operation for that channel.
DMA Request (DRQ 0-DRQ 3): These are individual asynchronous channel request inputs used by the peripherals to
obtain a DMA cycle. If not in the rotating priority mode then DRQ 0 has the highest priority and DRQ 3 has the lowest. A
request can be generated by raising the request line and holding it high until DMA acknowledge. For multiple DMA
cycles (Burst Mode) the request line is held high until the DMA acknowledge of the last cycle arrives.

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DMA Acknowledge (DACK 0 - DACK 3) : An active low level on the acknowledge output informs the peripheral connected
to that channel that it has been selected for a DMA cycle. The DACK output acts as a "chip select' for the peripheral
device requesting service. This line goes active (low) and inactive (high) once for each byte transferred even if a burst of
data is being transferred.

Data bus buffer

This bi-directional 8-bit interfaces the 8257 to the microprocessor system data bus.

Data Bus Lines: These are bi-directional three-state lines. When the 8257 is being programmed by the CPU. Eightbits of
data for a DMA address register, a terminal count register or the Mode Set register are received on the data bus. When
the CPU reads a DMA address register, a terminal count register or the Status register, the data is sent to the CPU over
the data bus. During DMA cycles (when the 8257 is the bus master), the 8257 will output the most significant eight-bits
of the memory address (from one of the DMA address registers) to the 8212 latch via the data bus.

Read/Write Logic
When the CPU is programming or reading one of the 8257’s registers (i.e., when the 8257 is a "slave" device on the
system bus), the Read/Write Logic accepts the I/O Read (USE) or I/O Write (175OT) signal, decodes the least significant
four address bits, (A0-A3), and either writes the contents of the data bus into the addressed register (if I/OW is true) or
places the contents of the addressed register onto the data bus (if I/OR is true). During DMA cycles (i.e., when the 8257
is the bus "master"), the Read/Write Logic generates the I/O read and memory write (DMA write cycle) or I/O Write and
memory read (DMA read cycle) signals which control the data link with the peripheral that has been granted the DMA
cycle.

Control Logic
This block controls the sequence of operations during all DMA cycles by generating the appropriate control signals and
the 16-bit address that specifies the memory location to be accessed.
Mode Sat Register
When set, the various bits in the Mode Set register enable each of the four DMA channels, and allow four different
options for the 8257:

Status Register
The eight-bit status register indicates which channels have reached a terminal count condition and includes the update
flag described previously. The TC status bits are set when the Terminal Count (TC) output is activated for that channel.
These bits remain set until the status register is read or the 8257 is reset. The UPDATE FLAG, however, is not affected by

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a status register read operation. The UPDATE FLAG can be cleared by resetting the 8257. by changing to the non-auto
load mode (i.e.. by resetting the AUTO LOAD bit in the Mode Set register) or it can be left to clear itself at the
completion of the update cycle.

Register Selection in 8257

PIN CONFIGURATION OF 8257

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Pin descriptions
D0-D7:
o These are bidirectional, tri state, Buffered, Multiplexed data (D0-D7) and (A8-A15).
o In the slave mode it is a bidirectional (Data is moving).
o In the Master mode it is a unidirectional (Address is moving)
IOR:
o It is active low ,tristate ,buffered ,Bidirectional lines.
o In the slave mode it function as a input line. IOR signal is generated by microprocessor to read the contents 8257
registers.
o In the master mode it function as a output line. IOR signal is generated by 8257 during write cycle.
IOW:
o It is active low ,tristate ,buffered ,Bidirectional control lines.
o In the slave mode it function as a input line. IOR signal is generated by microprocessor to write the contents
8257 registers.
o In the master mode it function as a output line. IOR signal is generated by 8257 during read cycle.
CLK:
o It is the input line ,connected with TTL clock generator.
o This signal is ignored in slave mode.
RESET: Used to clear mode set registers and status registers
A0-A3: These are the tristate, buffer, bidirectional address lines. In slave mode, these lines are used as address inputs
lines and internally decoded to access the internal registers. In master mode, these lines are used as address
outputs lines,A0-A3 bits of memory address on the lines.
CS: It is active low, Chip select input line. In the slave mode, it is used to select the chip. In the master mode, it is
ignored.
A4-A7: These are the tristate, buffer, output address lines. In slave mode, these lines are used as address outputs lines.
In master mode, these lines are used as address outputs lines,A0-A3 bits of memory address on the lines.
READY: It is a asynchronous input line. In master mode, When ready is high it is received the signal. When ready is low,
it adds wait state between S1 and S3 In slave mode, this signal is ignored.
HRQ: It is used to receiving the hold request signal from the output device.
HLDA: It is acknowledgment signal from microprocessor.
It is active low ,tristate ,Buffered control output line.In slave mode, it is tristated. In master mode, it activated
during DMA read cycle.
It is active low ,tristate ,Buffered control input line. In slave mode, it is tristated. In master mode ,it activated
during DMA write cycle.
AEN (Address enable): It is a control output line. In master mode ,it is high. In slave mode ,it is low.Used it isolate the
system address ,data ,and control lines.
ADSTB (Address Strobe): It is a control output line. Used to split data and address line. It is working in master mode
only. In slave mode it is ignore.
TC (Terminal Count): It is a status of output line. It is activated in master mode only. It is high , it selected the peripheral.
It is low ,it free and looking for a new peripheral.
MARK:
o It is a modulo 128 MARK output line.
o It is activated in master mode only.
o It goes high, after transferring every 128 bytes of data block.
DRQ0-DRQ3(DMA Request):
o These are the asynchronous peripheral request input signal.
o The request signals are generated by external peripheral device.
- :
o These are the active low DMA acknowledge output lines.
o Low level indicates that, peripheral is selected for giving the information (DMA cycle).
o In master mode it is used for chip select.

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OPERATING MODES OF 8257

The operating modes of 8257 DMA controller are
 Fixed priority mode
 Rotating priority mode
 Extended write mode
 TC stop mode
 Auto load mode

Fixed priority mode: If the ROTATING PRIORITY bit is not set (set to a zero), each DMA channel has a fixed priority. In this
mode Channel 0 has the highest priority and Channel 3 has the lowest priority.

Rotating priority mode: In the Rotating Priority Mode, the priority of the channels has a circular sequence. After each
DMA cycle, the priority of each channel changes. The channel which had just been serviced will have the lowest priority.

Extended write mode: If the EXTENDED WRITE bit is set, the duration of the MEMW and I/OW signals is extended by
activating them earlier in the DMA cycle. Data transfers within micro computer systems proceed asynchronously to
allow use of various types of memory and I/O devices with different access times.

TC stop mode: If the TC STOP bit is set a channel is disabled (i.e.. its enable bit is reset) after the Terminal Count (TC)
output goes true, thus automatically preventing further DMA operation on that channel. The enable bit for that channel
must be re-programmed to continue or begin another DMA operation. If the TC STOP bit is not set. The occurrence of
the TC output has no effect on the channel enable bits.

Auto load mode: The Auto Load mode permits Channel 2 to be used for repeat block or block chaining operations,
without immediate software intervention between blocks. Channel 2 registers are initialized as usual for the first data
block; Channel 3 registers, however, are used to store the block re-initialization parameters (DMA starting address,
terminal count and DMA transfer mode).

INTERFACING OF 8257 WITH 8086

--Refer your NOTE BOOK--

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