Lecture 9
Processor organization & Instruction
Cycle
Zelalem Birhanu, AAiT 1
Instruction Sets Review
Q. Consider the following assembly code
Memory
read:
199 235
(a) MOV R1, 200 (R1←200) 200 420
(b) MOV R2,[R1] 201 330
202 0
(c) MOV R3,[R1+1]
…
(d) JMP calculate 300 15
calculate: CPU
R1 0
(e) ADD R3, R2 (R3←R3+R2)
R2 0
(f) MOV [300], R3 R3 0
Zelalem Birhanu, AAiT 2
Instruction Sets Review
1. What types of instructions are used in the program?
2. What addressing modes are used in the program?
3. What will be the values of R1, R2 and R3 after the
execution of the program?
4. Assume a processor has 12 registers (16-bits each) and
an instruction set with 30 instructions. Show possible
instruction formats for the following instructions (How
many bits is required for the instruction fields?)
a. MOV R2,[R1]
b. ADD R3,R2,R1
Zelalem Birhanu, AAiT 3
Processor Organization
• What is a processor (CPU) required to do?
Fetch and execute instructions
PC, IR Fetch Instruction From memory
Decoding Interpret (decode)
circuit Instruction
MAR, MBR [Fetch Data] From memory, I/O
ALU [Process Data]
MAR, MBR [Write Data] To memory, I/O
Zelalem Birhanu, AAiT 4
Processor Organization…cntd
• CPU contains:
Registers
Internal processor memory
ALU
performs arithmetic and logic operations (processes data)
Operates only on data in registers
ALU with its inputs and outputs is termed as a data path
Control Unit
Decodes instructions, generates control signals to control
the processor
Internal Bus
Interconnects CPU parts
Zelalem Birhanu, AAiT 5
Register Organization
Types of registers
• User-visible registers
They can be directly accessed (read or written to) by
programmers (instructions)
Used to minimize memory reference
• Control registers
Used by control unit to control operation of the processor
• Status (flag) registers
Indicate the current state (status) of the processor
No clean separation of registers into these categories (depends
on the processor)
Zelalem Birhanu, AAiT 6
User-visible registers
• General purpose registers
Can be used for a variety of functions
(hold data, used for addressing)
• Data registers
Hold only data
e.g. Accumulator (working) register used to store
intermediate ALU results
• Address registers
Only used for addressing
e.g. Segment registers (SS, DS, CS and ES in x86)
Index registers (SI, DI in x86)
Stack pointer
Zelalem Birhanu, AAiT 7
Control registers
Program Counter (PC): Contains address of next instruction
to be fetched
Instruction Register (IR): Temporarily holds most recently
fetched instruction
Memory Address Register (MAR): Specifies the address in
memory of the word to be written from or read into the MBR
Memory Buffer Register (MBR): Contains a word to be stored
in memory or is used to receive a word from memory
Zelalem Birhanu, AAiT 8
Status registers
e.g. Flag register (x86), CPSR(ARM)
Flags : Indicate the occurrence of an event in the CPU
Carry flag (CF), Zero flag (ZF), Sign flag (SF), Interrupt
flag (IF), Overflow flag (OF)
Used by branch (jump) instructions and interrupts
(CPU checks the appropriate flags when a conditional branch
instruction is encountered or when interrupt is enabled)
Zelalem Birhanu, AAiT 9
e.g. PIC 8-bit microcontroller
Zelalem Birhanu, AAiT 10
Instruction Cycle
e.g. MOV R1, [200] 100 MOV R1, [200]
… Memory
200 10
CPU PC 100 Address Bus 100 MOV R1, [200] Memory
Fetch
Cycle
CPU IR MOV R1, [200] Data Bus 100 MOV R1, [200] Memory
CPU Decoder MAR 200 CPU
CPU MAR 200 Address Bus 200 10 Execute
Fetch Memory
Operand Cycle
CPU MBR 10 Data Bus 200 10 Memory
CPU MBR 10 R1 10 CPU
Zelalem Birhanu, AAiT 11
Instruction Cycle with Interrupt
Process Interrupt
Fetch Instruction
Store PC in
Interpret (decode) memory (stack)
Instruction
Load address of
[Fetch Data]
ISR on PC
[Process Data] Execute Interrupt
routine (ISR)
[Write Data]
Restore PC from
Interrupt No memory (stack)
?
Yes
Process Interrupt
Zelalem Birhanu, AAiT 12
Introducing ARMSim
• A windows program used to simulate execution of
ARM assembly language programs
• Includes assembler, linker and simulator
• Registers, memory, cache, I/O simulation
• Expect assignments with ARMSim
Zelalem Birhanu, AAiT 13
Next Class
• Instruction Pipelining
Zelalem Birhanu, AAiT 14
More Readings
1. Computer Architecture and Organization,
William Stallings, 8th edition (sections 12.1 to
12.3)
Zelalem Birhanu, AAiT 15
