CSD15380F3

SLPS579B – MAY 2016 – REVISED FEBRUARY 2022

CSD15380F3 20-V N-Channel FemtoFET™ MOSFET

Product Summary
1 Features TA = 25°C TYPICAL VALUE UNIT
• Ultra-low CiSS and COSS VDS Drain-to-Source Voltage 20 V
• Ultra-low Qg and Qgd Qg Gate Charge Total (4.5 V) 0.216 nC
• Ultra-small footprint Qgd Gate Charge Gate-to-Drain 0.027 nC
– 0.73 mm × 0.64 mm VGS = 2.5 V 2220
• Ultra-low profile RDS(on)
Drain-to-Source
VGS = 4.5 V 1170 mΩ
On-Resistance
– 0.36-mm max height VGS = 8 V 990
• Integrated ESD protection diode VGS(th) Threshold Voltage 1.1 V
– Rated > 4-kV HBM
– Rated > 2-kV CDM Device Information(1)
DEVICE QTY MEDIA PACKAGE SHIP
• Lead and halogen free
CSD15380F3 3000 Femto Tape
• RoHS compliant 7-Inch Reel 0.73-mm × 0.64-mm and
CSD15380F3T 250 Land Grid Array (LGA) Reel
2 Applications
(1) For all available packages, see the orderable addendum at
• Optimized for load switch applications
the end of the data sheet.
• Optimized for general purpose switching
applications Absolute Maximum Ratings
• Battery applications TA = 25°C (unless otherwise stated) VALUE UNIT
• Handheld and mobile applications VDS Drain-to-Source Voltage 20 V
VGS Gate-to-Source Voltage 10 V
3 Description
Continuous Drain Current(1) 0.9
This 20-V, 990-mΩ, N-Channel FemtoFET™ MOSFET ID A
Continuous Drain Current(2) 0.5
is designed and optimized to minimize the footprint IDM Pulsed Drain Current(3) 1.6 A
in many handheld and mobile applications. Ultra- Power Dissipation(1) 1.4
low capacitance improves switching speeds. When PD W
Power Dissipation(2) 0.5
used in data line applications, the low capacitance
Human-Body Model (HBM) 4
minimizes noise coupling. This technology is capable V(ESD) kV
Charged-Device Model (CDM) 2
of replacing standard small signal MOSFETs while
TJ, Operating Junction and
providing a substantial reduction in footprint size. Tstg Storage Temperature
–55 to 150 °C

(1) Typical RθJA = 90°C/W on 1-in2 (6.45-cm2), 2-oz (0.071-mm)

thick Cu pad on a 0.06-in (1.52-mm) thick FR4 PCB
(2) Typical RθJA = 255°C/W on min Cu board
0.36 mm
(3) Pulse duration ≤ 100 μs, duty cycle ≤ 1%.

G
0.64 mm 0.73 mm

D
Typical Part Dimensions
S

Top View

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD15380F3
SLPS579B – MAY 2016 – REVISED FEBRUARY 2022 www.ti.com

Table of Contents
1 Features............................................................................1 6 Device and Documentation Support..............................6
2 Applications..................................................................... 1 6.1 Receiving Notification of Documentation Updates......6
3 Description.......................................................................1 6.2 Trademarks................................................................. 6
4 Revision History.............................................................. 2 7 Mechanical, Packaging, and Orderable Information.... 7
5 Specifications.................................................................. 3 7.1 Mechanical Dimensions.............................................. 7
5.1 Electrical Characteristics.............................................3 7.2 Recommended Minimum PCB Layout........................8
5.2 Thermal Information....................................................3 7.3 Recommended Stencil Pattern................................... 8
5.3 Typical MOSFET Characteristics................................ 4

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2017) to Revision B (February 2022) Page
• Changed ultra-low profile bullet from 0.35 mm to 0.36 mm in height................................................................. 1
• Updated ultra-low profile image height from 0.35 mm to 0.36 mm..................................................................... 1
• Changed ultra-low profile image height from 0.35 mm to 0.36 mm.................................................................... 7
• Added FemtoFET Surface Mount Guide note.................................................................................................... 8

Changes from Revision A (July 2017) to Revision B (November 2018) Page

• Changed ultra-low profile bullet from 0.35 mm to 0.36 mm in height................................................................. 1
• Updated ultra-low profile image height from 0.35 mm to 0.36 mm..................................................................... 1
• Changed ultra-low profile image height from 0.35 mm to 0.36 mm.................................................................... 7
• Added FemtoFET Surface Mount Guide note.................................................................................................... 8

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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA 20 V
IDSS Drain-to-Source leakage current VGS = 0 V, VDS = 16 V 50 nA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 10 V 25 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 2.5 μA 0.85 1.10 1.35 V
VGS = 2.5 V, IDS = 0.1 A 2220 4000
RDS(on) Drain-to-source on-resistance VGS = 4.5 V, IDS = 0.1 A 1170 1460 mΩ
VGS = 8 V, IDS = 0.1 A 990 1190
gfs Transconductance VDS = 2 V, IDS = 0.1 A 0.64 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance 8.1 10.5 pF
VGS = 0 V, VDS = 10 V,
Coss Output capacitance 5.9 7.7 pF
ƒ = 1 MHz
Crss Reverse transfer capacitance 0.13 0.17 pF
RG Series gate resistance 9.6 Ω
Qg Gate charge total (4.5 V) 0.216 0.281 nC
Qgd Gate charge gate-to-drain 0.027 nC
VDS = 10 V, IDS = 0.1 A
Qgs Gate charge gate-to-source 0.077 nC
Qg(th) Gate charge at Vth 0.048 nC
td(on) Turnon delay time 3 ns
tr Rise time VDS = 10 V, VGS = 4.5 V, 1 ns
td(off) Turnoff delay time IDS = 0.1 A, RG = 0 Ω 7 ns
tf Fall time 7 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 0.1 A, VGS = 0 V 0.85 1 V

5.2 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC TYPICAL VALUES UNIT
Junction-to-ambient thermal resistance(1) 90
RθJA °C/W
Junction-to-ambient thermal resistance(2) 255

(1) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.

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5.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise stated)

0.7 0.5
VGS = 2.5 V TC = 125° C
VGS = 4.5 V 0.45 TC = 25° C
IDS - Drain-to-Source Current (A)

0.6

IDS - Drain-to-Source Current (A)

VGS = 8.0 V 0.4 TC = -55° C

0.5 0.35
0.3
0.4
0.25
0.3 0.2

0.2 0.15
0.1
0.1
0.05

0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.5 1 1.5 2 2.5 3 3.5 4
VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) D003
D002

Figure 5-1. Saturation Characteristics VDS = 5 V

Figure 5-2. Transfer Characteristics

Figure 5-3. Transient Thermal Impedance

8 100

7
VGS - Gate-to-Source Voltage (V)

6 10
C - Capacitance (pF)

4 1

2 0.1
Ciss = Cgd + Cgs
1 Coss = Cds + Cgd
Crss = Cgd
0.01
0
0 2 4 6 8 10 12 14 16 18 20
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
VDS - Drain-to-Source Voltage (V)
Qg - Gate Charge (nC) D004
D005

VDS = 10 V ID = 0.1 A Figure 5-5. Capacitance

Figure 5-4. Gate Charge

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1.4 4000
TC = 25° C, ID = 0.1 A
3600

RDS(on) - On-State Resistance (m:)

1.3 TC = 125° C, ID = 0.1 A
VGS(th) - Threshold Voltage (V)

3200
1.2
2800
1.1 2400

1 2000
1600
0.9
1200
0.8
800
0.7 400

0.6 0
-75 -50 -25 0 25 50 75 100 125 150 175 0 1 2 3 4 5 6 7 8 9 10
VGS - Gate-to-Source Voltage (V)
TC - Case Temperature (° C) D006
D007

ID = 2.5 µA Figure 5-7. On-State Resistance vs Gate-to-Source

Voltage
Figure 5-6. Threshold Voltage vs Temperature
1.5 10
VGS = 2.5 V TC = 25° C
1.4 VGS = 8.0 V TC = 125° C
Normalized On-State Resistance

ISD - Source-to-Drain Current (A)

1
1.3

1.2 0.1

1.1
0.01
1

0.9 0.001

0.8
0.0001
0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-75 -50 -25 0 25 50 75 100 125 150 175 VSD - Source-to-Drain Voltage (V) D009
TC - Case Temperature (° C) D008
Figure 5-9. Typical Diode Forward Voltage
ID = 0.1 A

Figure 5-8. Normalized On-State Resistance vs

Temperature
10 0.8
100 ms 100 µs
10 ms 10 µs 0.7
IDS - Drain-to-Source Current (A)

IDS - Drain-to-Source Current (A)

1 ms
0.6

0.5

1 0.4

0.3

0.2

0.1

0.1 0
0.1 1 10 100 -50 -25 0 25 50 75 100 125 150 175
VDS - Drain-to-Source Voltage (V) D010
TC - Case Temperature (° C) D012

Single pulse, typical RθJA = 255°C/W (min Cu) Figure 5-11. Maximum Drain Current vs
Figure 5-10. Maximum Safe Operating Area Temperature

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6 Device and Documentation Support

6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Trademarks
FemtoFET™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

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www.ti.com SLPS579B – MAY 2016 – REVISED FEBRUARY 2022

7 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
0.73 B
A
0.65

PIN 1 INDEX AREA

0.64
0.56

0.36 MAX C

SEATING PLANE

0.4

0.225

2
3
0.175
0.51
0.35
0.49

1
0.16
2X
0.14 0.16
0.015 C B A 0.14
0.015 C A B
0.26
2X
0.24
A. All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
B. This drawing is subject to change without notice.
C. This package is a lead-free solder land design.

Table 7-1. Pin

Configuration
POSITION DESIGNATION
Pin 1 Gate
Pin 2 Source
Pin 3 Drain

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7.2 Recommended Minimum PCB Layout

(0.15)
2X (0.25)
0.05 MIN
ALL AROUND
2X (0.15) TYP
1

3
SYMM
(0.35) (0.5)

2 EXAMPLE STENCIL DESIGN

(R0.05) TYP
SOLDER MASK TM
YJM0003A PKG PicoStar
OPENING - 0.35 mm max height
METAL UNDER TYP
SOLDER MASK PicoStar TM
TYP (0.175)

(0.4)

A. All dimensions are in millimeters. LAND PATTERN EXAMPLE

B. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
SOLDER MASK DEFINED
SCALE:50X
7.3 Recommended Stencil Pattern

2X (0.25)
(0.15)
2X (0.2)
1

3
SYMM
(0.4) (0.5)

2
2X (0.15) (R0.05) TYP
PKG
2X SOLDER MASK EDGE
(0.175)
(0.4)
4222304/A 09/2015
A. All dimensions are in millimeters.
NOTES: (continued) SOLDER PASTE EXAMPLE
ON 0.075 - 0.1 mm THICK STENCIL
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
SCALE:50X

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 PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CSD15380F3 ACTIVE PICOSTAR YJM 3 3000 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 6

CSD15380F3T ACTIVE PICOSTAR YJM 3 250 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 6

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2022

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Dec-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD15380F3 PICOSTAR YJM 3 3000 180.0 8.4 1.94 0.79 0.44 4.0 8.0 Q2
CSD15380F3 PICOSTAR YJM 3 3000 178.0 8.4 0.7 0.79 0.44 4.0 8.0 Q2
CSD15380F3T PICOSTAR YJM 3 250 180.0 8.4 1.94 0.79 0.44 4.0 8.0 Q2
CSD15380F3T PICOSTAR YJM 3 250 178.0 8.4 0.7 0.79 0.44 4.0 8.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CSD15380F3 PICOSTAR YJM 3 3000 182.0 182.0 20.0
CSD15380F3 PICOSTAR YJM 3 3000 220.0 220.0 35.0
CSD15380F3T PICOSTAR YJM 3 250 182.0 182.0 20.0
CSD15380F3T PICOSTAR YJM 3 250 220.0 220.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
YJM0003A SCALE 14.000
PicoStar TM - 0.36 mm max height
PicoStar TM

0.73 B
A
0.65

PIN 1 INDEX AREA

0.64
0.56

0.36 MAX C

SEATING PLANE

0.4

0.225

2
3
0.175
0.51
0.35 D: Max = 0.72 mm, Min = 0.66 mm
0.49

E: Max = 0.625 mm, Min =0.565 mm

1
0.16
2X
0.14 0.16
0.015 C B A 0.14
0.015 C A B
0.26
2X
0.24

4222304/B 03/2022

NOTES: PicoStar is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
3. This package is a Pb-free bump design. Bump finish may vary. To determine the exact finish, refer to the device datasheet
or contact a local TI representative.

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 EXAMPLE BOARD LAYOUT
YJM0003A PicoStar TM - 0.36 mm max height
PicoStar TM

(0.15)
2X (0.25)
0.05 MIN
ALL AROUND
2X (0.15) TYP
1

3
SYMM
(0.35) (0.5)

2
(R0.05) TYP
SOLDER MASK
PKG OPENING
METAL UNDER TYP
SOLDER MASK
TYP (0.175)

(0.4)

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED
SCALE:50X

4222304/B 03/2022

NOTES: (continued)

4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
YJM0003A PicoStar TM - 0.36 mm max height
PicoStar TM

2X (0.25)
(0.15)
2X (0.2)
1

3
SYMM
(0.4) (0.5)

2
2X (0.15) (R0.05) TYP
PKG
2X SOLDER MASK EDGE
(0.175)
(0.4)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:50X

4222304/B 03/2022

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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