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CSD18543Q3A
SLPS633 – DECEMBER 2016

CSD18543Q3A 60-V N-Channel NexFET™ Power MOSFET

1 Features
Product Summary
•
1 Ultra-Low Qg and Qgd
TA = 25°C TYPICAL VALUE UNIT
• Low RDS(on) VDS Drain-to-Source Voltage 60 V
• Low-Thermal Resistance Qg Gate Charge Total (10 V) 11.1 nC
• Avalanche Rated Qgd Gate Charge Gate-to-Drain 1.7 nC

• Lead Free RDS(on) Drain-to-Source On Resistance

VGS = 4.5 V 12.0
mΩ
VGS = 10 V 8.1
• RoHS Compliant
VGS(th) Threshold Voltage 2.0 V
• Halogen Free
• SON 3.3-mm × 3.3-mm Plastic Package
Device Information(1)
DEVICE MEDIA QTY PACKAGE SHIP
2 Applications CSD18543Q3A 13-Inch Reel 2500 SON Tape
• Solid State Relay Switch 3.30-mm × 3.30-mm and
CSD18543Q3AT 7-Inch Reel 250 Plastic Package Reel
• DC-DC Conversion
(1) For all available packages, see the orderable addendum at
• Secondary Side Synchronous Rectifier the end of the data sheet.
• Isolated Converter Primary Side Switch
• Motor Control Absolute Maximum Ratings
TA = 25°C VALUE UNIT
VDS Drain-to-Source Voltage 60 V
3 Description
VGS Gate-to-Source Voltage ±20 V
This 60-V, 8.1-mΩ, SON 3.3-mm × 3.3-mm
Continuous Drain Current (Package Limited) 35
NexFET™ power MOSFET is designed to minimize
losses in power conversion applications. Continuous Drain Current (Silicon Limited),
ID 60 A
TC = 25°C
Continuous Drain Current(1) 12
Top View
IDM Pulsed Drain Current(2) 156 A
S 1 8 D Power Dissipation(1) 2.8
PD W
Power Dissipation, TC = 25°C 66
S 2 7 D
TJ, Operating Junction,
–55 to 150 °C
Tstg Storage Temperature
S 3 6 D Avalanche Energy, Single Pulse
EAS 55 mJ
ID = 33 A, L = 0.1 mH, RG = 25 Ω
D
G 4 5 D
(1) Typical RθJA = 45°C/W on a 1-in2, 2-oz Cu pad on a
P0093-01 0.06-in thick FR4 PCB.
(2) Max RθJC = 1.9°C/W, pulse duration ≤ 100 μs, duty cycle ≤
. 1%.
.

RDS(on) vs VGS Gate Charge

30 10
TC = 25°C, I D = 12 A ID = 12 A
27 9 VDS = 30 V
RDS(on) - On-State Resistance (m:)

TC = 125°C, I D = 12 A
VGS - Gate-to-Source Voltage (V)

24 8
21 7
18 6
15 5
12 4
9 3
6 2
3 1
0 0
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12
VGS - Gate-to-Source Voltage (V) D007
Qg - Gate Charge (nC) D004
1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD18543Q3A
SLPS633 – DECEMBER 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 6.2 Community Resources.............................................. 7
2 Applications ........................................................... 1 6.3 Trademarks ............................................................... 7
3 Description ............................................................. 1 6.4 Electrostatic Discharge Caution ................................ 7
6.5 Glossary .................................................................... 7
4 Revision History..................................................... 2
5 Specifications......................................................... 3 7 Mechanical, Packaging, and Orderable
Information ............................................................. 8
5.1 Electrical Characteristics........................................... 3
7.1 Q3A Package Dimensions ........................................ 8
5.2 Thermal Information .................................................. 3
7.2 Q3A Recommended PCB Pattern ............................ 9
5.3 Typical MOSFET Characteristics.............................. 4
7.3 Q3A Recommended Stencil Pattern ....................... 10
6 Device and Documentation Support.................... 7
7.4 Q3A Tape and Reel Information ............................. 10
6.1 Receiving Notification of Documentation Updates.... 7

4 Revision History
DATE REVISION NOTES
December 2016 * Initial release.

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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 60 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 48 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 1.5 2.0 2.7 V
Drain-to-source VGS = 4.5 V, ID = 12 A 12.0 15.6 mΩ
RDS(on)
on resistance VGS = 10 V, ID = 12 A 8.1 9.9 mΩ
gfs Transconductance VDS = 6 V, ID = 12 A 40 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance 885 1150 pF
Coss Output capacitance VGS = 0 V, VDS = 30 V, ƒ = 1 MHz 168 218 pF
Crss Reverse transfer capacitance 4.8 6.2 pF
RG Series gate resistance 0.5 1.0 Ω
Qg Gate charge total (4.5 V) 5.6 7.3
nC
Qg Gate charge total (10 V) 11.1 14.5
Qgd Gate charge gate-to-drain VDS = 30 V, ID = 12 A 1.7 nC
Qgs Gate charge gate-to-source 3.1 nC
Qg(th) Gate charge at Vth 2.0 nC
Qoss Output charge VDS = 30 V, VGS = 0 V 24 nC
td(on) Turnon delay time 9 ns
tr Rise time VDS = 30 V, VGS = 10 V, 18 ns
td(off) Turnoff delay time IDS = 12 A, RG = 0 Ω 8 ns
tf Fall time 4 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 12 A, VGS = 0 V 0.8 1.0 V
Qrr Reverse recovery charge VDS= 30 V, IF = 12 A, 37 nC
trr Reverse recovery time di/dt = 300 A/μs 27 ns

5.2 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance (1) 1.9
°C/W
RθJA Junction-to-ambient thermal resistance (1) (2) 55

(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.

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GATE Source GATE Source

Max RθJA = 55°C/W Max RθJA = 160°C/W

when mounted on 1 in2 when mounted on a
(6.45 cm2) of minimum pad area of
2-oz (0.071-mm) thick 2-oz (0.071-mm) thick
Cu. Cu.

DRAIN DRAIN
M0161-01 M0161-02

5.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise stated)

Figure 1. Transient Thermal Impedance

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Typical MOSFET Characteristics (continued)

TA = 25°C (unless otherwise stated)
160 80
VGS = 4.5 V TC = 125°C
140 VGS = 6 V 70 TC = 25°C
IDS - Drain-to-Source Current (A)

IDS - Drain-to-Source Current (A)

VGS = 10 V TC = -55°C
120 60

100 50

80 40

60 30

40 20

20 10

0 0
0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 6
VDS - Drain-to-Source Voltage (V) D002
VGS - Gate-to-Source Voltage (V) D003
VDS = 5 V

Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics

10 10000
Ciss = Cgd + Cgs
9 Coss = Cds + Cgd
VGS - Gate-to-Source Voltage (V)

8 Crss = Cgd
1000
C - Capacitance (pF)

7
6
5 100
4
3
10
2
1
0 1
0 2 4 6 8 10 12 0 6 12 18 24 30 36 42 48 54 60
Qg - Gate Charge (nC) D004
VDS - Drain-to-Source Voltage (V) D005
ID = 12 A VDS = 30 V

Figure 4. Gate Charge Figure 5. Capacitance

2.6 30
TC = 25°C, I D = 12 A
27
RDS(on) - On-State Resistance (m:)

2.4 TC = 125°C, I D = 12 A
VGS(th) - Threshold Voltage (V)

24
2.2
21
2 18
1.8 15
12
1.6
9
1.4
6
1.2 3
1 0
-75 -50 -25 0 25 50 75 100 125 150 175 0 2 4 6 8 10 12 14 16 18 20
TC - Case Temperature (°C) D006
VGS - Gate-to-Source Voltage (V) D007
ID = 250 µA

Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage

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Typical MOSFET Characteristics (continued)

TA = 25°C (unless otherwise stated)
2 100
VGS = 4.5 V TC = 25qC
1.8 VGS = 10 V TC = 125qC

ISD - Source-To-Drain Current (A)

Normalized On-State Resistance

10
1.6
1
1.4

1.2 0.1

1
0.01
0.8
0.001
0.6

0.4 0.0001
-75 -50 -25 0 25 50 75 100 125 150 175 0 0.2 0.4 0.6 0.8 1
TC - Case Temperature (qC) D008
VSD - Source-To-Drain Voltage (V) D009
ID = 12 A

Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
1000 100
TC = 25q C
TC = 125q C
IDS - Drain-To-Source Current (A)

IAV - Peak Avalanche Current (A)

100

10 10

DC 1 ms
10 ms 100 µs
0.1 1
0.1 1 10 100 0.01 0.1 1
VDS - Drain-To-Source Voltage (V) D010
TAV - Time in Avalanche (ms) D011
Single pulse, max RθJC = 1.9°C/W

Figure 10. Maximum Safe Operating Area (SOA) Figure 11. Single Pulse Unclamped Inductive Switching
40

35
IDS - Drain-to-Source Current (A)

30

25

20

15

10

0
-50 -25 0 25 50 75 100 125 150 175
TC - Case Temperature (°C) D012
Max RθJC = 1.9°C/W

Figure 12. Maximum Drain Current vs Temperature

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6 Device and Documentation Support

6.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

6.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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7 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

7.1 Q3A Package Dimensions

3.1 A
B
2.9

PIN 1 INDEX AREA

3.25
3.05

2X 0.15 MAX

2X (0.2)
3.5
TYP
3.1

C
0.9 MAX

SEATING PLANE
0.05 (0.2)
0.00
1.74±0.1
0.52
4X
0.32
0.565±0.1
(0.15) TYP
EXPOSED THERMAL PAD
NOTE 3

4
5

9
2X 1.95

2.45±0.1
0.65 TYP
8
1

0.55 0.35
4X 8X
0.25 0.25
0.1 C B A
4X 1.45
2X 0.05 C
NOTE 4
4222499/A 12/2015
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical
performance.
4. Metalized features are supplier options and may not be on the package.
5. All dimensions do not include mold flash or protrusions.

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7.2 Q3A Recommended PCB Pattern

(1.775)

0.05 MIN PKG (0.635)

ALL SIDES TYP
(0.56)
4X (0.6) 4X (0.3)

4X (0.3) 8

(R0.05)
(0.975) TYP
TYP

9
SYMM (2.45)

3X (0.65) 3X (0.65)

4 5

(R0.05) TYP
SOLDER MASK
OPENING (0.207) (0.245)
( 0.2) VIA
TYP
METAL UNDER (0.905)
SOLDER MASK (1.55) TYP

LAND PATTERN EXAMPLE

1. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON
PCB Attachment (SLUA271).
2. Vias are optional depending on application, refer to device data sheet. If some or all are implemented,
recommended via locations are shown.

For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).

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7.3 Q3A Recommended Stencil Pattern

(0.905)

PKG

8X (0.6) (0.208) SOLDER MASK EDGE

8X (0.3) 8

(0.663)
SYMM 9

(1.325)

6X (0.65)
4X 1.125
5
4
(R0.05) TYP

4X 0.705 METAL
TYP

(3.1)

1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.

7.4 Q3A Tape and Reel Information

1.75 ±0.10

4.00 ±0.10 (See Note 1) 2.00 ±0.05

+0.10
8.00 ±0.10 Ø 1.50 –0.00
+0.30
–0.10
12.00

5.50 ±0.05

3.60
1.30

3.60

M0144-01

Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2.

2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material: black static-dissipative polystyrene.
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05 mm.
6. MSL1 260°C (IR and convection) PbF-reflow compatible.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CSD18543Q3A ACTIVE VSONP DNH 8 2500 RoHS & Green SN Level-1-260C-UNLIM -55 to 150 18543

CSD18543Q3AT ACTIVE VSONP DNH 8 250 RoHS & Green SN Level-1-260C-UNLIM -55 to 150 18543

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
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Addendum-Page 2
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