Selected Topics In VLSI
Lecture 1
Process Design Flow
Introduction
1 4
Motivation Chip Design
Motivation and
Introduction
Motivation
1971 -The Intel 4004 2006 - Itanium 2 "Montecito"
2,300 Transistors 1.7B Transistors
© Adam Teman, 2018
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Motivation
Predicirtion
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Motivation
• Houston, we have a problem...
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"Moore's Law of Engi.neers " © Adam Teman, 2018
Motivation
The Solution:
Design Design
Automation Re-use (IP)
Syllabus
• Lecture 1: Introduction
• Lecture 2: Verilog
• Lecture 3: Logic Synthesis
• Lecture 4: Static Timing Analysis
• Lecture 5: Moving to the
Physical Domain
• Lecture 6: Placement
• Lecture 7: Clock Tree Synthesis
• Lecture 8: Routing
• Lecture 9: 1/0 and Packaging
• Lecture 10: Design for Test
1 2 4
Motivation Building a Chip Design
Chip
Building a Chip
General Design Approach
• How do engineers build a bridge?
• Divide and conquer!!!!
• Partition design problem into many sub-problems, Partition
which are manageable
• Define mathematical model for sub-problem Model/Solution
and find an algorithmic solution
• Beware of model limitations and check them !!!!!!! J
• Implement algorithm in individual design tools, define Tools/Interfaces
and implement general interfaces between the tools
• Implement checking tools for boundary conditions Verify/Validate
• Concatenate design tools to general design flows J
which can be managed
• See what doesn't work and start over. Develop Flow
13 © Adam Teman, 2018
VLSI System Design Flow
VLSI Design
GDS (Graphic Data Stream) is a file that was developed by calma company in the year 1971
and the GDS II in the year 1978. It is a binary file format that represents layout data in a
hierarchical format. Data such as labels, shapes, layer information and other 2D and 3D layout
geometric data.
System Level
Gate Level
Transistor Level
Layout Level
Mask Level
1 3 4
Motivation Design Chip Design
Automation
Design Automation
The (really) Olden Days
Schematic of Intel 4004 (1971)
Mainframe CAD System
21 http://www.computerhistory.org/revolution/digital-logic
The (really) Olden Days
• Early chips were prepared entirely by hand:
.-..
-·
. a t
Hand drawn gate layout (Fairchild)
Rubylith Operators ( 1970) The original Tape-Out?
I NTEL BD D - EP n- 0 10 -18 - 6
http://www.computerhistory.org/revolution/digital-logic
8088A Mask Transparent Overlays (1976)
Design Automation Today
EDA tools
Questasim from Mentor Graphics, VCS
from synopsis and IES (ncsim) from
Cadence
1 4
Motivation Chip Design
Flow
Chip Design Flow
How a chip is built
26
Definition & Planning
Definition and Planning
Physical Design - Backend Flow Design and Verification
Logic Synthesis
RTL
Physical Design
SDC
Signoff and Tapeout
Standard Cells and GTL with Scan
Silicon Validation
Macros
Scan Chains Placed Design
Floorplan Design with
Clock Tree
Power Grid,
S ecial Routing
Router Routed Design
Clock Definitions
GDSII
