Freescale Semiconductor Document Number: MC33810

Technical Data Rev. 11.0, 8/2014

Automotive Engine Control IC

The 33810 is an eight channel output driver IC intended for automotive engine
33810
control applications. The IC consists of four integrated low-side drivers and four
low-side gate pre-drivers. The low-side drivers are suitable for driving fuel
injectors, solenoids, lamps, and relays. The four gate pre-drivers can function
either as ignition IGBT gate pre-drivers or as general purpose MOSFET gate ENGINE CONTROL
pre-drivers. This device is powered by SMARTMOS technology.
When configured as ignition IGBT gate pre-drivers, additional features are
enabled such as spark duration, dwell time, and ignition coil current sense.
When configured as a general purpose gate pre-driver (GPGD), the 33810
provides external MOSFETs with short-circuit protection, inductive flyback
protection and diagnostics. The device is packaged in a 32 pin (0.65mm pitch)
exposed pad SOIC.
EK SUFFIX (Pb-FREE)
Features 98ASA10556D
32 PIN SOICW -EP
• Designed to operate over the range of 4.5 V  VPWR  36 V
• Quad ignition IGBT or MOSFET gate pre-driver with parallel/SPI and/or PWM
control Applications
• Quad injector driver with parallel/SPI control • Automotive
• Interfaces directly to MCU using 3.3 V / 5.0 V SPI protocol • Motorcycle engine control unit (ECU) and small
• Injector driver current limit - 4.5 A max. engine control
• Independent fault protection and diagnostics • PSI5 airbag system
• VPWR standby current 10 A max. • Central gateway/in-vehicle networking
• Braking and stability control
• Gasoline engine management
• Hybrid electric vehicle (HEV) inverter controller

VBAT
VBAT 33810
VBAT
VPWR OUT0
VDD VBAT
OUT1
VDD VBAT
OUT2
MCU
OUT3
MOSI SI VBAT
GND
SCLK SCLK
FB0
CS CS
GD0 VBAT
MISO SO
FB1
ETPU DIN0
GD1 VBAT
ETPU DIN3

ETPU GIN0 FB2

ETPU GIN3 GD2 VBAT

GPIO OUT EN
FB3
ETPU SPKDUR
GD3
ETPU NOMI
RSP
ETPU MAXI RSN

Figure 1. MC33810 Simplified Application Diagram

© Freescale Semiconductor, Inc., 2006 - 2014. All rights reserved.

 ORDERABLE PARTS

ORDERABLE PARTS

This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are
provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers.

Table 1. Orderable Part Variations

Part Number Notes Temperature (TA) Package

MCZ33810EK (1) -40 °C to 125 °C 32 SOICW-EP

Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.

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 INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

VPWR VPWR, VDD

VDD V8.0 Analog
VDD VDD V2.5 Logic
~50 µA ~50 µA POR, Overvoltage
Undervoltage
CS LOGIC CONTROL
SI Oscillator
Bandgap
SCLK Bias
OUTEN ~15 µA ~15 µA SPI V2.5
VDD INTERFACE Outputs 0 to 3 OUT0
OUT1
SO OUT2
Gate Control VOC1 OUT3
DIN0
75 µA
Current Limit
~50 µA PARALLEL
CONTROL Temperature Limit
Short/Open
DIN1 + RS
–
~50 µA
lLimit
PWM Exposed
DIN2
CONTROLLER Pad
~50 µA

+
DIN3 – SPI
~50 µA NOMI,MAXI
DAC SPARK DURATION + FB0
– SPI FB1
GIN0 FB2
Open Secondary
~50 µA  FB3
VPWR  100 µA

VLVC
SPARK GPGD
DAC VOC Only
GIN1

~50 µA
Low V
Clamp GPGD
GIN2 GATE DRIVE Clamp
CONTROL
~50 µA
GD0
GIN3 GD1
~50 µA GD2
VDD GD3
NOMI +
– DAC
~5 0µA
SPKDUR
MAXI + RSP
– DAC

RSN

NOMI

MAXI
Exposed Pad

GND

Figure 2. 33810 Simplified Internal Block Diagram

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 PIN CONNECTIONS

PIN CONNECTIONS

Transparent Top View OUT0 1 32 OUT2

FB0 2 31 FB2
GD0 3 30 GD2
CS 4 29 MAXI
SCLK 5 28 NOMI
SI 6 27 RSN
SO 7 26 RSP
VDD 8 25 VPWR
GND
OUTEN 9 24 GIN0
DIN0 10 23 GIN1
DIN1 11 22 GIN2
DIN2 12 21 GIN3
DIN3 13 20 SPKDUR
GD1 14 19 GD3
FB1 15 18 FB3
OUT1 16 17 OUT3

Figure 3. 33810 Pin Connections

A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.

Table 2. 33810 Pin Definitions

Pin Number Pin Name Pin Function Formal Name Definition

OUT0, OUT1, Low-side Injector These pins are the Open drain low-side injector driver outputs.
1, 16, 32, 17 Output
OUT2, OUT3 Driver Output

FB0, FB1, Feedback Voltage In IGBT ignition gate pre-driver mode, these feedback inputs monitor the IGBT's
2, 15, 31, 18 Input collector voltage to provide the spark duration timer control signal.
FB2, FB3 Sense
IGBT/GPGD outputs are controlled by GIN0 - 3. Pull-up and pull-down current
GD0, GD1, sources are used to provide a controlled slew rate to an external IGBT or MOSFET
3, 14, 30,19 Output Gate Drive Output
GD2, GD3 connected as a low-side driver.

The Chip Select input pin is an active low signal sent by the MCU to indicate the
4 CS Input Chip Select device is being addressed. This input requires CMOS logic levels and has an
internal active pull-up current source.

The SCLK input pin is used to clock the serial data on the SI and SO pins in and
5 SCLK Input Serial Clock Input out while being addressed by the CS.

6 SI Input Serial Input Data The SI input pin is used to receive serial data from the MCU.

7 SO Output Serial Output Data The SO output pin is used to transmit serial data from the device to the MCU.

The VDD input supply voltage determines the interface voltage levels between the
Digital Logic Supply device and the MCU, and is used to supply power to the Serial Out buffer (SO),
8 VDD Input
Voltage SPKDUR buffer, MAXI, NOMI, and pull-up current source for the Chip Select (CS).

The Output Enable pin (OUTEN) is an active low input. When the OUTEN pin is low,
9 OUTEN Input Output Enable the device outputs are active. The outputs are disabled when OUTEN is high.

Driver Input 0, Driver Active high input control for injector outputs OUT0 - 3. The parallel input data is
DIN0,DIN1,
10, 11, 12, 13 Input Input 1, Driver Input 2, logically ORed with the corresponding SPI input data register contents.
DIN2,DIN3
Driver Input 3
This pin is the Spark Duration Output. This open drain output is low while feedback
20 SPKDUR Output Spark Duration Output inputs FB0 - 3 are above the programmed spark detection threshold.

Gate Driver Input 0 These pins are the active high input control for IGBT/GPGD outputs GD0 - 3. The
GIN0,GIN1, Gate Driver Input 1 parallel input data is logically ORed with the corresponding SPI input data register
24, 23, 22, 21 Input
GIN2,GIN3 Gate Driver Input 2 contents in GPGD mode only.
Gate Driver Input 3

25 VPWR Input Analog Supply Voltage VPWR is the main voltage input for all internal analog bias circuitry.

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 PIN CONNECTIONS

Table 2. 33810 Pin Definitions (continued)

Pin Number Pin Name Pin Function Formal Name Definition

Resistor Sense This pin is the Positive input of a current sense amplifier.
26 RSP Input
Positive

Resistor Sense This pin is the Negative input of a current sense amplifier.
27 RSN Input
Negative

Nominal Ignition Coil This pin is the Nominal Ignition Coil Current output flag. This output is asserted
28 NOMI Output when the IGBT Collector-Emitter current exceeds the level selected by the DAC.
Current
This pin is the Maximum Ignition Coil Current output flag. This output is asserted
when the IGBT Collector-Emitter current exceeds the selected level of the DAC.
Maximum Ignition Coil This signal also latches off the gate pre-drive outputs when configured as a GPGD.
29 MAXI Output
Current The MAXI current level is determined by the voltage drop across an external sense
resistor connected to pins RSP and RSN.

The exposed pad is the only ground reference for analog, digital and power ground
Exposed Pad connections. As such, it must be soldered directly to a low-impedance ground plane
(bottom of GND Ground Ground for both electrical and thermal considerations. For more information about this
package) package, see application note AN2409 on the Freescale web site,
www.freescale.com

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 ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted.
Symbol Ratings Value Unit Notes

ELECTRICAL RATINGS

VPWR VPWR Supply Voltage -1.5 to 45 VDC (1)

VDD Supply Voltage (1)

VDD -0.3 to 7.0 VDC

VIL SPI Interface and Logic Input Voltage (CS, SI, SO, SCLK, OUTEN, DIN0 - DIN3,
GIN0 - GIN3, SPKDUR, NOMI, MAXI, RSP,RSN) -0.3 to VDD VDC
VIH

VFB IGBT/GPGD Drain Voltage (VFB0 to VFB3) -1.5 to 60 VDC

VOUTX Injector Output Voltage (OUTx) -1.5 to 60 VDC

VGDx GPGD Output Voltage (GDx) -0.3 to 10 VDC

Output Clamp Energy (OUT0 to OUT3)(Single Pulse)
ECLAMP TJUNCTION = 150 °C, IOUT = 1.5 A 100 mJ

Output Clamp Energy (OUT0 to OUT3)(Continuous Pulse)

ECLAMP TJUNCTION = 125 °C, IOUT = 1.0 A (Max Injector frequency is 70 Hz) 100 mJ

Output Continuous Current (OUT0 to OUT3)

IOSSSS TJUNCTION = 150 °C 2.0 A

VRSX Maximum Voltage for RSN and RSP inputs -0.3 - VDD VDC

– Frequency of SPI Operation (VDD = 5.0 V) 6.0 MHz

ESD Voltage
VESD1 Human Body Model (HBM) 2000 (2), (3)
V
VESD2 Machine Model (MM) 200
VESD3 Charge Device Model (CDM) 750
THERMAL RATINGS

Operating Temperature
TA Ambient -40 to 125
Junction2
C
TJ -40 to 150
TC Case -40 to 125

TSTG Storage Temperature -55 to 150 C

PD Power Dissipation (TA  25 C) 1.7 W
Peak Package Flow Temperature During Solder Mounting
TSOLDER
EW Suffix
C
245

Thermal Resistance
RJA Junction-to-Ambient 75
C/W
RJL Junction- to-Lead 8.0
RJC Junction-to-Flag 1.2

Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. ESD data available upon request.
3. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-002), the Machine Model (MM) (AEC-Q100-003), and
the Charge Device Model (CDM), Robotic (AEC-Q100-011).

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 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics

Characteristics noted under conditions of 3.0 V  VDD  5.5 V, 6.0 V  VPWR  32 V, -40 C  TC  125 C, and calibrated timers, unless
otherwise noted. Typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA = 25 C.
Symbol Characteristic Min Typ Max Unit Notes

POWER INPUT (VDD, VPWR)

Supply Voltage
Fully Operational (4)
VPWR (FO) 4.5 – 36 V
Full Parameter Specification 6.0 – 32
Supply Current
IVPWR (ON) – 10.0 14.0 mA
All Outputs Disabled (Normal mode)
Sleep State Supply Current (Must have VDD  0.8 V for Sleep state),
IVPWR (SS) VPWR = 32 V – 15 30 A

VPWR Overvoltage Shutdown Threshold Voltage (5)

VPWR(OV) 36.5 39 42 V
VPWR(OV-HYS) VPWR Overvoltage Shutdown Hysteresis Voltage 0.5 1.5 3.0 V
VPWR Undervoltage Shutdown Threshold Voltage (6)
VPWR(UV) 3.0 4.0 4.4 V
VPWR(UV-HYS) VPWR Undervoltage Shutdown Hysteresis Voltage 100 200 300 mV
VPWR(LOV) VPWR Low Operating Voltage (Low-voltage reported via the SPI) 5.3 – 8.99 V (7)

VDD VDD Supply Voltage 3.0 – 5.5 V

VDD Supply Current
IVDD Static condition and does not include VDD current out of device – – 1.0 mA

VDD Supply Undervoltage (Sleep state) Threshold Voltage (8)

VDD(UV) 0.8 2.5 2.8 V
INJECTOR DRIVER OUTPUTS (OUT 0:3)
Drain-to-Source ON Resistance
IOUT = 1.0 A, TJ = 125 C, VPWR = 13 V – – 0.3
RDS (ON) IOUT = 1.0 A, TJ = 25 C, VPWR = 13 V 
– 0.2 –
IOUT = 1.0 A, TJ = -40 C, VPWR = 13 V – – –

IOUT (LIM) Output Self Limiting Current 3.0 – 6.0 A

Output Fault Detection Voltage Threshold
Outputs Programmed OFF (Open Load) (9)
VOUT(FLT-TH) 2.0 2.5 3.0 V
Outputs Programmed ON (Short to Battery)
Output OFF Open Load Detection Current
I(OFF)OCO VDRAIN = 18 V, Outputs Programmed OFF 40 75 115 A
VDRAIN = 32 V, Outputs Programmed OFF (-40 °C) 40 75 115
Output ON Open Load Detection Current
I(ON)OCO 20 100 200 mA
Current less then specification value considered open
Output Clamp Voltage 1
VOC1 ID = 20 mA 48 53 58 V

Notes
4. These parameters are guaranteed by design but not production tested. Fully operational means driver outputs toggle as expected with input
toggling. SPI is guaranteed to be operational when VPWR > 4.5 V. SPI may not report correctly when VPWR < 4.5 V.
5. Overvoltage thresholds minimum and maximum include hysteresis.
6. Undervoltage thresholds minimum and maximum include hysteresis.
7. Device is functional provided TJ is less than 150 °C. Some table parameters may be out of specification.
8. Device in Sleep state, returns from Sleep state with Power On Reset.
9. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.

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 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions of 3.0 V  VDD  5.5 V, 6.0 V  VPWR  32 V, -40 C  TC  125 C, and calibrated timers, unless
otherwise noted. Typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA = 25 C.
Symbol Characteristic Min Typ Max Unit Notes

INJECTOR DRIVER OUTPUTS (OUT 0:3) (Continued)

Output Leakage Current
VDD = 5.0 V, VDRAIN = 24 V, Open Load Detection Current – – 20
Disabled
IOUT (LKG) VDD = 5.0 V, VDRAIN = VOC - 1.0 V, Open Load Detection Current A
– – 3000
Disabled
VDD = 0 V, VDRAIN = 24 V, Sleep State – – 10

TLIM Overtemperature Shutdown 155 – 185 C (10)

TLIM (HYS) Overtemperature Shutdown Hysteresis 5.0 10 15 C (10)

IGNITION (IGBT) GATE DRIVER PARAMETERS (GD 0:3 FB0:3)

Gate Driver Output Voltage
V GS (ON) IGD = 500 A 4.8 7.0 9.0 V
V GS (OFF) IGD = -500 A 0.0 0.375 0.5

R GS (PULLDOWN) Sleep Mode Gate to Source Resistor 100 200 300 K

Sleep Mode FBx Pin Leakage Current
IFBX (LKG) VDD = 0 V, VFBx = 24 V, – – 1.0 A

Feedback Sense Current (FBx Input Current)

IFBX(FLT-SNS) – – 1.0 A
FBx = 32 V, Outputs Programmed OFF

I GATEDRIVE Gate Drive Source Current (1.0  VGD  3.0) 650 780 950 A
RDS(ON) Gate Drive Turn OFF Resistance 500 – 1000 
SOFT SHUTDOWN FUNCTION (VOLTAGES REFERENCED TO IGBT COLLECTOR)
Low Voltage Flyback Clamp
VLVC VPWR +9.0 VPWR +11 VPWR +13
Driver Command OFF, Soft Shutdown Enabled, GDx = 2.0 V V
Spark Duration Comparator Threshold (referenced to IC Ground Tab)
VTH-RISE 18 21 24 V
Rising Edge Relative to VPWR

Spark Duration Comparator Threshold (referenced to IC Ground Tab)

1.2 2.75 3.6
Falling Edge Relative to VPWR, Default = 5.5 V assuming ideal (11)
VTH-FALL 4.9 5.5 6.1 V
external 10:1 voltage divider. Voltage measured at high end of
divider, not at pin. Tolerance of divider not included. 7.4 8.2 9.1
9.9 11.00 12.1
Open Secondary Comparator Threshold (referenced from primary to
VTH-RISE rising edge relative to GND). No hysteresis with 10:1 voltage divider. 11.5 – 15.5 V

Notes
10. This parameter is guaranteed by design but not production tested.
11. Assuming ideal external 10:1 Voltage Divider. Tolerance of 10:1 Voltage Divider is not included. Voltage is measured on the high end of the divider
- not at the pin. 10:1 N.3.A 10:1 Voltage Divider is produced using two resistors with a 9:1 resistance ratio by the basic formula:
VOUT R1
------------------ = ---------------------- Where R2 = 9XR1
VIN R1 + R2

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 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions of 3.0 V  VDD  5.5 V, 6.0 V  VPWR  32 V, -40 C  TC  125 C, and calibrated timers, unless
otherwise noted. Typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA = 25 C.
Symbol Characteristic Min Typ Max Unit Notes

CURRENT SENSE COMPARATOR (RSP, RSN)

NOMI Trip Threshold Accuracy - Steady State Condition
NOMITRIPTA 3.0 A across 0.02  (RSP - RSN = 60 mV) -10 – 10 %
10.75 A across 0.04  (RSP - RSN = 430 mV)
MAXI Trip Threshold Accuracy - Steady State Condition
6.0 A across 0.02  (RSP - RSN = 120 mV) – – 7.5 %
MAXITRIPTA 21 A across 0.04  (RSP - RSN = 840 mV) -7.5 – –
MAXITRIPOD MAXI Trip Point During Overlapping Dwell -35 – +35 %
Input Bias Current
IBIASRSX -50 – 50 µA
RSP and RSN
Comparator Hysteresis Voltage
NOMIHYS NOMI 40 – 70
% of VT
MAXIIHYS MAXI 40 – 70
Input Voltage Range (Maximum voltage between RSN and RSP) (12)
VCMVRCMVR 0.0 – 2.0 V
Ground Offset Voltage Range (12)
VGNDOVR -0.3 – 0.3 V
Maximum offset between RSN pin and IC Ground (Exposed Pad)

GENERAL PURPOSE GATE PRE-DRIVER PARAMETERS (GD0:3)

IGD Gate Drive Sink and Source Current 1.0 2.0 5.0 mA
Gate Drive Output Voltage
V GS (ON) IGD = 1.0 mA 4.8 7.0 9.0 V
V GS (OFF) IGD = -1.0 mA 0.0 0.2 0.5 V
Short to Battery Fault Detection Voltage Threshold
VDS(FLT-TH) VDD = 5.0 V, Outputs Programmed ON -35% – +35% V
Programmable from 0.5 V to 3.0 V in 0.5 V increments. (Table 15)
Open Fault Detection Voltage Threshold (referenced to IC ground tab)
VDS(FLT-TH) VDD = 5.0 V, Outputs Programmed OFF 2.0 2.5 3.0 V

Output OFF Open Load Detection Current

IFBX(FLT-SNS) 50 75 120 A
FBx = 18 V, Outputs Programmed OFF
Output Clamp Voltage
VOC Driver Command OFF, Clamp Enabled, VGATE = 2.0 V 48 53 58 V

DIGITAL INTERFACE

VIH Input Logic High-voltage Thresholds 0.7 x VDD – VDD + 0.3 V

VIL Input Logic Low-voltage Thresholds GND - 0.3 – 0.2 x VDD V
VHYS Input Logic Voltage Hysteresis 100 – 400 mV
CIN Input Logic Capacitance – – 20 pF
Sleep Mode Input Logic Current
I LOGIC_SS VDD = 0 V -10 – 10 A

Input Logic Pull-down Current

0.8 to 5.0 V (DINX and GINX) 30 50 100 A
ILOGIC_PD
Input Logic Pull-down Current
ISI_PD 5.0 15 25 A
0.8 to 5.0 V (SI)
Input Logic Pull-up Current on OUTEN
IOUTEN_PU OUTEN = 0.0 V, VDD = 5.0 V -30 -50 -100 A

Notes
12. This parameter is guaranteed by design, but not production tested.

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 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions of 3.0 V  VDD  5.5 V, 6.0 V  VPWR  32 V, -40 C  TC  125 C, and calibrated timers, unless
otherwise noted. Typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA = 25 C.
Symbol Characteristic Min Typ Max Unit Notes

DIGITAL INTERFACE (CONTINUED)

OUTEN Leakage Current to VDD
IOUTEN(LKG) OUTEN = 5.0 V, VDD = 0 V – – 50 A

SCLK Pull-down Current

I SCLK VSCLK = VDD 5.0 15 25 A

Tri-state SO Output
I TRISO -10 – 10 A
0 to 5.0 V
CS Input Current
ICS CS = VDD -50 – 50 A

CS Pull-up Current
ICS_PU -30 -50 -100 A
CS = 0 V
CS Leakage Current to VDD
ICS(LKG) CS = 5.0 V, VDD = 0 V – – 50 A

CSO SO Input Capacitance in Tri-state Mode – 20 – pF

SO High State Output Voltage
VSO_HIGH ISO-HIGH = -1.0 mA VDD - 0.4 – – V

SO Low State Output Voltage

VSO_LOW ISO-LOW = 1.0 mA – – 0.4 V

NOMI, MAXI in V10 Mode Pull-down Current

IPD NOMI, MAXI = 0.8 V, VDD = 5.0 V 30 70 100 A

SPKDUR Output Voltage

VSPKDUR_LO ISPKDUR = 1.0 mA – – 0.4 V

ISPKDUR_PV Output Pull-up Current for SPKDUR 30 50 100 A

NOMI, MAXI High State Output Voltage
VI_HIGH INOMI-HIGH = -1.0 mA VDD - 0.4 – – V
IMAXI-HIGH = -1.0 mA

NOMI, MAXI Low State Output Voltage

VI_LOW INOMI-LOW = 250 µA – – 0.4 V
IMAXI-LOW = 250 µA

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 ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions of 3.0 V  VDD  5.5 V, 6.0 V  VPWR  32 V, -40 C  TC  125 C, and calibrated timers, unless
otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.
Symbol Characteristic Min Typ Max Unit Notes

POWER INPUT

Required Low State Duration on VPWR for Undervoltage Detect

tUV VPWR  0.2 V 1.0 – – s

Required Low State Duration on VDD for Power On Reset

t RESET VDD  0.2 V 1.0 – – s

INJECTOR DRIVERS

tSC Output ON Current Limit Fault Filter Timer (Short to Battery Fault) 30 60 90 µs
t(ON)OC Output ON Open Circuit Fault Filter Timer 3.0 7.5 12 ms

tREF Output Retry Timer – 10 15 ms

t(OFF)OC Output OFF Open Circuit Fault Filter Timer 100 – 400 µs
Output Slew Rate (No faster than 1.5 s from OFF to ON and ON to
t SR(RISE) OFF) 1.0 5.0 10 V/s
RLOAD = 14 VLOAD = 14 V

Output Slew Rate

t SR(FALL) RLOAD = 14 VLOAD = 14 V 1.0 5.0 10 V/s

Propagation Delay (Input Rising Edge OR CS to Output Falling Edge)

tPHL Input at 50%VDD to Output voltage 90% of VLOAD – 1.0 5.0 µs

Propagation Delay (Input Falling Edge OR CS to Output Rising Edge)

tPLH Input at 50%VDD to Output voltage 10% of VLOAD – 1.0 5.0 µs

IGNITION & GENERAL PURPOSE GATE PRE-DRIVER PARAMETERS

Propagation Delay (GINx Input Rising Edge OR CS to Output Rising
tPLH Edge) – 0.2 1.0 µs
Input at 50%VDD to Output voltage 10% of V GS (ON)

Propagation Delay (Input Falling Edge OR CS to Output Falling Edge)

tPHL Input at 50%VDD to Output voltage 90% of V GS (ON) – 0.2 1.0 µs

IGNITION PARAMETERS

Open Secondary Fault Timer Accuracy (uncalibrated) -35 – 35 %

Maximum Dwell Timer Accuracy (uncalibrated) -35 – 35 %
End of Spark Filter Accuracy (uncalibrated) (13)
-35 – 35 %

Notes
13. This parameter is guaranteed by design, however, it is not production tested.

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 ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions of 3.0 V  VDD  5.5 V, 6.0 V  VPWR  32 V, -40 C  TC  125 C, and calibrated timers, unless
otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.
Symbol Characteristic Min Typ Max Unit Notes

GENERAL PURPOSE GATE PRE-DRIVER PARAMETERS

Short to Battery Fault Detection Filter Timer Accuracy

VDD = High, Outputs Programmed ON
VDS(FLT-TH) Programmable from 30 µs to 960 µs in replicating increments %
Tolerance of timer after using calibration command
-10 – +10
Tolerance of timer before using calibration command
-35 – +35
Output OFF Open Circuit Fault Filter Timer
t(OFF)OC VDD = 5.0 V, Outputs OFF 100 – 400 µs
Tolerance of timer before using calibration command

PWM Frequency 10 Hz to 1.28 kHz Tolerance After Using Calibration

PWMFREQ
Command -10% – 10%
PWM Frequency 10 Hz to 1.28 kHz Tolerance Before Using
PWMFREQ Calibration Command -35% – 35%

GDSHRT_DC Gate Driver Short Fault Duty Cycle – 1.0 3.0 %

(14)
SPI DIGITAL INTERFACE TIMING

Falling Edge of CS to Rising Edge of SCLK

t LEAD 100 – – ns
Required Setup Time
Falling Edge of SCLK to Rising Edge of CS
t LAG 50 – – ns
Required Setup Time

SI to Rising Edge of SCLK

t SI (SU) 16 – – ns
Required Setup Time

Rising Edge of SCLK to SI

t SI (HOLD) 20 – – ns
Required Hold Time
SI, CS, SCLK Signal Rise Time (15)
t R (SI) – 5.0 – ns
SI, CS, SCLK Signal Fall Time (16)
t F (SI) – 5.0 – ns
t SO (EN) Time from Falling Edge of CS Low-impedance – – 55 ns (17)

Time from Rising Edge of CS to SO High-impedance (18)

t SO (DIS) – – 55 ns
Time from Falling Edge of SCLK to SO Data Valid (19)
t VALID – 25 55 ns
Sequential Transfer Rate
tSTR 1.0 – – µs
Time required between data transfers

DIGITAL INTERFACE

t TIMER Calibrated Timer Accuracy – – 10 %

t TIMER Un-calibrated Timer Accuracy – – 35 %

Notes
14. These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.
15. This parameter is guaranteed by design, however, it is not production tested.
16. Rise and Fall time of incoming SI, CS and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
17. Time required for valid output status data to be available on SO pin.
18. Time required for output states data to be terminated at SO pin.
19. Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.

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 ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS

TIMING DIAGRAMS

CS
0.2 VDD

tLEAD tLAG

0.7 VDD
SCLK 0.2 VDD

tSI(SU) tSI(HOLD)

SI 0.7 VDD
0.2 VDD MSB IN

tSO(EN) tVALID tSO(DIS)

0.7 VDD
SO MSB OUT LSB OUT
0.2 VDD

Figure 4. SPI Timing Diagram

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Freescale Semiconductor 13
 FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

ANALOG SUPPLY VOLTAGE (VPWR)

The VPWR pin is the battery input to the 33810. The VPWR pin requires external reverse battery and transient protection. All IC analog
current and internal logic current is provided from the VPWR pin. With VDD applied to the IC, the application of VPWR performs a POR.

DIGITAL LOGIC SUPPLY VOLTAGE (VDD)

The VDD input pin is used to determine communication logic levels between the microprocessor and the 33810. Current from VDD is
used to drive SO output and the pull-up current for CS. VDD must be applied for Normal mode operation. Removing VDD from the IC places
the device in Sleep mode. With VPWR applied to the IC, the application of VDD performs a POR.

GROUND (GND)
The bottom pad or FLAG provides the only ground connection for the IC. The VPWR and VDD supplies are both referenced to the GND
pad. The GND pad is used for both de-coupling the power supplies as well as power ground for the output drivers. Although the silicon
die is epoxy attached to the top side of the pad, the pad must be grounded for proper electrical operation.

SERIAL CLOCK INPUT (SCLK)

The system clock (SCLK) pin clocks the internal shift register of the 33810. The SI data is latched into the input shift register on the
rising edge of SCLK signal. The SO pin shifts status bits out on the falling edge of SCLK. The SO data is available for the MCU to read
on the rising edge of SCLK. With CS in a logic high state, signals on the SCLK and SI pins are ignored and the SO pin is tri-state.

CHIP SELECT (CS)

The system MCU selects the 33810 to receive communication using the chip select (CS) pin. With the CS in a logic low state, command
words may be sent to the 33810 via the serial input (SI) pin, and status information is received by the MCU via the serial output (SO) pin.
The falling edge of CS enables the SO output and transfers status information into the SO buffer.
Rising edge of the CS initiates the following operation:
Disables the SO driver (high-impedance)
Activates the received command word, allowing the 33810 to activate/deactivate output drivers.
To avoid any spurious data, it is essential the high-to-low and low-to-high transitions of the CS signal occur only when SCLK is in a
logic low state. Internal to the 33810 device is an active pull-up to VDD on CS.

SERIAL INPUT DATA (SI)

The SI pin is used for serial instruction data input. SI information is latched into the input register on the rising edge of SCLK. A logic
high state present on SI programs a logic [1] in the command word on the rising edge of the CS signal. To program a complete word,
16 bits of information or multiples of eight there of must be entered into the device.

SERIAL OUTPUT DATA (SO)

The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic low state. All normal
operating drivers are reported as a logic [0], all faulted drivers are reported as a logic [1]. The negative transition of CS enables the SO
driver.
The SI / SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit
(MSB) first.

OUTPUT ENABLE (OUTEN)

The OUTEN pin is an active low input. When the OUTEN pin is low, all the device outputs are active. The outputs are all disabled when
OUTEN pin is high. SPI and parallel communications are still active in either state of OUTEN.

FEEDBACK VOLTAGE SENSOR (FB0-FB3)

The FBx pin has multiple functions for control and diagnostics of the external MOSFET/IGBT ignition gate driver. In Ignition (IGBT)
mode, the feedback inputs monitor the IGBT's collector voltage to provide the Spark Duration Timer control signal. The Spark Duration
Timer monitors this input to determine if the secondary clamp function should be activated. In secondary clamp mode, the IGBT's collector
voltage is internally clamped to VPWR +11 V.

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 FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION

In the GPGD mode, this input monitors the drain of an external MOSFET to provide short-circuit and open circuit detection by monitoring
the MOSFET's drain to source voltage. The filter timer and threshold voltage are easily programmed through SPI (See Table 21 and
Table 22 for SPI messages). In GPGD mode the FBx pin also provides a drain to gate clamp for fast turn OFF of inductive loads and
external MOSFET protection.

GATE DRIVER OUTPUT (GD0-GD3)

The GDX pins are the gate drive outputs for an external MOSFET or IGBT. Internal to the device is a Gate to Source resistor designed
to hold the external device in the OFF state while the device is in the POR or Sleep state.

LOW-SIDE INJECTOR DRIVER OUTPUT (OUT0 - OUT3)

OUT0 - OUT3 are the open drain low-side (Injector) driver outputs. The drain voltage is actively clamped during turn OFF of inductive
loads. These outputs can be connected in parallel for higher current loads provided the turn OFF energy rating is not exceeded.

RESISTOR SENSE POSITIVE (RSP)

Resistor Sense Positive - Positive input of a current sense amplifier. The ignition coil current is monitored by sensing the voltage across
an external resistor connected between RSP and RSN. The output of the current sense amplifier feeds the inputs of the NOMI and MAXI
comparators.
Note: RSN and RSP must be grounded in V10 mode.

RESISTOR SENSE NEGATIVE (RSN)

Resistor Sense Negative - Negative input of a current sense amplifier. The ignition coil current is monitored by sensing the voltage
across an external resistor connected to RSP and RSN. The output of the current sense amplifier feeds the inputs of the NOMI and MAXI
comparators.
Note: RSN and RSP must be grounded in V10 mode.

NOMINAL IGNITION COIL CURRENT (NOMI)

Nominal ignition coil current output flag. This output is asserted when the output current exceeds the level selected by the DAC. NOMI
can be configured as an input pin for V10 mode applications where the gate drive needs to be latched off by another device’s MAXI current
sense amplifier output. The NOMI input latches off gate drivers 5 and 6 when configured as a V10 mode ignition gate driver See Figure 11.

SPARK DURATION OUTPUT (SPKDUR)

SPKDUR is the Spark Duration output. This open drain output is low while feedback inputs FB0 through FB3 are above the programmed
Spark Detection Threshold. This output indicates an ignition flyback event. Each feedback input (FB0 - FB3) is logically ORed to drive the
SPKDUR output. There is a 50 A pull up current source connected internally to the SPKDUR pin.

MAXIMUM IGNITION COIL CURRENT (MAXI)

Maximum ignition coil current output flag. This output is asserted when the output ignition coil current exceeds the selected level of the
DAC. This signal also latches off the gate drive outputs when configured as an ignition gate driver. The MAXI current level is determined
by the voltage drop across an external sense resistor connected to pins RSP and RSN.
MAXI can be configured as an input pin for V10 applications where the gate drive needs to be latched off by another devices MAXI
current sense amplifier output. The MAXI input latches off gate drivers 7 and 8 when configured as ignition gate drive outputs (IGBTs) See
Figure 11.

DRIVER INPUT (DIN0-DIN3), GATE DRIVER INPUT (GIN0-GIN3)

Parallel input pins for OUT0-OUT3 low-side drivers and GD0-GD3 gate drivers. Each parallel input control pin is active high and has an
internal pull-down current sink. The parallel input data is logically ORed with the corresponding SPI input data register contents, except
for the Ignition mode IGBT drivers. They are only controlled by the parallel inputs GIN0-GIN3. In GPGD mode, GIN0-GIN3 are logically
ORed with SPI input data. All outputs are disabled when the OUTEN pin is high, regardless of the state of the command inputs.

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Freescale Semiconductor 15
 FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

MC33810 Functional Block Diagram

Power Supply

POR Injector Drivers

Out1 - Out3

SPI Interface

Parallel Control Inputs

PWM Controller
Ignition Gate
Pre-drivers
NOMI/MAXI DAC GD0 - GD3

SPARKDUR DAC

Power Supply MCU Interface and Output Driver Control Drivers

Figure 5. Functional Internal Block Diagram

POWER SUPPLY/POR
The 33810 is designed to operate from 4.5 V to 36 V on the VPWR pin. The VPWR pin supplies power to all internal regulators, analog,
and logic circuit blocks. The VDD supply is used for setting communication threshold levels and supplying power to the SO driver. This IC
architecture provides a low quiescent current Sleep mode. Applying VPWR and VDD to the device generates a Power On Reset (POR) and
place the device in the Normal state. The Power On Reset circuit incorporates a timer to prevent high frequency transients from causing
a POR.

MCU INTERFACE AND OUTPUT CONTROL

This component provides parallel input pins for OUT0-OUT3 low-side drivers and GD0-GD3 gate drivers. Each parallel input control
pin is active high and has an internal pull-down current sink. The parallel input data is logically ORed with the corresponding SPI input
data register contents. All outputs are disabled when the OUTEN pin is high, regardless of the state of the command inputs.

INJECTOR DRIVERS: OUT0 – OUT3

These pins are the open drain low-side (Injector) driver outputs. The drain voltage is actively clamped during turn OFF of inductive
loads. These outputs can be connected in parallel for higher current loads, provided the turn OFF energy rating is not exceeded.

IGNITION GATE PRE-DRIVERS: GD0 – GD3

These pins are the gate drive outputs for an external MOSFET or IGBT. Internal to the device is a Gate to Source resistor designed to
hold the external device in the OFF state while the device is in the POR or Sleep state.

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 FUNCTIONAL DEVICE OPERATION
MODES OF OPERATION

FUNCTIONAL DEVICE OPERATION

MODES OF OPERATION

POWER SUPPLY
The 33810 is designed to operate from 4.5 V to 36 V on the VPWR pin. The VPWR pin supplies power to all internal regulators, analog
and logic circuit blocks. The VDD supply is used for setting communication threshold levels and supplying power to the SO driver. This IC
architecture provides flexible microprocessor interfacing and low quiescent current Sleep mode.

POWER ON RESET (POR)

Applying VPWR and VDD to the device generates a Power On Reset (POR) and place the device in the Normal State. The Power On
Reset circuit incorporates a filter to prevent high frequency transients from causing a POR.
All outputs are disabled when the OUTEN input pin is high regardless of the SPI control registers or the logic level on the parallel input
pins. With the OUTEN pin high, SPI messages may be sent and received by the device. Upon enabling the device (OUTEN low), outputs
are activated based on the state of the command register or parallel input.

Table 6. Operational States

VPWR VDD OUTEN OUTPUTS STATE
L L X OFF Power Off

L H X OFF POR
H L X OFF Sleep

H X OFF POR

H X OFF POR

L X OFF Sleep

H H L Active Normal

H H H OFF Normal

SLEEP STATE
Sleep state is entered when the VDD supply voltage is removed from the VDD pin. In Sleep state, all outputs are OFF. Applying VDD
forces the device to exit the Sleep state and generates a POR.

NORMAL STATE
The default Normal state is entered when power is applied to the VPWR and VDD pins. Control register settings from a Power On Reset
(POR) are as follows:
• All outputs OFF
• IGNITION gate driver mode enabled (IGBT Ignition mode).
• PWM frequency and duty cycle control disabled.
• OFF state open load detection enabled (LSD)
• MAXI dac set to 14 A, NOMI DAC set to 5.5 A
• Spark detect level VIL DAC set to VPWR +5.5 V
• Open secondary timer set to 100 s
• Dwell timer set 32 ms
• Soft shutdown disabled
• Low-voltage flyback clamp disabled
• Dwell overlap MAXI offset disabled

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 FUNCTIONAL DEVICE OPERATION
MODES OF OPERATION

MODES OF OPERATION
In Normal state, the 33810 gate driver has three modes of operation, Ignition mode, GPGD mode and V10 mode.The operating mode
of each gate driver may be set individually and is programmed using the Mode Select command.

MODE SELECT COMMAND

The Mode Select command is used to set the operating mode for the GDx gate driver outputs, over/undervoltage operation and to
enable V10 mode and the PWM generators. The Mode Select command programmable features are listed below.
• Ignition/GPGD mode select (gate drivers)
• V10 mode enable
• Over/Undervoltage operation for all drivers
• GPGD PWM controller enable

IGNITION/GPGD MODE SELECT

The Ignition/GPGD mode select bits determine independently, the operating mode of each of the GDx gate driver outputs. Bits 8, 9, 10,
11 correspond to GD0, GD1, GD2, and GD3 respectively. Setting the bit to a logic 0 sets the GDx driver to the Ignition mode. Setting the
bit to a logic [1] commands the GDX driver to the GPGD mode and disables the ignition features for that particular gate driver (except the
MAXI current shutdown feature). Further information on GDx gate driver in Ignition mode and GPGD mode is provided later in this section
of the data sheet.

V10 MODE ENABLE BIT

The V10 Enable bit allows the user to configure the device for 10 cylinder applications. When the V10 mode is enabled, the device
configures the NOMI pin and MAXI pin as digital inputs rather than outputs. The new MAXI input pin receives the MAXI shutdown signal
for GD0 and GD2 and the new NOMI input pin receives the MAXI shutdown signal for GD1 and GD3. Further information on V10 mode
is provided in the V10 application section.
Note: RSN and RSP must be grounded in V10 mode.

OVER/UNDERVOLTAGE SHUTDOWN/RETRY BIT

The Over/Undervoltage Shutdown/Retry bit allows the user to select the global over and undervoltage fault strategy for all the outputs.
In an overvoltage or undervoltage condition on the VPWR pin, all outputs are commanded OFF. The Over/Undervoltage control bit sets
the operation of the outputs when returning from over/under voltage. Setting the Over/Undervoltage bit to logic [1] forces all outputs to
remain OFF when VPWR returns to normal level. To turn the output ON again, the corresponding input pin or SPI bit must be reactivated.
Setting the Over/Undervoltage bit to logic [0] commands all outputs to resume their previous state when VPWR returns to normal level.
Table 7. below provides the output state when returning from over or undervoltage.

Table 7. Overvoltage/Undervoltage Truth Table

Over/
GINx DINx OUTEN State When Returning
SPI Bit Undervoltage
Input Pin Input pin From Over/Undervoltage
Control Bit
X X X 1 OFF
X X 1 0 OFF
0 0 0* 0 OFF
X 1 0* 0 ON
1 X 0* 0 ON
* Default setting
Note: The SPI bit does not control the Gate Driver outputs in the Ignition mode, only in the GPGD mode.
An undervoltage condition on VDD results in the global shutdown of all outputs and reset of all internal control registers. The VDD
undervoltage threshold is between 0.8 V and 2.8 V

PWMX ENABLE BIT

Gate Driver outputs programmed as GPGDs may be used as low frequency PWM outputs. The PWM generators are enabled via bits
0 through 3 in the Mode Select command. Bits 0 through 3 correspond to outputs GD0 through GD3, respectively. Once the frequency
and duty cycle are programmed through the PWM Frequency & DC command, the PWM output may be turned ON and OFF through the
PWM enable bit. Further information on PWM control is provided in the GPGD mode section of this data sheet.

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 FUNCTIONAL DEVICE OPERATION
MODES OF OPERATION

IGNITION (IGBT) GATE DRIVER MODE

The MC33810 contains dedicated circuitry necessary for automotive ignition control systems. Each gate driver may be individually
configured as an Ignition Gate Driver with the following features:
• Spark duration signal
• Open secondary timer
• Soft shutdown control
• Low-voltage flyback clamp
• Ignition ignition coil current measurement
• MAXI output and control
• NOMI output
• Maximum dwell timer
In the Ignition Mode, several control strategies are in place to control the IGBT for enhanced system performance. Information acquired
from the FBx pin allows the device to produce a Spark Duration signal output (SPKDUR) and detect open secondary ignition coils. Based
on the FBx signal and Spark Command register settings, the device performs the appropriate gate control (Low-voltage Flyback Clamp,
Soft Shutdown) and produces the SPKDUR output.
The FBx pin is connected to the collector of the IGBT through an external 9:1 resistor divider network. The recommended values for the
resistor divider network is 36 k and 4.02 k, with the 36 k resistor connected from the IGBT collector to the FBx pin and the 4.02 K resistor
connected from the FBx pin to ground.
Additional controls to the gate driver are achieved by sensing the current through the external IGBT. The Resistor Sense Positive (RSP)
and Resistor Sense Negative (RSN) inputs are use to measure the voltage across an external 20 mor 40 m current sense resistor. A
gain select bit in the Spark Command SPI Command messages should be set to a logic [1] (gain of 2) when using a 20 m current sense
resistor. When using a 40 m current sense resistor, the gain select bit should be set to a logic [0] (gain of 1 is the default value).
The ignition coil current is compared with the output of the DACs which have been programmed via the SPI Commands. The
comparison generates the Nominal Current signal (NOMI) and the Maximum Current signal (MAXI). Both signals have a low output when
the ignition coil current is below the programmed DAC value and a high output when the current is above the programmed DAC value.
When the GDx output is shutdown because of the control strategy, the output may be activated again by toggling the input control.

SPARK COMMAND
The Spark Command is an Ignition mode command used to program the parameters for the Ignition mode features listed below:
• End spark threshold (EndSparkTh bits)
• Open secondary fault timer (OSFLT bits)
• Secondary clamp (secondary clamp bit)
• Soft shutdown enable (SoftShutDn bit)
• Ignition ignition coil current amplifier gain (Gain Sel bit)
• Overlapping dwell disable (Overlap Dwell Disable bit)
• Maximum dwell enable (MaxDwellEn bit)
• Maximum dwell timer (MaxDwellTimer bits)
• End of spark filter timer value
Spark Command address and data bits are listed in Table 21
NOTE: Gate driver outputs programmed to be GPGDs are not affected by the Spark commands.

SPARK DURATION SIGNAL

The Spark Duration is defined as the beginning of current flow to the end of current flow across the spark plug gap. Because the
extremely high-voltage ignition coil secondary output is difficult to monitor, corresponding lower voltage signals generated on the ignition
coil primary are often used. The FBx pins monitor the ignition coil primary voltage (IGBT Collector) through a 10 to 1 voltage divider. When
the IGBT is disabled, the rise in the FBx signal indicates a sparkout condition is occurring at the spark plug gap.
The device considers the initial thresholds for spark duration to be VIH = VPWR + 21 V for rising edge as measured on the collector of
the IGBT. The spark duration falling edge reference is programmable via SPI through the End Spark Threshold bits 0 and 1 (See Table 8).
Figure 5 illustrates a typical ignition event with Dwell Time and Spark Duration indicated.

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 FUNCTIONAL DEVICE OPERATION
MODES OF OPERATION

Ignition Coil Current,

5.0 A/div

Channel 1: GINx IGBT Gate Drive

Channel 2: IGBT Collector Voltage
Channel 3: IGBT Current @ 5.0 A/Div

DWELL Time SPKDUR~3.0 ms

Figure 6. Ignition Coil Charge and Spark Event

VPWR = 16.0 V
Default settings
Begin spark threshold VIH = VPWR + 21 V
End spark threshold VIL = VPWR +5.5 V
The pulse width of the SPKDUR signal is measured by the MCU timer/input capture port to determine the actual spark duration. Spark
Duration information is then used by the MCU spark control algorithm to optimize the Dwell Time.

Table 8. End Spark Threshold

Spark Command Bit<b1,b0> End Spark Threshold (VIL)
00 VPWR + 2.75
01 VPWR + 5.5
10 VPWR + 8.2
11 VPWR + 11.0

OPEN SECONDARY TIMER

A fault due to open in the ignition coil secondary circuit can be determined by waveforms established on the ignition coil primary during
a spark event. The spark event is initiated by the turn OFF of the IGBT. The voltage on the collector of the IGBT rises up to the IGBT’s
internal collector to gate clamp voltage (typically 400 volts). Collector to gate clamp events normally last 5.0 s to 50 s. In an open ignition
coil secondary fault condition, the collector to gate clamp event lasts much longer. The oscilloscope waveform in Figure 7 and Figure 8
compares a normal spark signature with an open secondary fault condition signature.

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 FUNCTIONAL DEVICE OPERATION
MODES OF OPERATION

Figure 7. Normal Spark Event

Figure 8. Open Secondary Spark Event

The Open Secondary timer is initiated on the rising edge of the ignition coil primary spark signal and terminated on the falling edge. The
rising edge Open Secondary threshold is VIH = 135 V at primary, no hysteresis. The falling edge Open Secondary threshold is VIL = 135 V.
Collector to gate clamp durations lasting longer than the selected Open Secondary Fault Time interval (Table 9) indicate a failed spark
event. When the Open Secondary Fault Time is exceeded and the low-voltage clamp is enabled, the GDx output activates the low-voltage
clamp shown in Figure 9. The Logic for this low-voltage clamp is defined in Figure 9

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 FUNCTIONAL DEVICE OPERATION
MODES OF OPERATION

Table 9. Open Secondary Timer

Open Secondary Fault Timer
Spark Command Bits<b3,b2>
OSFLT (s)
00 10

01 20

10 50

11 100

LOW-VOLTAGE CLAMP
The low-voltage clamp is an internal clamp circuit which biases the IGBT's gate voltage in order to control the collector to emitter voltage
to VPWR +11 V. This technique is used to dissipate the energy stored in the ignition coil over a longer period of time than if the internal
IGBT clamp were used.
In the Open Secondary Fault condition, all of the stored energy in the ignition coil is dissipated by the IGBT. This fault condition requires
the use of a higher energy rated IGBT than would otherwise be needed. The low-voltage clamp spreads out the energy dissipation over
a longer period of time, thus allowing the use of a lower energy rated IGBTs. The internal low-voltage clamp is connected between the
IGBT's collector (through an external resistor) and the IGBT's gate. The energy stored in the ignition coil is dissipated by the IGBT, not
the internal clamp. The internal clamp only provides the bias to the IGBT.
Several logical signals are required as inputs to activate the GDx Low-voltage Clamp feature. The GDx Low-voltage Clamp feature may
be disabled through bit 4 of the Spark Command message.

+
– SPI

+ FB0
SPARK DURATION – SPI FB1
100 µA FB2
Open Secondary
FB3
VPWR 

13 V 53 V

SPI input
Low V GPGD
Clamp Clamp
GATE DRIVE
CONTROL

GD0
GD1
GD2
GD3
Figure 9. Low-voltage Clamp

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 FUNCTIONAL DEVICE OPERATION
MODES OF OPERATION

OSFLT_En

IGN Mode
Activate
OSFLT
Low-voltage
Clamp
MaxDwell
MaxDwellEn

SoftShutDnEn
IGN Mode

VPWR
overVOLTAGE
OUTEN
Figure 10. Low-voltage Clamp Logic

SOFT SHUTDOWN ENABLE

The Soft Shutdown feature is enabled via the SPI by asserting control bit 5 in the Spark Command message. When enabled, the
following events initiate a soft shutdown control of the gate driver.
• OUTEN = High (Outputs Disabled)
• Overvoltage on VPWR pin
• Max dwell time
Soft shutdown is designed to prevent an ignition spark while turning off the external IGBT. The low-voltage clamp is activated to provide
the mechanism for a soft shutdown.

GAIN SELECT BIT

The ignition coil current comparators are used to compare the programmed NOMI and MAXI DAC value with voltage across the external
current sense resistor. When selecting a gain of two, the ignition coil current sense resistor must be reduced from 40 m to 20 m

OVERLAPPING DWELL ENABLE BIT

Overlapping dwell occurs when two or more Ignition mode drivers are commanded ON at the same time. In this condition with the
Overlapping Dwell Bit enabled, the MAXI DAC threshold value is increased as a percentage of the nominal programmed value. The
percent increase is determined by bit 5 through bit 7 of the DAC Command.

Table 10. Overlapping Dwell Compensation

DAC Command Bits<b7,b6,b5> Overlap Compensation (%)
000 0%

001 7%

010 15%
011 24%

100 35% (default)

101 47%
110 63%

111 80%

MAXIMUM DWELL ENABLE BIT

Bit 8, the Maximum Dwell Enable bit, allows the user to enable the Maximum Dwell Gate Turnoff feature. When the Max Dwell bit is
programmed as logic 0 (disabled), the device does not perform a low-voltage clamp due to Max Dwell (See Figure ).

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 FUNCTIONAL DEVICE OPERATION
MODES OF OPERATION

MAXIMUM DWELL GATE TURN OFF FEATURE

In automotive ignition systems, dwell time is defined as the duration of time an ignition coil is allowed to charge. The 33810 starts the
measure of time from the gate drive ON command. If the dwell time is greater than the Max Dwell Timer setting (Table 11), the offending
ignition gate driver is commanded OFF. The Max Dwell Gate Turn OFF feature may be disabled via bit 8 of the Spark Command. When
the feature is disabled, the Max Dwell fault bits are always logic 0. The Max Dwell Timer feature pertains to Ignition mode only and does
not affect gate drivers configured as GPGDs.
The Max Dwell gate turn OFF signal is a logically ANDed with the Soft Shutdown bit to activate a Low-voltage Active Clamp (See
Figure ).

Table 11. Maximum Dwell Timer

Spark Command Bit<b11,b10,b9> MAX Dwell Timer MaxDwell (ms)
000 2

001 4

010 8

011 16

100 32 (default)
101 64

110 64

111 64

DAC COMMAND (DIGITAL TO ANALOG CONVERSION COMMAND)

The DAC command is an Ignition mode command which sets the nominal ignition coil current (NOMI) and maximum ignition coil current
(MAXI) DAC values. Bits 0 through 4 set the NOMI threshold value and bits 8 through 11 set the MAXI threshold values. The DAC
command and default values are listed in the SPI Command Summary Table 21. The NOMI output is used by the MCU as a variable in
dwell and spark control algorithms.

NOMI DAC BITS

The NOMI output signal is generated by comparing the external current sense resistor differential voltage (Resistor Sense Positive,
Resistor Sense Negative) with the SPI programmed NOMI DAC value. When the NOMI event occurs, the NOMI output pin is asserted
(high). The NOMI output is only a flag to the MCU and it’s output does not affect the gate driver.
When using a 20 m resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN
should be set to a gain of 2 via the SPI Command Message Spark command (Command 0100, hex 4), Control bit 6 =1. When using a
40 mresistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN, should be set to a
gain of 1 via the SPI Command Message Spark Command (Command 0100, hex 4), Control bit 6 = 0. This is also the default value. The
NOMI output provides a means to alert the MCU when the ignition coil primary current equals the value programmed into the NOMI DAC.
In V10 mode, the NOMI pin is reconfigured as a MAXI input pin from a third MC33810 device in the system. In this mode, a NOMI input
has effectively the same control as an internal MAXI signal. Further information is provided in the V10 mode application section of this
data sheet.

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Table 12. Nominal Current DAC Select

Differential Voltage Differential Voltage
DAC Command Bits<4,3,2,1,0> NOMI Current (A) (mV) RS = 20 m (mV) RS = 40 m
(Gain = 2) (Gain = 1)
00000 3.00 60 120
00001 3.25 65 130
00010 3.50 70 140
00011 3.75 75 150
00100 4.00 80 160
00101 4.25 85 170
00110 4.50 90 180
00111 4.75 95 190
01000 5.00 100 200
01001 5.25 105 210
01010 5.50 110 220
01011 5.75 115 230
01100 6.00 120 240
01101 6.25 125 250
01110 6.50 130 260
01111 6.75 135 270
10000 7.00 140 280
10001 7.25 145 290
10010 7.50 150 300
10011 7.75 155 310
10100 8.00 160 320
10101 8.25 165 330
10110 8.50 170 340
10111 8.75 175 350
11000 9.00 180 360
11001 9.25 185 370
11010 9.50 190 380
11011 9.75 195 390
11100 10.00 200 400
11101 10.25 205 410
11110 10.50 210 420
11111 10.75 215 430

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MAXI DAC BITS

The MAXI control block provides a means to shut off all the ignition coil drivers if the current reaches a SPI programmable maximum
level. Control is achieved by comparing the output of the current sense amplifier with a SPI programmed DAC value. The MAXI comparator
disables all gate drivers configured as ignition drivers when the DAC MAXI setting is exceeded. When a MAXI event occurs, the MAXI bit
in the fault status register is set and the MAXI pin is asserted (high).
When using a 20 m resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN
should be set to a gain of 2 via the SPI Command Message Spark command (Command 0100, 
hex 4), Control bit 6 =1. When using a 40 mresistor as the current sense resistor, the gain select of the differential amplifier connected
to RSP and RSN should be set to a gain of 1 via the SPI Command Message Spark command (Command 0100, 
hex 4), Control bit 6 = 0. This is also the default value. The MAXI fault bit in the SPI Fault Status register is cleared when the MAXI condition
no longer exists and the SPI fault status register was read by the MCU.
In V10 mode, the MAXI pin is configured as an input to receive the MAXI signal from a second MC33810 device in the system. In this
mode, an input MAXI signal has effectively the same control as an internal MAXI signal. Further information is provided in the V10 mode
application section of this specification.

Table 13. Maximum Current DAC Select

Differential Voltage Differential Voltage
DAC Command Bit<b11,b10,b9,b8> MAXI Current (A)
(mV) RS = 20 m (mV) RS = 40 m

0000 6.0 120 240

0001 7.0 140 280

0010 8.0 160 320

0011 9.0 180 360

0100 10.0 200 400

0101 11.0 220 440

0110 12.0 240 480

0111 13.0 260 520

1000 14.0 280 560

1001 15.0 300 600

1010 16.0 320 640

1011 17.0 340 680

1100 18.0 360 720

1101 19.0 380 760

1110 20.0 400 800

1111 21.0 420 840

END OF SPARK FILTER BITS

The ringing at the end of the spark signatures waveform can cause erroneous detection of the End of Spark event. To eliminate the
effect of this ringing, a low pass filter with variable time values can be selected. Four time values for the low pass filter are provided with
a zero value, indicating no low pass filtering is to be used. The End of Spark Filter bits specify a 0, 4 µs, 16 µs, or 32 µs time interval to
sample the spark ignition coil primary current to ignore the ringing at the end of spark.

Table 14. End of Spark Filter Time Select

End of Spark Filter Bits<1, 0> Filter Time (µs)
00 0.0
01 4.0
10 16.0
11 32.0

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GENERAL PURPOSE GATE PRE-DRIVER MODE

Each gate driver can be individually configured as a General Purpose Gate Pre-driver (GPGD) and controlled from the parallel GINx
input pins, SPI Driver ON/OFF command, or may be programmed through the SPI for a specific frequency and duty cycle output (PWM).
In GPGD mode, the gate drivers have the following features:
• Gate driver for discrete external MOSFET
• OFF state open load detect
• ON state short-circuit protection
• Programmable drain threshold and duration timer for short fault detection
• PWM frequency/duty cycle controller
In GPGD mode, the GDx output is a current controlled output driver with slew rate control, gate to source clamp, passive pull-down
resistor, and a drain to gate clamp for switching inductive loads.

Driver ON /OFF Command

For the Driver ON/OFF Command, bits 4 through 7 control gate drivers are Mode Select Command programmed as GPGD. A logic [1]
in bits 4 through 7 commands the specific output ON. A logic [0] in the appropriate bit location commands the specific output OFF. SPI
control bits for the integrated LSD output drivers are also contained in the Driver ON/OFF command. Further information on LSD control
is provided in the Low-side Injector Driver section of the data sheet.
Note that gate drivers programmed to Ignition mode have parallel input control only and cannot be turned OFF and ON via SPI
commands.

GPGD Short Threshold Voltage Command

Each GPGD is capable of detecting an open load in the OFF state and shorted load in the ON state. All faults are reported through the
SPI communication. For open load detection, a current source is placed between the FBx pin and ground of the IC. An open load fault is
reported when the FBx voltage is less than the 2.5 V threshold. Open load fault detect threshold is set internally to 2.5 V and may not be
programmed. A shorted load fault is reported when the FBx pin voltage is greater than the programmed short threshold voltage.
The short to battery fault threshold voltage of the external MOSFET is programmed via the GPGD Short Threshold Voltage command.
Table 15 illustrates the bit pattern to select a particular threshold. Drain voltages less than the selected threshold are considered normal
operation. Drain voltages greater than the selected threshold voltage are considered faulted.

Table 15. FBx Fault Threshold Select

GPGD VDS FLT Bits FBx Fault Threshold Select
000 0.5V
001 1.0V
010 1.5V
011 2.0 (default)
100 2.5V
101 3.0V
110 No Change
111 No Change

GPGD SHORT TIMER COMMAND

The GPGD Short Timer command allows the user to select the duration of time the drain voltage is allowed to be greater than the
programed threshold voltage without causing shutdown. External MOSFETS with drain voltages greater than the programed threshold for
longer than the Fault Duration Timer are shutdown. Timer durations are listed in Table 16.

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Table 16. FBx Short Fault Timer

GPGD FLT Timer Bits Fault Timer Select
000 30 µs
001 60 µs
010 120 µs
011 240 µs (default)
100 480 µs
101 960 µs
110 No Change
111 No Change
Notes
20. Tolerance on this fault timer setting is ±10% after using the Calibration Command.

GPGD FAULT OPERATION COMMAND

The GPGD Fault Operation command sets the operating parameters for the gate drivers under faulted conditions. A short fault is said
to be “detected” when the drain source voltage, VDS of the external MOSFET, exceeds the SPI programmed short threshold voltage. The
short fault is said to be “declared” when the VDS overvoltage lasts longer than the SPI programmed “fault timer.” (short duration time >
fault timer programmed value).
Each gate driver is individually set to either restore to the pre-fault state or shut down when a short fault is declared. By setting the
Retry/Shutdown bit in the GPGD Fault Operation Command to logic 1, the specific output tries to go back to the pre-fault state when the
fault is no longer declared, after a programmed “inhibit time”.
The retry strategy causes the output to try to return to the pre-fault state on a 1% duty cycle basis. For example: If the fault timer is set
to 120s and a fault is declared (drain voltage greater than the programmed threshold for greater than 120 s), the GDx output driver is
forced OFF for 12 ms. After 12 ms has elapsed, if the inputs, GINx or SPI, have not tried to shut off the particular GDx output in the interim,
the GDx output tries to set the external driver ON again (the pre-fault state). A continued declared fault on the output would result in another
12 ms shutdown period. By setting the Retry/Shutdown bit in the GPGD Fault Operation Command to logic 0, the specific output shuts
down and remains OFF when the short fault is declared. Only a reissue of the turn ON command, via SPI or GINx, forces the output to try
to turn ON again.
In the event a GPGD is selected as a PWM controller and a short occurs on the output, the output retry strategy forces the output to a
1.0% duty cycle, based on the fault timer setting. For example: If the fault timer is set to 120 s and a fault is detected (drain voltage greater
than programmed threshold), the PWM output is commanded OFF for 12 ms and commanded ON again at the next PWM cycle.
Care should be taken to select a fault timer is shorter than the minimum duty cycle ON time of the PWM controller. Selecting a longer
fault time allows the PWM controller to continue to drive the external MOSFET into a shorted load.

PWM FREQUENCY/DUTY CYCLE COMMAND

The PWMx Freq & Duty Cycle command is use to program the GDx outputs with a frequency and duty cycle. Table 17 defines the user
selectable output frequency. The frequency and duty cycle may be updated at any time using the PWM Freq&DC command, however,
the update only begins on the next PWM rising edge.
Once the PWM Freq & DC registers are programmed and the PWM controller is enabled through the Mode Command, the PWM
outputs are turned ON and OFF via the GINx pin or the SPI GPGD ON/OFF Command control bit. All parallel and serial ON and OFF
command updates to the PWM controller are synchronous with the rising edge of the previous PWM period.
The truth table for GDx control in GPGD mode is provided in Table 9. The duty cycle of the PWM outputs is controlled by bits 0-6,
inclusive. The duty cycle value is 1.0% per binary count from 1-100 with counts of 101-127 defaulting to 100%. For example, sending SPI
command 101001000001100 would set GD1, PWM output to 10 Hz and 12% duty cycle.

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.
Table 17. Frequency Select
PWM Freq&DC Command Bit<b9,b8,b7> Frequency Hz
000 10 Hz (default)
001 20 Hz
010 40 Hz
011 80 Hz
100 160 Hz
101 320 Hz
110 640 Hz
111 1.28 kHz

Notes: Tolerance on selected frequency is ±10% after using the Calibration command. Shorts to battery and open load faults are not detected for frequency
and duty cycle combinations inconsistent with fault timers.

Table 18. Pre-driver GDx Output Control

Mode Command Driver ON/OFF PWMx GINx
GDx Output
IGN/GP Bit GPGD Bit Enable Bit Terminal
1 0 X 0 OFF
1 0 0 1 ON
1 1 0 X ON
1 X 1 1 Freq/DC
1 1 1 X Freq/DC

V10 MODE
V10 mode provides a method for monitoring 10 ignition events while using only two current sense resistors. This is achieved using three
MC33810 devices. Two MC33810 devices are programmed as Normal Ignition mode outputs and one is programmed as a V10 Ignition
mode output. The ignition gate driver outputs are partitioned into two banks of five outputs each (See Figure 11). Each bank contains one
or two driver(s) from the V10 device.
Drivers in the V10 device are grouped in twos (GD0&GD2, GD1&GD3). Current from each V10 mode IGBT group is monitored by the
appropriate Normal mode device (See Figure 11). The MAXI signal from one Normal mode device is ported to the V10 mode MAXI input
pin. Likewise the MAXI signal from the second Normal mode device is ported to the V10 mode NOMI input pin. The V10 mode NOMI/MAXI
inputs are used as MAXI shutdown signals for the appropriate ignition gate drive group.
V10 mode contains the same features as Ignition mode gate drivers with the following exceptions:
• NOMI/MAXI configured as input pins
• MAXI shutdown for GPGD disabled
• NOMI/MAXI comparators disabled
In V10 mode, Spark command bits 7 and 8 (Gain Select, Overlapping Dwell) are disabled. These two features are achieved through
the Normal mode devices. RSN and RSP must be grounded in V10 mode.

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Bank 1 Bank 2

IC 1 “Parent” IC 3 “Child” IC 2 “Parent”

GIN0 GO0 GO0 GIN0 GO0 GIN0

IGBT14
Gate Drive 0 IGBT1 (0-3) IGBT26
Gate Drive 0
GIN1 GO1 GIN1 GO1 GO1 GIN1
IGBT15
Gate Drive 1 Gate Drive 1
IGBT 2 (0-3)
GO2 GO2 GO2
GIN2 GIN2 GIN2
Gate Drive 2 Gate Drive 2
GIN3 GO3 GIN3 GO3 GO3 GIN3
Gate Drive 3 IGBT27
Gate Drive 3 4
4 4 GIN GIN (0-3)
GIN (0-3) (0-3)
LOGIC LOGIC NOMI LOGIC NOMI
NOMI
MAXI RSP1 RSP MAXI MAXI
RSP2
VtNI Child VtNI
NOMI RS1 Ign 1 Comparator
NOMI
disabled Ign 2 VtNI
NOMI
Comparator Inputs Tied RS2
Comparator
to GND VtMI
MAXI VtMI
disabled
VtMI
MAXI
MAXI Logic Logic Comparator
Comparator Buffer Buffer

Logic Logic
Logic Logic
Buffer Buffer
Buffer Buffer

NOMI MAXI MAXI NOMI

MAXI NOMI
NOMI1 to uP

MAXI1 to uP

MAXI2 to uP

NOMI2 to uP

Note: For “child” input NOMI is for channel 1 and 3, input MAXI is for channel 0 and 2
Figure 11. V10 Mode

LOW-SIDE INJECTOR DRIVER

The four open drain low-side injector drivers are designed to control various automotive loads such as injectors, solenoids, lamps,
relays and unipolar stepper motors. Each driver includes OFF and ON state open load detection, short-circuit protection and diagnostics.
The injector drivers are individually controlled through the ON/OFF SPI input command Table 21 or parallel input pins DIN0 to DIN3. Serial
and parallel control of the output state is determined by the logical OR of the SPI serial bit and the DINx parallel input pins. All four outputs
are disabled when the OUTEN input pin is high regardless of the state of the SPI control bit or the state of the DINx pin. All four injector
drivers are not affected by the selection of the gate driver’s three modes of operation (Ignition mode, GPGD mode, V10 mode).

ON /OFF CONTROL COMMAND

To program the individual output of the 33810 ON or OFF, a 16-bit serial stream of data is entered into the SI pin. The first four bits of
the control word are used to identify the ON / OFF command. Bit 0 through bit 3 of the ON/OFF Control command turn ON or OFF the
specific output driver.

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INJECTOR DRIVER FAULT COMMANDS

Fault protection strategies for the injector drivers are programmed by the SPI LSD Fault Command. Bit 8 through 11 determine the type
of short circuit protection to be used, bits 0 through 7 set the open load strategy.
Short-circuit protection consists of three strategies. All strategies utilize current limiting as an active element to protect the output driver
from failure.The TLIM and Timer options are used to enhance the short circuit protection strategy of the Injector drivers. The timer protection
scheme uses a low duty cycle in the event of a short-circuit. The TLIM protection circuit uses the junction temperature of the output driver
to determine the fault. Both methods may be used together or individually.

TIMER PROTECTION
The first protection scheme uses a low ON to OFF duty cycle to protect the output driver. The low duty cycle allows the device to cool
so the maximum junction temperatures are not exceeded. During a short condition, the device enters current limit. The driver shuts down
for short conditions lasting longer than the current limit timer (~60 s).

TEMPERATURE LIMIT (TLIM)

The second scheme senses the temperature of the individual output driver. During a short event, the device enters current limit and
remains in current limit until the output driver temperature limit is exceeded (TLIM). At this point, the device shuts down until the junction
temperature falls below the hysteresis temperature value. The TLIM hysteresis value is listed in the previous specification tables.
The third method combines both protection schemes into one. During a short event, the device enters the current limit. The output driver
shuts down for short conditions lasting longer than the current limit timer. In the event the output driver temperature is higher than maximum
specified temperature, the output shuts down. The Shutdown/Retry bit allows the user to determine how the drivers responds to each short
circuit strategy. Table 19. provides fault operation for all three strategies.
Outputs may be used in parallel to drive higher current loads, provided the turn-off energy of the load does not exceed the energy rating
of a single output driver (100 mJ maximum).

Table 19. Injector Driver (OUTx) Fault Operation

ShutdnRetry Fault Timer
TLIM Bit 10 Operation During Short Fault
Bit 11 Bit 9
Timer only, outputs retry on period
1 0 X
OUT0-OUT3 = 60 s ON, ~10 ms OFF

1 1 0 TLIM only, outputs retry on TLIM hysteresis

Timer and TLIM, outputs retry on period and driver temperature
1 1 1 below threshold
OUT0-OUT3 = 60 s ON, ~10 ms OFF
Timer only, outputs do not retry on period
0 0 X
OUT0-OUT3 = 60 s ON, OFF

0 1 0 TLIM only, outputs do not retry on TLim hysteresis

Timer and TLIM, outputs do not retry on period or TLIM
0 1 1
OUT0-OUT3 = 60 s ON, OFF

OUTPUT DRIVER DIAGNOSTICS.

Short to battery, Temperature Limit (TLIM) and open load faults are reported through the All Status Response message Table 22.

OFF OPEN LOAD PULL-DOWN CURRENT ENABLE BITS

An open load on the output driver is detected by the voltage level on the drain of the MOSFET in the OFF state. Internal to the device
is a 75 A pull-down current sink. In the event of an open load, the drain voltage is pulled low. When the voltage crosses the threshold,
an open load is detected. The pull-down current source may be disabled by bit 0 through bit 3 in the LSD Fault Command. With the driver
OFF and the OFF open load bit disabled, the OFF open load fault status bit is a logic [0].

ON OPEN LOAD ENABLE BITS

The ON state open load enable bit allows the user to determine an ON state open load. When the ON state open load bit disabled, the
ON state Fault bit is always logic [0]. ON open load is determined by monitoring the current through the OUTx MOSFET. In the ON state,
currents less than 20 mA to 200 mA are considered open.

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Table 20. InjectorDriver Diagnostics

Program State Fault Fault Bits
OFF State Open Load ON State Open Load Output STB STG OUTx Batt Short OUTx OFF Open OUTx ON Open
Driver ON/OFF Fault Reported
Pull Dwn En Bit OPEN Fault Fault Fault

0 X OFF STB 0 0 0 No Fault

0 X OFF STG 0 0 0 No Fault

0 X OFF OPEN 0 0 0 No Fault

1 X OFF STB 0 0 0 No Fault

1 X OFF STG 0 1 0 Open Load

1 X OFF OPEN 0 1 0 Open Load

X 0 ON STB 1 0 0 Short to Batt

X 0 ON STG 0 0 0 No Fault

X 0 ON OPEN 0 0 0 No Fault

X 1 ON STB 1 0 0 Short to Batt

X 1 ON STG 0 0 1 Open Load

X 1 ON OPEN 0 0 1 Open Load

CLOCK CALIBRATION COMMAND

In cases where an accurate time base is required, the user must calibrate the internal timers using the Clock Calibration command
(refer to Table 21). After the 33810 device receives the Calibration command, the device expects to receive a 32 s logic [0] calibration
pulse on the CS pin. The pulse is used to calibrate the internal clock. Any SPI message may be sent during the 32 s calibration chip
select. Because the oscillator frequency may shift up to 35% with temperature, calibration is required for an accurate time base. The
Calibration command should be used to update the device on a periodic basis.

SPI COMMAND SUMMARY

The SPI commands are defined as 16 bits with 4 address control bits and 12 command data bits. There are 12 separate commands
used to set operational parameters of device. The operational parameters are stored internally in 16-bit registers. Table 21 defines the
commands and default state of the internal registers at POR. SPI commands may be sent to the device at any time in Normal state.
Messages sent are acted upon on the rising edge of the CS input.
.
Table 21. SPI Command Message Set and Default State
Command Control Address Bits Command Bits

hex 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read Registers <0000>

0 0 0 0 0 1 0 1 0 0 0 0 0
Command Internal Register Address

All Status Command 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0

SPI Check Command 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

<0000> <0> <0> <0> <0> <0> <0>

Mode Select Command IGN/GP Mode Select V10 OVR/ PWM3 PWM2 PWM1 PWM0
1 0 0 0 1 X X
En UNDR EN EN EN EN
Set to IGN Mode Disab Vtg Disab Disab Disab Disab

<10X> <1> <1> <1> <1> <1> <1> <1> <1>

LSD Fault Operation OUT3 OUT2 OUT1 OUT0 OUT3 OUT2 OUT1 OUT0
LSD Fault Command Shutdown,Tlim,Timer ON ON ON ON OFF OFF OFF OFF
2 0 0 1 0 X
Open Open Open Open Open Open Open Open
Retry on Timer Load Load Load Load Load Load Load LoadE
and No Tlim Enabl Enabl Enabl Enabl Enabl Enabl Enabl nabl

<0000>
Driver ON/OFF GPGD <0000>
Command 3 0 0 1 1 X X X X OFF OUTx Driver
0 = OFF, 1 = ON (IGNORED IN IGNITION OFF
MODE)

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Table 21. SPI Command Message Set and Default State (continued)
Command Control Address Bits Command Bits

hex 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

<100> <0> <0> <0> <0> <0> <11> <01>

Max Dwell Timer Max Over Gain Soft Open Open End Spark
Spark Command 4 0 1 0 0 MaxDwell Dwell lap Sel Shut 2ed Secondary Threshold
Default=32 ms En Dwell Gain Dn En Clmp OSFLT
(In Ignition Mode Only) Disab Disab =1 Disab Disab =100 s VPWR +5.5 V

<01>
End Spark Filter X End Spark
5 0 1 0 1 X X X X X X X X X Filter
4.0 s

<1000> <100> <01010>

DAC Command 6 0 1 1 0 MAXI DAC Threshold Overlap Setting NOMI DAC Threshold
MAXI=14 A Overlap 50% NOMI=5.5 A

GPGD Short Threshold <011> <011> <011> <011>

7 0 1 1 1 Short to Batt VFB3 Short to Batt VFB2 Short to Batt VFB1 Short to Batt VFB0
Voltage Command VTH = 2.0 V VTH = 2.0 V VTH = 2.0 V VTH = 2.0 V

GPGD Short Duration <011> <011> <011> <011>

8 1 0 0 0 Short to Batt tFB3 Short to Batt tFB2 Short to Batt tFB1 Short to Batt tFB0
Timer Command Timer = 240 s Timer = 240 s Timer = 240 s Timer = 240 s

GPGD Fault Operation <1111> <0000>

9 1 0 0 1 Retry/Shutdown Bit X X X X Shutdown Drivers on MAXI
Select Command Retry on Fault Disabled

<00>
PWM0 to PWM3 Freq & <000> <0000000>
PWMx
A 1 0 1 0 PWM Frequency PWM Duty Cycle
DC Command Address
10 Hz 0% Duty Cycle
PWM0

INVALID COMMAND B 1 0 1 1 X X X X X X X X X X X X

INVALID COMMAND C 1 1 0 0 X X X X X X X X X X X X

INVALID COMMAND D 1 1 0 1 X X X X X X X X X X X X

Clock Calibration
E 1 1 1 0 X X X X X X X X X X X X
Command

INVALID COMMAND F 1 1 1 1 X X X X X X X X X X X X

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SPI RESPONSE REGISTERS

Fault reporting is accomplished through the SPI interface. All logic [1]s received by the MCU via the SO pin indicate faults. All logic [0]s
received by the MCU via the SO pin indicate no faults. Timing between two write words must be greater than the fault timer to allow
adequate time to sense and report the proper fault status.

Table 22. SPI Response Messages

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Next SO Response to:

0 0 0 0 1 1 0 1 0 0 0 0 1 0 1 0
SPI Check Command

Next SO Response to
HEX1 to HEX A
Commands and Read IGN3 IGN2 IGN1 IGN0 GP3 GP2 GP1 GP0 OUT3 OUT2 OUT1 OUT0
Reset COR SOR NMF
All Status Command Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault
ALL STATUS
RESPONSE

Next SO Response to
READ REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMMAND

Address <0000>
All Status Register IGN3 IGN2 IGN1 IGN0 GP3 GP2 GP1 GP0 OUT3 OUT2 OUT1 OUT0
Reset COR SOR NMF Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault
0 = No Fault, 1 = Fault
Address <0001> OUT1 OUT1 OUT1 OUT0 OUT0 OUT0
OUT1, OUT0 Fault OUT1 OUT0
Over Low Battery OFF ON Battery OFF ON
Reset COR 0 0 0 0 TLIM TLIM
Register voltage Voltage Fault
Short Open Open
Fault
Short Open Open
0 = No Fault, 1 = Fault Fault Fault Fault Fault Fault Fault

Address <0010> OUT3 OUT3 OUT3 OUT2 OUT2 OUT2

OUT3, OUT2 Fault OUT3 OUT2
Over Low Battery OFF ON Battery OFF ON
Reset COR 0 0 0 0 TLIM TLIM
Register voltage Voltage
Fault
Short Open Open
Fault
Short Open Open
0 = No Fault, 1 = Fault Fault Fault Fault Fault Fault Fault

Address <0011> GP3 GP3 GP2 GP2 GP1 GP1 GP0 GP0
GPGD Mode Fault Over Low Short Open Short Open Short Open Short Open
Reset COR 0 0 0 0
Register voltage Voltage Circuit Load Circuit Load Circuit Load Circuit Load
0 = No Fault, 1 = Fault Fault Fault Fault Fault Fault Fault Fault Fault

Address <0100> IGN3

IGN3 IGN3
IGN2
IGN2 IGN2
IGN1
IGN1 IGN1
IGN0
IGN0 IGN0
IGN Mode Fault Register Reset Over Low Max Open Max Open Max Open Max Open
COR voltage Voltage
MAXI Dwell Second MAXI Dwell Second MAXI Dwell Second MAXI Dwell Second
0 = No Fault, 1 = Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault

Address <0101>
Mode Command Over Low V10 OVR PWM3 PWM2 PWM1 PWM0
Reset COR IGN/GPGD Mode Select X X
voltage Voltage En Vtg EN EN EN EN
Register

Address <0110> OUT3 OUT2 OUT1 OUT0 OUT3 OUT2 OUT1 OUT0
LSD Fault Command Over Low LSD Fault Operation ON ON ON ON OFF OFF OFF OFF
Reset COR voltage Voltage Shutdown,Tlim,Timer X Open Open Open Open Open Open Open Open
Register Load Load Load Load Load Load Load Load

Address <0111>
Drvr ON/OFF Command Over Low
Reset COR X X X X GPGD(21) OUTx Driver(21)
voltage Voltage
Reg

Address <1000> Max Soft Open

Spark Command Over Low Max Dwell Timer Overla Gain Open End Spark
Reset COR Dwell Shut 2ed
voltage Voltage MaxDwell En p Dwell Sel Dn En Secondary Threshold
Register Clmp

Address <1001>
End Spark Filter Over Low End Spark
Reset COR X X X X X X X X X X
voltage Voltage Filter
Register

Address <1010> Over Low

DAC Command Register Reset COR
voltage Voltage
MAXI DAC Threshold Overlap Setting NOMI DAC Threshold

Notes
21. These bits refer to command ON or OFF state in the command registers, not the state of the respective output lines. These bits are not to be
confused with the Ignition mode state which is controlled only by the parallel inputs. Their state is not reflected in these bits.

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 FUNCTIONAL DEVICE OPERATION
MODES OF OPERATION

Table 22. SPI Response Messages (continued)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Next SO Response to:

0 0 0 0 1 1 0 1 0 0 0 0 1 0 1 0
SPI Check Command

Address <1011>
GPGD FBx Short to Over Low
Reset COR Short to Batt VFB3 Short to Batt VFB2 Short to Batt VFB1 Short to Batt VFB0
Battery Threshold voltage Voltage
Voltage Register

Address <1100>
GPGD FBx Short to Over Low
Reset COR Short to Batt tFB3 Short to Batt tFB2 Short to Batt tFB1 Short to Batt tFB0
Battery Threshold Timer voltage Voltage
Register

Address <1101>
GPGD Fault Operation Over Low
Reset COR Retry/Shutdown Bit X X X X Shutdown Drivers on MAXI
voltage Voltage
Register

Address <1110>
PWM Freq&DC Register Over Low PWMx
Reset COR PWM Frequency PWM Duty Cycle
(last channel voltage Voltage Address
programmed)

Address <1111> CAL CAL TRIM TRIM

Revision ID, Trim, Clock Over Low
Reset COR voltage Voltage 3 REV 2 ID 1 0 X X Too Too X X Parity Lock
Cal. HI LOW Error Out

Legend
COR = Command Out of Range
SOR = Supply Out of Range
NMF = Set When Faults Occur on V10 Mode MAXI and NOMI Inputs and V10 Mode Ignition Driver are OFF.

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 PACKAGING
PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

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 PACKAGING
PACKAGE DIMENSIONS

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PACKAGING
PACKAGE DIMENSIONS

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38 Freescale Semiconductor
 REVISION HISTORY
PACKAGE DIMENSIONS

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

3.0 10/2007 • Initial Release

• Fixed several typos throughout document
• Changed Static Electrical Characteristics, Table 3, Digital Interface, OUTEN Leakage Current to VDD, maximum from
10 to 50 A.
4.0 2/2008
• Reworded Table 15.
• Added Table 16 back (it was inadvertently deleted.
• Added “Ignition &” to tile in Table 4.
5.0 8/2008 • Updated package drawing.
• Parameter changes to Gate Drive Source Current, Spark Duration Comparator Threshold, NOMI Trip Threshold Ac-
curacy, MAXI Trip Point During Overlapping Dwell, Comparator Hysteresis Voltage, Short to Battery Fault Detection
Voltage Threshold, Output OFF Open Load Detection Current, and Input Logic-voltage Hysteresis.
6.0 12/2008 • Made change to End of Spark Filter Time Select
• Changed orderable Part Number from PCZ33810EK/R2 to MCZ33810EK/R2 on Page 1.
• Revised Exposed Pad pin definition in Table 1, page 3.
• Changed Package outline drawing to 98ASA10556D.
• Changed introduction paragraph to Tables 3 and 4 from “9.0 V  VPWR  18 V” to “6.0 V  VPWR  32 V”
7.0 7/2010
• Changed Gate Driver Parameters of V GS (ON) from 5.0 to 4.8.

8.0 7/2010 • Changed Table 3 Characteristics from 18 V to 32 V for: IVPWR(SS), I(OFF)OCO and IFBX(FLT-SNS)

9.0 2/2011 • Changed See Output OFF Open Load Detection Current on page 7 from 100 A to 115 A for the maximum value.
• Corrected Table 14, End of Spark Filter Time Select.
4/2011
• Corrected Table 21, SPI Command Message Set and Default State (Command: End Spark Filter).
10.0
• No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to first para-
4/2013
graph.
• Updated format and back page
• Added Ordering Information section
11.0 8/2014 • Substituted general purpose gate driver/pre-driver with GPGD throughout the document.
• Corrected End Spark Filter SPI response register address (1001, not 0101)
• Corrected hex to binary conversion (C is 1100, not 1001)

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Freescale Semiconductor 39
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Document Number: MC33810

Rev. 11.0
8/2014