HTMOSTM High Temperature Products Preliminary

HIGH TEMPERATURE 83C51 HT83C51

MICROCONTROLLER
FEATURES
• HTMOS Specified Over -55 to +225°C • Hermetic 40-Pin Ceramic DIP

• 8-bit CPU Optimized For 5 Volt Control Applications • 64K External Data Memory Address Space

• Four 8-bit Bidirectional Parallel Ports • 256 Bytes Internal Data Memory

• Three 16-bit Timer/Counters with One Up/Down • 8K Byte Mask ROM

Timer/Counter and Clock Out
• On-Chip Oscillator
• Programmable Counter Array with:
• MCS-51Compatible Instruction Set
– Capture/Compare
– Software Timer with Watchdog Capability
– High Speed Output APPLICATIONS
– Pulse Width Modulator
• Down-Hole Oil Well
• Interrupt Structure with Seven Sources and
• Avionics
Four Priority Levels
• Turbine Engine Control
• Half Duplex Programmable Serial Port with:
– Framing Error Detection • Industrial Process Control
– Automatic Address Recognition
• Nuclear Reactor
• 64K External Program Memory Address Space
• Electric Power Conversion

• Heavy Duty Internal Combustion Engines

GENERAL DESCRIPTION

The HT83C51 is a monolithic 8-bit microcontroller that is and a hierarchical interrupt structure. Software selectable
pin equivalent to the Intel 8XC51FC microcontroller. Fab- idle is included for reduced power. The HT83C51 varies
ricated with Honeywell’s dielectrically isolated high-tem- from the standard 83C51FC, in that it supports half-duplex
perature (HTMOS™) process, it is designed specifically for serial communication, and has 8K Bytes of Mask program-
severe high-temperature applications such as down-hole mable ROM. The device is available in a standard pinout
oil well, aerospace, turbine engine and industrial control. DIP, with optional packages considered.

The HT83C51 uses the standard MCS-51 instruction set These microcontrollers provide guaranteed performance
which is optimized for control applications. Pin-for-pin supporting operating frequencies in excess of 16 MHz
equivalent to the MCS-51 series product, it is compatible over the full -55 to +225°C temperature range. Typically,
with all known development environments. Key features parts will operate up to +300°C for a year, with derated
include the programmable counter array, watch dog timer, performance. All parts are burned in at 250°C to eliminate
enhanced serial port for multi-processor communication infant mortality.

Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.ssec.honeywell.com
HT83C51
FUNCTIONAL BLOCK DIAGRAM

P0.0 - P0.7 P2.0 - P2.7

Port O Port 2
Drivers Drivers

RAM Addr.
Register
Port O Port 2 Program
RAM
Latch Latch ROM

Program
Address
Register
BB ACC Stack
Register
Register Pointer
Buffer
TMP2 TMP1

Special Function PC
ALU Registers, Incrementer
Timers,
PCA, Program
PSW TMP3 Serial Port Counter
Instruction

DPTR
sequencer

PSENn
Register
Micro-

ALE
EAn
Port 1 Port 3
RST Latch
Latch

Osc.
Port 1 Port 3
Drivers Drivers

XTAL1 XTAL2

P1.0 - P1.7 P3.0 - P3.7

2
 HT83C51
PIN DESCRIPTIONS
VDD: +5V Supply Voltage loads. When the Port 3 pins have 1’s written to them, they
are pulled high by the internal pullups and can be used as
VSS: Circuit Ground inputs in this state. As inputs, any pins that are externally
pulled low will source current because of the pullups. In
Port 0 (P0.0 - P0.7): Port 0 is an 8-bit bidirectional I/O port. addition, Port 3 pins have the alternate uses shown in the
If external Program and/or Data memory are used, port 0 table below:
cannot be used for general purpose I/O. During accesses
to external Program and Data memory Port 0 is used as the Port Pin Alternate Name Alternate Function
low-order multiplexed address and data bus. In this mode,
Port 0 pins use strong internal pullups when emitting 1’s, P3.0 RXD Serial port input
and are TTL compatible. If external Program and Data P3.1 TXD Serial port output
memory are not used, Port 0 pins can be used as general P3.2 INT0n External interrupt 0
purpose I/O. When the Port pins have 1’s written to them
P3.3 INT1n External interrupt 1
in I/O mode, the pins are floating and can be driven as
inputs. An external pullup is required to generate logic high P3.4 T0 External clock input for Timer 0
output in I/O mode. P3.5 T1 External clock input for Timer 1
P3.6 WRn External Data Memory write strobe
Port 1 (P1.0 - P1.7): Port 1 is an 8-bit bidirectional I/O port
with internal pullups. The output buffers can drive TTL P3.7 RDn External Data Memory read strobe
loads. When the Port 1 pins have 1’s written to them, they
are pulled high by the internal pullups and can be used as RST: Reset input. A high on this input for 2 or more
inputs in this state. As inputs, any pins that are externally oscillator periods while the oscillator is running resets the
pulled low will source current because of the pullups. In device. All ports and Special Function Registers will be
addition, Port 1 pins have the alternate uses shown in the reset to their default conditions. Internal data memory is
table below: undefined after reset. Program execution will begin within
12 oscillator periods (one machine cycle) after the RST
Port
Alternate Function
signal is brought low. RST contains an internal pulldown
Pin Name resistor to allow implementing power-up reset with only an
P1.0 T2 External clock input to timer/ Clock out external capacitor.
Timer/Counter 2 Capture/Reload trigger and
P1.1 T2EX ALE: Address Latch Enable. The ALE output is a pulse for
direction control

P1.2 ECI External count input to PCA

latching the low byte of the address during accesses to
external memory. In normal operation the ALE pulse is
P1.3 CEX0 External I/O for PCA capture/compare Module 0
output every 6th oscillator cycle and may be used for
P1.4 CEX1 External I/O for PCA capture/compare Module 1 external timing or clocking. However, during each access
P1.5 CEX2 External I/O for PCA capture/compare Module 2 to external Data Memory (MOVX instruction), one ALE
P1.6 CEX3 External I/O for PCA capture/compare Module 3 pulse is skipped. If desired, ALE operation can be disabled
by setting bit 0 of SFR 8EH. When this bit is set, ALE is
P1.7 CEX4 External I/O for PCA capture/compare Module 4
active only during a MOVX instruction. Otherwise, the pin
is held low. When ALE is disabled, program execution
Port 2 (P2.0 - P2.7): Port 2 is an 8-bit bidirectional I/O port must be limited to the internal 8K program ROM.
with internal pullups. The output buffers can drive TTL
loads. When the Port 2 pins have 1’s written to them, they PSENn: Program Store Enable. This active low signal is
are pulled high by the internal pullups and can be used as the read strobe to the external program memory. PSENn
inputs in this state. As inputs, any pins that are externally is activated every 6th oscillator cycle except that 2 PSENn
pulled low will source current because of the pullups. activations are skipped during external data memory
accesses.
Port 2 is used as the high-order address byte during
accesses to external Program Memory and during accesses EAn: External Access Enable. The EAn pin must be
to external Data Memory that use 16-bit addresses (i.e. strapped to VSS for the HT51 to fetch code from external
MOVX @DPTR). It uses strong internal pullups when Program Memory locations 0000H to 1FFFH. The EAn pin
emitting 1’s in this mode. During accesses to external Data must be strapped to VDD for internal program execution
Memory that use 8 bit addresses, Port 2 emits the contents from memory locations 0000H to 1FFFH.
of the P2 SFR.
XTAL1: Input to the inverting oscillator amplifier.
Port 3 (P3.0 - P3.7): Port 3 is an 8-bit bidirectional I/O port
with internal pullups. The output buffers can drive TTL XTAL2: Output from the inverting oscillator amplifier.

3
HT83C51
OSCILLATOR CHARACTERISTICS

The input is XTAL1 and the output is XTAL2 for an inverting The other way that Idle mode can be terminated is through
amplifier which can be used as an on-chip oscillator as a hardware reset, which can be accomplished by holding
shown in Figure 1. Make sure to qualify the crystal or the RST pin high for 4 clock periods while the clock is
alternate timing source over the temperature range of the running. Exiting Idle mode with a hardware reset will retain
intended application. If an external clock source such as the contents of the on-chip RAM but the values in the SFRs
the HTOSC is used, XTAL1 should be driven while XTAL2 will be lost and program execution will begin at address 0.
floats as shown in Figure 2. There are no duty cycle
requirements on the external clock signal, but minimum
and maximum high and low times must be observed. MEMORY
C2 The HT51 has a separate address space for Program and
XTAL 2 Data Memory. Internally the HT51 contains 8 Kbytes of
Program Memory and 256 bytes of Data Memory. It can
C1 address up to 64 Kbytes of external Data Memory and 64
XTAL 1 Kbytes of external Program Memory.
Vss
There are 8 Kbytes of internal program memory in the
HT51. The EAn pin must be tied to Vdd (power) to enable
For C1 and C2 values,
contact crystal manufacturer
access to internal program memory locations. When the
EAn pin is tied to Vdd, program fetches to addresses
Figure 1. Oscillator Connections 0000H to 1FFFH will be made to internal program ROM.
Program fetches to addresses 2000H through FFFFH are
to external memory. The EAn pin must be tied to Vss
(ground) to enable access to external program memory
locations 0000H through 1FFFH.
N/C XTAL 2
The HT51 implements 256 bytes of internal data RAM. The
External upper 128 bytes of this RAM occupy a parallel address
Oscillator XTAL 1 space to the Special Function Registers (SFRs). The CPU
Signal
Vss determines if the internal access to an address above 7FH
is to the upper 128 bytes of RAM or to the SFR space by the
addressing mode of the instruction. If direct addressing is
used, the access is to the SFR space. If indirect addressing
Figure 2. External Clock Drive Configuration is used, the access is to the internal RAM. Stack operations
are indirectly addressed so the upper portion of RAM can
be used as stack space.
IDLE MODE

An instruction that sets the PCON.0-bit causes that to be TIMER/COUNTERS

the last instruction executed prior to going into Idle
mode. In the Idle mode, the internal clock to the CPU is The HT51 contains three 16-bit timer/counters. Each of
gated off but not to the Interrupt, Timer, and Serial Port these are made up of two 8-bit registers (THx, TLx where
functions. The PCA can be programmed to either pause x = 0, 1, or 2). Each of these three can operate in either
or continue operating during Idle Mode. The CPU status timer or counter mode. In the timer mode, the TLx register
is completely preserved and all registers maintain their is incremented once every machine cycle (12 oscillator
previous values during Idle Mode. The port pins hold the periods). The count rate is 1/12th of the oscillator frequency.
logical values that they had at the time the Idle mode In counter mode, the register is incremented when a 1 to 0
was activated. ALE and PSENn hold at logic high levels. transition is detected on the alternate function input
corresponding to that timer (Tx where x = 0, 1, or 2). The
Idle mode can be terminated in two ways. Activation of any maximum rate of count in counter mode that the HT51 can
enabled interrupt will cause the PCON.0-bit to be cleared detect is 1/24th of the oscillator frequency.
by hardware, terminating Idle mode. The interrupt will be
serviced, and following the RETI instruction execution, the
instruction after the one that caused Idle mode will be
executed. Recovery from Idle mode is 3 oscillator periods
plus 3 instruction cycles.

4
 HT83C51
PCA COUNTER /TIMER

The Programmable Counter Array (PCA) contains a single will be made immediately after the RST line is brought low,
16-bit counter/timer made up of the CL and CH registers. but the data is not brought into the processor. The memory
This timer is used by all 5 capture/compare modules. Its access will be repeated on the next machine cycle and
clock input can be programmed to be from one of four actual processing will begin at that time.
sources. These are the oscillator frequency divided by 12,
the oscillator frequency divided by 4, Timer 0 overflow, and INSTRUCTION SET
an external clock input, ECI, on the alternate function of
port pin P1.2. The instruction set for the HT51 is compatible to the Intel
MCS-51 instruction set used on the 8XC51FC.
SERIAL PORT
AC CHARACTERISTICS
The serial port has physically separate receive and transmit
buffers, automatic address recognition and four modes of The AC characteristics for the HT51 are shown in the
operation as shown below. following tables. Each of the timing symbols has 5 charac-
ters. The first character is always a ‘T’ (Time). The other
Mode Description Baud Rate characters, depending on their positions, stand for the
0 8-bit shift register 1/12 times oscillator freq. logical name of a signal or the logical status of that signal.
1 8-bit UART variable The following is a list of the characters and what they stand for:
2 9-bit UART 1/64 or 1/32 times oscillator freq.
3 9-bit UART variable A: Address Q: OutputData
C: Clock R: RDn signal
D: Data T: Time
INTERRUPTS H: Logic level HIGH V: Valid
There are seven interrupt sources in the HT51. Two are I: Instruction W: WRn signal
external interrupts (INT0n, INT1n), three are timer interrupts (program memory contents) X: No longer a
(Timer 0, Timer 1, and Timer2), one is a PCA interrupt, and L: Logic level LOW, or ALE valid logic
one is a serial port interrupt as shown below. level
P: PSENn Z: Float
PCA interrupt enable
Timer 2 interrupt enable For example, TAVLL = Time from address valid to ALE
Serial port interrupt enable low. The characteristics given are over the operating
conditions TA = -55°C to +225°C, VDD = 5V ± 10 %, VSS = 0V.
Timer 1 interrupt enable The load capacitance on Port 0, ALE and PSENn = 100
External interrupt 1 enable pF. Load capacitance for all other outputs = 50 pF. Inputs
during AC testing are to be driven at VDD - 0.5V for logic 1
Timer 0 interrupt enable
and 0.45 V for logic 0. Timing measurements are to be
External interrupt 0 enable made at VIH min for logic 1 and VIL max for logic 0. For
timing purposes, a port pin is no longer floating when a 100
RESET mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOL/VOH level
The reset input is the RST pin. A reset is accomplished by
occurs. Timing diagrams are shown to illustrate the signal
holding the RST pin high for a minimum of 4 clock periods
relationships depicted in the tables.
while the clock is running. The CPU generates an internal
reset from the external signal. The port pins are driven to
the reset state 2 oscillator periods after a valid 1 is detected
on the RST pin.

While RST is high, PSENn is pulled high, ALE is pulled low,

and the port pins are pulled weakly high. All SFRs are reset
to their reset values. The internal Data Memory content is
not affected by reset. In addition, if the HT51 is in Idle or
Power Down mode prior to activation of RST, the HT51 will
be taken out of Idle or Power Down mode by the reset.

The processor will begin operation on the second machine

cycle after the RST line is brought low. A memory access

5
HT83C51
DC CHARACTERISTICS

Symbol Parameter Min Max Unit Test Conditions (3)

VIL Input Low Voltage VSS-0.3 0.8
VIH Input High Voltage (except XTAL1, RST) 2.0 VDD+0.5 V
VIH1 Input High Voltage (XTAL1, RST) 3.85 VDD+0.5 V
0.3 V IOL = 100 µA
VOL Output Low Voltage (1, 2)
(Ports 1, 2, and 3) 0.45 V IOL = 1.6 mA
1.0 V IOL = 3.5 mA
0.3 V IOL = 200 µA
VOL1 Output Low Voltage (1, 2)
(Port 0, ALE, PSENn) 0.45 V IOL = 3.2 mA
1.0 V IOL = 7.0 mA
4.2 V IOH = -10 µA
VOH Output High Voltage
(Port 1, 2, 3, ALE, PSENn) 3.8 V IOH = -30 µA
3.0 V IOH = -60 µA
4.2 V IOH = -200 µA
VOH1 Output High Voltage (Port 0)
3.8 V IOH = -3.2 mA
3.0 V IOH = -7.0 mA
IIL Logical 0 Input Current(Ports 1, 2, and 3) -50 µA VIN = 0.45 V
I LI Input Leakage Current (Port 0) ±10 µA 0.45 V < Vin < VDD
ITL Logical 1 to 0 Transition Current(Ports 1, 2, and 3) -650 µA VIN = 2 V
RRST RST Pulldown Resistor 10 225 KW
CIO Pin Capacitance 10 typical pF @ 1 MHz, 25° C
Power Supply Current Operating 70 mA 16 MHz
IDD
Idle 15 mA 16 MHz

(1) Under steady state (non-transient conditions, IOL must be limited externally as follows:
maximum IOL per port pin 10mA
maximum IOL per 8-bit port
– port 0 26 mA
– port 1,2,3 15 mA
maximum total IOL for all output pins 71 mA
(2) If IOL exceeds the test conditions, VOL may exceed the related specifications.
(3) Pins are not guaranteed to sink current greater than the listed test conditions.

ABSOLUTE MAXIMUM RATINGS (1)

Input Voltage, VDD to VSS ......................... -0.5 V to 7.0 V
Voltage On Any Pin to VSS ............... -0.5 V to VDD+0.3 V
Power Dissipation ............................................. 750 mW
Storage Temperature ............................... -65 to +325°C
Lead Temperature (attachment, 10 sec) .............. 355°C
IOL per Output Pin ............................................... 15 mA
Stresses in excess of those listed above may result in permanent damage. These
are stress ratings only, and operation at these levels is not implied. Frequent or
extended exposure to absolute maximum conditions may effect device reliability.

6
 HT83C51
EXTERNAL PROGRAM AND DATA MEMORY CHARATERISTICS
Symbol Parameter Min Max Unit
TCLCL Clock Period 62.5 ns
1/TCLCL Oscillator Frequency 16 MHz

TLHLL ALE Pulse Width 2 TCLCL-40 ns

TAVLL Address Valid to ALE Low TCLCL-40 ns
TLLAX Address hold after ALE low TCLCL-30 ns

TLLIV ALE low to Valid Instruction In 4 TCLCL-100 ns

TLLPL ALE Low to PSENn Low TCLCL-30 ns
TPLPH PSENn Pulse Width 3 TCLCL-45 ns
TPLIV PSENn low to Valid Instruction In 3 TCLCL-105 ns

TPXIX Input Instruction hold after PSENn 0 ns

TPXIZ Input Instruction Float After PSENn TCLCL-25 ns
TAVIV Address to Valid Instruction In 5 TCLCL-105 ns

TPLAZ PSENn Low to Address Float 10 ns

TRLRH RDn Pulse Width 6 TCLCL-100 ns
TWLWH WRn Pulse Width 6 TCLCL-100 ns
TRLDV RDn Low to Valid Data In 5 TCLCL-165 ns

TRHDX Data Hold After RDn 0 ns

TRHDZ Data Float After RDn 2 TCLCL-60 ns
TLLDV ALE Low to Valid Data In 8 TCLCL-150 ns

TAVDV Address to Valid Data In 9 TCLCL-165 ns

TLLWL ALE Low to RDn or WRn Low 3 TCLCL-50 3 TCLCL+50 ns
TAVWL Address Valid to WRn Low 4 TCLCL-130 ns
TQVWX Data Valid Before WRn TCLCL-50 ns

TWHQX Data Hold After WRn TCLCL-50 ns

TQVWH Data Valid to WRn High 7 TCLCL-150 ns
TRLAZ RDn Low to Address Float 0 ns
TWHLH RDn or WRn High to ALE High TCLCL-40 TCLCL+40 ns

7
HT83C51
EXTERNAL PROGRAM MEMORY READ CYCLE

TLHLL

ALE
TLLPL TPLPH
TAVLL TLLIV

TPLIV
PSENn

TPLAZ TPXIZ
TPXIX
TLLAX

PORT 0 A0 - A7 INSTR IN A0 - A7
TAVIV

PORT 2 A8 - A15 A8 - A15

EXTERNAL DATA MEMORY READ CYCLE

ALE
TLHLL

TWHLH

PSENn
TLLDV

TLLWL TRLRH

RDn
TRLDV
TAVLL TRHDX
TLLAX TRLAZ
TRHDZ
PORT 0 A0 - A7 from RI or DPL DATA IN A0 - A7 from PCL INSTR. IN

TAVWL
TAVDV

PORT 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH

EXTERNAL DATA MEMORY WRITE CYCLE

ALE
TLHLL

TWHLH

PSENn

TLLWL TWLWH

WRn
TAVLL

TQVWX TWHQX
TLLAX
TQVWH

PORT 0 A0 - A7 from RI or DPL DATA OUT A0 - A7 from PCL INSTR. IN

TAVWL

PORT 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH

8
 HT83C51
SERIAL PORT TIMING CHARACTERISTICS—SHIFT REGISTER MODE (MODE 0)
16 MHz Oscillator Variable Oscillator
Symbol Parameter Unit
Min Max Min Max
TXLXL Serial Port Clock Period 750 12 TCLCL ns
TQVXH Output Data Setup to Clock Rising Edge 492 10 TCLCL-133 ns
TXHQX Output Data Hold after Clock Rising Edge 8 2 TCLCL-117 ns
TXHDX Input Data Hold after Clock Rising Edge 0 0 ns
TXHDV Clock Rising Edge to Input Data Valid 492 10 TCLCL-133 ns

SERIAL PORT TIMING WAVEFORMS

0 1 2 3 4 5 6 7 8

ALE

TXLXL

CLOCK

TXHQX
TQVXH

OUTPUT 0 1 2 3 4 5 6 7
DATA
(WRITE TO SBUF) TXHDX
TXHDV SET TI
INPUT
VALID VALID VALID VALID VALID VALID VALID VALID
DATA
(CLEAR RI)

SET RI

9
HT83C51
PERFORMANCE CURVES OVER TEMPERATURE

40 5.0

4.8

4.6
30
4.4

Output Voltage (V)

Frequency (MHz)

4.2
6µA
20 4.0

3.8
7mA
3.6
10
3.4

3.2

0 3.0
-100 0 100 200 300 -100 0 100 200 300
Temperature (C)
Temperature (°C)

Maximum frequency vs. temperature Output drive vs. temperature

70

-55°C
60
25°C

125°C
Operating Current (mA)

50
225°C

40

30

20

10
0 5 10 15 20 25

Frequency (MHz)

Operating current vs. frequency vs. temperature

10
 HT83C51
PROGRAMMING THE MASK ROM

The HT83C51 has 8K bytes of on-chip mask program- 5. DC Characteristics

mable ROM. The part is usable with or without this memory
space personalised. Once the designer’s code has been VIL min for the 8XC51FC is -0.5V for all inputs except EAn
finalized, the ROM information can be transmitted to Hon- which has a VIL min of 0V. The HT51 has a VIL min for all
eywell for metal programming of these memory locations. inputs of Vss-0.3V.
A non-recurring fee is required to personalize the ROM and
a quantity purchase commitment fulfilled. 6. Internal Program Memory

The 8XC51FC contains 32 Kbytes of internal program

DIFFERENCES BETWEEN
ROM (83C51FC) or EPROM (87C51FC). The HT51
INTEL 8XC51FC AND HT83C51 contains 8 Kbytes of internal program ROM.

There are a few areas in which the HT51 differs from the 7. Serial Communications
8XC51FC. These differences will be covered in this
appendix. In this discussion, 8XC51FC will be used There is a chance the part will miss hardware interrupts
generically to refer to all speed grades of the Intel 8XC51FC when performing full-duplex (simultaneous send and
family, including the 16MHz 8XC51FC-1. receive) communication or when using the capture or
compare modes in the Programmable Counter Array (PCA).
1. Reset

The 8XC51FC requires the RST input to be held high for at As a result, the HT83C51 supports half-duplex operation.
least 24 oscillator periods to guarantee the reset is completed Full duplex operation is not supported without additional
in the chip. Also, the port pins are reset asynchronously as external hardware. Several acceptable work-around pro-
soon as the RST pin is pulled high. On the HT51, all portions cedures have been identified for the problem associated
of the chip are reset synchronously when the RST pin has with the PCA.
been high during 2 rising edges of the input clock.

When coming out of reset, the 8XC51FC takes 1 to 2

machine cycles to begin driving ALE and PSENn. The PINOUT DIAGRAM
HT51 will begin driving ALE and PSENn 2 oscillator periods
after the RST is removed but the access during the first
machine cycle after reset is ignored by the processor. The
second cycle will repeat the access and processing will (T2) P1.0 1 40 Vdd
begin. 2 39
(T2EX) P1.1 P0.0 (AD0)

(ECI) P1.2 3 38 P0.1 (AD1)

2. Power Off Flag
(CEXO) P1.3 4 37 P0.2 (AD2)

(CEX1) P1.4 5 36 P0.3 (AD3)

The Power Off Flag in the PCON register has not been
(CEX2) P1.5 6 35 P0.4 (AD4)
implemented in the HT51.
(CEX3) P1.6 7 34 P0.5 (AD5)

3. On Circuit Emulation (CEX4) P1.7 8 33 P0.6 (AD6)

RST 9 32 P0.7 (AD7)

The On Circuit Emulation mode of operation in the 8XC51FC (RXD) P3.0 10 31 EAn
HT51
has not been implemented in the HT51. (TXD) P3.1 11 30 ALE

(INT0n) P3.2 12 29 PSENn

`4. Operating Conditions (INT1n) P3.3 13 28 P2.7 (A15)

(T0) P3.4 14 27 P2.6 (A14)

The operating voltage range for the 8XC51FC is 5V ± 20%. (T1) P3.5 15 26 P2.5 (A13)
The operating temperature range is 0° to 70°C. On the (WRn) P3.6 16 25 P2.4 (A12)
HT51, the operating voltage range is 5V ± 10%. The full 17 24
(RDn) P3.7 P2.3 (A11)
speed operating temperature range is -55° to +225°C; 18
XTAL2 23 P2.2 (A10)
typically, parts will operate up to +300°C for a year, with
XTAL1 19 22 P2.1 (A9)
derated performance.
Vss 20 21 P2.0 (A8)

11
HT83C51
40-LEAD PACKAGE DETAIL
C
D
All dimensions in inches
A 0.175 (max)
Right b 0.018 ± 0.002
Reading E eA
b2 0.050 typ
on Lid C 0.010 ± 0.002
D 2.000 ±0.020
E 0.594 ± 0.010
Ceramic 1 e 0.100 ±0.005
Body Kovar eA 0.600 ± 0.010
Lid [3] S2
L 0.125 to 0.175
Q 0.050 ± 0.010
A Q S1 0.005 (min)
S2 0.005 (min)
L
S1
b2
b e
(width) (pitch)

THERMAL CHARACTERISTICS
Assumes static air convection

θjc ................................... 0.9°C/W

θja .................................. 32.8°C/W

ORDERING INFORMATION
HT83C51DC

D - Indicates package type* C - Indicates screening level

D = Standard DIP B = High Temperature Class B
C = Commercial
*For packaging options, call Honeywell

To learn more about Honeywell Solid State Electronics Center,

visit our web site at http://www.ssec.honeywell.com

Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

900141 Rev. B
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