Hu_ch05v3.

fm Page 186 Friday, February 13, 2009 2:38 PM

186 Chapter 5 ● MOS Capacitor

N-type device P-type device

(N+ -gate over P-substrate) (P+ -gate over N-substrate)

QS C–V
Transistor C–V

Capacitor
HF C–V

Vg Vg

FIGURE 5–34 N-type and P-type MOS capacitors.

The number 3 is the ratio of silicon permittivity (11.9) to SiO2 permittivity (3.9).
Toxe is usually determined from the inversion-region capacitance measured at
Vg = Vdd. Quantization of states in the inversion layer causes the threshold voltage
to increase beyond the prediction of the basic threshold voltage theory.
A CCD (charge−coupled device) is an imaging device based on an array of
MOS capacitors operating under the deep-depletion condition, starved of
inversion charge. Photo-generated carriers are collected in the surface potential
wells, and the collected charge packets are transferred in a serial manner to the
charge-sensing circuit located at the edge of the array. CCD imagers have been
replaced by CMOS imagers where cost, size, and power consumption are more
important than the best image quality. CMOS imagers integrate a charge-to-
voltage conversion circuit in each sensing array element. In both types of imagers,
color sensing is achieved with separate sensing elements for red, green, and blue
in each pixel.

● PROBLEMS ●

● Energy Band Diagram ●

5.1 Sketch the energy band diagrams of an MOS capacitor with N-type silicon substrate
and N+ poly-Si gate at flatband, in accumulation, in depletion, at threshold, and in
inversion.

5.2 Sketch the energy band diagrams (i) at thermal equilibrium and (ii) at flat band for the
following MOS systems. Use a work function value that you find from any source.
(a) Tungsten, W, gate with 1 Ωcm N-type silicon substrate.
(b) Tungsten, W, gate with 1 Ωcm P-type silicon substrate.
(c) Heavily doped P+ polycrystalline silicon gate with 1 Ωcm N-type silicon substrate.
(d) Heavily doped N+-polycrystalline silicon gate with 1 Ωcm P-type silicon substrate.
Hu_ch05v3.fm Page 187 Friday, February 13, 2009 2:38 PM

Problems 187

● MOS System: Inversion, Threshold, Depletion, and Accumulation ●

5.3 The body of an MOS capacitor is N type. Match the “charge” diagrams (1) through (5) in
Fig. 5–35 to (a) flat band, (b) accumulation, (c) depletion, (d) threshold, and (e) inversion.

MOS System
Gate Substrate Gate Substrate Gate Substrate

Q Q

x x x
Q Q
Ionized donors
Electrons

(1) (2) (3)

Gate Substrate Gate Substrate

Q Q
x x
Q Q
Ionized Ionized
Holes Holes
donors donors

(4) (5)
FIGURE 5–35

5.4 Consider an ideal MOS capacitor fabricated on a P-type silicon with a doping of
Na = 5 × 1016cm–3 with an oxide thickness of 2 nm and an N+ poly-gate.
(a) What is the flat-band voltage, Vfb, of this capacitor?
(b) Calculate the maximum depletion region width, Wdmax.
(c) Find the threshold voltage, Vt, of this device.
(d) If the gate is changed to P+ poly, what would the threshold voltage be now?
5.5 Figure 5–36 shows the total charge per unit area in the P-type Si as a function of Vg for
an MOS capacitor at 300 K.
(a) What is the oxide thickness?
(b) What is the doping concentration in Si?
(c) Find the voltage drop in oxide (Vox) when Vg – Vfb = –1 V.
(d) Find the band bending in Si when Vg – Vfb = 0.5 V.
5.6 Make a series of qualitative sketches paralleling Figs. 5–11 to 5–14 (φs, Wdep, and
charge as function of Vg) for an MOS capacitor having an N-type substrate and P+poly
gate. (Hint: At Vg = Vt, φs is negative. You may assume that Vt is negative.)
5.7 (a) Solve Eq. (5.3.1) for φs as a function of Vg.
(b) Find an expression for Vox as a function of Vg.
(c) Make a rough sketch of φs vs. Vg and Vox vs. Vg for –3 V < Vg < 2 V, Vfb = –0.9 V,
Na = 1017cm–3, and Tox = 3 nm.
(d) Find Wdep as a function of Vg.
Hu_ch05v3.fm Page 188 Friday, February 13, 2009 2:38 PM

188 Chapter 5 ● MOS Capacitor

Qs(coul/cm2)
4  107

1 2
Vg Vfb(V)
1
5  108

4.5  107

FIGURE 5–36
5.8 Consider an MOS capacitor fabricated on P-type Si substrate with a doping of
5 × 1016 cm–3 with oxide thickness of 10nm and N+ poly-gate.
(a) Find Cox, Vfb, and Vt.
(b) Find the accumulation charge (C/cm2) at Vg = Vfb –1 V.
(c) Find the depletion and inversion charge at Vg = 2 V.
(d) Plot the total substrate charge as a function of Vg for Vg from –2 to 2 V.

5.9 If we decrease the substrate doping concentration, how will the following parameters
be affected? (Please indicate your answer by putting a mark, X, in the correct
column.) Write down any relevant equation and explain briefly how you obtain the
answer (a few words or one sentence). Assume the gate material is N+poly and the
body is P type.

Parameters Increase Decrease Unchanged

A Accumulation region capacitance
B Flat-band voltage, Vfb
C Depletion-region capacitance
D Threshold voltage, Vt
E Inversion region capacitance

5.10 From the high-frequency C–V measurements on an MOS capacitor with P-Si substrate
performed at 300 K, the following characteristics were deduced:

Oxide thickness = 30 nm
Substrate doping = 1016 cm–3
Flat-band voltage = –2 V

Construct the C–V curve, labeling everything, including the values of the oxide
capacitance, flat-band voltage, and threshold voltage. Assuming an Al gate with 4.1 V
work function, compute the effective oxide charge.
Hu_ch05v3.fm Page 189 Friday, February 13, 2009 2:38 PM

Problems 189

● Field Threshold Voltage ●

5.11 Metal interconnect lines in IC circuits form parasitic MOS capacitors as illustrated in
Fig. 5–37. Generally, one wants to prevent the underlying Si substrate from becoming
inverted. Otherwise, parasitic transistors may be formed and create undesirable current
paths between the N+ diffusions.

Al interconnect (qcg
4.1 eV)

Insulating layer

P-sub, Na
1015cm3

FIGURE 5–37

(a) Find Vfb of this parasitic MOS capacitor.

(b) If the interconnect voltage can be as high as 5 V, what is the maximum capacitance
(F/cm2) of the insulating layer that can be tolerated without forming an inversion
layer?
(c) If the insulating layer thickness must be 1 µm for fabrication considerations, what
should the dielectric constant K = ε/ε0 of the insulating material be to make
Vt = 5 V?
(d) Is the answer in (c) the minimum or maximum allowable K to prevent inversion?
(e) At Vg = Vt + 2 V (Vt = 5 V), what is the area charge density (C/cm2) in the
inversion layer?
(f) At Vg = Vt = 5 V, what is the high-frequency MOS capacitance (F/cm2)?
(g) At Vg = Vt + 2 V (Vt = 5 V), what voltage is dropped across the insulating layer?

● Oxide Charge ●

5.12 Consider the C–V curve of an MOS capacitor in Fig. 5–38 (the solid line). The capacitor
area is 6,400 µm2. C0 = 45 pF and C1 = 5.6 pF.

Cox

C1

Vg
V
FIGURE 5–38
Hu_ch05v3.fm Page 190 Friday, February 13, 2009 2:38 PM

190 Chapter 5 ● MOS Capacitor

If, due to the oxide fixed charge, the C–V curve is shifted from the solid line to the
dashed line with ∆V = 0.05 V, what is the charge polarity and the area density (C/cm2 )
of the oxide fixed charge?
5.13 Why is oxide charge undesirable? How do mobile charges get introduced into the
oxide? How can this problem be overcome?

● C–V Characteristics ●

5.14 Derive C(Vg) in Eq. (5.6.4). [Hint: Solve Eq. (5.3.3) for Wdep.]
5.15 Answer the following questions based on the C–V curve for an MOS capacitor shown
in Fig. 5–39. The area of the capacitor is 104 µm2.

C(pF)

A E
QS C–V

C D
B HF C–V

Vg(V)
1 0 0.5 1
FIGURE 5–39

(a) Is the substrate doping N type or P type?

(b) What is the thickness of the oxide in the MOS capacitor?
(c) What is the doping concentration of the substrate, Nsub?
(d) What is the value of the capacitance at position C on the C–V curve shown above?
(e) Sketch the energy band diagram of the MOS structure at positions A, B, C, D, and
E on the C–V curve.
(f) At location B on the C–V curve, what is the band bending, φs?
5.16 The C–V characteristics of MOS capacitors A (solid line) and B (dashed line), both
having the same area, are shown in Fig. 5–40.

C
A

Vg

FIGURE 5–40

(a) Are the substrate P type or N type? How do you know this?
Hu_ch05v3.fm Page 191 Friday, February 13, 2009 2:38 PM

Problems 191

(b) Circle A or B to select the capacitor having larger

Xox: A B
Vfb: A B
Xdmax: A B
Nsub: A B
Vt: A B

5.17 Compare the maximum capacitance that can be achieved in an area 100 × 100 µm2 by
using either an MOS capacitor or a reverse-biased P+N junction diode. Assume an
oxide breakdown field of 8 × 106 V/cm, a 5V operating voltage, and a safety factor of
two (i.e., design the MOS oxide for 10 V breakdown). The P+N junction is built by
diffusing boron into N-type silicon doped to 1016 cm–3
5.18 Consider the silicon–oxide–silicon structure shown in Fig. 5–41. Both silicon regions are
N type with uniform doping of Nd = 1016 cm–3.

Vg Silicon Oxide Silicon GND

FIGURE 5–41

(a) What would be the flat-band voltage for this structure? Draw the energy band
diagram for the structure for (i) Vg = 0, (ii) Vg < 0 and large, and (iii) Vg > 0 and
large.
(b) Sketch the expected shape of the high-frequency C–V characteristics for the
structure. What are the values of the capacitance for large positive and large
negative Vg?
(c) If silicon on the left-hand side in the figure above is P-type doped with
Na = 1016 cm–3, sketch the C–V characteristics for the new structure.
5.19 Fill in the following table with appropriate mathematical expressions using the basic
MOS C–V theory.

Surface MOS capacitance MOS capacitance MOSFET

Bias condition potential (LF) (HF) capacitance
Accumulation
Flat band
Just below
threshold
Inversion

5.20 The oxide thickness (Tox) and the doping concentration (Na or Nd) of the silicon
substrate can be determined using the high-frequency C–V data shown in Fig. 5–42 for
an MOS structure.
Hu_ch05v3.fm Page 192 Friday, February 13, 2009 2:38 PM

192 Chapter 5 ● MOS Capacitor

1.0

0.8

0.6 C/C 0

High frequency
0.4

0.2

(V)
12 10 8 6 4 2 0 2 4
FIGURE 5–42

(a) Identify the regions of accumulation, depletion, and inversion in the substrate
corresponding to this C–V curve. What is the doping type of the semiconductor?
(b) If the maximum capacitance of the structure C0 (which is equal to Cox × Area) is
82 pF and the gate area is 4.75 × 10–3 cm2, what is the value of Tox?
(c) Determine the concentration in the silicon substrate. Assume a uniform doping
concentration.
(d) Assuming that the gate is P+type, what is Qox?

● Poly-Gate Depletion ●

5.21 (a) Derive Eq. (5.8.1).

(b) Derive an expression for the voltage drop in the poly-depletion region, i.e., the
band bending in the poly-Si gate, φs. Assume that the electric field inside the oxide,
Ᏹox, is known.
(c) Continue from (b) and express φpoly in terms of Vg, not Ᏹox. Assume surface
inversion, i.e., Vg > Vt. Other usual MOS parameters such as Vfb, Tox, and φB may
also appear. Hint: Vg = Vfb + Vox + 2φB + φpoly.
(d) Using the result of (c), find an expression for Wdpoly in terms of Vg, not Ᏹox.
For part (e), (f), and (g), assume Tox = 2 nm, Na = 1017cm–3, Nd = 6 × 1019 cm–3 (for
N+poly-gate), and Vg = 1.5 V.
(e) Evaluate φpoly and Wdpoly.
(f) Calculate Vt using Eq. (5.4.3). (The poly-depletion effect maybe ignored in Vt
calculation because Ᏹox is very low at Vg = Vt.) Then, using φpoly from part (e) in
Eq. (5.8.3), find Qinv.
(g) Calculate Qinv = Coxe(Vg _ Vt) with Coxe given by Eq. (5.8.2).
Hu_ch05v3.fm Page 193 Friday, February 13, 2009 2:50 PM

General References 193

Discussion:
Equation (5.8.2) is correct for the small signal capacitance

C ( V g ) = dQ ( V g ) ⁄ dV g ⇒ Q ( V g ) = ∫ C ( V g ) dV g
Here, part (g) does not yield the correct Qinv because it assumes a constant Coxe. Coxe
varies with Vg due to the poly-depletion effect even for Vg >; Vt. The answer for part (f)
is the correct value for Qinv.
5.22 Draw an energy band diagram for Example 5–3 in Section 5.8. You need to decide
whether Vg and Vox are positive or negative. (Hint: The problem is about gate
depletion.)
5.23 There is a voltage drop in the gate depletion region (Vpoly). Express the following items
using Vpoly, the gate doping concentration Npoly, and the oxide capacitance Cox as
given variables.
(a) What is the charge density Qpoly in the gate depletion region?
(b) What is Cpoly? (Cpoly = εs / Wdpoly)
(c) What is the total MOS capacitance in the inversion region when poly depletion is
included?

● Threshold Voltage Expression ●

5.24 After studying the derivation of Eq. (5.4.3), write down the steps of derivation on your
own.

● REFERENCES ●
1. Lee, W. C., T-J. King, and C. Hu. “Observation of Reduced Boron Penetration and Gate
Depletion for Poly-SiGe Gated PMOS Devices.” IEEE Electron Device Letters. 20 (1)
(1999), 9–11.
2. Stern, F. “Quantum Properties of Surface Space-Charge Layers.” CDC Critical Review Solid
State Science. 4 (1974), 499.
3. Yang, K., Y-C. King, and C. Hu. “Quantum Effect in Oxide Thickness Determination from
Capacitance Measurement.” Technical Digest of Symposium on VLSI Technology, 1999, 77–78.
4. Taur, Y., and T. H. Ning. Fundamentals of Modern VLSI Devices. Cambridge, UK: Cambridge
University Press, 1998.
5. Tompsett, M.F. Video Signal Generation, in Electronic Imaging, T. P. McLean, ed. New
York: Academic, 1979, 55.

● GENERAL REFERENCES ●
1. Muller, R. S., T. I. Kamins, and M. Chen. Device Electronics for Integrated Circuits, 3rd ed.
New York: John Wiley & Sons, 2003.
2. Pierret, R. F. Semiconductor Device Fundamentals. Reading, MA: Addison-Wesley, 1996.
Hu_ch06v3.fm Page 247 Friday, February 13, 2009 4:51 PM

Problems 247

If ᏱsatL >> Vgs − Vt, Eqs. (6.9.10) and (6.9.11) reduce to the long-channel
model, Eqs. (6.6.5) and (6.6.6). If ᏱsatL << Vgs − Vt
V dsat ≈ Ᏹ sat L < long-channel V dsat (6.9.13)
I dsat = Wv sat C oxe ( V gs – V t – Ᏹ sat L ) (6.9.14)
If L is reduced to tens of nanometers, velocity overshoot will raise Ᏹsat and vsat
in the above equations somewhat. Eventually, the carrier injection velocity at the
source will limit Idsat. Interestingly, The present estimate of this limit is not
significantly different from what Eq. (6.9.14) would predict.
The intrinsic voltage gain of a MOSFET is gmsat/gds . gds = dIdsat /dVd is the
output conductance. To achieve a small gds requires a large L and/or small Tox,
Wdep, and Xj (see Section 7.9).
For high-frequency applications, it is important to reduce the (poly-Si) gate
electrode resistance by breaking a wide-W transistor into a large number of smaller-
W transistors connected in parallel. Reducing the channel length can reduce the
intrinsic input resistance as shown in Eq. (6.14.3).
MOSFET noise arises from the channel, gate, substrate thermal noise, and the
flicker noise. While the thermal noise is a white noise, the flicker noise per
bandwidth is proportional to 1/f. The flicker (1/f) noise is reduced if the trap
densities in the gate dielectric or the oxide–semiconductor interface are reduced.
A basic SRAM cell employs six MOSFETs. SRAM is commonly embedded in
logic chips. DRAM cell consists of one transistor and one capacitor. Its size is very
small. DRAM requires refreshing and a specialized technology, partly because of
the complex capacitor structure that has a large surface area. The prevalent NVM is
the flash memory. It uses even smaller Si area per bit than DRAM and can store
data without power for many years. While floating-gate NAND is the dominant
NVM, several new NVM concepts are under active investigation.

● PROBLEMS ●

● MOSFET AND MESFET Vt ●

6.1 An N-channel MOSFET with N+-poly gate is fabricated on a 15 Ω cm P-type Si wafer

with oxide fixed charge density = q × 8 × 1010cm–2, W = 50 µm, L = 2 µm, Tox = 5 nm.
(a) Determine the flat-band voltage, Vfb.
(b) What is the threshold voltage, Vt?
(c) A circuit designer requested N-MOSFET with Vt = 0.5 V from a device engineer.
It was not allowed to change the gate oxide thickness. If you are the device
engineer, what can you do? Give specific answers including what type of
equipment to use.
6.2 A GaAs MESFET has a 0.2 µm thick N-channel doped to Nd = 1017 cm–3. Assume that
φBn of the Au–GaAs Schottky gate is 1 V. εs of GaAs is 13 times the vacuum dielectric
constant. Vd = Vs = 0.
(a) What is Wdep at Vg = 0? (Hint: Please refer to Table 1–4 for the value of Nc of
GaAs at room temperature.)
(b) At what Vg (including the sign) will Wdep be equal to the channel thickness? This is
the cut-off gate voltage of the MESFET. The channel is shut off at this Vg.
Hu_ch06v3.fm Page 248 Friday, February 13, 2009 4:51 PM

248 Chapter 6 ● MOS Transistor

(c) Can any gate voltage of the opposite sign to (b) be applied to the gate without
producing expression gate current? What is its effect on Wdep and Ids?
(d) What needs to be done to redesign this MESFET so that its channel is cut off at
Vg = 0 and the channel only conducts current at Vg larger than a threshold
voltage?

Discussion: The device in (d) is called an enhancement-mode transistor. The device of

(b) is a depletion mode transistor.

6.3 An N-MOSFET and a P-MOSFET are fabricated with substrate doping concentration of
6 × 1017cm–3 (P-type substrate for N-MOSFET and N-type substrate for P-MOSFET).
The gate oxide thickness is 5 nm. See Fig. 6–39.
(a) Find Vt of the N-MOSFET when N+ poly-Si is used to fabricate the gate electrode.
(b) Find Vt of the P-MOSFET when N+ poly-Si is used to fabricate the gate electrode.
(c) Find Vt of the P-MOSFET when P+ poly-Si is used to fabricate the gate electrode.
(d) Assume that the only two voltages available on the chip are the supply voltage
Vdd = 2.5 V and ground, 0 V. What voltages should be applied to each of the
terminals (body, source, drain, and gate) to maximize the source-to-drain current
of the N-MOSFET?
(e) Repeat part (d) for P-MOSFET.
(f) Which of the two transistors (b) or (c) is going to have a higher saturation current.
Assuming that the supply voltage is 2.5 V, find the ratio of the saturation current of
transistor (c) to that of transistor (b).
(g) What is the ratio of the saturation current of transistor (c) to that of transistor (a)?
Use the mobility values from Fig. 6–9.

Vg

Vd Vs

Vb
FIGURE 6–39

● Basic MOSFET IV Characteristics ●

6.4 CV and Id – Vg characteristics of a hypothetical MOSFET with channel length

L = 1 µm are given in Fig. 6–40.
(a) Is the CV characteristic obtained at high frequency or low frequency? Or, is it
impossible to determine? Explain.
(b) Is this a PMOSFET or an NMOSFET?
(c) Find the threshold voltage of this transistor.
(d) Determine the mobility of the carriers in the channel of the transistor.
(e) Plot Id – Vd curves at Vg = 1 V and Vg = 2.5 V.
Hu_ch06v3.fm Page 249 Friday, February 13, 2009 4:51 PM

Problems 249

14
C(pF)
12
10

Id (mA)
1 8
6
4
2
0
Vg 0 1 2 3 4
Vg (V)

FIGURE 6–40

6.5 Figure 6–41 is the IV characteristics of an NMOSFET with Tox = 10 nm, W = 10 µm,
and L = 2 µm. (Assume m = 1 and do not consider velocity saturation.)
(a) Estimate Vt from the plot.
(b) Estimate µns in the inversion layer.
(c) Add the I–V curve corresponding to Vgs = 3 V to the plot.

Vgs4 V

2
Id (mA)

1
Vgs2 V

0
0 1 2 3 4 5
Vds (V)
FIGURE 6–41

6.6 The MOSFET in the circuit shown in Fig. 6–42 is described by

Vdd  2V
k'W 2
I dsat = ----------- ( V g – V t ) , for Vd > Vdsat
2L

2
k'W V ds
Vi
I d = ----------- ( V g – V t ) V ds – --------
- for Vd < Vdsat
 L 2

FIGURE 6–42
Hu_ch06v3.fm Page 250 Friday, February 13, 2009 4:51 PM

250 Chapter 6 ● MOS Transistor

where k' is µnsCox and obtained in practical case by measuring Idsat at a given gate bias.
When k' = 25 µA/V2, Vt = 0. 5 V, W = 10 µm, L = 1 µm, and Vi varied from 0 to 3 V,
(a) Make a careful plot of I dsat as a function of Vi showing any break points on the
curve.
(b) Make a plot of the MOSFET transconductance using a solid line.
(c) On the plot of part (b), use a dotted line to indicate a curve of the output
conductance, dIds/dVds.
6.7 One Ids – Vds curve of an ideal MOSFET is shown in Fig. 6–43. Note that Idsat = 10 –3A
and Vdsat = 2 V for the given characteristic. (You may or may not need the following
information: m = 1, L = 0.5 µm, W = 2.5 µm, Tox = 10 nm. Do not consider velocity
saturation.)
(a) Given a Vt of 0.5 V, what is the gate voltage Vgs one must apply to obtain the I–V
curve?
(b) What is the inversion-layer charge per unit area at the drain end of the channel
when the MOSFET is biased at point (1) on the curve?
(c) Suppose the gate voltage is changed such that Vgs – Vt = 3 V. For the new
condition, determine Ids at Vds = 4 V.
(d) If Vd = Vs = Vb = 0 V, sketch the general shape of the gate capacitance C vs. Vg to
be expected from the MOSFET, when measured at 1 MHz. Do not calculate any
capacitance but do label the Vg = Vt point in the C–V curve.

Ids
(1) (2)
Idsat I03A

Vds
Vdsat 2 V 4V

FIGURE 6–43

6.8 An ideal N-channel MOSFET has the following parameters: W = 50 µm, L = 5 µm,
Tox = 0.05 µm, Na = 1015 cm–3, N+ poly-Si gate, µns = 800 cm2/V/s (and independent of
Vg). Ignore the bulk charge effect and velocity saturation.
Determine:
(a) Vt
(b) Idsat if Vg = 2 V
(c) dIds/dVds if Vg = 2 V and Vd = 0
(d) dIds/dVgs if Vg = 2 V and Vd = 2 V.

● Potential and Carrier Velocity in MOSFET Channel ●

6.9 Derive the equation Vc(x) = (Vg – Vt) [1 √ 1 –x/L ] in Section 6.6. Assume m = 1. (Do
not consider velocity saturation.)
6.10 This is an expanded version of Problem 6.9.
(a) Provide the derivation of Eq. (6.6.7).
(b) Find the expression for Qinv(x).
Hu_ch06v3.fm Page 251 Friday, February 13, 2009 4:51 PM

Problems 251

(c) Find the expression for v(x) = µndVcs/dx.

(d) Show that WQinv(x)v(x) = Idsat expressed in Eq. (6.6.6).
(e) Make a qualitative sketch of Vcs(x).

● IV Characteristics of Novel MOSFET ●

6.11 An NMOSFET has thinner Tox at the center of the channel and thicker Tox near the
source and drain (Fig. 6–44). This could be approximately expressed as Tox = Ax2 + B.
Assume that Vt is independent of x and m = 1. (Do not consider velocity saturation.)
(a) Derive an expression for Id.
(b) Derive an expression for Vdsat.
(c) Does the assumption of nearly constant Vt suggest a large or small Wdmax?

N
Poly gate

Oxide


N N

L/2 0 L/2
P-substrate
x
FIGURE 6–44

6.12 Suppose you have a MOSFET whose gate width changes as a function of distance along
the channel as:
W(x) = W0 + x

where x = 0 at the source and x = L at the drain. Except for its gate width, assume that
this MOSFET is like the typical MOSFET you studied in Chapter 6. (Do not consider
velocity saturation.)
(a) Find an expression for Id for this device. Ignore the bulk charge effect (m = 1).
(b) Derive an expression for Idsat for this device.

● CMOS ●

6.13 MOS circuits perform best when the Vt of NMOS and the Vt of PMOS devices are
about equal in magnitude and of opposite signs. To achieve this symmetry in Vt, PFET
and NFET should have equal Nsubstrate, and symmetrical flat-band voltages, i.e., Vfb,
PMOS = –Vfb, NMOS.
(a) Calculate the Vfb of NMOS and PMOS devices if the substrate doping is
5 × 1016 cm–3 and the gate is N+. Are the flat-band voltages symmetrical?
(b) Assume the NMOS and PMOS devices now have a P+ gate. Redo (a).
(c) If you were restricted to one type of gate material, what work function value
would you choose to achieve the same |Vt|?
(d) If you were allowed to use both N+ and P+ gates, which type of gate would you use
with your NMOS and which with your PMOS devices?
(Hint: Use the results of (a) and (b). Consider the need to achieve symmetrical Vt and
the fact that large |Vt| is bad for circuit speed.)
Hu_ch06v3.fm Page 252 Friday, February 13, 2009 4:51 PM

252 Chapter 6 ● MOS Transistor

6.14

Al Al
Tox  5 nm
3
Nd  2  1016 cm3 Na  10 cm 17

FIGURE 6–45

(a) Determine the flat-band voltage of the NMOS and PMOS capacitors fabricated on
the same chip. (The devices are shown in Fig. 6–45.)
(b) Find the threshold voltages of these two devices.
(c) It is desirable to make the NMOS and PMOS threshold voltages equal in
magnitude (VtPMOS = –VtNMOS). One can in principle implant dopant with
ionized dopant charge Qimpl(C/cm2) at the Si–SiO2 interface to change the
threshold voltage. Assume that such an implant is applied to PMOS only. Find
the value of Qimpl necessary to achieve VtPMOS = –VtNMOS.
6.15 Supply the missing steps between (a) Eqs. (6.7.1) and (6.7.3) and between (b) Eqs. (6.7.3)
and (6.7.4).
6.16

Vout (V)

2V Vdd 2.0 A
Idd B
PFET
S
1.5
D
Vin Vout
D 1.0
S
NFET
0.5
0V Vdd
C
D
Vin (V)
0 0.5 1.0 1.5 2.0
FIGURE 6–46

The voltage transfer curve of an inverter is given in Fig. 6–46. The threshold voltages of
the NFET and PFET are +0.4 and –0.4 V, respectively. Determine the states of the two
transistors (cut-off, linear, or saturation) at points A, B, C, and D, respectively.
(Assume the output conductance of the transistor is very large.) Assume the two
transistors have identical µCox(W/L), m = 1.333.
Hu_ch06v3.fm Page 253 Friday, February 13, 2009 4:51 PM

Problems 253

NFET operation mode PFET operation mode

A
B
C
D

6.17 Consider the CMOS inverter shown in Fig. 6–47.

(a) Sketch the voltage transfer characteristics (VTC), i.e., a plot of V0 vs. Vi for this
inverter, if the threshold voltages of the N-channel and P-channel MOSFETs are
Vtn and Vtp, respectively. Indicate the state (off, linear, or saturation) of each
MOSFET as Vi is changed from 0 to Vdd. Indicate all points on the VTC where a
MOSFET changes its conduction state.
(b) Calculate the voltage at all points indicated in part (a) if both MOSFETs Id – Vd
are characterized by the square-law theory with the following parameters.
For the N-channel MOSFET: µns Cox(W/L) = 40 mA /V–2 and Vtn = 1 V.
For the P-channel MOSFET: µps Cox(W/L) = 35 mA /V–2 and Vtp = 1 V.
The supply voltage Vdd = 5 V.

Vdd

P-channel

Vi V0
Input Output

N-channel

FIGURE 6–47

● Body Effect ●

6.18 P-channel MOSFET with heavily doped P-type poly-Si gate has a threshold voltage of
–1.5 V with Vsb = 0 V. When a 5 V reverse bias is applied to the substrate, the threshold
voltage changes to –2.3 V.
(a) What is the dopant concentration in the substrate if the oxide thickness is 100 nm?
(b) What is the threshold voltage if Vsb is –2.5 V?
Hu_ch06v3.fm Page 254 Friday, February 13, 2009 4:51 PM

254 Chapter 6 ● MOS Transistor

● Velocity-Saturation Effect ●

6.19 The Id – Vd characteristics of an NMOSFET are shown in Fig. 6–48.

0 1 2 3 4 5 6
5 5

Vg  5 V
4 4
C
B
3 3
Id (mA)

2 2
Weff / Leff  15/1 m
A
Tox  250 Å
1 1
Vt  0.7 V

0 0
0 1 2 3 4 5 6
Vd (Volt)
FIGURE 6–48

What are the velocities of the electrons near the drain and near the source at points A,
B, and C? Use the following numbers in your calculations:
A: Ids = 1.5 mA Vds = 0.5 V
B: Ids = 3.75 mA Vds = 2.5 V
C: Ids = 4.0 mA Vds = 5.0 V
(Hint: Id = W × Qinv × v.)
6.20 For an NMOS device with velocity saturation, indicate whether Vdsat and Idsat increase,
decrease, or remain unchanged when the following device parameters are reduced.

Tox W L Vt Vg
Vdsat
Idsat

6.21 Verify Eq. (6.9.10) by equating Eqs. (6.9.3) and (6.9.9).

6.22 Verify Eq. (6.9.11) by substituting Eq. (6.9.10) into Eq. (6.9.3).
6.23 Consider a MOSFET with εsat = 104 V cm–1. For Vg – Vt = 2 V, find Vdsat when:
(a) L = 0.1 µm.
(b) L = 10 µm.
(c) For the device in part (a) with Idsat = 7 mA, calculate the low field electron
mobility if the gate capacitance is 10 fF.
Hu_ch06v3.fm Page 255 Friday, February 13, 2009 4:51 PM

Problems 255

6.24 An NMOSFET with a threshold voltage of 0.5 V and oxide thickness of 6 nm has a
Vdsat of 0.75 V when biased at Vgs = 2.5 V. What is the channel length and saturation
current per unit width of his device? (Hint: Use the universal mobility curve to find µs.
From µs, you can determine
6
8 × 10 cm ⁄ s-
ε sat = v sat ⁄ 2 µ ns = -------------------------------
2 µ ns

6.25 The MOSFET drain current with velocity saturation is given as follows:

I dlin (no velocity saturation)

In linear region, I dlin (velocity saturation) = -----------------------------------------------------------------
-
V ds
1 + ---------------
E sat L
I dsat (no velocity saturation)
In saturation region, I dsat (velocity saturation) = ------------------------------------------------------------------
V –V gs t
1 + --------------------
mE sat L

Consider a MOSFET with bulk charge factor m = 1.2, saturation velocity νsat =
6 2
8 × 10 cm ⁄ s and surface mobility µ ns = 300 cm ⁄ V – s . Under what condition
will velocity saturation cause the drain current to degrade by a factor of two? Assume
mV ds > V gs – V t
(a) If L = 100 nm, Vgs – Vth = ?
(b) If Vgs – Vt = 0.2 V, L = ?

● Effective Channel Length ●

6.26 The total resistance across the source and drain contacts of a MOSFET is (Rs + Rd +
RChannel), where Rs and Rd are source and drain series resistances, respectively, and
RChannel is the channel resistance. Assume that Vds is very small in this problem.
(a) Write down an expression for RChannel, which depends on Vgs (Hint: RChannel =
Vds /Ids).
(b) Consider that Leffective = Lgate –∆L, where Lgate is the known gate length and ∆L
accounts for source and drain diffusion, which extend beneath the gate. Define Rsd
to be equal to (Rs + Rd). Explain how you can find what Rsd and ∆L are. (Hint:
Study the expression from part (a). Note that ∆L is the same for devices of all gate
lengths. You may want to take measurements using a range of gate voltages and
lengths.)
(c) Prove that
I dsat0
I dsat = ----------------------------------
-
I dsat0 R s
1 + -------------------------
( V gs – V t )

where Idsat0 is the saturation current in the absence of Rs.

(d) Given Tox = 3 nm, W/L = 1/0.1 µm, Vgs = 1.5 V and Vt = 0.4 V, what is Idsat for
Rs = 0, 100, and 1,000 Ω?
Hu_ch06v3.fm Page 256 Friday, February 13, 2009 4:51 PM

256 Chapter 6 ● MOS Transistor

6.27 The drawn channel length of a transistor is in general different from the electrical
channel length. We call the electrical channel length Leff, while the drawn channel
length is called Ldrawn. Therefore the transistor Id–Vd curves should be represented by
µ n C ox W 2
- ( Vg – Vt )
I dsat = --------------------- for Vd > Vdsat
2L eff
2
µ n C ox W V ds
- ( V g – V t ) V ds – --------
I dsat = --------------------- - for Vd < Vdsat
L eff 2
(a) How can you find the Leff? (Hints: You may assume that several MOSFETs of
different Ldrawn, such as 1, 3, and 5 µm, are available. W and Vt are known.)
Describe the procedure.
(b) Find the ∆L = Ldrawn – Leff and gate oxide thickness when you have three sets of
Idsat data measured at the same Vg as follows.

L (Drawn channel length) 1 (µm) 3 (µm) 5 (µm)

Idsat (mA) 2.59 0.8 0.476

The channel width, W, is 10 µm, and the mobility, µ, is 300 cm2/V/s.

(c) If the Idsat of the transistor is measured at Vgs = 2 V, what is the threshold voltage
of the transistor with Ldrawn = 1 µm?

● Memory Devices ●

6.28 (a) Qualitatively describe the differences among SRAM, DRAM, and flash memory
in terms of closeness to the basic CMOS manufacturing technology, write speed,
volatility, and cell size.
(b) What are the main applications of SRAM, DRAM, and flash memory? Why are
each suitable for the applications. Hint: Consider your answers to (a).
6.29 (a) Match the six transistors in Fig. 6–34b to the transistors in Fig. 6–34a. (Hint: M5
and M6 usually have larger W than the transistors in the inverters.)
(b) Add the possible layout of the bit line and word line into Fig. 6–34b.
(c) Starting from the answer of (b), add another cell to the right and a third cell to the
top of the original cell.
(d) Try to think of another way to arrange the six transistors (a new layout) that will
pack them and the word line/bit lines into an even smaller cell area. (Hint: It is
unlikely that you can pack them into a smaller area, although it should be fun
spending 10 minutes trying. Furthermore, one cannot do this exercise fairly unless
you know the detailed “design rules,” which are the rules governing the size and
spacing of all the features in a layout.)

● REFERENCES ●
1. Lilienfeld, J. E. “Method and Apparatus for Controlling Electronic Current.” U.S. Patent
1,745,175 (1930).
2. Heil, O. “Improvements in or Relating to Electrical Amplifiers and Other Control
Arrangements and Devices.” British Patent 439,457 (1935).
Hu_ch06v3.fm Page 257 Friday, February 13, 2009 4:51 PM

General References 257

3. Timp, G., et al. “The Ballistic Nano-transistor.” International Electron Devices Meeting
Technical Digest 1999, 55–58.
4. Chen, K., H. C. Wann, et al. “The Impact of Device Scaling and Power Supply Change on
CMOS Gate Performance,” IEEE Electron Device Letters 17 (5) (1996) 202–204.
5. Takagi, S., M. Iwase, and A. Toriumi. “On Universality of Inversion-Layer Mobility in N-
and-P-channel MOSFETs.” International Electron Devices Meeting Technical Digest (1988),
398–401.
6. Komohara, S., et al. MOSFET Carrier Mobility Model Based on the Density of States at the
DC Centroid in the Quantized Inversion Layer. 5th International Conference on VLSI and
CAD (1997), 398–401.
7. Chen, K., C. Hu, et al. “Optimizing Sub-Quarter Micron CMOS Circuit Speed Considering
Interconnect Loading Effects.” IEEE Transactions on Electron Devices 44 (9) (1997), 1556.
8. Assaderaghi, F., et al. “High-Field Transport of Inversion-Layer Electrons and Holes
Including Velocity Overshoot.” IEEE Transactions on Electron Devices 44 (4) (1997),
664–671.
9. Toh, K. Y., P. K. Ko, and R. G. Meyer. “An Engineering Model for Short-Channel MOS
Devices.” IEEE Journal of Solid State Circuits (1988), 23 (4), 950.
10. Hu, G. J., C. Chang, and Y. T. Chia. “Gate-Voltage Dependent Channel Length and Series
Resistance of LDD MOSFETs.” IEEE Transactions on Electron Devices 34 (1985), 2469.
11. Assad, F., et al. “Performance Limits of Silicon MOSFETs.” International Electron Devices
Meeting Technical Digest (1999) 547–550.
12. Hu, C. “A Compact Model for Rapidly Shrinking MOSFETs.” Electron Devices Meeting
Technical Digest (2001), 13.1.1–13.1.4.
13. Hu, C. “BSIM Model for Circuit Design Using Advanced Technologies.” VLSI Circuits
Symposium Digest of Technical Papers (2001), 5–10.
14. Hung, K. K., et al. “A Physics-Based MOSFET Noise Model for Circuit Simulations.” IEEE
Transactions on Electron Devices Technical Digest (1990), 1323–1333.
15. Fukuda, K., et al. “Random Telegraph Noise in Flash Memories—Model and Technology
Scaling.” Electron Devices Meeting Technical Digest (2007), 169–172.
16. Wu, S-Y., et al. “A 32 nm CMOS Low Power SoC Platform Technology for Foundry
Applications with Functional High Density SRAM.” IEDM Technical Digest (2007),
263–266.
17. Park, Y. K., et al. “Highly Manufacturable 90 nm DRAM Technology.” International
Electron Devices Meeting Technical Digest (2002), 819–822.
18. Brewer, J. E., and M. Gill, eds. Nonvolatile Memory Technologies with Emphasis on Flash.
Hoboken, NJ: John Wiley & Sons, Inc., 2008.
19. Quader, K., et al. “Hot-Carrier Reliability Design Rules for Translating Device
Degradation to CMOS Digital Circuit Degradation.” IEEE Transactions on Electron
Devices 41 (1994), 681–691.

● GENERAL REFERENCES ●
1. Taur, Y., and T. H. Ning. Fundamentals of Modern VLSI Devices. Cambridge, UK:
Cambridge University Press, 1998.
2. Pierret, R. F. Semiconductor Device Fundamentals. Reading, MA: Addison-Wesley, 1996.
Hu_ch07v3.fm Page 286 Friday, February 13, 2009 4:55 PM

286 Chapter 7 ● MOSFETs in ICs—Scaling, Leakage, and Other Topics

S is the subthreshold swing. To keep Ioff below a given level, there is a mini-
mum acceptable Vt. Unfortunately, a larger Vt is deleterious to Ion and speed.
Therefore, it is important to reduce S by reducing the ratio Toxe/Wdep. Furthermore,
Vt decreases with L, a fact known as Vt roll-off, caused by DIBL.
–L ⁄ l d
V t = V t-long – ( V ds + 0.4V ) ⋅ e (7.3.3)

where I d ∝ 3 T oxe W dep X j (7.3.4)

Since Vt is a sensitive function of L, even the small (a few nm) manufacturing vari-
ations in L can cause problematic variations in Vt, Ioff, and Ion. To allow L reduction,
Eq. (7.3.3) states that ld must be reduced, i.e., Toxe, Wdep, and/or Xj must be reduced.
Tox reduction is limited mostly by gate tunneling leakage, which can be
suppressed by replacing SiO2 with a high-k dielectric such as HfO2. Metal gate can
reduce Toxe by eliminating the poly-Si gate depletion effect.
Wdep can be reduced with retrograde body doping. Xj can be reduced with mS
flash annealing or the metal source–drain MOSFET structure. Xj and Wdep can also
be reduced with the ultra-thin-body SOI device structure or the multigate
MOSFET structure. More importantly, these new structures eliminate the more
vulnerable leakage paths, which are the farthest from the gate.
Equation (7.3.3) also provides a theory for output conductance of the short
channel transistors.
–L ⁄ l d
g ds = g msat × e (7.9.3)

● PROBLEMS ●

● Subthreshold Leakage Current ●

7.1 Assume that the gate oxide between an n+ poly-Si gate and the p-substrate is 11 Å
thick and Na = 1E18 cm–3.
(a) What is the Vt of this device?
(b) What is the subthreshold swing, S?
(c) What is the maximum leakage current if W = 1 µm, L = 18 nm? (Assume Ids =
100 W/L (nA) at Vg = Vt.)

● Field Oxide Leakage ●

7.2 Assume the field oxide between an n+ poly-Si wire and the p-substrate is 0.3 µm thick
and that Na = 5E17 cm–3.
(a) What is the Vt of this field oxide device?
(b) What is the subthreshold swing, S?
(c) What is the maximum field leakage current if W = 10 µm, L = 0.3 µm, and
Vdd = 2.0 V?

● Vt Roll-off ●
7.3 Qualitatively sketch log(Ids) vs. Vg (assume Vds = Vdd) for the following:
(a) L = 0.2 µm, Na = 1E15 cm–3.
(b) L = 0.2 µm, Na = 1E17 cm–3.
Hu_ch07v3.fm Page 287 Friday, February 13, 2009 4:55 PM

Problems 287

(c) L = 1 µm, Na = 1E15 cm–3.

(d) L = 1 µm, Na = 1E17 cm–3.
Please pay attention to the positions of the curves relative to each other and label all
curves.

● Trade-off between Ioff and Ion ●

7.4 Does each of the following changes increase or decrease Ioff and Ion? A larger Vt. A
larger L. A shallower junction. A smaller Vdd. A smaller Tox. Which of these changes
contribute to leakage reduction without reducing the precious Ion?
7.5 There is a lot of concern that we will soon be unable to extend Moore’s Law. In your
own words, explain this concern and the difficulties of achieving high Ion and low Ioff.
(a) Answer this question in one paragraph of less than 50 words.
(b) Support your description in (a) with three hand-drawn sketches of your choice.
(c) Why is it not possible to maximize Ion and minimize Ioff by simply picking the right
values of Tox, Xj, and Wdep? Please explain in your own words.
(d) Provide three equations that help to quantify the issues discussed in (c).
7.6 (a) Rewrite Eq. (7.3.4) in a form that does not contain Wdep but contains Vt. Do so by
using Eqs. (5.5.1) and (5.4.3) assuming that Vt is given.
(b) Based on the answer to (a), state what actions can be taken to reduce the
minimum acceptable channel length.
7.7 (a) What is the advantage of having a small Wdep?
(b) For given L and Vt, what is the impact of reducing Wdep on Idsat and gate? (Hint:
consider the “m” in Chapter 6)
Discussion: Overall, smaller Wdep is desirable because it is more important to be able
to suppress Vt roll-off so that L can be scaled.

● MOSFET with Ideal Retrograde Doping Profile ●

7.8 Assume an N-channel MOSFET with an N+ poly gate and a substrate with an idealized
retrograde substrate doping profile as shown in Fig. 7–23.

Nsub

Gate Oxide Substrate

P

Very light P type

x
Tox Xrg

FIGURE 7–23
Hu_ch07v3.fm Page 288 Friday, February 13, 2009 4:55 PM

288 Chapter 7 ● MOSFETs in ICs—Scaling, Leakage, and Other Topics

(a) Draw the energy band diagram of the MOSFET along the x direction from the
gate through the oxide and the substrate, when the gate is biased at threshold
voltage. (Hint: Since the P region is very lightly doped you may assume that the
field in this region is constant or dε/dx = 0). Assume that the Fermi level in the P+
region coincides with Ev and the Fermi level in the N+ gate coincides with Ec.
Remember to label Ec, Ev, and EF.
(b) Find an expression for Vt of this ideal retrograde device in terms of Vox. Assume
Vox is known. (Hint: Use the diagram from (a) and remember that Vt is the
difference between the Fermi levels in the gate and in the substrate. At threshold,
Ec of Si coincides with the Fermi level at the Si–SiO2 interface).
(c) Now write an expression for Vt in terms of Xrg, Tox, εox, εsi and any other common
parameters you see fit, but not in terms of Vox. Hint: Remember Nsub in the lightly
doped region is almost 0, so if your answer is in terms of Nsub, you might want to
rethink your strategy. Maybe εoxεox = εsiεsi could be a starting point.
(d) Show that the depletion layer width, Wdep in an ideal retrograde MOSFET can be
about half the Xdep of a uniformly doped device and still yield the same Vt.
(e) What is the advantage of having a small Wdep?
(f) For given L and Vt, what is the impact of reducing Wdep on Idsat and inverter
delay?

● REFERENCES ●
1. International Technology Roadmap for Semiconductors (http://public.itrs.net/)
2. Ghani, T., et al. “A 90 Nm High Volume Manufacturing Logic Technology Featuring Novel
45 nm Gate Length Strained Silicon CMOS Transistors,” IEDM Technical Digest. 2003,
978–980.
3. Yeo, Y-C., et al. “Enhanced Performance in Sub-100nm CMOSFETs Using Strained
Epitaxial Si-Ge.” IEDM Technical Digest. 2000, 753–756.
4. Liu, Z. H., et al. “Threshold Voltage Model for Deep-Submicrometer MOSFETs.” IEEE
Trans. on Electron Devices. 40, 1 (January 1993), 86–95.
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Transactions on Electron Devices. 43, 10 (October 1996), 1742–1753.
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Alternative Gate Dielectrics Based on Leakage Considerations.” IEEE Transactions on
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● GENERAL REFERENCES ●
1. Taur, Y., and T. H. Ning. Fundamentals of Modern VLSI Devices. Cambridge, UK:
Cambridge University Press, 1998.
2. Wolf, S. VLSI Devices. Sunset Beach, CA: Lattice Press, 1999.