High-k dielectric materials for CMOS

technology: Lecture 1
Sourav De
Assistant Professor
College of
Semiconductor
Research, NTHU

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 Overview of the Course: Syllabus

21st of February: Introduction to MOS Capacitors, MOSFETs, MOSFETs Scaling, and limitations.
3rd of March: High-k dielectrics and its stack interfaces, UV-engineering of high-k films.
14th of March: ALD deposition process of hf-based high-k materials.
21st of March: Structural and electrical characterization
28th of March: Characterization of high-k internal structure by X-ray spectroscopy and reflectometry.
11th of April: Interface engineering on high-k.
18th of April: Mid-term Evaluation
25th of April: High-k metal gate evolution from Si to Ge platform
2nd of May: Introduction to ferroelectricity and HfO2-based ferroelectric material.
9th of May: Ferroelectric memories and their applications.
16th of May: Defect analysis of high-k gate dielectric by flicker noise and charge pumping.
23rd of May: Negative capacitance field effect transistors.
6th of June: Final Evaluation

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 Evaluation Criteria

Component Weight (%) Purpose Structure Deadlines/Key Dates

Students select a research paper on
high-k dielectrics, write a 2-page
1. Research Article To develop critical thinking summary, and present key takeaways. Submission and
40
Review and literature analysis skills. Example: Review an article on presentation in Week 8
reliability issues in hafnium-based
high-k dielectrics.
Groups (2 members) propose, design,
and analyze a high-k dielectric
application or process. Deliverables: -
To encourage collaborative Proposal (Week 5) - Final Report (10 Proposal in Week 5, Final
2. Group Presentation 30 research and application of pages) and Presentation (Week 15). Report and Presentation
course knowledge. Example Topics: - Comparative in Week 15
analysis of ALD and sputtering for
high-k deposition. - Integration of
high-k dielectrics in GAA transistors.

Closed-book written exam (2 hours)

with conceptual questions, numerical
To test the comprehensive Conducted in Week 16
problems, and case studies. Example
3. Final Examination 30 understanding of course during the university’s
Question: Discuss the role of
content. examination period.
interfacial layers in mitigating leakage
currents in high-k gate stacks.

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 Introduction to MOS Capacitors

➢ Definition of MOS: Stands for Metal–Oxide–Semiconductor.

➢ Structure: Semiconductor substrate, Metal
insulating oxide, and a gate electrode.
Oxide
➢ Key Features of the MOS Capacitor:
➢ Insulating Layer as thin as 1.5 nm Semiconductor
(approximately 10 Å or a few oxide molecules).
➢ Gate Electrode Evolution:
➢ Pre-1970: Metal gates (e.g., Al).

➢ Post-1970: Heavily doped polycrystalline silicon (poly-Si) for its thermal stability.

➢ Post-2008: Return to metal gates and introduction of advanced high-k dielectrics.

➢ MOS Capacitor Applications:

➢ Not commonly used as a standalone device.
➢ Integral part of the MOS transistor, the most widely used semiconductor device.
➢ Key developments: Transition from SiO₂ to high-k dielectrics and reintroduction of metal gates in
advanced technologies.
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 MOS Capacitors: Band Diagram

Semiconductor
Oxide
Metal

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 Flat-Band Condition

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 Surface Accumulation

The surface hole concentration:

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 Surface Depletion

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 Threshold Condition and Vt

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 Threshold Condition and V th

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 Strong Inversion

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Vt and Gate Doping

•A p-body is almost always paired with an

N+ gate to achieve a small positive
threshold voltage.
•An n-body is typically paired with a P+
gate to achieve a small negative threshold
voltage.
•The other body-gate combinations are
rarely encountered.

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 Surface Potential

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 Depletion Region

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 Charge Components In The
Substrate: Depletion Charge

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 Charge Components In The
Substrate: Inversion Charge

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 Charge Components In The
Substrate: Accumulation

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 Charge Components In The
Substrate: Total Charge

C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
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 MOS CV Characteristics

◼ The capacitance in the MOS theory is

always the small-signal capacitance.
◼ The negative sign in the equation arises
from the fact that Vg is taken at the top
capacitor plate, but Qsub is taken at the
bottom capacitor plate.

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 MOS CV Characteristics

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 Oxide charge- A Modification To Vfb
and Vt

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 Poly-Si Gate Depletion- Effective
Increase In Tox

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Inversion and Accumulation Charge-
layer Thicknesses And Quantum
Mechanical Effect

C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
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 Inversion and Accumulation Charge-
layer Thicknesses And Quantum
Mechanical Effect

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 Poly-depletion and Charge-layer
Thickness

C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
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 Equivalent Circuit for the C–V

Equivalent circuit for understanding the C–V curve in the depletion region
and the inversion region. (a) General case for both depletion and inversion
regions; (b) in the depletion regions; (c) Vg ≈ Vt; and (d) strong inversion.

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 Let’s Summarize the MOSCAP

The three regions (accumulation, depletion, and inversion) and the two
transition points (flat-band and threshold)

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 Let’s Summarize the MOSCAP

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Introduction to MOSFET

The two PN junctions are the source and the drain that supplies the
electrons or holes to the transistor and drains them away respectively. The
name field-effect transistor or FET refers to the fact that the gate turns the
transistor (inversion layer) on and off with an electric field through the
oxide. A transistor is a device that presents a high input resistance to the
signal source, drawing little input power, and a low resistance to the output
circuit, capable of supplying a large current to drive the circuit load.
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 CMOS Technology

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 CMOS Technology

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 Surface Mobilities And High-mobility
FETs
◼ It is highly desirable to have a large transistor current
so that the MOSFET can charge and discharge the
circuit capacitances quickly and achieve a high
circuit speed.
◼ The electron or hole mobility in the surface inversion
layer is an important factor determining the MOSFET
current.

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice
 Effect of Wafer Surface
Orientation and Drift Direction
◼ **Surface Mobility Factors**:
- Surface mobility is influenced by surface orientation and drift direction.
◼ - **Standard CMOS Technology**:

- Utilizes [100] surface silicon wafers.

- Transistor layout allows electron and hole flow along identical directions (0 ±1 ±1).
◼ - **Reason for Material Choice**:
- Configuration provides the highest electron mobility (µns).
- Does not yield the highest hole mobility (µps).
◼ **Impact of Orientation and Current Direction**:

- These factors affect how µns and µps respond to mechanical stress.
◼ **Theoretical Explanation**:
- Orientation effects can be explained using the solution of Schrödinger’s wave equation.
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 MOSFET Vt and Body Effect

The depletion-layer capacitance is

Charge in the inversion layer:

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Body Effect and Steep Retrograde
Doping

γ is called the body-effect parameter

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 Inversion Charge in MOSFET

However, including m in the equations significantly improves their later-reference accuracy.

The body is sometimes called the back gate since it clearly has a similar though weaker
effect on the channel charge. The back-gate effect on Qinv is often called the bulk-charge
effect. m is called the bulk-charge factor. Clearly, the bulk-charge effect is closely linked to
the body effect.

C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
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 Basic MOSFET IV Curve

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 Channel Voltage Profile (Vds = Vdsat)

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 Channel Voltage Profile (Vds > Vdsat)

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 Voltage Transfer Characteristics

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Voltage Transfer Characteristics

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Inverter Speed—The Importance of Ion

τd is the average of the delays of pull-down (rising

V1 pulling down the output, V2) and pull-up (falling
V2 pulling up the output, V3). The propagation
delay of an inverter may be expressed as

The delay is the time for the on-state transistor supplying a current, Ion, to change the
output by Vdd/2 (not Vdd). The charge drained from (or supplied to) C by the FET
during the delay is CVdd/2. Therefore, the delay is Q/I = CVdd/2Ion. One may interpret
the delay as RC with Vdd/2Ion as the switching resistance of the transistor.
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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Power Consumption

f is the clock frequency, and k is an activity factor that represents that a particular
gate in a given circuit is not switched every clock cycle all the time.
This Pdynamic plays a key role in power usage when the inverter is frequently toggled.
Power usage can be decreased by reducing Vdd, minimizing all capacitances in the
circuit, and lowering k. It is noteworthy that increasing Ion through a smaller L or
enhancing carrier mobility does not raise Pdynamic.
A high Ion is beneficial for reducing circuit switching delays, while a low Vdd helps
decrease power usage. By minimizing the transistor's L and W, gate and source-
drain junction capacitance are reduced, leading to a smaller chip size and lower
interconnect capacitance. This approach effectively lowers power consumption per
circuit function.
Static power, or leakage, occurs when the inverter is inactive and contributes to
overall power consumption.

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Velocity Saturation and Velocity
Overshoot

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 MOSFET IV Model With Velocity
Saturation

Basic MOSFET eqn

Velocity Saturation

Together

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 MOSFET IV Model With Velocity
Saturation

◼ The effect of velocity saturation is to decrease the drain current (Ids) by

a factor of 1 + 𝑉𝑑𝑠/𝜉𝑠𝑎𝑡 𝐿.
◼ This factor approaches one—meaning velocity saturation becomes
negligible—when 𝑉𝑑𝑠 is small or L is large.
𝜉𝑎𝑣𝑒 𝑉𝑑𝑠
◼ This factor can also be interpreted as 1 + where 𝜉𝑎𝑣𝑒 ≡ is the
𝜉𝑠𝑎𝑡 𝐿
average electric field in the channel. The saturation voltage 𝑉𝑠𝑎𝑡 can be
𝑑𝐼
determined by solving the equation 𝑑𝑉𝑑𝑠 = 0
𝑑𝑠

Inconvenient

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 MOSFET IV Model With Velocity
Saturation
➢ A simpler and even more accurate Vdsat model may be derived from a piece-wise
model that fits the 𝜈 − 𝜉𝑠𝑎𝑡 data better.
Equation leads to Id which is valid when the
carrier speed is less than vsat, i.e., Vds<Vdsat

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 MOSFET IV Model With Velocity
Saturation

Taylor Series Expansion

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Understanding Long and Short-
Channel Behaviors in MOSFETs
Case Analysis
1.For Digital Circuits:
Key Conditions 𝜉𝑠𝑎𝑡 = 6 × 10⁴ V/cm, Vgs - Vt = 2V
❑ The inequality is pivotal: Channel Length, L = 0.2 µm
𝜉𝑠𝑎𝑡 𝐿 ≫ 𝑉𝑔𝑠 − 𝑉𝑡 Condition NOT satisfied → Significant short-
channel behaviors observed.
❑ L Large: Ensures long-channel 2.For Low-Power Analog Circuits:
behavior. Vgs - Vt = 0.1 V
❑ Vgs ~ Vt: Often occurs in low-
Channel Length, L = 0.1 µm satisfies the
power analog circuits to reduce condition.
power consumption. Long-Channel Characteristics emerge:
1. Idsat ∝ (Vgs - Vt)² / L
2. Vdsat = (Vgs - Vt) / m

Observations in Analog Circuits

•Even with L = 0.05 µm, long-channel equations apply.
•Short- channel effects still present, such as:
• Increased leakage current.
• Steeper Id–Vd slope at Vds > Vdsat
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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Understanding Long and Short-
Channel Behaviors in MOSFETs

❑ Idsat is proportional to Vgs− Vt rather than (Vgs − Vt)2 and

is less sensitive to L than the long-channel Idsat (∝ 1/L).
❑ Idsat is proportional to W.
❑ Carriers travels at saturation velocity at the drain end of
the channel where, Qinv= Coxe(Vgs-Vt-mVdsat) and Vdsat is
𝜉𝑠𝑎𝑡 L
Key Observations
Short-Channel Device (L = 0.15 µm):
1. Idsat ∝ Vgs → Follows Equation.
2. Vdsat significantly less than (Vgs−Vt)/m

Long-Channel Device (L = 2 µm):

1. Superlinear increase in Idsat with Vg​.
2. Follows Equation approximately.

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Parasitic Source-Drain Resistance

•Idsat₀: Current in the absence of Rs (source resistance).

•Idsat Reduction:
Parasitic resistance significantly reduces Idsat.
The impact is expected to increase with future technology
scaling.
Contributors to Parasitic Resistance
Shallow Diffusion Region:
Located under the dielectric spacer.
Designed to prevent excessive off-state leakage in short-
channel transistors.
Silicide Layers:
Materials: TiSi₂ or NiSi₂.
Reduces sheet resistivity of N+ (or P+) regions by a factor of 10.
Minimizes contact resistance between silicide and N+/P+ silicon.
Role of Dielectric Spacer
•Fabrication process:
Conformal dielectric film coats the structure.
Anisotropic dry etching removes dielectric from horizontal
surfaces.
•Silicides Formation:
• Metal reacts with silicon at high temperatures.
• Unreacted metal is removed with acid cleaning.

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Channel Length and Related
Quantities

Drawn Gate Length (Ldrawn):

•Specified by the circuit designer in the circuit layout.

Physical Gate Length (Lg):

•Final gate length after pattern transfer.
•It may differ from Ldrawn due to during fabrication. Woo Young Choi, et al.,, "100-nm n-/p-channel I-MOS using a
novel self-aligned structure," in IEEE Electron Device Letters,
vol. 26, no. 4, pp. 261-263, April 2005

Efforts to Minimize Ldrawn−Lg:

•Optical Proximity Correction: Reduces dimensional differences.
•Assumption: Ldrawn≈Lg after corrections.

Measurement of Lg:
•Done using Scanning Electron Microscopy (SEM).

Effective Channel Length (L eff/Le):

•Also called the electrical channel length.
•Required for device analysis and modeling.
•Differentiates from Ldrawn and Lg​.
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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Channel Length and Related
Quantities

This difference is called ∆L, which is assumed to be a constant, independent of Ldrawn

Measuring ∆L in short transistors is quite difficult. There are several imperfect options.
The following method is the oldest and is still commonly used.

When the series resistance, Rds ≡ Rd + Rs

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Channel Length and Related
Quantities

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Velocity Overshoot and Source
Velocity Limit
Mobility loses significance when the channel length is
comparable to or smaller than the mean free path.

Equation Independence from Mobility:

The saturation velocity may increase for channels shorter

than 100 nm due to velocity overshoot.

The carrier velocity at the source, constrained by thermal

velocity, becomes the limiting factor for Idsat.

Carriers enter the channel from the source at thermal

velocity—this is the source injection velocity limit.
•Carrier Dynamics at Zero Channel Length:
• As the channel length approaches zero:
• All carriers moving from the source to the channel are
captured by the drain.
• No carriers flow from the drain to the source due to
the voltage difference or energy barrier
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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Output Conductance

◼ The slope of the I–V curve is called the output

conductance.

A clear saturation of Ids, i.e., a small gds is desirable.

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 High-Frequency Performance

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 Reducing Gate-Electrode Resistance
Using Multi-Finger Layout

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Reducing Gate-Electrode Resistance
Using Multi-Finger Layout

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Reducing Gate-Electrode Resistance
Using Multi-Finger Layout

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 Thermal Noise of a Resistor

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 MOSFET Thermal Noise

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
 MOSFET Flicker Noise

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C. Hu, “Modern Semiconductor Devices for Integrated Circuits,” Pearson/Prentice Hall, New Jersey, 351 pages, 2010.