High-κ gate dielectrics: Current status and

materials properties considerations

Cite as: Journal of Applied Physics 89, 5243 (2001); https://doi.org/10.1063/1.1361065
Submitted: 09 November 2000 • Accepted: 19 January 2001 • Published Online: 01 May 2001

G. D. Wilk, R. M. Wallace and J. M. Anthony

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Journal of Applied Physics 89, 5243 (2001); https://doi.org/10.1063/1.1361065 89, 5243

© 2001 American Institute of Physics.

JOURNAL OF APPLIED PHYSICS VOLUME 89, NUMBER 10 15 MAY 2001

APPLIED PHYSICS REVIEW

High-␬ gate dielectrics: Current status and materials properties

considerations
G. D. Wilka)
Agere Systems, Electronic Device Research Laboratory, Murray Hill, New Jersey 07974
R. M. Wallaceb)
University of North Texas, Department of Materials Science, Denton, Texas 76203
J. M. Anthony
University of South Florida, Center for Microelectronics Research, Tampa, Florida 33620
共Received 9 November 2000; accepted for publication 19 January 2001兲
Many materials systems are currently under consideration as potential replacements for SiO2 as the
gate dielectric material for sub-0.1 ␮m complementary metal–oxide–semiconductor 共CMOS兲
technology. A systematic consideration of the required properties of gate dielectrics indicates that
the key guidelines for selecting an alternative gate dielectric are 共a兲 permittivity, band gap, and band
alignment to silicon, 共b兲 thermodynamic stability, 共c兲 film morphology, 共d兲 interface quality, 共e兲
compatibility with the current or expected materials to be used in processing for CMOS devices, 共f兲
process compatibility, and 共g兲 reliability. Many dielectrics appear favorable in some of these areas,
but very few materials are promising with respect to all of these guidelines. A review of current
work and literature in the area of alternate gate dielectrics is given. Based on reported results and
fundamental considerations, the pseudobinary materials systems offer large flexibility and show the
most promise toward successful integration into the expected processing conditions for future
CMOS technologies, especially due to their tendency to form at interfaces with Si 共e.g. silicates兲.
These pseudobinary systems also thereby enable the use of other high-␬ materials by serving as an
interfacial high-␬ layer. While work is ongoing, much research is still required, as it is clear that any
material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The
requirements for process integration compatibility are remarkably demanding, and any serious
candidates will emerge only through continued, intensive investigation. © 2001 American Institute
of Physics. 关DOI: 10.1063/1.1361065兴

I. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5243 1. Group IIIA and IIIB metal oxides. . . . . . . . . 5254

II. SCALING AND IMPROVED 2. Group IVB metal oxides. . . . . . . . . . . . . . . . 5256
PERFORMANCE. . . . . . . . . . . . . . . . . . . . . . . . . . . 5244 3. Pseudobinary alloys. . . . . . . . . . . . . . . . . . . . 5262
III. METAL-INSULATOR-SEMICONDUCTOR 4. High-␬ device modeling and transport. . . . . 5265
共MIS兲 GATE STACK STRUCTURES. . . . . . . . . . 5245 VI. MATERIALS PROPERTIES
IV. SCALING LIMITS FOR CURRENT GATE CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . 5266
DIELECTRICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5247 A. Permittivity and barrier height. . . . . . . . . . . . . . . 5266
A. Ultrathin SiO2 properties. . . . . . . . . . . . . . . . . . . 5247 B. Thermodynamic stability on Si. . . . . . . . . . . . . . 5268
B. Ultrathin SiO2 reliability. . . . . . . . . . . . . . . . . . . 5248 C. Interface quality. . . . . . . . . . . . . . . . . . . . . . . . . . 5269
C. Boron penetration and surface preparation. . . . . 5249 D. Film morphology. . . . . . . . . . . . . . . . . . . . . . . . . 5270
E. Gate compatibility. . . . . . . . . . . . . . . . . . . . . . . . 5271
D. SiOx Ny and Si–N/SiO2 dielectrics. . . . . . . . . . . . 5249
F. Process compatibility. . . . . . . . . . . . . . . . . . . . . . 5272
E. Fundamental limitations. . . . . . . . . . . . . . . . . . . . 5249
G. Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5272
F. Device structures. . . . . . . . . . . . . . . . . . . . . . . . . 5250
VII. CONCLUSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . 5273
V. ALTERNATIVE HIGH-␬ GATE DIELECTRICS.. 5250
A. High-␬ candidates from memory applications. . 5251
I. INTRODUCTION
B. Issues for interface engineering. . . . . . . . . . . . . . 5252
C. Recent high-␬ results. . . . . . . . . . . . . . . . . . . . . . 5253 The rapid progress of complementary metal–oxide–
semiconductor 共CMOS兲 integrated circuit technology since
a兲 the late 1980’s has enabled the Si-based microelectronics
G. D. Wilk is formerly of Bell Laboratories, Lucent Technologies; elec-
tronic mail: gwilk@agere.com industry to simultaneously meet several technological re-
b兲
Electronic mail: rwallace@unt.edu quirements to fuel market expansion. These requirements in-

0021-8979/2001/89(10)/5243/33/$18.00 5243 © 2001 American Institute of Physics

5244 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

clude performance 共speed兲, low static 共off-state兲 power, and (V D /L) along the channel direction. Initially, I D increases
a wide range of power supply and output voltages.1 This has linearly with V D and then eventually saturates to a maximum
been accomplished by developing the ability to perform a when V D,sat⫽V G ⫺V T to yield
calculated reduction of the dimensions of the fundamental
W 共 V G ⫺V T 兲 2
active device in the circuit: the field effect transistor I D,sat⫽ ␮ C inv . 共2兲
共FET兲—a practice termed ‘‘scaling.’’2–4 The result has been L 2
a dramatic expansion in technology and communications The term (V G ⫺V T ) is limited in range due to reliability
markets including the market associated with high- and room temperature operation constraints, since too large a
performance microprocessors as well as low static-power ap- V G would create an undesirable, high electric field across the
plications, such as wireless systems.5 oxide. Furthermore, V T cannot easily be reduced below
It can be argued that the key element enabling the scal- about 200 mV, because kT⬃25 mV at room temperature.
ing of the Si-based metal–oxide–semiconductor field effect Typical specification temperatures 共⭐100 °C兲 could there-
transistor 共MOSFET兲 is the materials 共and resultant electri- fore cause statistical fluctuations in thermal energy, which
cal兲 properties associated with the dielectric employed to iso- would adversely affect the desired the V T value. Thus, even
late the transistor gate from the Si channel in CMOS devices in this simplified approximation, a reduction in the channel
for decades: silicon dioxide. The use of amorphous, ther- length or an increase in the gate dielectric capacitance will
mally grown SiO2 as a gate dielectric offers several key ad- result in an increased I D,sat .
vantages in CMOS processing including a stable 共thermody- In the case of increasing the gate capacitance, consider a
namically and electrically兲, high-quality Si–SiO2 interface as parallel plate capacitor 共ignoring quantum mechanical and
well as superior electrical isolation properties. In modern depletion effects from a Si substrate and gate兲6
CMOS processing, defect charge densities are on the order of
1010/cm2, midgap interface state densities are ⬃1010/ ␬⑀ 0 A
C⫽ , 共3兲
cm2 eV, and hard breakdown fields of 15 MV/cm are rou- t
tinely obtained and are therefore expected regardless of the where ␬ is the dielectric constant 共also referred to as the
device dimensions. These outstanding electrical properties relative permittivity in this article兲 of the material,7 ⑀ 0 is the
clearly present a significant challenge for any alternative gate permittivity of free space (⫽8.85⫻10⫺3 fF/ ␮ m), A is the
dielectric candidate. area of the capacitor, and t is the thickness of the dielectric.
This expression for C can be rewritten in terms of t eq 共i.e.,
equivalent oxide thickness兲 and ␬ ox 共⫽3.9, dielectric con-
II. SCALING AND IMPROVED PERFORMANCE stant of SiO2兲 of the capacitor. The term t eq represents the
theoretical thickness of SiO2 that would be required to
The industry’s demand for greater integrated circuit achieve the same capacitance density as the dielectric 共ignor-
functionality and performance at lower cost requires an in- ing issues such as leakage current and reliability兲. For ex-
creased circuit density, which has translated into a higher ample, if the capacitor dielectric is SiO2, t eq⫽3.9⑀ 0 (A/C),
density of transistors on a wafer.3 This rapid shrinking of the and a capacitance density of C/A⫽34.5 fF/ ␮ m2 corresponds
transistor feature size has forced the channel length and gate to t eq⫽10 Å. Thus, the physical thickness of an alternative
dielectric thickness to also decrease rapidly. As will be dis- dielectric employed to achieve the equivalent capacitance
cussed in the next few sections, the current CMOS gate di- density of t eq⫽10 Å can be obtained from the expression
electric SiO2 thickness can scale to at least 13 Å, but there
are several critical device parameters that must be balanced t eq t high⫺ ␬
⫽
during this process. ␬ ox ␬ high⫺ ␬
The improved performance associated with the scaling
␬ high⫺ ␬ ␬ high⫺ ␬
of logic device dimensions can be seen by considering a or simply, t high⫺ ␬ ⫽ t eq⫽ t . 共4兲
simple model for the drive current associated with a FET.1 ␬ ox 3.9 eq
The drive current can be written 共using the gradual channel A dielectric with a relative permittivity of 16 therefore af-
approximation兲 as fords a physical thickness of ⬃40 Å to obtain t eq⫽10 Å. 共As

冉 冊
noted above, actual performance of a CMOS gate stack does
W VD not scale directly with the dielectric due to possible quantum
I D⫽ ␮ C inv V G ⫺V T ⫺ VD , 共1兲
L 2 mechanical and depletion effects.兲6
From a CMOS circuit performance point of view, a per-
where W is the width of the transistor channel, L is the chan- formance metric considers the dynamic response 共i.e., charg-
nel length, ␮ is the channel carrier mobility 共assumed con- ing and discharging兲 of the transistors, associated with a spe-
stant here兲, C inv is the capacitance density associated with cific circuit element, and the supply voltage provided to the
the gate dielectric when the underlying channel is in the in- element at a representative 共clock兲 frequency. A common
verted state, V G and V D are the voltages applied to the tran- element employed to examine such switching time effects is
sistor gate and drain, respectively, and the threshold voltage a CMOS inverter.1 This circuit element is shown in Fig. 1
is given by V T . It can be seen that in this approximation the where the input signal is attached to the gates and the output
drain current is proportional to the average charge across the signal is connected to both the n-type MOS 共nMOS兲 and
channel 共with a potential V D /2兲 and the average electric field p-type MOS 共pMOS兲 transistors associated with the CMOS
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5245

FIG. 1. Components used to test a CMOS FET technology. V DD and V S

serve as the source and drain voltages, respectively, and are common to the
NAND gates shown. Each NAND gate is connected to three others resulting
in a fanout of 3.

FIG. 2. FOM as a function of equivalent oxide thickness, t eq . Parasitic

stage. The switching time is limited by both the fall time capacitances and resistances result in transistor design tradeoffs to optimize
required to discharge the load capacitance by the n-FET performance.
drive current and the rise time required to charge the load
capacitance by the p-FET drive current. That is, the switch-
ing response times are given by1 dielectric capacitance. This can be seen in Fig. 2 where vari-
ous FOM calculations are plotted as a function of an
C LOADV DD ‘‘equivalent oxide thickness,’’ t eq , as described earlier.
␶⫽ , where C LOAD⫽FC GATE⫹C j ⫹C i ,
ID Each FOM calculation shown in Fig. 2 corresponds to
共5兲 specific assumptions on the values of parasitic capacitance
and C j and C i are parasitic junction and local interconnec- and gate sheet resistance, as indicated 共gate length is kept
tion capacitances, respectively. The ‘‘fan out’’ for intercon- constant in this analysis兲. Important aspects such as gate in-
nected devices is given by the factor ‘‘F.’’ Ignoring delay in duced drain leakage and reliability are ignored in this simple
gate electrode response, as ␶ GATEⰆ ␶ n,p , the average switch- model.1 Nevertheless, the result of the FOM calculation
ing time is therefore shown in Fig. 1 indicates that tradeoffs on all aspects of the

再 冎
transistor design and scaling, including parasitics, must be
␶ p⫹ ␶ n 1 carefully considered in order to increase the circuit
¯␶ ⫽ ⫽C LOADV DD n . 共6兲
2 I D ⫹I Dp performance.8
The load capacitance in the case of a single CMOS inverter
is simply the gate capacitance if one ignores parasitic contri- III. METAL–INSULATOR–SEMICONDUCTOR „MIS…
butions such as junction and interconnect capacitance. GATE STACK STRUCTURES
Hence, an increase in I D is desirable to reduce switching Figure 3 provides the reader a schematic overview of the
speeds. For more realistic estimates of microprocessor per- various regions associated with the gate stack of a CMOS
formance, the load capacitance is connected 共‘‘fanned out’’兲 FET 共regions are separated simply to clarify the following
to other inverter elements in a predetermined fashion. When discussion兲. The gate dielectric insulates the gate electrode
coupled with other NMOS/PMOS transistor pairs in the con- 共gate兲 from the Si substrate. Gate electrodes in modern
figuration shown in Fig. 1, one can create a logic ‘‘NAND’’ CMOS technology are composed of polycrystalline Si 共poly-
gate which can be used to investigate the dynamic response Si兲 which can be highly doped 共e.g. by ion implantation兲 and
of the transistors and thus examine their performance under subsequently annealed in order to substantially increase con-
such configurations. For example, in microprocessor esti- ductivity. The selection of the dopant species and concentra-
mates, a fan out of F⫽3 is often employed, as shown in
Fig. 1.1
One can then characterize the performance of a circuit
共based on a particular transistor structure兲 through this
switching time. To do this, various ‘‘figures of merit’’
共FOM兲 have been proposed which incorporate parasitic ca-
pacitance as well as the influence of gate sheet resistance on
the switching time.8 For example, a common FOM employed
is related to Eq. 共6兲 simply by
1 2
FOM⬵ ⫽ . 共7兲
¯␶ ␶ p ⫹ ␶ n
In the case where parasitics are ignored, it is easily seen
then that an increase in the device drive current I D results in
a decrease in the switching time and an increase in the FOM
value 共performance兲. Even in this simple model, however,
the incorporation of parasitic effects, results in the ‘‘clamp-
ing’’ of FOM improvement, despite an increase in the gate FIG. 3. Schematic of important regions of a field effect transistor gate stack.
5246 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

FIG. 4. Energy-band diagrams and associated high-

frequency C – V curves for ideal MIS diodes for 共a兲
n-type and 共b兲 p-type semiconductor substrates. For
these ideal diodes, V⫽0 corresponds to a flatband con-
dition. For dielectrics with positive (⫹Q f ) or negative
(⫺Q f ) fixed charge, an applied voltage (V FB) is re-
quired to obtain a flatband condition and the corre-
sponding C – V curve shifts in proportion to the fixed
charge. 共after Refs. 9 and 10兲.

tion permits the adjustment of the poly-Si Fermi level for

either nMOS or pMOS FETs. Metals can also be used as the
gate electrode, and, in fact, are commonly used for evalua-
⌽ MS⫽⌽ M⫺ ␹ ⫹冉 Eg
2q
⫹⌿ B ⫽0;冊 p-type, 共8兲

tion of capacitor structures. Work is underway to find suit- where ⌽ M is the metal work function, ␹ is the semiconductor
able metal gates for CMOS 共see Sec. VI E兲. electron affinity, E g is the semiconductor band gap, ⌽ B is the
The interfaces with either the gate or the Si channel re- potential barrier between the metal and dielectric, and ␺ B is
gion are particularly important in regard to device perfor- the potential difference between the Fermi level E F and the
mance. These regions, ⬃5 Å thick, serve as a transition be- intrinsic Fermi level, E I . Under these conditions, the energy
tween the atoms associated with the materials in the gate bands are flat across the structure as shown in Fig. 4 and V
electrode, gate dielectric and Si channel. As will be dis- ⫽V FB⫽0, where V FB is the flat band voltage 共i.e., the volt-
cussed, these interface regions can alter the overall capaci- age required to bring the Fermi levels into alignment兲. A
tance of the gate stack, particularly if they have a thickness more typical case is that the Fermi levels of the electrode and
which is substantial relative to the gate dielectric. Addition- substrate are misaligned by an energy difference, and a volt-
ally, these interfacial regions can be exploited to obtain de- age (V FB⫽0) must be applied to bring the Fermi levels into
sirable properties. The upper interface, for example, can be alignment.
engineered in order to block boron outdiffusion from the p ⫹ Many dielectrics exhibit a fixed charge (Q f ), however,
poly-Si gate. The lower interface, which is in direct contact resulting in a required applied voltage V⫽V FB⫽0 to achieve
with the CMOS channel region, must be engineered to per- a flat band condition. The amount of fixed charge can be
mit low interface trap densities 共e.g. dangling bonds兲 and related to the measured V FB value by the expression9
minimize carrier scattering 共maximize mobility兲 in order to
obtain reliable, high performance. V FB⫽⌽ MS⫾Q f /C acc , 共9兲
It is instructive to consider the band diagrams for the where C acc is the measured capacitance in accumulation.
MIS structures discussed in this review. Figure 4 shows the Thus, a value for fixed charge density Q f can be determined
energy-band diagrams for ideal MIS diode structures using from measured values of V FB , ⌽ MS and C acc . The sign of
共a兲 n-type and 共b兲 p-type semiconductor substrates.9,10 For the fixed charge is also important, as negative fixed charge
these ideal structures, at V⫽0 applied voltage on the metal correlates with the plus sign in Eq. 共9兲, and positive fixed
gate, the work function difference between the metal and charge correlates with the minus sign. These expressions will
semiconductor, ⌽ MS , is zero be discussed further in Sec. V C 2.

冉 冊
The source of such fixed charge, often though not always
Eg positive, is thought to originate from the detailed bonding of
⌽ MS⫽⌽ M⫺ ␹ ⫹ ⫺⌿ B ⫽0; n-type
2q the atoms associated with the dielectric near the dielectric/
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5247

semiconductor interface. Several proposed explanations for An earlier ab inito model by Tang et al.13 of extremely
the cause of the observed fixed charge will be discussed in thin SiO2, which was modeled as a modified beta-
Sec. V C 2. Figure 4 shows that for positive Q f , a negative cristoballite phase, showed an important result, in that the
shift in the V FB from ideal conditions 共where V⫽0兲 is re- band gap of SiO2 did not begin to decrease until there were
quired for both n-type and p-type MIS structures. Similarly, fewer than three monolayers of oxide. Moreover, estimates
a positive V FB is required for negative Q f . of the changes in the associated conduction and valance band
Most of the alternate dielectric candidates examined to offsets for these systems indicated that a minimum of 7 Å of
date appear to have a substantial amount of fixed charge, SiO2 is required to obtain bulk properties. The recent first
which could present significant issues for CMOS applica- principles study by Neaton et al.14 determined that the local
tions. Given the scaling limitations on applied voltages due
energy gap in SiO2 is directly related to the number of O
to power consumption, shifts in the V FB value are undesir-
second nearest neighbors, for a given O atom. The last row
able and must be minimized. In some applications, biasing
of O atoms 共next to the Si substrate兲 by definition cannot
the substrate to compensate for the fixed charge has been
have the full six nearest neighbor O atoms. The second row
proposed.5 Moreover, a reproducible V FB 共correspondingly
V T for transistors兲 value is also required for stable, reliable of O atoms from the Si interface is thus the first layer of O
transistor operation. Thus, hysteretic changes in the V FB from atoms that have the required six second-nearest neighbor O
voltage cycling of less than 20 mV are often required. atoms. The distance required to obtain the full band gap of
Some dielectrics which incorporate aluminum, however, SiO2 at each interface is therefore given by 1.6 Å 共the spac-
thus far suggest that a negative fixed charge is present. It has ing of one Si–O bond length兲 ⫹2.4 Å 共the distance between
been recently proposed to combine Al ions with some alter- neighboring O atoms is 2.7 Å, but this is variable because of
nate dielectric candidates in order to compensate positive Si–O bond bending. The distance is typically in the range
and negative fixed charges to achieve a neutral state or, at ⬃2 to 2.4 Å兲. The thickness at each interface required for the
least, minimize such fixed charge effects.11 If fixed charge is full SiO2 band gap is therefore ⬃3.5–4.0 Å. Counting both
determined to be large and difficult to minimize and control interfaces, the total thickness of 7–8 Å is required, in agree-
in high-␬ dielectrics, it will be a significant issue for obtain- ment with Tang et al.13 and with the experiment.12 These
ing the desired device performance on both nMOS and results set an absolute physical thickness limit of SiO2 of 7
pMOS transistors. The magnitude of measured V FB shifts for Å. Below this thickness, the Si-rich interfacial regions from
many alternate dielectrics will be discussed later. the channel and polycrystalline Si gate interfaces used in
MOSFETs overlap, causing an effective ‘‘short’’ through the
dielectric, rendering it useless as an insulator.
The agreement between the experiment and simulation
in these cases indicates that the inherent band gap of SiO2
IV. SCALING LIMITS FOR CURRENT GATE
DIELECTRICS remains intact, even down to only a few monolayers of ma-
terial. Other important properties of SiO2 have been reported
The previous sections outlined the need to scale oxide in the ultrathin, sub-20 Å regime, such as the conduction
thicknesses to improve performance. The next two sections band offset ⌬E C to Si 关using x-ray photoelectron spectros-
describe the present understanding in the field regarding the copy 共XPS兲兴,16 the tunneling electron effective mass m *
limits of scaling current gate dielectric materials, SiO2 and 共from tunneling I – V measurements兲,17 and the photoelectron
Si-oxide-nitride variations, for CMOS. Issues include band attenuation length.18 These measurements have further dem-
offset, interfacial structure, boron penetration and reliability. onstrated very little change in fundamental SiO2 properties
Beyond this scaling limit, another material will be required between bulk and ultrathin sub-20 Å films.
as the gate dielectric to allow further CMOS scaling. The apparent robust nature of SiO2, coupled with indus-
A. Ultrathin SiO2 properties try’s acquired knowledge of oxide process control, has
helped the continued use of SiO2 for the past several decades
Experiments and modeling have been done on ultrathin in CMOS technology. As experimental evidence of the ex-
SiO2 films on Si, as a way to determine how the SiO2 band
cellent electrical properties of such ultrathin SiO2 films, it
gap or band offsets to Si change with decreasing film
has been demonstrated that transistors with gate oxides as
thickness.12–15 In the study by Muller et al.,12 electron en-
thin as 13–15 Å continue to operate satisfactorily.19–24 Al-
ergy loss spectroscopy 共EELS兲 was carried out on 7–15 Å
SiO2 layers on Si. It was found that the density of states 共as though high leakage current densities of 1–10 A/cm2 共at
measured by the oxygen K-edge in EELS, with a probe reso- V DD兲 are measured for such devices,25 transistors intended
lution ⬍2 Å兲 transition from the substrate into the SiO2 layer for high-performance microprocessor applications can sus-
indicated that the full band gap of SiO2 is obtained after only tain these currents. As first reported by Timp et al.20–22 scal-
about two monolayers of SiO2. This indicates that within two ing of CMOS structures with SiO2 gate oxides thinner than
monolayers of the Si channel interface, oxygen atoms do not about 10–12 Å results in no further gains in transistor drive
have the full arrangement of oxygen neighbors and therefore current. This result has been subsequently and independently
cannot form the full band gap that exists within the ‘‘bulk’’ reported by other groups, thus 10–12 Å could serve as a
of the SiO2 film. practical limit for reducing the SiO2 thickness.23,24,26
5248 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

ing must be ‘‘accelerated’’ at higher voltages and tempera-

tures than are actually experienced by typical devices. Mak-
ing reliability projections from accelerated to actual
conditions requires proper scaling for area 共from one device
area to an entire chip area兲, voltage, temperature, and the
failed fraction of devices.27,32 Recent results by Stathis
et al.,31 Weir et al.,25 and Nicollian et al.33 show that ex-
trapolations of reliability factors, such as the critical defect
共trap兲 density, with voltage scaling changes dramatically at
lower voltages, such as those used for testing oxides ⬍20 Å
thick. This realization of the change in voltage scaling be-
havior at low voltages is the largest factor contributing to the
improved reliability projections described earlier. In addi-
tion, improved macroscopic oxide uniformity across the wa-
FIG. 5. Power consumption and gate leakage current density for a chip
which has a 15 Å thick SiO2 gate dielectric compared to the potential re- fer and wafer-to-wafer has also been shown to give more
duction in leakage current by an alternate dielectric exhibiting the same accurate reliability projections.25,34 This analysis should not
equivalent oxide thickness. Assumes at total gate area of 0.1 cm2. be misinterpreted as meaning that the oxide reliability itself
is improved. Rather, the reliability projection becomes more
accurate 共regardless of whether the projection is for good or
In contrast to the high performance microprocessor mar- poor oxide reliability兲 with higher macroscopic oxide
ket, the rapidly growing market of low-power applications uniformity.35 Improving microscopic oxide uniformity
requires transistors with much lower (⬃10⫺3 A/cm2) leak- should further produce more accurate reliability projections,
age currents.5 This is illustrated in Fig. 5, where the current according to simulation.36 It has also been demonstrated that
density and standby power consumption are plotted as a making reliability measurements on a large number of
function of gate voltage. The curve for 15 Å oxide is based samples is important for obtaining better breakdown statis-
on measured values,17 but the curve for a high-␬ film is tics and accurate projections.34
meant to show the potential reduction in leakage current for A fundamental mechanism for oxide breakdown in this
a high-␬ dielectric with the same t eq value. Depending on the ultrathin SiO2 regime was first reported by DeGraeve
specific materials and conditions, leakage current reduction et al.37,38 as a percolation model. This model describes ultra-
may be less than shown. It is clear that a gate dielectric with thin oxide breakdown as the buildup of many ‘‘defects’’
a permittivity higher than that of SiO2 is required to meet within the SiO2 layer, where after a certain amount of stress
low-power application requirements. 共either constant voltage or constant current through the oxide
at a given temperature兲, a complete path of defects form
B. Ultrathin SiO2 reliability across the oxide thickness.37 This point defines breakdown or
An equally important issue regarding ultrathin SiO2 gate failure of the oxide. While there is general agreement on the
oxides has been understanding and predicting oxide reliabil- percolation model for oxide breakdown, the defects which
ity. Considerable debate existed over whether SiO2 gate ox- act as precursors to breakdown are not defined or specified.
ides ⬍22–27 Å thick would exhibit the stringent ten year The mechanism which leads to the creation of these defects
reliability criteria,27 which is required for CMOS devices. is under debate, and has been proposed as an anode hole
The first report of a sub-20 Å SiO2 gate oxide to meet reli- injection model36,39 and a hydrogen release model.40,41
ability requirements was given by Weir et al.,25 where a 16 It is also important to distinguish between previously
Å oxide was shown to have reliability projections at 1.6 V reported leakage current projections by simulation for oxide
operation for greater than ten years. This is much thinner thicknesses measured in accumulation, and the presently ac-
than projected even three to five years ago.28,29 The high cepted methods.25,31,33 Extrapolated leakage current versus
reliability of ultrathin oxides suggests that there is no intrin- gate oxide thickness data from three to five years ago was
sic 共i.e., not limited by intrinsic defects or thickness varia- valuable at the time, when sufficient data for oxides ⬍16 Å
tions兲 reliability limitation to SiO2 layers at least down to was not available. Caution should be used, however, when
thicknesses of about 16 Å. In fact, more recent projections referring to such extrapolations now,42 as data from more
indicate that oxides down to 14 Å 共as measured by ellipsom- recent measurement methodology must be adopted for useful
etry兲 at 1.4 V operating voltage will meet ten year reliability comparisons. Much of the understanding for ultrathin oxides
requirements.30 Several independent groups have also re- have come about only in the past five years, despite decades
cently reached similarly encouraging reliability projections of research on SiO2. This suggests that understanding the
for such thin SiO2 gate oxides.26,31 Other extrinsic reliability reliability and failure mechanisms in high-␬ dielectrics will
factors, however, such as particles or contaminants, could require significant effort, especially if any material is to re-
still yield an ultimately poorer oxide reliability. place SiO2 within five years, as most roadmaps suggest.
Part of the difficulty in making reliability projections
C. Boron penetration and surface preparation
arises from the difference between test conditions and oper-
ating conditions. It is clearly not feasible to test individual In addition to leakage current increasing with scaled ox-
devices for ten years prior to product incorporation, thus test- ide thickness, the issue of boron penetration through the ox-
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5249

ide is a significant concern. The large boron concentration contrast, improved electrical properties have been obtained
gradient between the heavily doped poly-Si gate electrode, by using various oxynitrides. Yang and Lucovsky demon-
the undoped oxide and lightly doped Si channel causes boron strated that an oxynitride alloy with a 1:1 ratio of SiO2 :Six Ny
to diffuse rapidly through a sub-20 Å oxide upon thermal can achieve t eq⬍17 Å with a leakage current of
annealing, which results in a higher concentration of boron ⬃10⫺3 A/cm2 at 1.0 V bias.56 This leakage current is
in the channel region. A change in channel doping then ⬃100⫻ lower than that for a pure SiO2 layer of the same
causes a shift in threshold voltage, which clearly alters the thickness, and the leakage reduction arises from both a
intended device properties in an unacceptable way.43 As will physically thicker film and from a small amount of N at the
be discussed in the next section, incorporating nitrogen into channel interface. Song et al.59 have also shown that a proper
the oxide can greatly reduce boron diffusion. choice of thermal processing steps using a NO passivation
Some approaches to enhance performance have also fo- layer, Six Ny deposition with SiH4 and NH3 and further an-
cused on surface preparation as a way to provide a flatter, neals in NH3 and N2O can achieve oxynitride layers with
more uniform Si interface in attempts to minimize electron t eq⫽18 Å and a leakage current density of 10⫺4 A/cm2 at 1.0
channel mobility degradation 共due to scattering at the inter- V bias. Guo and Ma60 have reported results with jet vapor
face兲 and gate leakage.44,45 Growing or depositing sub-15 Å deposited nitrides demonstrating t eq⫽15 Å with a leakage
oxides has also been investigated as a potential means for current density of J⬃10⫺4 A/cm2 at 1.0 V.
producing high-quality, reproducible and uniform gate ox- Despite these encouraging results from a variety of
ides, either for use as the gate dielectric or as the bottom deposition and growth techniques, scaling with oxynitrides/
layer of a dielectric stack.46,47 Obtaining high-quality oxides nitrides appears to be limited to t eq⬃13 Å. 61 Below this, the
in this thickness regime is challenging, because intrinsic pin- effects of gate leakage, reliability or electron channel mobil-
hole formation has been reported in ultrathin SiO2 films.48–50 ity degradation will most likely prevent further improve-
Perhaps the most significant benefit resulting from the ments in device performance. According to the most recent
incorporation of an alternative gate dielectric with a relative industry roadmaps, SiOx Ny and Six Ny /SiO2 dielectrics rep-
permittivity higher than SiO2 is the dramatic reduction in the resent current three year near-term solutions for scaling the
off-state tunneling 共leakage兲 current which is observed in CMOS transistor.5
devices using ultrathin SiO2 gate dielectric films. Thus, the
area of alternative gate dielectrics has gained considerable E. Fundamental limitations
attention recently because technology roadmaps predict the Despite the current efforts with SiO2, oxynitrides and
need for a sub-20 Å Si-oxide gate dielectric for sub-0.1 ␮m even high-␬ gate dielectrics, several potential fundamental
CMOS.4,5 limitations could seriously threaten the continued scaling of
all gate dielectrics, regardless of the material.26 First, the
D. SiOx Ny and Si–NÕSiO2 dielectrics
electrical thickness of any dielectric is given by the distance
The concerns regarding high leakage currents, boron between the centroids of charge in the gate and the substrate.
penetration and reliability of ultrathin SiO2 have led to ma- This thickness, typically denoted by t eq , therefore includes
terials structures such as oxynitrides and oxide/nitride stacks the effective thickness of the charge sheet in the gate and the
for near-term gate dielectric alternatives. These structures inversion layer in the substrate 共channel兲. These effects can
provide a slightly higher ␬ value than SiO2 共pure Si3N4 has add significantly to the expected t eq derived from the physi-
␬ ⬃7兲 for reduced leakage 共since the film is physically cal thickness of the dielectric alone.6 Depletion in the poly-Si
slightly thicker兲, reduced boron penetration and better reli- gate electrode arises from the depletion of mobile charge
ability characteristics.51–53 The addition of N to SiO2 greatly carriers in the poly-Si near the gate dielectric interface, par-
reduces boron diffusion through the dielectric, and has been ticularly in the gate bias polarity required to invert the chan-
shown to result from the particular Si–O–N network bond- nel. The result is often that ⬃3–4 Å in the poly-Si electrode
ing formed in silicon nitride and oxynitride.54,55 Furthermore, nearest to the gate dielectric interface essentially behaves
small amounts of N 共⬃0.1 at. %兲 at or near the Si channel like intrinsic Si, which adds ⬃3–4 Å to the effective dielec-
interface have been shown to improve device performance.56 tric thickness 共rather than acting as a metal with a Fermi sea
Larger amounts of N near this interface degrade device per- of electrons right up to the dielectric interface兲. In the best
formance, as discussed later. case, the electrode depletion region can be reduced to ⬃1–2
The simplest approach is to use a pure nitride layer at or Å for degenerately doped poly-Si electrode right up to the
near the channel interface, but device performance is typi- interface, but this is difficult to obtain.
cally degraded in these structures. Recent work using remote The nature of the inversion charge layer in the Si sub-
plasma enhanced chemical vapor deposition 共PECVD兲 to de- strate 共or channel, for transistors兲 contributes about 3–6 Å to
posit Si-nitride directly on the Si channel57 resulted in poor the effective t eq value, thus even for ideal, degenerately
pMOS performance, with significant degradation of channel doped poly-Si gates, it is difficult to realize an overall t eq
mobility and drive current. This degradation is attributed to ⬍10 Å in MOSFETs using current process technology.
several factors, including excess charge of pentavalent nitro- Metal gates offer a possible solution to the gate depletion
gen atoms, a high defect density arising from bonding con- problem, but the addition of 3–6 Å to the t eq value from the
straints imposed at the interface58 共which causes increased Si channel will remain. We note that most of the high-␬
channel carrier scattering兲, and from the defect levels in the dielectrics discussed later in this review are measured on
Si-nitride layer which reside near the valence band of Si. In capacitors and transistors with metal gates. Although metal
5250 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

gates are convenient for obtaining properties of the dielec-

tric, current CMOS technology does not use metal gates.
Therefore, for a given high-␬ dielectric, any realistic device
using current CMOS processing techniques should exhibit a
t eq value 4–8 Å larger than that reported in this review 共ex-
cept where poly-Si gates are noted as being used, and where
no quantum mechanical correction has been performed兲.
Second, the ideal scaling scenario is one in which the
operating voltage and transistor dimensions are reduced by
the same factor, thus maintaining a constant electric field
across the gate dielectric for a given technology node. In
practice, however, the feature dimensions have been reduced FIG. 6. Cross-sectional TEM image of a vertical replacement gate transistor,
more rapidly than the operating voltage, thereby causing a with a 50 nm gate length and 25 ÅSiO2 gate oxide 共as measured by ellip-
rapidly increasing electric field across the gate dielectric. The sometry兲 共see Ref. 63兲. © 2000 IEEE, reprinted with permission from IEEE.
continually decreasing t eq value for scaling CMOS also in-
creases the effective electric field in the channel region. This transmission electron microscopy 共TEM兲 image of a VRG
increased electric field pulls the carriers in the channel closer device with parallel 50 nm gate lengths and 25 Å gate oxides
against the dielectric interface, which causes increased pho- 共as measured by ellipsometry兲 and a single crystal, epitaxi-
non scattering of more confined carriers and thereby de- ally grown Si body.62 As an example of the potential for
creases the channel carrier mobility. At very high electric increased performance with thicker gate oxides, VRG tran-
fields in the channel, such as would exist for t eq⬍10 Å, in- sistors with 100 nm gate lengths, 25 Å gate oxides, and
terface roughness scattering further reduces carrier mobility. operating voltage 1.5 V have shown an 80% increase in drive
Thus, for t eq⬍10 Å, the combination of these deleterious current63 compared to that required by the SIA Roadmap 共at
effects may result in not only reducing the expected perfor- the same off current兲 using much thinner, sub-20 A oxides.
mance increase for a given increase in gate capacitance, but High-performance planar devices reported to date have
may indeed even decrease device performance at fixed sup- shown only about 20% increase in drive current compared to
ply voltage. If this effect on channel mobility is in fact real- that of the roadmap, under comparable operating
ized, then it may be the case that no dielectric will be accept- conditions.23,24 For 50 nm gate length devices and 1.0 V
able in the required t eq range 共since this effect depends only operation, VRG transistors have been demonstrated to meet
on t eq , not on the material兲. the requirements of the roadmap, while still using 25 Å gate
oxides.63 In contrast, no reported planar CMOS devices to
F. Device structures
date have been able to even approach the drive current and
In addition to ongoing work in scaling gate dielectrics, off-current roadmap requirements for 50 nm gate length, 1.0
there is also a substantial amount of research being con- V operation.
ducted toward obtaining a device structure for CMOS, such These device approaches to stave off CMOS scaling will
that the demand for scaling SiO2 or oxynitrides 共and lithog- continue in parallel with investigations into high-␬ gate di-
raphy兲 will be somewhat alleviated. In particular, efforts electrics. One of these structures may ultimately prove to be
have been focused on structures such as vertical a viable replacement for the planar, bulk CMOS transistor
transistors,62–65 and double gate planar transistors.66–68 The and retard the need to scale SiO2 gate oxides. Most device
premise of double gate transistors arises from the potential of structures under consideration therefore will not immediately
achieving nearly twice the drive current over a planar, bulk suffer from the limitations discussed in the previous section,
CMOS device for a given channel length. Alternatively, a because a thicker gate oxide reduces the effects of dopant
nearly equal drive current could be produced while using a depletion in the poly-Si gate electrode, as well as reduces the
SiO2 layer that is twice the thickness as that required in the electric field present in the channel region. Since these del-
planar geometry 共and thereby meet roadmap performance re- eterious effects become amplified as the gate oxide thickness
quirements with a much thicker gate oxide兲. This potential decreases, even device structures would eventually suffer
gain from a double gate device is explained simply by the from these degradation mechanisms, but in the meantime
fact that there are two parallel, aligned channels operating would afford more time to find other solutions to these prob-
simultaneously, compared to one channel in a standard, pla- lems. In this case, high-␬ dielectrics can be combined with
nar bulk device. these device structures to further improve performance and
One particularly promising vertical transistor uses a ver- power consumption.
tical replacement gate 共VRG兲 structure,62 where standard
V. ALTERNATIVE HIGH-␬ GATE DIELECTRICS
CMOS processes are used in an innovative way to remove
the lithography constraint for defining the gate length. In- As an alternative to oxide/nitride systems, much work
stead, a deposited oxide layer thickness defines the gate has been done on high-␬ metal oxides as a means to provide
length, which can thus be easily controlled below 50 nm. a substantially thicker 共physical thickness兲 dielectric for re-
This dummy oxide layer can then be etched away, followed duced leakage and improved gate capacitance. In the search
by growth and deposition of the gate oxide and poly-Si gate to find suitable high-␬ gate dielectrics for use beyond oxyni-
electrode, respectively. Figure 6 shows a cross-sectional tride systems, several approaches have been used in fabricat-
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5251

ing potential materials candidates. The following sections re-

view the current status of work in this field. We also describe
the materials properties considerations that are necessary for
determining the best high-␬ candidate to replace SiO2 as the
gate dielectric for CMOS. It is important to note that we do
not compile all of the relevant, measured electrical and
physical characteristics on high-␬ materials into one table.
Although a table format can be helpful for organizational
purposes, at the present time for high-␬ gate dielectrics, it is
too cumbersome 共and potentially misleading兲 to attempt to
provide all of the proper caveats 共e.g., leakage current values
for the same material system can vary widely depending on
surface preparation, deposition method and conditions, gate
electrode type, bias voltage ramp rate, stated bias for a given
current 共J@V bias⫽1 V, or V FB⫹1 V, etc.兲.
A. High-␬ candidates from memory applications
FIG. 7. Reaction at the Ta2O5 /Si interface is observed resulting in the
Many of the materials initially chosen as potential alter- formation of a thin SiO2 layer 共see Ref. 75兲.
native gate dielectric candidates were inspired by memory
capacitor applications42 and the resultant semiconductor
manufacturing tool development infrastructure. and Si, as well as to help maintain a high channel carrier
The most commonly studied high-␬ gate dielectric can- mobility.
didates have been materials systems such as Ta2O5, 68–78 It is important to note, however, that using an interfacial
SrTiO3, 79–84 and Al2O3, 85–95 which have dielectric constants layer of SiO2 or another low permittivity material, will limit
ranging from 10 to 80, and have been employed mainly due the highest possible gate stack capacitance, or equivalently,
to their maturity in memory capacitor applications. With the the lowest achievable t eq value 关see Eq. 共4兲兴. In addition, the
exception of Al2O3, however, these materials are not thermo- increased process complexity for the deposition and control
dynamically stable in direct contact with Si 共this thermody- of additional ultrathin dielectric layers, as well as scalability
namic stability is not a requirement for memory capacitors, to later technology nodes, remains a concern.
since the dielectric is in contact with the electrodes, which This effect of reduced capacitance can be seen by noting
are typically nitrided poly-Si or metal兲. An excellent and that when the structure contains several dielectrics in series,
thorough review on the Ta2O5 system, for both memory ca- the lowest capacitance layer will dominate the overall ca-
pacitance and also set a limit on the minimum achievable t eq
pacitor and transistor applications, has been given by Chane-
value. For example, the total capacitance of two dielectrics in
liere et al.77 The Ta2O5 system is known to exhibit Frenkel–
series is given by
Poole and Schottky transport mechanisms, depending on bias
polarity, under typical voltage bias conditions. The mecha- 1/C tot⫽1/C 1 ⫹1/C 2 , 共10兲
nisms for relaxation or transient current of Ta2O5 have re- where C 1 and C 2 are the capacitances of the two layers,
cently been attributed to a defect band near the conduction respectively. If one considers a dielectric stack structure such
band in thin Ta2O5 films, which allows ac transient conduc- that the bottom layer 共layer 1兲 of the stack is SiO2, and the
tion leakage that follows a widely observed power law top layer 共layer 2兲 is the high-␬ alternative gate dielectric,
decay.78 Eq. 共4兲 is simplified 共assuming equal areas兲 to
Interfacial reaction, seen in Fig. 7, has been observed for
the case of Ta2O5 on Si,75 as is expected based on thermo- t eq⫽t SiO2⫹ 共 ␬ ox / ␬ high- ␬ 兲 t high- ␬ . 共11兲
dynamic arguments discussed later and in agreement with It is clear from Eq. 共11兲 that the minimum achievable
previous work in dynamic random-access memory capacitor equivalent oxide thickness 关defined as t eq in Eq. 共11兲兴 will
applications.76 As evidenced by these studies, the earlier- never be less than that of the lower-␬ 共in this case pure SiO2兲
mentioned metal oxides require that both the gate electrode layer. Therefore, much of the expected increase in the gate
and the channel interfaces be modified to limit the amount of capacitance associated with the high-␬ dielectric is compro-
reaction. mised. The implications of current transport through such
Interface engineering schemes have been developed to stacked structures will be considered further later.
form oxynitrides and oxide/nitride reaction barriers between The largest benefit of using SiO2 as the underlayer of a
these high-␬ metal oxide materials and Si in an attempt to stack 共at the Si channel interface兲 is that the unparalleled
prevent or at least minimize reaction with the underlying quality of the SiO2 – Si interface will help maintain a high
Si.69–74 The passivating properties of such reaction barriers is channel carrier mobility. The prospect of using such SiO2
widely reported.94 In most cases, this amounts to further interface layers was examined by Kizilyalli and Roy.70,71 In
scaling the approaches used to form oxynitrides, discussed in that work, a Ta2O5 film was sandwiched between SiO2 layers
the previous section. These barrier layers have been shown to located at the substrate and gate 共poly-Si兲 interfaces. The
reduce the extent of reaction between the high-␬ dielectric SiO2 /Si substrate interface layer was formed by a low pres-
5252 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

activation anneals were accomplished with a relatively low

temperature 共600–800 °C兲 rapid thermal anneal process, pre-
sumably to avoid crystallization of the Ta2O5 layer and to
prevent further SiO2 formation at the interfaces within the
constraints of a conventional CMOS process flow.70,71 An
interface state density (D it) comparable to transistors incor-
porating only SiO2 as the gate dielectric was observed based
on subthreshold slope measurements. The effective dielectric
thickness estimate from the transistor transconductance and
drain current measurements results in a larger value, ⬃30 Å.
The 20% discrepancy with the MIS capacitor C – V measure-
ments was attributed to partial dopant activation 共from the
relatively low temperature anneal process兲. Some degrada-
tion in mobility, relative to SiO2, was also measured. As
expected, leakage currents were well below 1 A/cm2 as a
result of the physically thicker dielectric.
It is essential at this point to distinguish between the
requirements for memory42 and transistor applications.
Memory capacitors require extremely low leakage currents
共typically J⬍10⫺8 A/cm2兲 and very high capacitance density
for charge storage, but the interface quality is not as critical.
Memory capacitor applications require control of the inter-
face primarily to limit interfacial reactions to keep the total
capacitance high. Since the main requirement is that the ca-
pacitors store charge, however, current transport along the
dielectric interface is not important. Furthermore, no electric
field penetration is required below the bottom electrode, so
the bottom electrode is often metal, or nitrided poly-Si
共heavily doped兲. All of the requirements amount to the im-
portant distinction that the bottom dielectric interface quality
FIG. 8. 共a兲 Drain current and transconductance for long channel PMOS is not as critical to capacitor performance.
transistors incorporating a SiO2 /Ta2O5 /SiO2 dielectric stack 共see Ref. 70兲. In contrast, a key requirement of a FET is that the elec-
共b兲 Comparison of drain current drive and saturation characteristics.
tric field penetrate into the Si channel to modulate carrier
transport, and that the dielectric-channel interface be of very
high quality. The channel must of course be Si, so any po-
sure 共850 mTorr兲 thermal anneal at 850 °C in O2, resulting in tential high-␬ dielectric must be compatible with Si. Transis-
a ⬃10-Å-thick oxide layer. A Ta2O5 layer was then depos- tors have more lenient leakage requirements 共⬍102 A/cm2
ited by 共CVD兲, followed by a 10 Å capping layer of CVD for high-performance processors, and ⬃10⫺3 A/cm2 for low-
SiO2. The entire structure was then reoxidized in O2 or N2O power applications兲, although high capacitance densities are
at 650 °C and 850 mTorr. Given the stacked structure of the still needed. The most critical distinction between high-␬
dielectric, the total capacitance of the stack will be dimin- materials requirements for capacitors versus gate dielectrics
ished by the presence of the two lower-permittivity layers. is the interface and materials compatibility: gate dielectrics
For the Ta2O5 sandwich,70,71 using Eq. 共11兲 for the must form an extremely high-quality interface with Si, and
Ta2O5 layer 共t⬇50– 60 Å, ␬ ⬇20– 30), an equivalent oxide also be able to withstand CMOS processing conditions while
thickness t eq⫽10⫹10⫹(3.9/␬ )t⫽25– 30 Å is expected. The in contact 共or near contact兲 with Si.
experimentally determined value from capacitance–voltage
B. Issues for interface engineering
(C – V) measurements was in good agreement with this esti-
mate: 23 Å. No charge trapping was observed in the C – V It is well known that the industry roadmap presents a
experiments, as evidenced by a lack of hysteresis. This study major problem for the core transistor gate dielectric, because
is an important attempt to demonstrate the feasibility of in- it calls for a much thinner effective thickness for future al-
tegrating Ta2O5 into a standard CMOS process, but it is clear ternative gate dielectrics: t eq⭐10 Å. 4,5 This would then re-
that the presence of a SiO2 layer 共or any low-␬ layer兲 at quire the SiO2 layer to be ⬃5 Å thick. Such an extremely
either interface limits the ultimate device performance. thin SiO2 layer is very difficult to obtain with high quality.22
Long channel transistor measurements utilizing this The resulting voltage drop across the oxide could also lead to
stack were also made using poly-Si gates and WSix contacts, significant charge trapping in the film, especially since the
as shown in Fig. 8. Figure 8共a兲 shows drain current and interface between such stacked dielectrics may almost cer-
transconductance for long-channel PMOS transistors as a tainly contain a large density of traps. Furthermore, such a
function of gate voltage, and Fig. 8共b兲 shows a comparison thin interface layer most likely will not prevent reaction be-
of drain current drive and saturation characteristics. Dopant tween the substrate and any high-␬ material which is not
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5253

FIG. 9. Comparison of stacked and single layer gate dielectrics in a hypo-

thetical transistor gate stack. Either structure results in the same overall gate
stack capacitance or equivalent oxide thickness, t eq⫽10 Å.

thermodynamically stable to SiO2 formation on Si, under

standard thermal processing required for CMOS 共previously
FIG. 10. Transistor results for effective gate length L eff⫽1.3 ␮ m which
discussed pinhole formation in ultrathin SiO2 is also a incorporate a high-␬ SrTiO3 gate dielectric 共see Refs. 82–84兲.
concern兲.48
To illustrate this point, an example for obtaining a di-
electric stack with t eq⫽10 Å is considered in Fig. 9. One
way to achieve this would be to use 5 Å of SiO2(t eq⫽5 Å) In the study by Eisenbeiser et al., TaN gate electrodes
as the lower 共first兲 layer, at the Si interface, and 30 Å of a were used, and devices exhibited t eq⬇8 Å 共with quantum
dielectric with ␬ ⫽25 (t eq,high- ␬ ⬃5 Å) as the upper 共second兲 mechanical correction to the C – V data兲 with a leakage cur-
layer. Even for low applied voltages, such a thin layer will rent density J⬃10⫺2 A/cm2 at 1 V bias, for a 110 Å physi-
have a large enough electric field to create a significant cally thick SrTiO3 film.82 Transistors with a 1.2 ␮m effective
amount of charge trapping. In addition, an oxide layer this channel length showed electron and hole mobilities of 221
thin will allow a large amount of direct electron tunneling and 62 cm2/V s, respectively. Device characteristics are
into the high-␬ dielectric, likely causing further deleterious shown in Fig. 10, with a subthreshold slope of 103 mV/
effects to the electrical performance of the stack. decade for n-channel devices, 95 mV/decade for p-channel
It is important to note, however, that if a single layer devices. The extracted interface state density showed a low
dielectric can be used, then t eq⫽10 Å can be achieved with D it⬃6⫻1010/cm2, but the fixed, low work function (⌽ B
40 Å 共physical thickness兲 of a material which only has a ⫽4.2 eV) of the TaN gates produced undesirable threshold
moderate permittivity of ␬ ⫽16 共see Fig. 9兲. This physical voltages for p-channel devices.82 Figure 11 shows that the
thickness is greater than the total physical thickness of the dielectric deposition process can cause interfacial reaction to
stack in the earlier example 共⫽35 Å兲, even though the per- occur with Si, resulting in an amorphous SiOx -containing
mittivity of the single layer gate dielectric ( ␬ ⫽16) is much layer.84 This layer most likely provides a better interface to
lower than that of the alternate dielectric in the stack ( ␬ the Si channel than the SrTiO3 would, thereby exhibiting
⫽25). In addition, any potential charge trapping at a encouraging device properties. This MBE approach and the
dielectric-dielectric interface would be avoided. These con- implications of the UHV conditions required for MBE will
siderations for the choice of the best high-␬ materials will be be discussed further in Sec. VI F.
covered in more detail later.
The approach of using an epitaxial high-␬ gate dielec-
C. Recent high-␬ results
tric, such as SrTiO3, requires submonolayer control of the
channel interface for dielectric deposition.79–84 As with the Considering the potential problems and limitations in us-
use of all perovskites for dynamic random access memory ing a ⬃5 Å SiO2 layer in a dielectric stack, it is highly
共DRAM兲 applications 共e.g., Bax Sr1⫺x TiO3 ,Pbx Zr1⫺x TiO3, desirable to employ an advanced gate dielectric which is
etc.兲, the dielectric must be crystalline 共usually polycrystal- stable on Si, and exhibits an interface quality to Si which is
line兲 to obtain the enormous permittivities typically observed comparable to that of SiO2. This would avoid the need for an
( ␬ ⬎300). The work done thus far on gate dielectrics there- interfacial layer and at the same time, the high permittivity of
fore has required molecular beam epitaxy 共MBE兲, to obtain the material could be fully realized. Table I is a compilation
interface control and layer-by-layer deposition. Since it is of several potential high-␬ dielectric candidates, with the col-
difficult to attain a crystalline oxide on Si, interface engi- umns indicating the most relevant properties, which will be
neering has been employed to provide submonolayer depo- discussed in detail throughout the remainder of this review.
sition of several initial ‘‘template’’ Sr–Si–O layers.79,82,84 Although a substantial amount of work has been reported on
This interface helps reduce reaction due to the thermody- Ta2O5 as a gate dielectric,77 and it clearly has many attributes
namic instability of SrTiO3 on Si, and also helps accommo- for memory capacitor applications, the inherent thermal in-
date the difference in lattice constants between Si and stability when in direct contact with Si is a severe limitation
SrTiO3. Transistors showing encouraging results have been as a gate dielectric. We now examine the available results
fabricated using SrTiO3 gate dielectrics, with metal gates 共to from the literature on such metal oxide and pseudobinary
prevent reaction between SrTiO3 and poly-Si gates兲 and systems, and have categorized them for chemical similarities
modified device processing.80,82 by group in the periodic table.
5254 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

FIG. 12. HRTEM image of CVD Al2O3 on Si with an interfacial Al-silicate

reaction layer evident 共see Ref. 85兲.

desirable attributes of Al2O3 have resulted in several recent

studies of both its physical and electrical properties as a gate
dielectric.
As mentioned before, Al2O3 is thermodynamically stable
on Si against SiO2 formation, but any deposition technique
of interest typically operates under nonequilibrium condi-
tions. This means that reactions can occur, and phases can
form which are not predicted by equilibrium phase diagrams,
although further thermal processing 共depending on the tem-
peratures and times involved兲 will tend to drive the system
toward the equilibrium state. Klein et al.85 studied thin Al2O3
FIG. 11. Reaction at the interface of the SrTiO3 gate dielectric and the Si films deposited by CVD 共using triethyldialuminum for the Al
interface 共see Ref. 82兲.
precursor兲 at temperatures below 400 °C, and found evidence
of an aluminum silicate phase formed at the interface with
1. Group IIIA and IIIB metal oxides
Si, as seen in Fig. 12. Nuclear resonance profiling 共NRP兲
共which measures the Al concentration兲 of the films showed a
Among the group III candidate dielectrics, alumina two-layered structure, with the expected Al concentration for
(Al2O3) is a very stable and robust material, and has been Al2O3 in the top layer, and a marked decrease in Al content
extensively studied for many applications. Regarding its use- in the interface layer. XPS indicated the presence of Al–
fulness as an alternate gate dielectric, Al2O3 has many favor- O–Si bonds in an interface layer for a 35 Å deposited Al2O3
able properties, as shown in Table I, including a high band film. A significant amount of carbon was also observed in the
gap, thermodynamic stability on Si up to high temperatures, films 共⬃20 at. %兲, but it is nevertheless apparent that kinetics
and is amorphous under the conditions of interest. The draw- can play an important role in determining the interface struc-
back is that Al2O3 only has ␬ ⬃8 – 10, and would therefore ture, which is the most critical region for thin gate dielec-
make it a relatively short-term solution for industry’s needs trics.
共1–2 generations兲. If no longer-term solution is available by Atomic layer CVD 共ALCVD兲 Al2O3 has been studied by
the time that a replacement is required, however, such a Gusev et al.87 both physically and electrically, in particular
short-term solution may indeed be suitable. The otherwise to better understand the interface formed between Si and
Al2O3 deposited by this technique. Using NRP, medium en-
TABLE I. Comparison of relevant properties for high-␬ candidates.
ergy ion scattering 共MEIS兲 and high-resolution TEM, it was
determined that ALCVD-deposited Al2O3 共using trimethyla-
Dielectric Band gap ⌬E C 共eV兲 Crystal luminum and water as the Al and O precursors, respectively兲
Material constant 共␬兲 E G 共eV兲 to Si structure共s兲 could be deposited on H-terminated Si without forming an
SiO2 3.9 8.9 3.2 Amorphous interfacial SiO2 layer, as shown in Fig. 13.87 This is an im-
Si3N4 7 5.1 2 Amorphous portant result, because even though Al2O3 is thermodynami-
Al2O3 9 8.7 2.8a Amorphous cally stable on Si 共as mentioned previously兲, all of the depo-
Y2O3 15 5.6 2.3a Cubic sition and growth techniques discussed here occur under
La2O3 30 4.3 2.3a Hexagonal, cubic
Ta2O5 26 4.5 1–1.5 Orthorhombic
nonequilibrium conditions. It is therefore usually found that
TiO2 80 3.5 1.2 Tetrag.c 共rutile, anatase兲 an interfacial SiO2-containing layer forms during deposition,
HfO2 25 5.7 1.5a Mono.b, tetrag.c, cubic between the high-␬ material 共in this case Al2O3兲 and the Si
ZrO2 25 7.8 1.4a Mono.b, tetrag.c, cubic substrate. The combination of the three physical analyses
a
Calculated by Robertson 共See Ref. 153兲.
used in the study by Gusev et al.87 show that it is possible to
b
Mono.⫽monoclinic. control the interface reactions, at least for this case of pre-
c
Tetrag.⫽tetragonal. cursors and deposition conditions.
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5255

contribute ⬃8 Å to the overall the overall t eq value. The

composition of the interface reaction layer is currently not
known, but apparently has a ␬ value larger than that of pure
SiO2. At an effective field of 1 MV/cm, the channel carrier
mobility value for Al2O3 was measured to be smaller by a
factor of ⬃2⫻ 共100 cm2/V s compared to 220 cm2/V s for the
universal mobility curve兲 than that expected by the universal
mobility curve.91 Encouraging drive currents and reliability
characteristics were demonstrated for these devices, but the
significant mobility degradation clearly indicates some del-
eterious effects of the ALCVD Al2O3 which warrant further
investigation.
The study by Park et al.90 demonstrated that boron dif-
fuses through ALCVD Al2O3 during dopant activation an-
neals, and indeed this may be a serious issue for any alter-
native dielectric. It was reported that dopant activation
anneals of 800–900 °C performed on boron implanted
poly-Si gates on top of ⬃60 Å Al2O3 caused significant dif-
fusion of boron through the Al2O3 film and into the n-Si
substrate, as evidenced by a flatband shift of ⬃1.5 V. Sec-
ondary ion mass spectroscopy profiles also indicated a sig-
nificant amount of boron in the substrate after anneal. Fur-
thermore, the addition of an oxynitride layer, grown by an
N2O anneal before Al2O3 deposition, greatly reduced the
flatband shift to 90 mV. In a different study by Lee et al.,92
phosphorous diffusion from the n ⫹ poly-Si electrode into
ALCVD Al2O3 was observed under reasonable annealing
conditions of 850 °C for 30 min. C – V analysis showed a
FIG. 13. 共a兲 TEM image of Al2O3 film deposited by ALCVD methods on a
hydrogen passivated surface from a HF-last process. 共b兲 Corresponding
flatband shift ⌬V FB⫽670– 740 mV 共depending on the par-
MEIS profile of the film. No interfacial layer is detected 共see Ref. 87兲. © ticular dopant incorporation process兲, which corresponds to
2000 IEEE, Fig. 13共a兲 reprinted with permission from IEEE. ⬎1012 cm⫺2 of negative fixed charge in the film. These re-
sults indicate that in this case, phosphorous not only diffused
through the Al2O3 layer, but also introduced fixed charge
Transistor results for 48 Å of Al2O3 共thermally evapo- into dielectric. The authors propose that phosphorous modi-
rated Al followed by thermal oxidation兲 were reported by fies the Al2O3 network, causing negatively charged Al–O
Chin et al.,88 which exhibited t eq⫽21 Å with a leakage cur- dangling bonds. It will continue to be extremely important to
rent of ⬃10⫺8 A/cm2 at 1 V gate bias, compared to identify and understand dopant diffusion in any potential al-
⬃10⫺1 A/cm2 for 21 Å of pure SiO2. The Al2O3 films ex- ternative gate dielectric.
hibited low stress-induced leakage current 共SILC兲 effects, Most of the high-␬ films thus far exhibit a flatband volt-
but did show a high interface state density, D it age different from that expected for the given choice of elec-
⬎1011 eV⫺1 cm⫺2. A follow-up study by Chin et al.89 trode and substrate type. As can be seen in Fig. 4, the flat-
achieved a thinner physical thickness of 21 Å Al2O3 to pro- band voltage is ideally determined only by the electrode
duce T eq⫽9.6 Å, with 22 mV of hysteresis and D it⭓3 work function and the electron affinity of the substrate. We
⫻1010 cm⫺2, and a flatband shift ⌬V FB⬃⫹600 mV, sug- therefore very roughly estimate flatband shifts from the data
gesting negative fixed charge in the film. Very good transis- reported in the literature. 共Note that this shift is different
tor properties were reported for these films, again with low from the hysteresis flatband shift, which is required to be at
SILC effects. least an order of magnitude smaller, and arises from sweep-
Buchanan et al.91 reported nMOSFET results on AL- ing the C – V curve in opposite polarity directions.兲 In most
CVD Al2O3 for 0.08 ␮m gate length transistors with poly-Si studies, ⌬V FB values are not reported by the authors. We
gates, using standard processing conditions, including a estimate the value of ⌬V FB from published C – V curves,
rapid-thermal dopant activation anneal at T⬎1000 °C. A however, using work function values reported by
leakage current of J⬃10⫺1 A/cm2 共at V bias⫽V FB⫹1 V兲 was Michaelson95 for a given electrode, along with electron af-
measured for t eq⫽13 Å, showing a reduction in leakage cur- finity values of 4.18 and 5.3 eV for n-Si and p-Si substrates,
rent of ⬃100⫻ compared to SiO2 of the same t eq value. A respectively. The ⌬V FB values we estimate are not intended
trend in fixed charge correlated with Al2O3 thickness was to be extremely accurate, but rather to show an approximate
demonstrated, showing that fixed charge increases with de- value, within a few hundred millivolts.
creasing film thickness. Extrapolation of that data indicated In the studies mentioned above for Al2O3 on Si, the mea-
that the fixed charge is concentrated near the top, poly-Si sured flatband voltage shift ⌬V FB is about ⫹300 to ⫹800
interface. Furthermore, an interfacial layer was determined to mV, compared to that expected by the electrode and sub-
5256 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

strate types used. This shift is typically interpreted as fixed from that expected for an ideal capacitor using the respective
charge within the film, although it can also arise from oxide electrodes and substrate types in these studies. As with
damage associated with gate electrode deposition or other Al2O3, these are very large voltage shifts measured in a
forms of processing treatments. As mentioned previously, a broad array of sample conditions.
positive ⌬V FB value corresponds to a negative fixed charge. Chin et al.89 reported results from La2O3 films which
Considering that large ⌬V FB values have been measured by were formed by evaporation of La onto Si, followed by low-
several independent groups, using different processing con- temperature thermal oxidation and ex situ Al gate deposition.
ditions and electrodes, this is currently being interpreted as The actual composition and structure in the films may re-
fixed charge within the films. quire further examination, as pure La is well known to be
Several groups have studied the group IIIB metal oxides very volatile and reactive in air, and La2O3 will absorb water
Y2O3, 96–100 La2O389,99 and Pr2O3101 for the purposes of vapor from air. These characteristics signify that any ex situ
high-␬ gate dielectrics. Manchanda and Gurvitch96,97 ther- exposure of these films to air will certainly result in an un-
mally oxidized sputtered yttrium films to form Y2O3, for controlled reaction. Nevertheless, remarkable device results
structures with and without an intentional SiO2 layer be- were shown for these films, as a physical thickness of
tween the Y2O3 and Si substrate. It was found that structures 33 ÅLa2O3 produced t eq⫽4.8 Å, J⬃10⫺1 A/cm2 at 1.0 V
with ⬃260 Å Y2O3 showed very low leakage of gate bias, and D it⬃3⫻1010 eV⫺1 cm⫺2 共almost no quantum
⬍10⫺10 A/cm2 at 5 V bias and breakdown fields of E BD mechanical effect on the t eq value because of the Al gate兲.
⬃4 MV/cm. Capacitors accumulated well with little hyster- Long-channel transistors with the same films for the gate
esis and dispersion, but showed an interface charge density dielectric exhibited very good turn-on characteristics, a sub-
of ⬃6⫻1011 cm⫺2 and showed an interface trap density of threshhold slope of 75 mV/decade, and a high field effective
⬃1011 cm⫺2 eV⫺1. The dielectric constant of the Y2O3 mobility 共at 1 MV/cm兲 of ␮ eff⬎300 cm2 /V s. These films
grown on SiO2 was found to be ␬ ⬃17– 20, but for Y2O3 also showed a flat band voltage shift of ⬃⫹700 mV.
grown directly on Si, it was found that ␬ ⬃12. This lower Guha et al. also recently investigated thin (t eq
measured permittivity value likely resulted from growth of ⬃10– 14 Å) La2O3 films99 where leakage currents of
interfacial SiO2 during the thermal oxidation step. 10⫺4 – 10⫺7 A/cm2 at 1 V are reported. An amorphous film
Kwo et al. investigated Y2O3 and Gd2O3 films deposited structure with ⬃10% Si and a thin interfacial SiOx layer was
by molecular beam epitaxy 共see Secs. VI D and VI F兲, in reported. A large flat band voltage shift of ⫺1.4 V was also
both crystalline and amorphous phases 共as measured by observed.
x-ray diffraction兲.98 Amorphous films showed lower leakage There are clearly many attributes to the group III metal
current densities than crystalline layers, and capacitors oxides, as many promising and encouraging properties have
showed t eq⫽10– 15 Å with leakage current densities of J already been demonstrated using these materials systems. As
⫽10⫺6 – 10⫺3 A/cm2, depending on morphology, deposition will be discussed in Sec. VI, the beneficial properties of
and postannealing conditions. Breakdown fields were mea- M2O3 metal oxides arise in part because the mole fraction of
sured as E BD⬃3 MV/cm, with interface state density D it cations is higher 共40 mol.%兲 compared to MO2 共Group IV兲
⬍1012 cm⫺2 eV⫺1. The C – V curves for these films also ex- metal oxides, with a cation fraction of 33.3 mol %.
hibited frequency dependence between 100 Hz and 1 MHz. The magnitude of the flatband voltage shifts measured in
Guha et al. recently investigated relatively thick (t eq all of these high-␬ systems, suggests a substantial fixed
⬃45 Å) Y2O3 films using an atomic O and Y metal beam charge density of Q⬎1012 cm⫺2 in the films, and must be
epitaxy approach.99 It was found that quasistatic and high further investigated. Interface stability under standard pro-
frequency 共100 kHz兲 C – V measurements using Al elec- cessing conditions remains a concern, as the earlier cases
trodes overlap well upon postmetallization annealing sug- illustrate that uncontrolled reaction tends to occur during the
gesting that interface state densities less than 1011 cm⫺2 were nonequilibrium deposition process through kinetics 共with the
obtained. Little or no flatband voltage shift was reported. apparent exception of the ALCVD-deposited Al2O3兲, despite
Leakage currents at 1 V in thinner films (t eq⬃21 Å) were some thermodynamic predictions. Control of the Si channel
reported to be ⬃10⫺8 A/cm2. High resolution TEM and interface is a key issue for high-␬ gate dielectrics, and will be
MEIS studies, however, indicate the formation of a columnar revisited later.
polycrystalline structure with ⬃10% Si in the film and a
15-Å-thick interfacial SiOx layer which was attributed to 2. Group IVB metal oxides
oxygen diffusion 共possibly along grain boundaries兲 and/or A substantial amount of investigation has gone into the
catalytic reaction. group IVB metal oxides, specifically TiO2, 102–109
Chambers and Parsons100 recently investigated the inter- ZrO2, 110–121 and HfO2, 110,120,122–126 as these systems have
face associated with Y2O3, Si and oxidized/nitrides Si sur- shown much promise in overall materials properties as can-
faces. They found that silicides can readily form depending didates to replace SiO2.
on the kinetics of the deposition process, and that subsequent The TiO2 system has been heavily studied for high-␬
oxidation of the silicide yields an interfacial silicate layer. applications both for memory capacitors and in
They also point out that such reaction kinetics may well be transistors.102,106,107 It is attractive because it has a high per-
expected for other metal–oxide systems used for alternate mittivity of ␬ ⫽80– 110, depending on the crystal structure
gate dielectrics. The flatband voltages for the Y2O3 films and method of deposition. This anomalously high permittiv-
reported to this point are shifted by ⌬V FB⫽300– 600 mV ity, which arises through a strong contribution from soft
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5257

states that allow higher leakage currents. A carbon-free

precursor104 for Ti was synthesized and used to prevent car-
bon incorporation in the film, thereby attempting to reduce
leakage currents. Furthermore, a thermal nitride was grown
at the channel interface by an initial anneal in NH3. The
resulting devices showed values of t eq⬍20 Å, and leakage
currents which were reduced by 100⫻ compared to compa-
rable SiO2 films.105 A hysteresis of 80 mV measured in the
devices indicates the effect of fixed charge from the nitride
layer at the channel interface. The flatband voltage shift was
⌬V FB⬃⫺200 mV, perhaps arising from the presence of
fixed charge in the film.
The jet vapor deposition 共JVD兲 method has been used by
Guo et al.106 to make long-channel transistors with a
TiO2 /SiN stacked gate dielectric. An interfacial nitride bar-
rier 共15 Å thick兲 was first deposited by JVD at 25 °C and
annealed by rapid thermal annealing 共RTA兲 in N2 at 600 °C,
in order to minimize any interfacial layer containing SiO2
FIG. 14. C – V curves for a 190 Å TiO2 gate dielectric in a Pt/TiO2 /p-type which may form during postannealing of the structure. The
Si MIS capacitor structure 共150 ␮m2 area兲. A gate bias-dependent accumu- TiO2 layer was subsequently deposited at a thickness of
lation capacitance was observed. Analysis which incorporates an estimate of
the accumulation layer thickness indicates the presence of a SiO2 interfacial ⬃120 Å, followed by RTA in O2. These structures were seen
layer, resulting in an overall ␬ ⬃30 for the stack 共see Ref. 102兲. © 1997 to be stable up to 900 °C, but at higher temperatures, the
IEEE, reprinted with permission from IEEE. leakage and capacitance measurements were severely de-
graded. Devices using Al electrodes achieved t eq⬍20 Å, and
the nMOS drive current obtained was 0.18 mA/␮m for a 5
phonons involving Ti ions, is not exhibited by the other ␮m gate length and 10 ␮m gate width, at V D ⫽2.5 V and
group IVB metal oxides. On the other hand, Ti has several (V G ⫺V T )⫽1.5 V. No mobility values were reported.
stable oxidation states of Ti3⫹ and Ti4⫹ which lead to a well- Ma et al.107 reported that after forming TiO2 layers by
known problem with materials containing Ti–O bonds: a re- CVD, a postprocessing treatment sequence of plasma ozone
duced oxide. Such a reduced oxide has many oxygen vacan- (O3) at 200 °C followed by rapid thermal anneals in N2O or
cies which act as carrier traps and high leakage paths. Since O2 served to minimize the interfacial reaction between TiO2
TiO2 crystallizes at temperatures much above 400 °C, it is
and Si. This process had the effect of reducing the leakage
also expected to exhibit a polycrystalline morphology, which
current by four orders of magnitude 共for TiO2 films less than
is undesirable, as will be discussed in Sec. VI D. It is impor-
100 Å thick兲. The performance of MOSFETs with TiN gates
tant to note that since TiO2 is not stable on Si during depo-
was also reported, and the relatively low drive currents of
sition by CVD,103 all of the studies on this high-␬ system
⬃40 ␮A/␮m 共at V G ⫽1.2 V, V D ⫽1 V兲 obtained for a 0.5
contain both a reaction layer at the channel interface 共either
␮m device were attributed to nonuniformity in the polycrys-
intentional or unintentional兲 and metal electrodes/gates to
prevent reaction at the gate interface. talline TiO2 layer and corresponding roughness at the inter-
Transistors fabricated with TiO2 as the gate dielectric face.
have shown results with t eq⭐20 Å, with a physical thickness Work on alternate dielectric materials systems of group
of 80–120 Å, and leakage current varies widely depending IVB metal oxides such as ZrO2 and HfO2 was reported in the
on deposition method and postdeposition processing. 1970’s and 80’s for the purpose of optical coatings and
Full transistors using CVD TiO2 as the gate dielectric DRAM applications.
were first reported by Campbell et al.,102 using Pt electrodes Balog et al.110 performed C – V measurements on very
to prevent reaction at the gate interface. A subthreshold slope thick 共3000–4000 Å兲 polycrystalline HfO2 films in
of 83–91 mV/decade was achieved for very large transistors Al/HfO2 /Si structures. For films grown 共by CVD兲 at 450 °C
共100⫻100 ␮ m and 1⫻6 ␮ m, respectively兲 and a transcon- in pure O2, a large hysteresis was observed. It was indicated
ductance of 322 ␮A/V was reported, indicating that the mo- that subsequent anneals in inert ambients, such as in N2 at
bility is only ⬃160 cm2/V s. The transistor performance in 800 °C, led to a reduction in the observed hysteresis. How-
these devices, as illustrated in Fig. 14, was limited by a thick ever, HfO2 films grown at T⭓500 °C resulted in no observed
interfacial oxide layer which formed as a result of the CVD hysteresis and D it⬃1 – 6⫻1011/cm2. Breakdown fields for
process and postannealing of the structure, and the relatively these films were reported to be ⬃1–2 MV/cm and ␬
large interface state density (1012/cm2 eV). Leakage currents ⫽22– 25 at 1 MHz. Balog et al. also found essentially iden-
were also unacceptably high in the transistors, and a rela- tical results for ZrO2 films in Al/ZrO2 /Si structures.110 The
tively large interface state density (1012/cm2 eV) was re- permittivity for these films ranged from 17 to 18. The flat-
ported. Although the role of carbon in high-␬ dielectrics is band voltage shift for both HfO2 and ZrO2 thick films ranged
not yet well understood in relation to leakage current, it is from ⌬V FB⫽⫺600 to ⫹200 mV. However, we note that the
possible that carbon incorporated into the film creates defect reported Si surface preparation procedure most likely re-
5258 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

sulted in the formation of a native oxide prior to HfO2 and

ZrO2 deposition.
Shappir et al. examined thinner 共300–600 Å兲 ZrO2 films
共deposited by metalorganic CVD at 450 °C兲 in various MIS
structures 共with a native oxide on the substrate兲 that included
Al, Mo, and poly-Si gates.111 For Al gate capacitors, anneal-
ing at T⭓800 °C in N2 resulted in a large reduction in leak-
age current. Interestingly, anneals in O2 /HCl at 800 °C re-
sulted in the largest reduction in leakage although no
reduction in the measured dielectric constant 共due to poten-
tial SiO2 formation兲 was observed. Breakdown fields of 4
MV/cm were reported for the subsequently annealed films. A
large hysteresis was observed in all C – V curves, with a shift
of ⬃600 mV for unannealed and N2-annealed samples, and a
shift of ⬃200 mV for O2 /HCl-annealed samples. These films
were estimated to have D it⬃1⫻1012/cm2, which may have
been even higher from the polycrystalline ZrO2 were it not
for the presence of the native oxide. A dielectric constant at
1 MHz ranging from 14 to 19 was observed 共␬ decreased
with increasing anneal temperature兲, even with the native FIG. 15. HRTEM images of ZrO2 deposited by ALCVD methods on 共a兲
oxidized and 共b兲 HF-last treated Si surfaces. Deposition on the H-passivated
oxide present.111 Leakage currents in these very thick films surface appears to result in island nucleation 共see Ref. 113兲.
were reported to be as low as 8⫻10⫺9 A/cm2 at 1.5 MV/cm.
Mo gate devices exhibited similar dielectric constants
with a higher 共⬃10⫻兲 loss tangent than that for the Al gate
structures. Leakage currents were somewhat higher and the minimum achievable t eq value, but it is also required for
breakdown was observed at a slightly lower value 共⬃3.7 the ZrCl4 precursors used in this ALCVD process. Without a
MV/cm兲. Since Mo has a larger work function (⌽ B reactive SiO2 layer on the surface, the ZrCl4 precursors can-
⫽4.5 eV) 95 than that of Al (⌽ B ⫽4.3 eV), 95 Mo is expected not easily displace the Si–H bonds present on the surface of
to result in a lower tunneling current for gate injection, but a standard HF-last wet clean process. This initial oxidation
apparently reaction at the gate interface altered the tunneling therefore serves a dual purpose by providing a very high
properties. The increase in the leakage current was attributed quality interface and at the same time a reactive surface on
to MoO or MoN formation during the postdeposition anneal- which to deposit the ultrathin layer of ZrO2. These ZrO2
ing process. layers were found to be thermally stable under vacuum an-
It was found that poly-Si gates produced good perfor- nealing up to 900 °C, which is important, but were observed
mance when the amorphous Si was deposited at 550 °C, fol- to decompose at higher-temperature vacuum anneals of
lowed by a POCl3 doping 共885 °C兲 and drive step 共920 °C for 1000 °C.
2.5 h兲, which also served to crystallize the Si electrode.111 关It The uniformity of these layers was found to be remark-
was reported that poly-Si deposition at higher temperatures ably good, with thickness variations less than a few percent
共620 °C兲 results in the reduction of ZrO2 to form a Zr-rich across the wafer. It was additionally noted that ALCVD
layer near the poly-Si/ZrO2 interface, leading to very high films deposited on Si surfaces prepared by a HF-last process
leakage currents.兴 Leakage currents were comparable to that did not produce flat and uniform films, but rather resulted in
observed for the Al or Mo gate structures, but the reported the nucleation of ZrO2 islands interspersed with disordered
breakdown field was lower than Al, ⬃3 MV/cm. A dielectric material. It was suggested that this undesirable morphology
constant of ␬ ⬃16 was measured, again with the presence of might be controlled though further investigation of deposi-
a native oxide. tion parameters. Perkins et al.127 reported the electrical char-
The large hysteresis and other shifts in the C – V curves acteristics of polycrystalline ZrO2 ALCVD films deposited
were observed for all of the electrodes and annealing condi- on chemically grown oxides. Using TiN electrodes, encour-
tions used in this study, which indicates that the shifts prob- aging results of t eq⬍14 Å with a leakage current density J
ably arise from mobile ion transport in the pure ZrO2 ⬃2⫻10⫺4 A/cm2 at (V G ⫺V FB)⫽1 V were achieved. The
films.112 All of these studies on ZrO2 and HfO2 indicate crys- flatband voltage shift in the ZrO2 films was ⌬V FB⬃
tallization of the metal oxides either during the deposition ⫺600 mV, and hysteresis in the films varied with bias sweep
process or upon moderate postannealing conditions. range, as ⫾3 V sweeps showed hysteresis of ⬃80 mV and
More recent work has shown encouraging results for ⫾2 V sweeps showed ⬃10 mV hysteresis, respectively, for
both CVD and sputtered films. Using ALCVD, Copel the same film.127 The combination of the observed flatband
et al.113 demonstrated that a highly uniform layer of ZrO2 voltage and hysteresis suggests the presence of positive
can be deposited as thin as 20 Å on top of an SiO2 layer 共Fig. charge in the films, either at the interface or in the ZrO2
15兲. In that work, the 15 ÅSiO2 layer was intentionally layer.
grown by a thermal anneal, to form a very high quality in- Device properties have been measured on sputtered ul-
terfacial oxide.113 As mentioned previously, this layer limits trathin films of ZrO2 and HfO2 using Pt electrodes.114,122 By
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5259

initially sputtering only Hf metal onto the Si substrate, fol-

lowed by reactive sputtering of Hf in an Ar/O2 ambient, low
t eq values of 11.5 Å with a leakage current J⬃1
⫻10⫺2 A/cm2 共at a bias of V G ⫺V FB⫽1 V兲 were reported
共no quantum corrections taken into account兲 with Pt
electrodes.122 Negligible hysteresis was reported for certain
processing conditions, but a relatively high ⌬V FB value of
⬃⫹600 mV was reported in one case,122 and ⬃⫺300 mV
was reported in another,124 with slightly different processing
conditions. These significant flatband shifts perhaps arise
from a large amount of negative fixed charge 共for positive
⌬V FB兲 and positive fixed charge 共for negative ⌬V FB兲, respec-
tively, in the films. The breakdown appears to occur in the
HfO2 layer, as somewhat low breakdown fields of E BD
⬃4 MV/cm were measured, as was previously reported for
thicker films.110,134 An interfacial layer always forms through
this sputtering deposition and postannealing process 共Fig.
16兲, because of the well-known fast diffusion of oxygen
through ZrO2 and HfO2. 112 In this case, oxygen which dif-
fuses through these metal oxides reacts with Si at the inter-
face to form an uncontrolled interfacial layer.
Under optimized processing conditions,122 it was re-
ported that the contribution from the interfacial layer is t eq
⬃5 Å, although a significant level of interface states is still
apparent in the C – V curves at low frequencies, as seen in
Fig. 17. Although x-ray diffraction shows the HfO2 films to
be amorphous as-deposited, annealing above 700 °C was ob-
served to cause crystallization in these thin films, as was
previously reported for thick films.110 Polycrystalline gate
dielectric films will most likely have higher leakage current,
be less uniform and less reproducible than amorphous films,
but the correlation between gate dielectric morphology and
device performance requires more investigation.
In the case of ZrO2, it has been reported114,115 that sput-
tering Zr in a process similar to that described for HfO2
above leads to capacitors 共using Pt electrodes兲 with t eq FIG. 16. Effect of postdeposition annealing on HfO2 gate dielectrics. 共a兲 N2
⫽16 Å, and leakage current density J⬃3⫻10⫺2 A/cm2 共at a and O2 anneals, 共b兲 equivalent oxide thickness, and 共c兲 leakage current after
O2 anneals 共see Refs. 122 and 124兲. © 2000 IEEE, reprinted with permission
bias of V G ⫺V FB⫽0.5 V兲. The interface once again shows a from IEEE.
reaction layer between the ZrO2 and Si, and this layer was
reduced to a physical thickness of about 10 Å by optimizing
the deposition conditions. The interface was seen to yield a
hysteresis of 50 mV, a flatband voltage shift ⌬V FB⬃⫹200 to
⫹300 mV and D it⬃1011 cm⫺2 eV⫺1, indicating the limiting
quality of the reaction layer. The particularly large flatband
voltages may arise in part from processing conditions during
deposition and postannealing.
Houssa et al.118 reported a systematic attempt at under-
standing the flatband voltage and fixed charge in ZrO2 layers
deposited by ALCVD on native silicon oxide. Their study
showed that the net fixed charge density could be altered
significantly depending only on the post-annealing condi-
tions. Using Eq. 共9兲 to obtain values for the amount and sign
of the fixed charge in the dielectric, it was found that as-
deposited ZrO2 /SiOx stacks exhibit negative fixed charge,
and that postannealing in O2 introduced compensating posi-
tive fixed charge and at the same time increased the density
FIG. 17. C – V curve of HfO2 after a rapid thermal anneal at 600 °C. The
of midgap interface states.118 These results are shown in Fig. dispersion for V G ⬍⫺2 V is attributed to higher leakage. Interface states are
18共a兲, where the as-deposited fixed charge density is esti- noted near V G ⬃0.5 V 共see Ref. 122兲. © 2000 IEEE, reprinted with permis-
mated to be ⫺2.5⫻1012 cm⫺2 共with ⌬V FB⬃⫹200 to ⫹600 sion from IEEE.
5260 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

TABLE II. Thermal neutron cross section data for device relevant materials
共after Ref. 132兲.

Thermal
Natural neutron Weighted average
abundance cross section cross section
Element Isotope 共at. %兲 共b兲 共b兲

Zr 90 51.46 0.1
91 11.23 1
92 17.11 0.2 0.213
94 17.4 0.08
96 2.8 0.05
Hf 174 0.163 400
176 5.21 30
177 18.6 370
178 27.1 50 97
179 13.75 65
180 35.22 10
Cu 63 69.1 4.5
65 30.9 2.3 3.82
Si 28 92.18 0.08
29 4.71 0.3 0.0913
30 3.12 0.11
B 10 19.7 3837
11 80.3 0.005 756

FIG. 18. Extrapolated values of 共a兲 fixed charge density Q f and 共b兲 midgap
interface state density N it as a function of postannealing conditions in O2
dioactive isotopes 96Zr and 174Hf. The following analysis
and H2 for ALCVD ZrO2 共see Ref. 118兲. suggests, however, that neither element should be a concern
with respect to radioactive decay.131
The naturally occurring radioactive isotope for zirco-
mV, depending on film thickness兲. Postannealing in O2 at nium is 96Zr. The natural abundance is 2.80 at. %. The half-
progressively higher temperatures is seen to decrease the net life T 1/2 is ⬎3.6⫻1017 years. Assuming reasonable values
amount of negative fixed charge 共presumably through com- for transistor dimensions, the number of Zr atoms resulting
pensation by the introduction of positive fixed charge兲, until from a ZrSiO4 stoichiometry associated with the gate dielec-
a net positive fixed charge is observed for O2 anneals above tric is ⬃1.5⫻106 , resulting in 4.2⫻104 96Zr atoms/gate. As-
600 °C 共a net positive fixed charge density of 2⫻1012 cm⫺2 suming 109 transistors in a device, this results in 4.2⫻1013
results after a 700 °C anneal in O2兲.118 96
Zr atoms per device. The number of disintegrations/year is
Figure 18共b兲 shows that for the same annealing condi- given by A * ␭, where A⫽number of atoms and ␭
tions, the midgap interface state density also increases. Un- ⫽probability for decay, viz. ␭⫽0.693/T 1/2⫽1.9
der subsequent annealing in H2, the midgap interface states ⫻10⫺18 yr⫺1. As a result, one might expect 8⫻10⫺5 disin-
are minimized, while little effect is seen on the net fixed tegrations per device per year, or one disintegration every
charge. If the subsequent H2 anneals are carried out after 1.2⫻104 years per device. A similar analysis for 174Hf indi-
deposition of the metal gate, however, the net fixed charge is cates that one disintegration every 1.6⫻103 years per device
found to become significantly more negative, such that even if HfSiO4 is used as the gate dielectric.
the higher temperature anneals in O2 do not produce a net There is general agreement that the flux of particles that
positive fixed charge. It is proposed that the resulting sign might interact with a device consists of more than 97% neu-
and amount of fixed charge is dependent on the annealing trons at sea level.132 The relevant parameters 共neutron cross
conditions, and that the positive fixed charge arises from sections and natural abundances兲 are given in Table II for
over coordinated oxygen atoms, possibly induced by the hafnium and zirconium, as well as other materials that will
presence of hydrogen,128 as has been proposed for the case of be found in future generation devices. Hafnium has a larger
pure SiO2. 129 thermal neutron cross section than zirconium, but to deter-
We note that hafnium suffers the misconception that it mine whether or not this cross section is significant, one
exhibits sufficient radioactivity to cause sensitivity to single must also consider the number of hafnium atoms present in
event upsets in integrated circuits. It is well known that Hf the gate dielectric. To determine if hafnium is more of a
has been used in nuclear reactors as the control rod material, liability than copper for example, one must take into account
because it has a high thermal neutron capture cross section, the relative number of hafnium atoms to copper atoms, or
and shows little decrease in capture cross-section after long even relative to silicon in the silicon substrates. Ziegler132
periods of radiation exposure.130 Hafnium also shows high describes this as the active atoms/chip, given by
corrosion resistance in hot water, which makes it a low- active atoms/chip
maintenance material for control rod purposes. Both zirco-
nium and hafnium have naturally occurring, long-lived ra- ⫽ 共 active area兲 •electrical depth•atom density.
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5261

TABLE III. Active cross section for different elements, using the thermal In the cases where a flatband voltage has been reported
neutron cross section 共after Ref. 132兲.
for the earlier oxide systems, the measured flatband voltage
Neutron cross Active cross shifts ⌬V FB are substantial 共compared to that expected for
Element Active atoms section section the given electrode work function兲, ranging from ⫺600 to
Si 2.0⫻1018 9.0⫻10⫺26 1.8⫻107
⫹800 mV for the high-␬ films discussed thus far. As men-
Zr 1.5⫻1015 2.1⫻10⫺25 3.2⫻10⫺10 tioned previously, in this case the term ⌬V FB does not refer
Hf 1.1⫻1015 9.7⫻10⫺23 1.1⫻10⫺7 to a flatband shift arising from C – V voltage sweeps in op-
Cu 3.0⫻1017 3.8⫻10⫺24 1.1⫻10⫺6 posite polarities, but rather refers to the difference in the
B 1.0⫻1015 7.6⫻10⫺22 7.6⫻10⫺7
measured flatband voltage 共for a single sweep兲 from that ex-
pected for an ideal capacitor 共for a given electrode and sub-
strate doping level兲.
This shift is normally interpreted as fixed charge within
Assuming a 1 cm2 silicon-based device with 4% of the the film, although it can also arise from oxide damage asso-
device active and a 1 ␮m electrical depth, one arrives at ciated with gate electrode deposition or other forms of pro-
(0.04 cm2 )•(10⫺3 cm)•(5⫻1022 atoms/cm3 )⫽2⫻1018 Si cessing treatments. Considering that large ⌬V FB values have
atoms. One must also determine the active cross section been measured by so many independent groups, using differ-
共⫽active atoms•neutron cross section兲, which takes into ac- ent processing conditions and electrodes, it is currently being
count the differences in neutron cross sections for the differ- attributed to fixed charge within the film. A large fixed
ent elements 共shown in Table II兲. For Si, the weighted aver- charge 共e.g., that which corresponds to ⌬V T ⬎50 mV兲 in a
age neutron capture cross section is 9.13⫻10⫺26 cm2 gate dielectric can have a serious, deleterious effect on the
resulting in an active cross section of 2⫻10⫺7 cm2. Other transistor performance, because the threshold voltage V T be-
relevant elements are shown in Table II. comes too large for adequate compensation by dopant im-
While this approximation does not provide an estimate plants. Smaller fixed charges 共⬃10–20 mV兲 can be accept-
of the absolute single event upset rate, it should provide an able, and even desirable, since this can adjust the V T such
estimate of the relative sensitivity for different elements in that smaller channel implant doses can be used 共which re-
the device to cosmic rays. Thermal neutron cross-sections sults in less ion impurity scattering of carriers in the chan-
were used as an estimate of the overall neutron cross section nel兲.
which is likely an overestimate of the interaction cross sec- Although it is not yet known whether the observed flat
tion. band shifts arise from a fixed charge within the high-␬ di-
Table III compares these sensitivities for the different electrics or from some other phenomenon, a large amount of
elements and their associated isotopes discussed earlier.
fixed charge in these films could have an enormous influence
Even with the relatively high thermal neutron cross sections
on the viability of their insertion into a CMOS process. If
for Zr and Hf, these data would suggest that neither Hf nor
these high-␬ gate dielectrics indeed prove to contain signifi-
Zr should cause as many upsets as Cu. The number of Cu
cant amount of fixed charge, then the sign of the charge will
atoms was determined by assuming a copper metallization
also become extremely important. The band diagram in Fig.
process consisting of 0.3-␮m-thick layers, five levels of
4 illustrates the different effects on a device threshold volt-
metal, and 4% of each layer is made up of Cu. Boron was
age for the cases of positive and negative flatband voltage
estimated assuming an implant dose of 1⫻1015 atoms/cm2.
The results obtained on the ZrO2 and HfO2 metal oxide shifts. This observed phenomenon has been suggested11 to
systems described earlier indeed are important demonstra- arise from the detailed bonding structure of the various cat-
tions of the ability to achieve low t eq values with lower leak- ions near the Si interface, while another report by Houssa
age currents than would be achieved using comparable SiO2 et al.,118 mentioned previously, suggested that the sign and
films. The interface quality of these systems remains a criti- amount of fixed charge depends only on the annealing con-
cal issue, however, since the materials in particular are ex- ditions. It should be noted that only positive ⌬V FB values
tremely susceptible to O diffusion and reaction at the channel have been measured for Al2O2, but both positive and nega-
interface. The ultimate device performance will depend tive ⌬V FB values have been measured for several high-␬
heavily on the channel carrier mobility, which in turn can be dielectrics.
easily degraded by high interface trap levels. A large hyster- For example, TiO2, ZrO2, and HfO2 show a range of
esis or shift in flatband voltage for any gate dielectric will ⌬V FB⫽⫺600 to ⫹800 mV, while Y2O3 and La2O3 show
also result in unacceptable transistor threshold voltage shifts. ⌬V FB⫽⫹300 to ⫹1400 mV 共on much less data than for
Finally, these metal oxides have not yet demonstrated the group IVB oxides兲, but Al2O3 shows ⌬V FB⬃⫹300 to ⫹800
required stability under the high temperatures required for mV. Since a negative value corresponds to positive fixed
CMOS processing, including dopant activation anneals up to charge 共assuming again that these shifts are due to fixed
1050 °C. At this point, lower thermal budget processes have charge兲 and vice versa, Al2O3 seems to show opposing be-
been considered, such as the replacement gate process,69 but havior in that it may possess negative fixed charge. These
no proven manufacturable flow has yet emerged. Until this two cases clearly have different impacts on nMOS and
occurs, it should be considered a critical requirement for pMOS devices. Much more work must be done to determine
high-␬ dielectrics to withstand such high-temperature an- if indeed there is a substantial amount of fixed charge in
neals. these high-␬ dielectrics on Si, and if so, how to remove it or
5262 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

at least make manageable adjustments for acceptable device

performance.
To summarize the many results reported thus far on the
unary, simple oxide systems, all high-␬ metal oxides inves-
tigated to this point have demonstrated encouraging electri-
cal properties. All of the unary oxides reported have
achieved t eq⬍15 Å, with J⬍10⫺2 A/cm2 共at V G ⫺V FB
⫽1 V兲. Nearly all of the metal oxides, however, show sig-
nificant frequency dependence, hysteresis and flatband volt-
age shifts, as well as concerns regarding oxygen diffusion
and interface stability during subsequent high-temperature
thermal processing.
The following section focuses on alloys of these oxides,
in an attempt to combine and complement the desirable prop-
erties from several materials, and thereby overcome the de-
ficiencies associated with the individual materials. These al-
loy systems are predominantly non-stoichiometric mixtures,
and are therefore termed pseudobinary alloys.

3. Pseudobinary alloys FIG. 19. Ternary phase diagrams for 共a兲 Ta–Si–O, 共b兲 Ti–Si–O, and 共c兲
Zr–Si-O compounds 共after Refs. 156 and 158兲.
All of the earlier mentioned materials clearly have many
advantages as high-␬ gate dielectrics, but they also have un-
desirable properties which remain a concern regarding re- where x⬍2 or x⬎4. Additionally, investigation of interface
placement of SiO2. An encouraging system of materials are engineering using SiO2 /Hf4SiO10 /Si3N4 insulator stacks
pseudobinaries, such as (ZrO2 ) x (SiO2 ) 1⫺x and provided improved performance compared to similar struc-
(HfO2 ) x (SiO2 ) 1⫺x , which for this purpose combine two ox- tures incorporating Ta2O5.
ides, typically 共although not necessarily兲 in nonstoichiomet- Recent work on two such systems of pseudobinaries,
ric compositions. In this way, it is possible to combine the namely silicates 共M–Si–O兲, with M⫽Zr,
desirable properties from two different oxides while elimi- Hf,115,116,135–138,143共a兲 La143共b兲 and Gd,143共c兲 and aluminates
nating the undesirable properties of each individual material. 共M–Al–O兲, with M⫽Zr, 139,140 indicate that such materials
It is instructive to consider the chemical and electrical systems already exhibit encouraging gate dielectric proper-
characteristics associated with Zr and Hf that serve to create ties toward this end. Both materials systems have the same
such favorable electrical properties for the CMOS applica- underlying principle of mixing a high-␬ 共crystalline兲 metal
tions 共and conversely why Ti is not favorable兲. The four-fold oxide with an amorphous, stable, lower-␬ material 共SiO2 or
coordination of Si and the desire to minimize the presence of Al2O3兲 to obtain a desirable morphology with suitable prop-
dangling bonds at the interface suggests that high-Z elements erties for a CMOS gate dielectric. The effect of adding SiO2
in group IVB are desirable when incorporated into an insu- and Al2O3 to metal oxides such as ZrO2 is to produce an
lator oxide or silicate. amorphous film that is thermodynamically stable on Si 共for
Some work in the 1970’s and 80’s 共as mentioned previ- low leakage currents兲. The overall permittivity of the
ously, the work was primarily intended for use in optical lens pseudobinary alloy is inevitably lower than that of the pure
coatings兲 was carried out on such pseudobinary materials. metal oxide, but this tradeoff can be very adequate, for the
Examination of sputtered ZrO2 – SiO2 codeposited, thick improved stability. In particular, ZrO2 :SiO2 and HfO2 :SiO2
共⬃3000 Å兲 films has been reported by Russack and silicates within an appropriate composition range have been
co-workers.133 X-ray diffraction analysis of the films indi- demonstrated to exhibit very low leakage currents and im-
cated that the films with ⬎10 %SiO2 remain amorphous proved ␬ values with only small amounts of ZrO2 or HfO2 in
even upon annealing at 500 °C in air for 60 h. Films with the material.135–137
⬍10 %SiO2 exhibited a crystalline ZrSiO4 diffraction pattern Since Figs. 19共a兲 and 共b兲 show that there are no apparent
under similar annealing conditions. Composition analysis of thermodynamically stable ternary compounds for the Ta–
their films, as deduced by Rutherford backscattering spec- Si–O and Ti–Si–O systems, glassy silicates 共Tax Siy Oz or
troscopy, indicated that the films have a metal:oxygen ratio Tix Siy Oz 兲 of these materials may be obtained. The subse-
of 2:1, signifying that they are fully oxidized. quent thermal processing that these materials experience will
Roberts et al. investigated HfO2 :SiO2 films also pre- be of key importance, though, as these systems are likely to
pared by sputter techniques.134 They found that Hf-silicate separate into more stable Mx Oy and Mx Siy phases. Further-
films provided superior performance to sputtered Ta2O5 films more, an extension of constraint theory for glasses, as for-
for thin capacitor insulator film thicknesses 共100–150 Å mulated by Phillips141 has recently been applied to glassy
range兲. A preferred stoichiometry of Hf4SiO10 was identified phases of high-␬ gate dielectrics. It has been found142 that
as a result of breakdown measurements and ␬ ⫽13 was re- there is excellent agreement between the expected stability
ported. It was noted that interfacial SiO2 growth occurs upon and low defect densities specifically for certain composition
subsequent O2 annealing above 800 °C for Hfx SiO2x⫹2 , ranges of ZrO2 :SiO2 and HfO2 :SiO2 silicates.
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5263

Many other silicate systems are possible, but the main

concerns for all of them are whether the ␬ value is large
enough for gate dielectric applications, and whether or not
they will tend to phase separate when placed next to Si at the
temperatures of interest. Ternary systems such as Al–Si–O,
Y–Si–O, or Sc–Si–O are possibilities, because their metal
oxide phases are stable on Si, but these silicates may suffer
from relatively low ␬ values. Other possible silicate candi-
dates which may work well are those which contain rare
earth metals with high atomic numbers, such as La–Si–O,
Ce–Si–O, and Ba–Si–O. There may be some stability con-
cerns, however, for Ce–Si–O on Si, and BaO is notorious
for its hygroscopic nature.
Glassy phases of a ternary or quaternary system contain- FIG. 20. Structure of crystalline ZrSiO4 showing the Zr bonding to SiO2
units. Zr–O bonding also exists in and out of the plane of the page.
ing only metals and oxygen may also be obtained, but this
again raises concerns of uncontrolled reaction at the Si chan-
nel interface. For example, TiOx films have been doped with these materials, however, depends on an extremely high
various metals to obtain an amorphous film, as a means of level of quality and control over the channel interface, which
reducing leakage and improving thickness uniformity.107,109 has not yet been demonstrated.
In the study by Ma et al.,139 Al and Zr were cosputtered Quaternary silicate films containing Zr and Hf, and pos-
to form (ZrO2) x (Al2O3 ) 1⫺x amorphous alloys with x sibly other elements, are certainly conceivable, but the ma-
⫽0.75. Using TiN gates, these pseudobinary alloys achieved terial which satisfies the demands of technology while re-
t eq⬃12 Å with J⬃0.1 A/cm2 at 1 V gate bias. The flatband quiring the least change, is preferred. At this point, we will
shift on capacitors was ⌬V FB⫽⫹200 to ⫹300 mV. Transis- focus on the Hf–Si–O and Zr–Si–O systems because
tors fabricated using these alloys showed good characteris- of the combination of all their desirable properties
tics, with a subthreshold swing of 72 mV and I d ⫽1.3 mA for listed earlier and the promising results recently
a 0.6 ␮ m⫻1 ␮ m pMOSFET, with V D ⫽V G ⫽⫺1.5 V. Hole reported.115,116,135–137,143共a兲,143共b兲,143共c兲
mobilities were found to be ⬃30% lower than for compa- One potentially large advantage for silicates is that this
rable SiO2 FETs at E eff⬃1 MV/cm. The work by Manchanda class of materials should have a silicate-Si interface that is
et al.140 also used sputtered Zr–Al–Si on 5 Å SiO2 or Si– chemically similar to the SiO2 –Si interface, which is unpar-
O–N films, followed by thermal oxidation, to form alleled in quality for transistor channel regions. This is espe-
(ZrO2 ) x (Al2O3 ) 1⫺x pseudobinary alloys with x⬃0.75 共there cially important since the channel interface is playing a
was also ⬃1.7% Si in the films兲. The films were found to dominant role in determining device performance, and be-
remain amorphous up to 800 °C for 30 min. TiN gates were cause almost any simple oxide (Mx Oy ) deposited on Si will
used to form capacitors, and t eq⫽12 Å was achieved with form a silicate interfacial layer, even if it is very thin. In this
J⫽0.1 A/cm2 at 1.5 V gate bias. An interface state density of light, the tetravalent transition metal cations such as Zr and
D it⬃1 – 5⫻1011 cm2 was reported for the Zr–Al–Si–O Hf offer the advantage of substituting well at Si sites, which
films. No channel carrier mobilities were reported. form SiO4 tetrahedra. For the case of forming nonstoichio-
Other work by van Dover109 examined the effect of a metric silicates 关e.g., (ZrO2 ) x (SiO2 ) y 兴, where x and y are not
wide range of dopants in sputtered TiOx films on film struc- integers兲, a tetravalent cation such as Zr4⫹ or Hf4⫹ ion
ture and leakage. The incorporation of up to 10% Nd, Tb, should substitute well for Si4⫹, to provide a favorable bond-
and Dy lanthanide dopants in Ti–O films produced amor- ing for a silicate network with low defect densities. In the
phous structures with low leakage and high specific capaci- case where stoichiometric compounds are formed, then other
tance 共no postannealing was done兲. Using Pt top electrodes cations may also work, such as La3⫹ in a compound
and TiN bottom electrodes, permittivities ranging from 50 to (La2O3 ) x (SiO2 ) 1⫺x silicate, where x⫽0.5.42,143共b兲
135 were measured for 350-Å-thick films, while maintaining There has been much less information reported on
an amorphous layer. Leakage currents of 5⫻10⫺7 A/cm2 (HfO2) x (SiO2 ) y than on (ZrO2 ) x (SiO2 ) y , but the chemical
were obtained at an applied field of 2 MV/cm for each of the similarities between Hf and Zr allow for comparison be-
cases of Nd, Tb, and Dy doping. Although these materials tween the respective silicate systems. As described by
systems are better-suited for memory capacitors than for Blumenthal,144 and Bragg et al.,145 the Bravais lattice for the
transistors 共due to thermal instability on Si兲, the results indi- stoichiometric compound ZrSiO4 共zircon兲 is body-centered
cate the importance of considering dopants as a means of tetragonal, and belongs to point group D 4h . The crystal is
reducing leakage current without substantially degrading composed of SiO4 tetrahedra interspersed with Zr atoms, but
other electrical properties of the high-␬ dielectric. The par- can be considered as parallel chains of ZrO2 and SiO2 struc-
ticular dopants presumably tie up dangling bond deep trap tural unit molecules, as shown in Fig. 20. Each Zr and Si
levels associated with unsatisfied cation bonds 共Ti in this atom shares bonds to four O atoms within each chain, and
case兲, while not introducing deleterious trap levels of their each successive pair of O atoms is oriented in a transverse
own. A performance improvement is clearly attainable using configuration, forming ZrO2 and SiO2 units. The Si–O bond
high-␬ dielectrics such as TiO2. The ultimate success of length is shorter than the Zr–O bond length within a chain,
5264 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

FIG. 21. HRTEM image of Hf-silicate between Si layers. 共a兲 After deposi-
tion of amorphous Si at 500 °C and 共b兲 after annealing at 1050 °C for 20 s in
N2 共see Ref. 137兲.

as is represented in the figure. Figure 20 shows that each Zr

atom also shares bonds with other O atoms in neighboring
chains 共only two of the four bonds to neighboring chains are
shown for each Zr atom, for clarity兲, providing a three-
dimensional stability to the material.
It is important to note that each Zr and Si atom has only FIG. 22. Comparison of C – V and J – V performance for a MIS structure
incorporating Hf silicate. The Al electrode results in interfacial reactions
O atoms as nearest neighbors. Chemical analysis of homo- 共see Ref. 137兲.
geneous silicate films is therefore expected to show only
Zr–O nearest-neighbor bonding, with a slight effect from Si
as a next-nearest neighbor. Although the films presented in served for the Al gate electrode sample. High-resolution
this study are amorphous, it is reasonable to assume that for TEM 共HRTEM兲 results, not shown, also indicate a contrast
Hf and Zr concentrations less than that of the stoichiometric change at the Al/silicate interface, similar to that observed in
MO2 – SiO2 compound, nearly all bonds will be Zr–O 共or the case of Al/Zr-silicate structures.137 These results suggest
Hf–O兲 and Si–O bonds.115,116,135–137,143共c兲 that Al/silicate reactions likely occur with postdeposition
Using coordination chemistry arguments between Hf and processing, as may be expected for silicate materials sys-
Zr, HfSiO4 should have the same structure as ZrSiO4. A tems. Leakage current densities, however, remained well be-
value of ␬ ⫽12.6 for bulk ZrSiO4 was reported by low that for equivalent SiO2 gate dielectric films, with J
Blumenthal.144 Similarly, since HfO2 has reported ⬍10⫺5 A/cm2 at V G ⫺V FB⫽1 V.
values110,146 of ␬ ⫽21⫺25 共Ref. 146 also reports ␬ ⫽40, but We further note that the potential use of silicate 共and
this value has not been confirmed in more recent studies兲, a perhaps to a lesser extent aluminate兲 pseudobinary alloy sys-
HfSiO4 compound is expected to have a range of ␬ tems as a replacement for SiO2 gate dielectrics, in conven-
⬃13– 20. The exact value of ␬ will certainly depend strongly tional CMOS processing, arguably represents the historical
on film composition, density and structure 共amorphous ma- evolution of dielectrics in CMOS technology. Silicon diox-
terials typically have less lattice polarizability than their ide has been unimaginably ideal for integrated circuits, be-
crystalline counterparts兲. Considering all of the desired prop- cause it has been used for decades both as the interlevel
erties, (ZrO2 ) x (SiO2 ) 1⫺x and (HfO2 ) x (SiO2 ) 1⫺x should be dielectric 共ILD兲 between successive metal interconnect levels
excellent materials candidates for advanced gate dielectrics, and as the gate oxide for MOSFETs. Recent technology de-
and indeed some very encouraging results have been previ- mands, however, have required that SiO2 in the ILD be
ously reported.115,116,135–137,143共c兲 modified to create a lower dielectric constant, so that lower
In the first demonstration of a stable gate dielectric with RC time delays can be achieved. These changes have been
a t eq⬍20 Å deposited directly on Si, a smooth interface was made by simply incorporating H, F, and C into the SiO2 to
demonstrated in the work by Wilk and Wallace for both Hf lower the ␬ value of the oxide. These modifications, while
and Zr silicate films.135,136 Figure 21 shows this interface for certainly not trivial, have thus far proved to be manageable
a HfO2 :SiO2 dielectric with Si at both interfaces where it is in the integration process.
seen that the annealing required to activate and crystallize Similar demands for higher drive currents and lower
the amorphous Si 关Fig. 21共a兲兴 does not result in a detectable leakage have required SiO2 in the gate dielectric to be altered
interfacial layer. Figure 22 shows the results of using Al and by adding N, both in the form of doping and as a silicon
Au electrodes in MIS a capacitor evaluation of the Hf- nitride layer on top of SiO2. This process slightly increases
silicate layer. It is seen that somewhat lower accumulation the effective dielectric constant, allowing use of a physically
capacitance and somewhat higher leakage current is ob- thicker film, and thereby achieves a higher drive current with
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5265

less leakage. With these trends in mind, silicate and alumi-

nate gate dielectrics should also be viewed as only another
modification of SiO2. These pseudobinary systems allow for
control in obtaining the desired materials properties by
‘‘doping’’ SiO2 or Al2O3 with Zr or Hf, to further improve
device performance while remaining compatible with the rest
of well-established CMOS processing procedures. In fact, if
these silicate films can be used, then by simply increasing the
doping level of Zr or Hf from one technology node to the
next for gradually improved device performance, this same
materials system should fulfill the requirements on current
roadmaps until the year 2010.

4. High-␬ device modeling and transport

The incorporation of stacked structures has been inves-
tigated by a number of researchers in recent years. As dis-
cussed previously, the layer within the stack that has the
lower dielectric constant will limit the overall capacitance of
the stack. However, the minimization of interface states may
require suitable interfacial layers that serve as a transition
region between the Si substrate and the dielectric. One can
also obviously envision a graded composition throughout the
dielectric permitting control of interfacial state formation
which preserves, to some extent, the high-␬ properties
sought for the alternative gate dielectric in the gate stack.
Vogel et al.147 considered such effects in a model of
potential gate stack materials. As acknowledged in the work,
the model does not incorporate trap assisted tunneling
mechanisms but does provide an indication of the trends as-
sociated with stack layers and scaling.
As seen in Fig. 23共a兲, tunneling currents associated with
idealized gate dielectrics (t eq⫽2 nm) are reduced dramati-
cally in the voltage regime anticipated for future devices
(V DD ⬃1 V). Dielectric constants assumed for each curve
are ␬ ⫽3.9(SiO2), 7.5(Si3N4), 5.7(SiOx Ny ), 25 共D1兲, and 30
共D2兲. It is noted in that work, however, that it is more ben-
eficial for a suitable alternate dielectric to exhibit a barrier
slightly higher than V DD in order to minimize tunneling,
rather than a slightly higher dielectric constant. This is seen
in the cross over point in the tunneling current for candidate FIG. 23. 共a兲 Tunneling current calculated for gate dielectrics in a n ⫹ p
dielectrics D1 and D2. capacitor structure exhibiting an equivalent oxide thickness of t eq⫽2 nm.
共b兲 Tunneling current calculated for stacked structures. The layer listed first
The incorporation of an interfacial SiO2 layer 共0.5 and is the layer initially encountered by the tunneling electron. Interfacial SiO2
1.0 nm thick兲 as a part of a gate stack is examined in Fig. layers 0.5 and 1 nm thick are considered 共see Ref. 147兲. © 1998 IEEE,
23共b兲. The effect of electron injection through this interfacial reprinted with permission from IEEE.
layer from either the gate or the substrate is also examined
by simply changing the direction of the electric field. In ad-
dition to the expected reduction in the overall tunneling cur- For an even thinner SiO2 layer, electrons of the same
rent, it is seen that the tunneling current changes substan- energy as that in Fig. 24共a兲 encounter substantial regions
tially depending on the dielectric layer first encountered by associated with the high-␬ barrier 关Fig. 24共b兲兴. Hence, for
the electron. higher biases, the electron will eventually encounter only the
This can be understood by consideration of the dielectric barrier associated with the interfacial layer and therefore a
band diagrams associated with the stacked structure 共Fig. substantial increase in tunneling current would be evident
24兲. For a 1 nm SiO2 interfacial layer, it can be seen in Fig. 关cf. to Fig. 23共b兲兴.
24共a兲 that an electron with a suitable energy 共from V ins⫽ In an attempt to predict the effect of high-␬ gate dielec-
⫺2.68 V兲 that first encounters the SiO2 layer avoids the bar- trics on transistor performance, Frank et al.148 modeled gate
rier associated with the high-␬ layer, D1. Tunneling from the dielectrics with various permittivities in a planar, bulk
opposite direction, however, results in encounters with the CMOS structure. It was reported that the upper limit of per-
barriers associated with both layers and a concomitant exten- mittivity would be limited to ␬ ⬃20 due to fringing field-
sive reduction in tunneling 共leakage兲 current. induced barrier lowering at the drain region of the device.
5266 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

now consider a summary of the appropriate materials prop-

erties for the selection of materials for gate dielectric appli-
cations.
A. Permittivity and barrier height
Selecting a gate dielectric with a higher permittivity than
that of SiO2 is clearly essential. For many simple oxides,
permittivities have been measured on bulk samples and in
some cases even on thin films, but for the more complex
materials 共more elemental constituents兲, the dielectric con-
stants may not be as well known. Shannon151 used a method
involving the Classius–Mossoti equation for calculating
ionic polarizabilities as a means to make predictions of per-
mittivities for many dielectrics. Good agreement has been
found for some materials, but there are also many cases of
poor agreement between calculated and measured values.
This discrepancy between calculation and measurement can
be attributed to many factors, including film thickness,
method of film deposition, and local electronic structure
within the dielectrics. It is clear that much more experimen-
tal data is needed for measurements of dielectric constant for
these high-␬ dielectrics, particularly below the 100 Å thick-
ness regime.
FIG. 24. Band diagrams for results in Fig. 23共b兲. 共a兲 1 nm SiO2 interface The required permittivity must be balanced, however,
layer, 共b兲 0.5 nm interface layer. The injection polarity 共and energy兲 of the against the barrier height for the tunneling process. For elec-
electron results in sampling different portions of the barriers associated with
each dielectric 共see Ref. 147兲. © 1998 IEEE, reprinted with permission from
trons traveling from the Si substrate to the gate, this is the
IEEE. conduction band offset, ⌬E C ⬵q 关 ␹ ⫺(⌽ M ⫺⌽ B ) 兴 ; for elec-
trons traveling from the gate to the Si substrate, this is ⌽ B
共see Fig. 4兲. This is because leakage current increases expo-
This phenomenon is a large concern, because a significant nentially with decreasing barrier height 共and thickness兲 for
fringing field from the edge of a high-␬ dielectric could electron direct tunneling transport,9,10 as shown in Eq. 共12兲:
lower the barrier for transport into the drain enough to seri-
ously degrade the on/off characteristics of the device. Krish-
nan et al.149 reported similar modeling results for high-␬ gate
J DT ⫽
A
2
t diel
冉
exp ⫺2t diel 冑 2m * q
ប2 再
⌽ B⫺
V diel
2 冎冊 . 共12兲

dielectrics, but also claimed that a dielectric stack with SiO2 Here A is a constant, t diel is the physical thickness of the
at the channel interface could reduce any barrier-lowering dielectric, V diel is the voltage drop across the dielectric, and
effects from the high-␬ fringing fields.150 m * is the electron effective mass in the dielectric. For highly
Perhaps even more important is the issue of field pen- defective films which have electron trap energy levels in the
etration into the Si channel region.148 The inversion charge in insulator band gap, electron transport will instead be gov-
the channel experiences an increasing electric field with in- erned by a trap-assisted mechanism such as Frenkel–Poole
creasing gate capacitance, regardless of the gate dielectric emission or hopping conduction, as described by Eqs. 共13兲
material. At a high enough electric field penetration through and 共14兲, respectively,

冉 再 冑 冎冊
the gate dielectric, channel carriers will undergo increased
scattering, ultimately leading to a decrease in mobility and q qE
J FP⫽E exp ⫺ ⌽ B⫺ 共13兲
drive current. Additionally, this inversion layer will have an kT ␲⑀i
associated capacitance in series with the gate stack and will
q 2 l 2 n * ⌫E
also eventually limit the ultimate gate stack capacitance for J hop⫽ . 共14兲
any high-␬ dielectric.26 kT
This effect was first reported by Timp et al.20 using pure Here l is the interval of separation between adjacent hop-
SiO2, as 30 nm gate length transistors showed that for t eq ping sites, n * is the density of free electrons in the dielectric,
⬍13 Å, the drive current actually decreased. If this phenom- and ⌫ is the mean hopping frequency. Leakage current also
enon causes a degradation in device performance for t eq depends on other factors, including the structure of the layer,
⬍11– 13 Å, then tradeoffs may have to be considered for as discussed later in Sec. VI D. In order to obtain low leak-
technologies using these materials.23 age currents, it is desirable to find a gate dielectric that has a
large ⌬E C value to Si and perhaps to other gate metals which
may be used at some point. Reported values of ⌬E C for most
VI. MATERIALS PROPERTIES CONSIDERATIONS
dielectric-Si systems are scarce in the literature, but recent
All of the materials systems discussed earlier must meet calculations by Robertson and Chen152 indicate that many of
a set of criteria to perform as successful gate dielectric. We the metal oxide and complex oxide materials, such as Ta2O5
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5267

FIG. 26. The frequency dependence of the real (␧ r⬘ ) and imaginary (␧ r⬙ )

parts of the dielectric permittivity. In CMOS devices, ionic and electronic
contributions are present 共see Ref. 154兲.

to the dielectric constant which give rise to the polarizability:

FIG. 25. Band offset calculations for a number of potential high-k gate
dielectric materials 共see Refs. 152 and 153兲.
electronic and ionic dipoles 共the molecular dipole contribu-
tion is not relevant to this study兲. Figure 26 illustrates the
frequency ranges where each contribution is important, and
also highlights the current frequency range for CMOS opera-
and SrTiO3, will have ⌬E C ⬍0.5 eV on Si. On the other tion 共100 MHz–10 GHz兲.154 In general, atoms with a large
hand, an expanded study by Robertson et al.153 includes ionic radius 共e.g., high atomic number兲 exhibit more electron
many more high-␬ dielectrics which are currently under in- dipole response to an external electric field, because there are
vestigation 共see Fig. 25兲. Robertson found that ⌬E C more electrons to respond to the field 共electron screening
⬃2.3–2.8 eV for Al2O3 and Y2O3, and ⌬E C ⬃1.5 eV for effects also play a role in this response兲. This electronic con-
ZrO2 and ZrSiO4, as illustrated in Fig. 25.153 tribution tends to increase the permittivity for oxides of ele-
These calculations are an important insight into predict- ments with higher atomic numbers.
ing relevant barrier height 共such as ⌬E C 兲 values for many The ionic contribution to the permittivity can be much
potential dielectrics based on the charge neutrality level of larger than the electronic portion in cases such as perovskite
the material. If the experimental ⌬E C values for these oxides crystals of 共Ba, Sr兲TiO3 and 共Pb, Zr兲TiO3 共which exhibit
are even much less than 1.0 eV, it will likely preclude using ferroelectric behavior below the Curie point兲. In these cases,
these oxides in gate dielectric applications, since electron Ti ions in unit cells throughout the crystal are uniformly
transport 共either by thermal emission or tunneling兲 would displaced in response to an applied electric field 共for the case
lead to unacceptably high leakage currents. Since many po- of ferroelectric materials, the Ti ions reside in one of two
tential gate dielectrics do not have reported ⌬E C values, the stable, nonisosymmetric positions about the center of the
closest, most readily attainable indicator of band offset is the Ti–O octahedra兲. This displacement of Ti ions causes an
band gap (E G ) of the dielectric. A large E G generally corre- enormous polarization in the material, and thus can give rise
sponds to a large ⌬E C 共see Table I兲, but the band structure to very large dielectric constants of 2000–3000. Since ions
for some materials has a large valence band offset ⌬E V respond more slowly than electrons to an applied field, the
which constitutes most of the band gap of the dielectric. This ionic contribution begins to decrease at very high frequen-
uncertainty places more importance on predictive methods cies, in the infrared range of ⬃1012 Hz, as shown in Fig. 26.
such as that demonstrated by Robertson.152,153 We note that some of the potential candidate materials
As noted before, it is extremely difficult to achieve the may have other contributions to the permittivity, which do
juxtaposition of these high-␬ dielectrics on Si, as an not exhibit the same phenomena as the perovskites. The ad-
SiO2-like interface usually forms. This interface layer will of dition of certain levels of network modifier ions 共e.g., Zr or
course alter the ⌬E C value of the system, and must be taken Hf兲 to materials such as SiO2 can produce an increased di-
into consideration when comparing measured and calculated electric constant even at low incorporation levels, through a
results. discernable change in the bond order of the material. Lucov-
Referring back to Table I, a list of several metal oxide sky and Rayner155 describe this effect for several experimen-
共and nitride兲 systems, some of which have been investigated tal cases, where the localized bonding order, which changes
as gate dielectrics, compares values for ␬ and E G , along with Zr 共or Hf兲 concentration, results in substantial changes
with ⌬E C values on Si where available. For these high-␬ in the vibrational modes in the associated infrared spectra of
materials, Table I indicates that E G will be somewhat lim- the silicate. This effect can be further modeled to demon-
ited, since it can be seen that the dielectric constant and band strate that a transverse effective charge scales inversely with
gap of a given material generally exhibit an inverse relation- Zr 共Hf兲 concentration, and the contribution of the vibrational
ship 共although some materials have significant departures mode to the dielectric constant is proportional to the square
from this trend兲. of this effective charge. As a result, an enhancement in the
The detailed relationship between permittivity and band dielectric constant, over that expected by simple linear inter-
gap is by no means trivial, since many factors give rise to polation between SiO2 ( ␬ ⫽3.9) and ZrSiO4 ( ␬ ⫽12), may be
both properties. There are two main contributions of interest expected at low concentrations for these materials 共see bond-
5268 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

ing model in Fig. 20兲. Recent independent measurements of often observed for higher atomic number metal oxides, par-
the enhanced dielectric constants have also been ticularly for the transition metals. It is important to note that
confirmed.143共a兲,143共b兲,143共c兲 these partially filled and nonbonding levels are not the result
Another phenomenon which can contribute to an in- of defects within the material, but rather are intrinsic to such
creased dielectric constant involving atom motion is soft atomic constituents where many orbitals are available for
phonons. This differs from a non-volatile polarization 共e.g., electron conduction. This general band gap reduction for
as found in ferroelectrics兲, in that the atoms do not remain higher-␬ materials is a limitation that must be realized and
displaced after the electric field is removed 共ferroelectricity expected when selecting a suitable high-␬ gate dielectric.
is the limit at which certain cations remain displaced in one In the cases of Ta2O5 and TiO2, both materials have
of two stable positions after the external field is removed兲. small E G values and correspondingly small ⌬E C values.
Rather, higher atomic number atoms can resonate in their These small ⌬E C values directly correlate with high leakage
bonding structures at low vibrational frequency modes, currents for both materials, making pure Ta2O5 and TiO2
which produces a soft phonon 共since it is at relatively low unlikely choices for gate dielectrics. Table I also shows,
frequency兲. These phonons then make a lattice contribution however, that La2O3, HfO2, and ZrO2 offer relatively high
to the overall polarizability, and therefore to the permittivity values for both ␬ and E G . It is important to note that all of
of the material. It appears that some of the high-␬ dielectrics the high-␬ metal oxides listed in Table I, which includes
of interest exhibit the earlier-mentioned effects, leading to those studied for gate dielectric applications, are crystalline
substantially increased permittivities even at compositions at relatively low temperature 共except Al2O3兲. The signifi-
with low metal levels. By achieving good bonding models of cance of the film structure will be further discussed in Sec.
these materials, some of these materials properties can begin VI D.
to be better understood and predicted, as a way to optimize Although many researchers originally assumed that se-
the choice of dielectric for this application. lecting a dielectric with ␬ ⬎25 would be necessary to replace
It is therefore reasonable to expect any intrinsic contri- SiO2, the more relevant consideration is whether the desired
bution to the dielectric constant will be maintained for rea- device performance 共i.e., drive current兲 can be obtained at
sonable device operation frequencies, although other extrin- the prescribed operating voltage without producing unac-
sic factors such as defects may lead to an effective decrease ceptable off-state 共leakage兲 currents and reliability character-
in permittivity at much lower frequencies. istics. It is therefore more appropriate to find a dielectric
In contrast to the general trend of increasing permittivity which provides even a moderate increase in ␬, but which
with increasing atomic number for a given cation in a metal also produces a large tunneling barrier and high-quality in-
oxide, the band gap E G of the metal oxides tends to decrease terface to Si. With this in mind, if a single dielectric layer
with increasing atomic number, particularly within a particu- can be used, then even a material with ␬ ⬃12– 20 will allow
lar group in the periodic table. An intuitive explanation for a physical dielectric thickness of 35–50 Å to obtain the t eq
this phenomenon is that the corresponding bonding and anti- values required for 0.1 ␮m CMOS and beyond.
bonding orbitals of the metal-oxygen atoms form a valence
band and a conduction band, respectively. For the case of
B. Thermodynamic stability on Si
SiO2, the ␴ bonds formed by the sp hybrid orbitals 共which
arise from Si s,p and O p orbitals兲 have a ␴ bonding orbital For all thin gate dielectrics, the interface with Si plays a
energy level and a higher ␴ * antibonding orbital energy key role, and in most cases is the dominant factor in deter-
level. The energy separation between these levels defines a mining the overall electrical properties. Most of the high-␬
band gap, but this may or may not be the minimum band gap metal oxide systems investigated thus far have unstable in-
in the material. For even the simple case of SiO2, where terfaces with Si: that is, they react with Si under equilibrium
there are only s and p electron orbitals that are all filled conditions to form an undesirable interfacial layer. These
during bonding, the oxygen electron lone pair energy level materials therefore require an interfacial reaction barrier, as
actually defines the valence band maximum 共rather than the mentioned previously. Any ultrathin interfacial reaction bar-
␴ bonding energy level兲. The result is the often reported rier with t eq⬍20 Å will have the same quality, uniformity
band gap of SiO2 ,E G ⬃9 eV. If the ␴ and ␴ * bonds defined and reliability concerns as SiO2 does in this thickness re-
the valence band maximum and conduction band minimum, gime. This is especially true when the interface plays a de-
respectively, then the band gap of SiO2 would be larger. termining role in the resulting electrical properties. It is im-
Thus for the transition metal oxides, which all have five portant to understand the thermodynamics of these systems,
d electron orbitals and other non-bonding p orbitals, the band and thereby attempt to control the interface with Si.
gaps of these oxides can be significantly decreased by the An important approach toward predicting and under-
presence of partially filled d orbitals, which have available standing the relative stability of a particular three-component
states for electron occupancy. These orbital energy levels system for device applications can be explained through ter-
tend to lie within the gap defined by the ␴ and ␴ * orbitals. nary phase diagrams.156,157 An analysis of the Gibbs free
The d orbital levels which lie within the gap defined by ␴ energies governing the relevant chemical reactions for the
and ␴ * levels are all therefore available for electron conduc- Ta–Si–O and Ti–Si–O ternary systems, as shown in Figs.
tion at significantly lower energy levels than would be ex- 19共a兲 and 19共b兲, indicates that Ta2O5 and TiO2 共or mixtures
pected from ␴ and ␴ * alone. This effect offers a somewhat with Si兲, respectively, are not stable to SiO2 formation when
intuitive explanation regarding the lower band gaps that are placed next to Si. Rather, the tie lines in 共a兲 and 共b兲 show that
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5269

Ta2O5 and TiO2 on Si will tend to phase separate into SiO2 Sec. VI A, this tradeoff for interfacial control will be accept-
and metal oxide 共Mx Oy , M⫽metal兲, and possibly silicide able as long as the resulting leakage currents are low enough.
(Mx Siy ) phases. The phase diagrams in Figs. 19共a兲 and 19共b兲
are shown for temperatures of 700–900 °C, but these rela-
tions are also valid at much lower temperatures. As men- C. Interface quality
tioned in Sec. I, this instability to SiO2 formation has been A clear goal of any potential high-␬ gate dielectric is to
observed experimentally for both of these metal oxides,75,103 attain a sufficiently high-quality interface with the Si chan-
which leads to the necessity for an additional interfacial nel, as close as possible to that of SiO2. It is difficult to
layer. imagine any material creating a better interface than that of
In contrast to the Ta and Ti systems, the tie lines in the SiO2, since typical production SiO2 gate dielectrics have a
phase diagram for the Zr–Si–O system,158 shown in Fig. midgap interface state density D it⬃2⫻1010 states/cm2. Most
19共c兲, indicate that the metal oxide ZrO2 and the compound of the high-␬ materials reported in this paper show D it
silicate ZrSiO4 will both be stable in direct contact with Si up ⬃1011 – 1012 states/cm2, and in addition exhibit a substantial
to high temperature. The gray shaded area in Fig. 19共c兲 de- flatband voltage shift ⌬V FB⬎300 mV 共possibly from fixed
notes a large phase field of (ZrO2 ) x (SiO2 ) 1⫺x compositions charge densityⲏ1012/cm2 at the interface兲. It is crucial to
which are expected to be stable on Si up to high tempera- understand the origin of the interface properties of any
tures. Other (ZrO2 ) x (SiO2 ) 1⫺x compositions outside of the high-␬ gate dielectric, so that an optimal high-␬ –Si interface
gray area are also stable on Si, but since it is desirable to may be obtained.
prevent any Zr–Si bonding, film compositions within the Recent work by Lucovsky et al.58 previously has shown
gray area may be preferable. Furthermore, even within the that bonding constraints must also be considered at the Si-
shaded area, compositions with high O levels 共closer to dielectric interface. It is shown empirically58 that if the av-
ZrSiO4兲 are preferred because this will be more likely to erage number of bonds per atom N av⬎3, the interface defect
prevent M–Si bond 共and silicide phase兲 formation. In fact, density increases proportionally, with a corresponding deg-
the existence of this large phase field of stable radation in device performance. Metal oxides which contain
(ZrO2 ) x (SiO2 ) 1⫺x compositions implies yet another poten- elements with a high coordination 共such as Ta and Ti兲 will
tial advantage, in that the level of Zr 共or Hf兲 incorporated have a high N av , and form an overconstrained interface with
into the silicate film could be gradually increased from one Si. Degradation in leakage current and electron channel mo-
technology node to the next. This gradual shift in film com- bility is therefore expected. Similarly, cations with low co-
position could provide a continually higher ␬ value 共up to a ordination 共e.g., Ba, Ca兲 compared to that of Si lead to un-
point兲, as is needed to meet device performance require- derconstrained systems in the corresponding metal oxides.
ments. These systems 共metal oxides, ternary alloys, etc.兲 which are
This behavior is expected to be the same for the Hf– either over- or underconstrained with respect to SiO2, lead to
Si–O system based on coordination chemistry arguments. formation of a high density of electrical defects near the
Although the thermodynamic information is incomplete for Si-dielectric interface, resulting in poor electrical properties.
the Hf–Si–O system, the available data suggests that HfO2 These bonding arguments can be extended to silicide
and HfSiO4, as well as a large range of (HfO2 ) x (SiO2 ) 1⫺x formation in the gate dielectric, or even to any M–Si bond-
compositions, will be stable in direct contact with Si up to ing 共not necessarily a full silicide phase兲. Any silicide bond-
high temperatures.159–161 This fundamental difference from ing which forms near the channel interface 共as may result
the Ta and Ti systems is extremely important, because it when a metal oxide is placed in direct contact with, or near,
suggests that there is potential to control the dielectric-Si Si兲, will tend to produce unfavorable bonding conditions,
interface. While it is certainly the case that all deposition leading to poor leakage current and electron channel mobili-
techniques of interest are done under nonequilibrium condi- ties. In order to maintain a high-quality interface and channel
tions, it is unlikely that a desirable, metastable phase, such as mobility, it is expected to be important to have no metal
amorphous Ta2O5 共which can be obtained under nonequilib- oxide or silicide phases present at or near the channel inter-
rium deposition conditions兲, will be maintained throughout face.
all of the thermal cycling required for CMOS processing. It is interesting to consider the binary oxides which are
Even in the case of process modifications such as a replace- more thermally stable than SiO2, some of which are shown
ment gate flow,69 which allows the high-temperature pro- in Table I, including Al2O3, Y2O3, La2O3, ZrO2, and HfO2
cessing to be done before deposition of the final gate dielec- 共also covered in a thorough study by Hubbard and
tric, the continued thermal cycling afterward is sufficient to Schlom兲.157 The requirement on bonding constraints men-
result in poor electrical properties.69 It is therefore important tioned earlier, however, may significantly reduce the list of
to select a materials system in which the desired final state is materials. Although Al2O3 is a special case in the way that
a stable one. Al cations bond within the network 共alternating Al–O tetra-
Figure 19共c兲 indicates that use of (ZrO2 ) x (SiO2 ) 1⫺x hedra and octahedra兲, Y2O3 and La2O3 are underconstrained
关and therefore (HfO2 ) x (SiO2 ) 1⫺x 兴 should allow for control and may therefore form very high defect densities at the
of the Si interface, which may solve a key problem for the channel interface. More highly coordinated metals such as
high-␬ gate dielectric materials approaches. The ␬ values of Nb, V, and Mn are not only overconstrained, but each also
(HfO2 ) x (SiO2 ) 1⫺x and (ZrO2 ) x (SiO2 ) 1⫺x are substantially has several different stable oxidation states, and will there-
lower than those of pure HfO2 and ZrO2, but as mentioned in fore lead to oxygen vacancies and electron trap sites. In ad-
5270 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

dition to binary systems, pseudobinary systems are excellent cant variations in ␬, leading to irreproducible properties. The
candidates for gate dielectrics. Adding a third component to previously mentioned studies by Houssa et al.118 and Perkins
an alloy or network may favorably affect the material in et al.,127 however, appear to be counter-examples, as both
terms of thermal stability, bonding constraints and in mor- reported very encouraging electrical properties for ALCVD
phology. ZrO2. It should be noted, however, that both studies also
Several simple oxides such as ZrO2 and HfO2 have been used a gate dielectric stack, with the ZrO2 film on top of an
previously reported as having high oxygen diffusivities.112 amorphous SiO2 layer. It is unclear at this point to what
This is a serious concern regarding control of the interface extent the amorphous SiO2 layer affords the encouraging
once it is initially formed. Any annealing treatments which electrical properties, but this issue will become important, as
have an excess of oxygen present 共either from the ambient or the SiO2 layer presents a limit to the minimum achievable t eq
from a sidewall oxide, for example兲, will lead to rapid oxy- value for these structures.
gen diffusion through the oxides, resulting in SiO2 or Work by van Dover,109 as previously discussed, used
SiO2-containing interface layers. Although we have already lanthanide dopants in TiOx films to create and maintain an
shown that SiO2 is an ideal interface with Si, an uncontrolled amorphous film for capacitor applications, even though TiO2
amount of SiO2 formation at the interface will severely com- is typically crystalline even at low temperatures 共see Table
promise the capacitance gain from any high-␬ layers in the I兲. Very encouraging results were obtained, as both high per-
gate stack. Caution must therefore be used in assessing the mittivities and low leakage currents were achievable with
interface stability of high-␬ dielectrics, as resistance to oxy- Nd, Tb, and Dy dopants. Although these particular films are
gen diffusion in annealing ambients should be characterized. not stable on Si, similar approaches may be useful for gate
Another annealing ambient of concern is forming gas 共typi- dielectrics.
cally 90% N2:10%H2兲, which is a standard final anneal in Single crystal oxides grown by MBE methods82,98 can in
the CMOS process and is believed to passivate interfacial principle avoid grain boundaries while providing a good in-
traps 共dangling bonds兲 with hydrogen. Since many high-␬ terface, but these materials also require submonolayer depo-
dielectrics will be reduced in the presence of H2 共the Ti- sition control, which may only be obtainable by MBE ap-
containing perovskites are all severely reduced by even low proaches 共see Sec. VI F for further discussion on the MBE
temperature anneals in forming gas兲, high-␬ gate dielectrics deposition method兲. Kwo et al.98 formed capacitors with
also need to be characterized with respect to the effect of single-domain, crystalline Gd2O3 films on Si by MBE, which
anneals in reducing ambients. had no apparent interfacial layer according to infrared ab-
The ideal gate dielectric stack may well turn out to have sorption spectroscopy 共not shown in the article兲. The leakage
an interface comprised of several monolayers of Si–O 共and current for these films was 10⫺3 A/cm2 at 1 V bias, and C – V
possibly N兲 containing material, which could be a pseudobi- analysis showed ␬ ⬃14, while some frequency dependence
nary layer, at the channel interface. This layer could serve to was observed and the permittivity decreased with decreasing
preserve the critical, high-quality nature of the SiO2 interface film thickness.98 For perovskite materials such as SrTiO3,
while providing a higher-␬ value for that thin layer. The where the structure consists of alternating SrO and TiO2
same pseudobinary material could also extend beyond the planes, each single atomic-height step edge 共which always
interface, or a different high-␬ material could be used on top exist on the surface of Si wafers兲 may possibly serve as a
of the interfacial layer. nucleation site for an antiphase boundary and possibly a
grain boundary. As will be discussed in Sec. VI E, any of
these dielectrics which require interfacial layers on the Si
D. Film morphology
channel 共to avoid reaction between the high-␬ material and
Most of the advanced gate dielectrics studied to date are Si兲 will also require metal gate, or perhaps a buffer layer at
either polycrystalline or single crystal films, but it is desir- the poly-Si gate interface. In contrast, amorphous films will
able to select a material which remains in a glassy phase exhibit isotropic electrical properties, will not suffer from
共amorphous兲 throughout the necessary processing treatments. grain boundaries, and can easily be deposited by manufac-
As shown in Table I, nearly all metal oxides of interest, with turable techniques.
the exception of Al2O3, will form a polycrystalline film ei- Given the concerns regarding polycrystalline and single
ther during deposition or upon modest thermal treatments: crystal films, it appears that an amorphous film structure is
HfO2 and ZrO2 are no exceptions. It is important to note, the ideal one for the gate dielectric 共although some initial
however, that the phases listed in Table I are bulk properties, electrical results for a polycrystalline ZrO2 layer on an amor-
and there will certainly be some suppression of crystalliza- phous SiO2-containing layer look encouraging兲. This is yet
tion for very thin films such as gate dielectrics, at tempera- another clear virtue of SiO2. The Zr–Si–O system in Fig.
tures where crystallization would otherwise be expected to 17共c兲, and analogously the Hf–Si–O system, indicates that
occur. The extent of crystallization suppression for a given the only stable ternary crystalline compound is ZrSiO4 共or
oxide will depend on composition and thermal processing. HfSiO4兲. While it is possible that other ternary crystalline
Polycrystalline gate dielectrics may be problematic be- compounds do exist, it is unlikely. Bulk thermodynamics
cause grain boundaries serve as high-leakage paths, and this therefore suggests that a phase field 关gray shaded area in Fig.
may lead to the need for an amorphous interfacial layer to 17共c兲兴 exists for relatively low levels of Zr or Hf in which a
reduce leakage current. In addition, grain size and orientation (ZrO2) x (SiO2) 1⫺x or (HfO2) x (SiO2) 1⫺x composition can be
changes throughout a polycrystalline film can cause signifi- obtained which will remain amorphous and stable on Si up to
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5271

high temperatures, without phase separating into crystalline

MSiO4 or MO2 and SiO2.

E. Gate compatibility
A significant issue for integrating any advanced gate di-
electric into standard CMOS is that the dielectric should be
compatible with Si-based gates, rather than require a metal
gate. Si-based gates are desirable because dopant implant FIG. 27. Energy diagrams of threshold voltages for nMOS and pMOS
conditions can be tuned to create the desired threshold volt- devices using 共a兲 midgap metal gates and 共b兲 dual metal gates.
age V T for both nMOS and pMOS, and the process integra-
tion schemes are well established in industry. Nearly all of
the potential advanced gate dielectrics investigated to this one metal would be required for the gate electrode 共no ion
point, however, require metal gates. This is expected because implantation step would be required兲.
the same instability with Si, mentioned in Sec. VI B, will For the case of sub-0.13 ␮m bulk CMOS devices, how-
exist at both the channel and the poly-Si gate interfaces. ever, a major drawback is that the band gap of Si is fixed at
Specifically, metal gates such as TiN and Pt have been 1.1 eV, thus the threshold voltage for any midgap metal on
used with most of the high-␬ gate dielectrics mentioned Si will be ⬃0.5 V for both nMOS and pMOS. Since voltage
above to prevent reaction at the gate interface. Attempts have supplies are expected to be ⭐1.0 V for sub-0.13 ␮m CMOS
been made to use doped poly-Si gates with Ta2O5, by depos- technology, V T ⬃0.5 V is much too large, as it would be
iting a CVD SiO2 reaction barrier, which is of lower electri- difficult to turn on the device. Typical threshold voltages for
cal quality than thermal oxide, on top of the Ta2O5 layer.71 these devices are expected to be 0.2–0.3 V. Compensation
The presence of SiO2 at both the channel and gate interface implants can be made in the channel to lower the V T , but
predictably limited the device performance, and the lowest other concerns then arise regarding increased impurity ion
obtainable oxide equivalent was t eq⫽23Å. Even initial at- scattering, which would degrade the channel carrier mobility.
tempts to use poly-Si gates with ZrO2116,120 have been un- Furthermore, midgap work function metal gate systems have
successful 共recent work, however, has shown improved been predicted not to provide a performance improvement
poly-Si stability on HfO2兲,125,126 as reaction layers have been worthy of the added process complexity to replace Si-based
observed at the interface. On the other hand, another benefit gates.162
of a pseudobinary system such as a silicate116,137 in contact The second main approach toward metal electrodes in-
with a poly-Si electrode is more inherent stability, since a volves two separate metals, one for pMOS and one for
significant amount of Si is already contained within the di- nMOS devices. As shown in Fig. 27共b兲, two metals could be
electric. Al2O3 has been shown to be stable with respect to chosen by their work functions, ⌽ M , such that their Fermi
reaction with the poly-Si gates throughout typical CMOS levels line up favorably with the conduction and valence
processing, as expected.90–92 As mentioned previously in bands of Si, respectively. In the ideal case depicted in Fig.
Sec. V C 1, however, both boron and phosphorous dopant 27共b兲, the ⌽ M value of Al could achieve V T ⬃0.2 V for
diffusion have been observed with Al2O3 gate dielectrics, nMOS, while the higher ⌽ M value of Pt could achieve V T
which cause significant, undesired shifts of V FB and V T ⬃0.2 V for pMOS. In practice, Al is not a feasible electrode
values.90,92 These results place more emphasis on the need to metal because it will reduce nearly any oxide gate dielectric
better understand dopant diffusion through all potential to form an Al2O3-containing interface layer. Other metals
high-␬ candidates. with relatively low work functions, such as Ta and TaN,
Metal gates are very desirable for eliminating dopant however, are feasible gate metals for nMOS. Similarly for
depletion effects and sheet resistance constraints. In addition, pMOS, Pt is not a practical choice for the gate metal, since
use of metal gates in a replacement gate process69,139 can it is not easily processed, does not adhere well to most di-
lower the required thermal budget by eliminating the need electrics, and is expensive. Other elemental metals with high
for a dopant activation anneal in the poly-Si electrode. There ⌽ M values such as Au are also not practical, for the same
are two basic approaches toward achieving successful inser- reasons as for Pt.
tion of metal electrodes: a single midgap metal or two sepa- As an alternative to elemental metals, conducting metal
rate metals. The energy diagrams associated with these two oxides such as IrO2 and RuO2, which have been studied for
approaches are shown in Fig. 27. years in DRAM applications,1 can provide high ⌽ M values
The first approach is to use a metal 共such as TiN兲 that in addition to affording the use of standard etching and pro-
has a work function that places its Fermi level at the midgap cessing techniques. Alloys of these and similar conducting
of the Si substrate, as shown in Fig. 27共a兲. These are gener- oxides can also potentially be fabricated to achieve a desired
ally referred to as ‘‘midgap metals.’’ The main advantage of work function. Regarding potential gate electrodes for
employing a midgap metal arises from a symmetrical V T pMOS devices, Zhong et al.163,164 made initial measure-
value for both nMOS and pMOS, because by definition the ments of the important properties of RuO2, including thermal
same energy difference exists between the metal Fermi level stability up to 800 °C, a low resistivity of 65 ␮⍀ cm, and a
and the conduction and valence bands of Si. This affords a measured work function of ⌽ M ⫽5.1 eV. All of the measure-
simpler CMOS processing scheme, since only one mask and ments were made on capacitors with both SiO2 and Zr-
5272 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

silicate dielectrics. More work must be done to better under- iting Al2O3, 87 ZrO2, 113,118,120,127 and HfO2120 appears to pro-
stand alternative metal electrodes, both for midgap metal and vide much promise, where self-limiting chemistries are em-
dual metal approaches, as a means to alleviate potentially ployed to control film formation in a layer-by-layer fashion.
limiting properties of doped poly-Si. As discussed before, attention to the surface preparation and
It should also be noted that for the scaling trend to sub- the resultant chemistry must be carefully considered.
0.1 ␮m CMOS, other efforts are focused on using poly- In addition to the examples discussed above which em-
Si1⫺x Gex gates for achieving higher boron activation ploy PVD and CVD methods, very high-␬ dielectrics, such
levels165,166 and therefore better performance in pMOS de- as SrTiO3 have been deposited directly on Si using MBE
vices, and potentially better performance in nMOS devices methods 共Fig. 11兲. An equivalent oxide thickness of less than
as well.166 It is therefore still desirable to employ a gate 10 Å was reported 共physical thickness 110 Å兲 with dramatic
dielectric which will be compatible in direct contact with improvements in transistor performance 共Fig. 10兲. More re-
Si-based gates. The pseudobinary alloys mentioned in Sec. cently, crystalline ZrO2 共stabilized by Y2O3 ) has also been
V C 3 are predicted to be stable next to Si-based gates as well examined by MBE methods.167 However, a manufacturable
as metal gates. Since doped poly-Si is the incumbent gate scaled CMOS process incorporating MBE methods, with the
electrode material, however, dopant diffusion studies must inherent poor throughput relative to present Si-based fabri-
be carried out to determine how dopants in poly-Si diffuse cation operations, remains a clear challenge. Further ad-
through any potential high-␬ gate material. vances in ALCVD approaches, however, may make such
For CMOS scaling in the longer term, however, current polycrystalline dielectrics a reality in the manufacturing en-
roadmap predictions indicate that poly-Si gate technology vironment.
will likely be phased out beyond the 70 nm node, after which
a metal gate substitute appears to be required.5 It is therefore
also desirable to focus efforts on dielectric materials systems G. Reliability
which are compatible with potential metal gate materials. A As previously discussed in Sec. IV B, the electrical reli-
key issue for gate electrode materials research will be the ability of a new gate dielectric must also be considered criti-
control of the gate electrode work function 共Fermi level兲 af- cal for application in CMOS technology. The determination
ter CMOS processing. of whether or not a high-␬ dielectric satisfies the strict reli-
ability criteria requires a well-characterized materials
system—a prospect not yet available for the alternate dielec-
F. Process compatibility
tric materials considered here. The nuances of 共1兲 the depen-
A crucial factor in determining the final film quality and dence of voltage acceleration extrapolation on dielectric
properties is the method by which the dielectrics are depos- thickness and 共2兲 the improvement of reliability projection
ited in a fabrication process. The deposition process for the arising from improved oxide thickness uniformity, both dis-
dielectric must be compatible with current or expected cussed in Sec. IV B, have only recently become understood,
CMOS processing, cost, and throughput. Since all of the fea- despite decades of research on SiO2. This further emphasizes
sible deposition techniques available occur under nonequilib- the importance and urgency to investigate the reliability
rium conditions, it is certainly possible to obtain properties characteristics of alternative dielectrics, as these materials
different from those expected under equilibrium conditions. are sure to exhibit subtleties in reliability that differ from
It is therefore important to consider the various methods for those of SiO2.
depositing the gate dielectrics, and the following techniques This being stated, some preliminary projections for reli-
will be discussed here: physical vapor deposition 共PVD兲 ability, as determined by stess-induced leakage current
共e.g., sputtering and evaporation兲, CVD, ALCVD, and MBE. 共SILC兲, time-dependent dielectric breakdown, and mean
PVD methods have provided a convenient means to time to failure measurements, appear to be encouraging for
evaluate materials systems for alternate dielectric applica- Al2O389–91 and HfO2 films.122,124 Similar preliminary mea-
tions. The damage inherent in a sputter PVD process, how- surements of ZrO2 films appear to be somewhat mixed, as
ever, results in surface damage and thereby creates unwanted both very promising114 and less encouraging139 results have
interfacial states. Additionally, device morphology inherent been reported. Despite excellent ten-year reliability projec-
to the scaling process generally rules out such line-of-sight tions at high applied voltages of 2.0–2.5 V reported for these
PVD deposition approaches. For this reason, CVD methods materials,89–91,114,122,124 it is essential to carry out proper area
have proven to be quite successful in providing uniform cov- scaling conversion, to account for the difference between
erage over complicated device topologies. individual capacitors in these cases, and a full chip area in a
As pointed out, the reaction kinetics associated with film realistic situation.32 Proper area scaling can significantly de-
CVD deposition require careful attention in order to control grade the ten-year reliability projection. Results of reliability
interfacial layer formation. The precursor employed in the investigations for pseudobinary alloys are not yet published.
deposition process must also be tailored to avoid unwanted It is clear, however, that the determination of the preferred
impurities in the film as well as permit useful final compo- dielectric constituent composition has yet to be completed
sitions in the dielectric film. Indeed, a graded composition thus making even initial reliability extrapolations problem-
for dielectric films may be a key requirement in order to atic. Moreover, recent lessons from the scaling changes as-
control interface state formation to a level comparable to sociated with ultrathin SiO2 may come into play with these
SiO2. The recent application of ALCVD methods for depos- new materials. Clearly, more work in production-worthy de-
J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony 5273

velopment fabrication facilities will be required to critically nologies, and Luigi Colombo of Texas Instruments, for many
address these issues. useful discussions. The authors are grateful to Charles Wilk
for several insightful suggestions regarding the manuscript.
VII. CONCLUSIONS One of the authors 共R.M.W.兲 gratefully acknowledges the
A review of the state-of-the-art of the ongoing research support of the Texas Advanced Technology Program, the
for an alternative gate dielectric to SiO2 for Si-based CMOS Semiconductor Research Corporation, and the Defense Ad-
was presented. Key materials considerations discussed in- vanced Research Projects Agency in the preparation of this
clude: 共a兲 permittivity, band gap, and barrier height, 共b兲 ther- review.
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