Topics

Pseudo-nMOS gates.
DCVS gates.
Dynamic CMOS
Domino gates.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 A Pseudo-nMOS Gate
VDD VDD

PUN
Pull
up
network

Output Output

PDN
Inputs

Inputs
Pull
down
PDN
network

CMOS Gate Pseudo-nMOS Gate

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Pseudo-nMOS

Uses a p-type as a resistive pullup, n-type network

for pulldowns.
a b out
Always on.
0 0 1
0 1 0
1 0 0
1 1 0

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Characteristics

Consumes static power.

Has much smaller pullup network than
static gate.
Pulldown time is longer because pullup is
fighting.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Output voltages

Logic 1 output is always at VDD.

Logic 0 output is above Vss.
VOL = 0.25 (VDD - VSS) is one plausible
choice.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Producing output voltages

For logic 0 output, pullup and pulldown

form a voltage divider.
Must choose n, p transistor sizes to create
effective resistances of the required ratio.
Effective resistance of pulldown network
must be computed in worst case—series n-
types means larger transistors.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Transistor ratio calculation

In steady state logic 0 output:

– pullup is in linear region,Vds = Vout - (VDD -
VSS) ;
– pulldown is in saturation.
Pullup and pulldown have same current
flowing through them.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Transistor ratio, cont’d.

Equate two currents with pull-down

transistor in saturation and pull-up in linear
region:
– Idp = Idd.
Using 0.5 mm parameters, 3.3V power
supply:
– Wp/Lp / Wn/Ln = 3.9.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Pseudo-nMOS NOR
VDD

Output

Input 1 Input 2 Input 3

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Pseudo-nMOS NAND
VDD

Output

Input 1

Input 2

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Pseudo-nMOS Inverter
VDD

Output

Input

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Negative Aspects of Pseudo-nMOS

Output 0 state is ratioed logic.

Faster gates mean higher static power.
Low static power means slow gates.
Possible remedy: Try dynamic logic.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 DCVS logic

DCVSL = differential cascode voltage logic.

Static logic—consumes no dynamic or static
power.
Uses latch to compute output quickly.
Requires true/complement inputs, produces
true/complement outputs.
The cascode (sometimes verbified to cascoding) is a universal technique for improving
analog circuit performance, applicable to both vacuum tubes and transistors. The word
was first used in an article by F.V. Hunt and R.W. Hickman in 1939, in a discussion for
application in low-voltage stabilizers. They proposed a cascade of two triodes (first one
with common cathode, the second one with common grid) as a replacement of a
pentode.
http://en.wikipedia.org/wiki/Cascode
Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 DCVS structure

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 DCVS operation

Exactly one of true/complement pulldown

networks will complete a path to the power
supply.
Pulldown network will lower output
voltage, turning on other p-type, which also
turns off p-type for node which is going
down.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 DCVS example

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 A Dynamic CMOS Gate
VDD

Precharge
transistor
Output
Inputs

PDN CL

Evaluate
CK transistor

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Two-Phase Operation in a Vector Period

Phase CK Inputs Output

Precharge low don’t care high

Evaluation high Valid inputs Valid outputs

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 4-Input NAND Dynamic CMOS Gate

VDD

CK
Output
A = CK’ + (ABCD)’∙ CK
CL
B

C tL→H ≈ 0

CK

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Characteristics of Dynamic CMOS
Nonratioed logic – sizing of pMOS transistor is not important for
output levels.
Smaller number of transistors, N+2 vs. 2N for CMOS.
Faster switching due to smaller capacitance.
Larger precharge transistor reduces output precharge time, but
increases precharge power.
Static power – negligible, similar to CMOS.
Short-circuit power – none.
Dynamic power
– no glitches – following precharge, signals can either make transition only in
one direction, 1→0, or no transition, 1→1.
– only logic transitions – all nodes at logic 0 are charged to VDD during
precharge phase.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 A Problems With Dynamic CMOS

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Remedy

Set all gate inputs to 0 during precharge.

Since precharge raises all outputs to 1,
inserting inverters between gates will do the
trick.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Domino CMOS
VDD VDD
CK prech. evaluate
CK CK C
A
A = 0 →1 B

CK B
CK

R. H. Krambeck, C. M. Lee and H.-F. S. Law, “High-Speed Compact

Circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3,
pp. 614-619, June 1982.
Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Domino CMOS

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Domino logic

Uses precharge clock to compute output in

two phases:
– precharge;
– evaluate.
Is not a complete logic family—cannot
invert.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR
 Domino gate structure

Domino OR gate
Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR