VLSI Lab Report

Department of Electronics and Electrical Communication

Engineering

Submitted by:
Aditya Agarwal (Roll No.: 22EC10004)
Shreyans Sharma (Roll No. 22EC10072)

Group Number: 4

Experiment No.: 4
Finite State Machines

Date of Submission: 17th February 2025

 OBJECTIVE
To design an FSM that outputs ”1” if the aggregate binary input is divisible by 5 using verilog
and demonstrate through testbench waveforms.

THEORY
Finite State Machines (FSMs)
A Finite State Machine (FSM) is a sequential circuit model used to design digital logic that
transitions between a finite number of states based on input values.

State Transition Logic

The transitions between states are determined based on the incoming binary digit (0 or 1). The
current remainder is updated based on the following logic:
• S0 : Remainder = 0, transitions to S1 if input is 1, stays in S0 if input is 0.
• S1 : Remainder = 1, transitions to S3 if input is 1, S2 if input is 0.
• S2 : Remainder = 2, transitions to S0 if input is 1, S4 if input is 0.
• S3 : Remainder = 3, transitions to S2 if input is 1, S1 if input is 0.
• S4 : Remainder = 4, transitions to S4 if input is 1, S3 if input is 0.

State Transition Diagram

0

1
start S0 S1

0
0
1 1
1
S3 S2

0
0

S4

Output Function
Since this is a Moore FSM, the output is solely dependent on the current state. The output is
defined as: (
1, if state = S0 (i.e., remainder 0)
out =
0, otherwise

1
 VERILOG CODES
Design of FSM
1 module FSM_Div5 (
2 input wire clk ,
3 input wire rst ,
4 input wire serial_in ,
5 output reg out
6 );
7
8 parameter S0 = 3 ’ b000 , S1 = 3 ’ b001 , S2 = 3 ’ b010 , S3 = 3 ’ b011 , S4 =
3 ’ b100 ;
9 reg [2:0] state ;
10
11 always @ ( posedge clk or posedge rst ) begin
12 if ( rst ) begin
13 state <= S0 ;
14 out <= 1;
15 end
16 else begin
17 case ( state )
18 S0 : state <= ( serial_in ) ? S1 : S0 ;
19 S1 : state <= ( serial_in ) ? S3 : S2 ;
20 S2 : state <= ( serial_in ) ? S0 : S4 ;
21 S3 : state <= ( serial_in ) ? S2 : S1 ;
22 S4 : state <= ( serial_in ) ? S4 : S3 ;
23 default : state <= S0 ;
24 endcase
25
26 out <= ( state == S0 ) ? 1 : 0;
27 end
28 end
29
30 endmodule

2
 Testbench
1 ‘timescale 1 ns / 1 ps
2
3 module fsmdiv5tb ;
4

5 reg clk , rst , serial_in ;

6 wire out ;
7
8 FSM_Div5 uut (. clk ( clk ) , . rst ( rst ) , . serial_in ( serial_in ) , . out ( out ) ) ;
9
10 always #5 clk = ~ clk ;
11
12 initial begin
13 clk = 0; rst = 1; serial_in = 0;
14
15 #10 rst = 0;
16

17 #10 serial_in = 1;
18 #10 serial_in = 1;
19 #10 serial_in = 1;
20 #10 serial_in = 1;
21 #10 serial_in = 0;
22 #10 serial_in = 0;
23 #10 serial_in = 0;
24 #10 serial_in = 1;
25 #10 serial_in = 1;
26 #10 serial_in = 1;
27 #10 serial_in = 1;
28

29 #20 $stop ;
30 end
31
32 initial begin
33 $monitor ( " Time =%0 t | serial_in =% b | state =% b | out =% b " , $time ,
serial_in , uut . state , out ) ;
34 end
35
36 endmodule

3
 OBSERVATIONS
Monitor Output

Timing Diagram

4
 DISCUSSIONS
Shreyans Sharma [22EC10072]
• The FSM follows a Moore model where the output depends only on the current state. It
has five states S0 , S1 , S2 , S3 , S4 , each representing the remainder of the accumulated binary
number divided by 5.

• S0 is the initial and accepting state, indicating divisibility by 5. The states transition
based on incoming bits, updating the remainder accordingly.

• The transition logic follows: shifting the accumulated value left by one and adding the
new bit, then computing the new remainder modulo 5 to determine the next state.

• The output logic is simple: the FSM outputs ‘1’ only when in S0 , otherwise it outputs ‘0’,
ensuring correct divisibility detection.

• The testbench initializes the FSM, applies a clock, and feeds a sequence of binary numbers
while monitoring transitions, verifying that the FSM correctly tracks divisibility.

• The expected output confirms correct functionality, with the FSM producing ‘1’ whenever
the accumulated number is divisible by 5 and ‘0’ otherwise.

Aditya Agarwal [22EC10004]

• This experiment focused on designing a finite state machine (FSM) that determines whether
a given serial binary input is divisible by 5.

• The FSM keeps track of the remainder when the accumulated binary number is divided
by 5, transitioning through five states:

– S0 (000) – Represents a remainder of 0 (number is divisible by 5).

– S1 (001) – Represents a remainder of 1.
– S2 (010) – Represents a remainder of 2.
– S3 (011) – Represents a remainder of 3.
– S4 (100) – Represents a remainder of 4.

• To ensure the output responds in real time, the state transition logic was carefully syn-
chronized with the input signal.

• The FSM updates its state on the falling edge of the clock and outputs a high signal when
it reaches S0, indicating divisibility by 5.

• Testing and waveform analysis confirmed that the FSM functions as expected, correctly
detecting numbers divisible by 5.

• The state transitions followed the predicted pattern, and the output changed immediately
upon recognizing a divisible number.