TLV5630

TLV5631
TLV5632
www.ti.com SLAS269E – MAY 2000 – REVISED JUNE 2005

8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG

CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
FEATURES APPLICATIONS
• Eight Voltage Output DACs in One Package • Digital Servo Control Loops
– TLV5630 . . . 12-Bit • Digital Offset and Gain Adjustment
– TLV5631 . . . 10-Bit • Industrial Process Control
– TLV5632 . . . 8-Bit • Machine and Motion Control Devices
• Mass Storage Devices
– 1 µs in Fast Mode
– 3 µs in Slow Mode DW OR PW PACKAGE
(TOP VIEW)
• Programmable Settling Time vs Power
Consumption DGND 1 20 DVDD
– 1 µs in Fast Mode DIN 2 19 DOUT
SCLK 3 18 LDAC
– 3 µs in Slow Mode
FS 4 17 MODE
– 18 mW in Slow Mode at 3 V 5 16
PRE REF
– 48 mW in Fast Mode at 3 V OUTE 6 15 OUTD
• Compatible With TMS320 and SPI Serial Ports OUTF 7 14 OUTC
• Monotonic Over Temperature OUTG 8 13 OUTB
OUTH 9 12 OUTA
• Low Power Consumption: AGND 10 11 AVDD
– 18 mW in Slow Mode at 3 V
– 48 mW in Fast Mode at 3 V
• Power-Down Mode
• Internal Reference
• Data Output for Daisy-Chaining

DESCRIPTION
The TLV5630, TLV5631, and TLV5632 are pin-compatible, eight-channel, 12-/10-/8-bit voltage output DACs
each with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and
Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits.
Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs,
and a data output which can be used to cascade multiple devices, and an internal programmable band-gap
reference.
The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to
allow the designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be
connected to the supply voltage.
Implemented with a CMOS process, the DACs are designed for single-supply operation from 2.7 V to 5.5 V, and
can operate on two separate analog and digital power supplies. The devices are available in 20-pin SOIC and
TSSOP packages.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2000–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV5630
TLV5631
TLV5632 www.ti.com
SLAS269E – MAY 2000 – REVISED JUNE 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS
PACKAGE
TA
SOIC (DW) TSSOP (PW) RESOLUTION
TLV5630IDW TLV5630IPW 12
40°C to 85°C TLV5631IDW TLV5631IPW 10
TLV5632IDW TLV5632IPW 8

FUNCTIONAL BLOCK DIAGRAM

REF

Band-Gap
Voltage

12/10/8 12/10/8
12/10/8
X2 OUTA
1 V or 2 V
(Trimmed) DAC A
with Enable 2 DAC A
Holding
Latch
Latch
SCLK

DIN

DOUT Serial 12
Interface
FS 8
OUT
MODE DAC B, C, D, E, F, G and H B, C, D,
Same as DAC A E, F, G
PRE and H

LDAC

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
AGND 10 P Analog ground
AVDD 11 P Analog power supply
DGND 1 P Digital ground
DIN 2 I Digital serial data input
DOUT 19 O Digital serial data output
DVDD 20 P Digital power supply
FS 4 I Frame sync input
LDAC 18 I Load DAC. The DAC outputs are only updated, if this signal is low. It is an asynchronous input.
MODE 17 I DSP/µC mode pin. High = µC mode, NC = DSP mode.
PRE 5 I Preset input
REF 16 I/O Voltage reference input/output
SCLK 3 I Serial clock input
OUTA-OUTH 12-15, 6-9 O DAC outputs A, B, C, D, E, F, G and H

2
 TLV5630
TLV5631
www.ti.com
TLV5632
SLAS269E – MAY 2000 – REVISED JUNE 2005

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature (unless otherwise noted)
UNIT
Supply voltage, (AVDD, DVDD to GND) 7V
Reference input voltage range - 0.3 V to AVDD + 0.3
Digital input voltage range - 0.3 V to DVDD + 0.3
Operating free-air temperature range, TA -40°C to 85°C
Storage temperature range, Tstg -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
5-V operation 4.5 5 5.5 V
Supply voltage, AVDD, DVDD
3-V operation 2.7 3 3.3 V
DVDD = 2.7 V 2
High-level digital input, VIH V
DVDD = 5.5 V 2.4
DVDD = 2.7 V 0.6
Low-level digital input, VIL V
DVDD = 5.5 V 1.0
AVDD = 5 V, See (1) GND 2.048 AVDD
Reference voltage, Vref V
AVDD = 3 V, See (1) GND 1.024 AVDD
Analog output load resistance, RL 2 kΩ
Analog output load capacitance, CL 100 pF
Clock frequency, fCLK 30 MHz
Operating free-air temperature, TA -40 85 °C

(1) Reference input voltages greater than AVDD/2 causes saturation for large DAC codes.

ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
No load, All inputs = DVDD or GND, Fast 16 21
IDD Power supply current mA
Vref = 2.048 V, See (1) Slow 6 8
Power-down supply
0.1 µA
current
POR Power on threshold 2 V
Power supply rejection (2)
PSRR Full scale, See -50 dB
ratio

(1) IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7 V and VIL > 0.7 V, supply current increases.
(2) Power supply rejection ratio at full scale is measured by varying AVDD and is given by: PSRR = 20 log [(EG(AVDDmax) -
EG(AVDDmin))/VDDmax]

3
TLV5630
TLV5631
TLV5632 www.ti.com
SLAS269E – MAY 2000 – REVISED JUNE 2005

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC DAC SPECIFICATIONS
TLV5630 12 Bits
Resolution TLV5631 10 Bits
TLV5632 8 Bits
TLV5630 Code 40 to 4095 ±2 ±6 LSB
INL Integral nonlinearity TLV5631 Vref = 1 V, 2 V Code 20 to 1023 ±0.5 ±2 LSB
TLV5632 Code 6 to 255 ±0.3 ±1 LSB
TLV5630 Code 40 to 4095 ±0.5 ±1 LSB
DNL Differential nonlinearity TLV5631 Vref = 1 V, 2 V Code 20 to 1023 ±0.1 ±1 LSB
TLV5632 Code 6 to 255 ±0.1 ±1 LSB
Zero scale error (offset error at zero
EZS ±30 mV
scale)
Zero scale error temperature
EZS TC 30 µV/°C
coefficient
%Full
EG Gain error ±0.6
Scale V
EGTC Gain error temperature coefficient 10 ppm/°C
OUTPUT SPECIFICATIONS
VO Voltage output range RL = 10 kΩ 0 AVDD-0.4 V
Output load regulation %Full
RL = 2 kΩ vs 10 kΩ ±0.3
accuracy Scale V
REFERENCE OUTPUT
VREFOUTL Low reference voltage VDD > 4.75 V 1.010 1.024 1.040 V
VREFOUTH High reference voltage 2.020 2.048 2.096 V
Iref(Source) Output source current 1 mA
Iref(Sink) Output sink current -1 mA
Load capacitance See (3) 1 10 µF
Power supply rejection
PSRR 60 dB
ratio
REFERENCE INPUT
VI Input voltage range 0 AVDD V
RI Input resistance 50 kΩ
CI Input capacitance 10 pF
Reference input Vref = 0.4 Vpp + 2.048 Vdc, Fast 2.2 MHz
bandwidth Input code = 0x800 Slow 1.9 MHz
Reference feedthrough Vref = 2 Vpp at 1 kHz + 2.048 Vdc, See (4) 84 dB
DIGITAL INPUTS
High-level digital input
IIH VI = DVDD 1 µA
current
Low-level digital input
IIL VI = 0 V 1 µA
current
CI Input capacitance 8 pF

(3) In parallel with a 100-nF capacitor

(4) Reference feedthrough is measured at the DAC output with an input code = 0x000.

4
 TLV5630
TLV5631
www.ti.com
TLV5632
SLAS269E – MAY 2000 – REVISED JUNE 2005

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL OUTPUT
High-level digital output RL = 10 kΩ
VOH 2.6 V
voltage
Low-level digital output RL = 10 kΩ
VOL 0.4 V
voltage
Output voltage rise time RL = 10 kΩ, CL = 20 pF, Includes propagation delay 5 10 ns
ANALOG OUTPUT DYNAMIC PERFORMANCE
Output settling time, full Fast 1 3
ts(FS) RL = 10 kΩ, CL = 100 pF, See (5) µs
scale Slow 3 7
Output settling time, Fast 0.5 1
ts(CC) RL = 10 kΩ, CL = 100 pF, See (6) µs
code to code Slow 1 2
Fast 4 10
SR Slew rate RL = 10 kΩ, CL = 100 pF, See (7) V/µs
Slow 1 3
Glitch energy See (8) 4 nV-s
Channel crosstalk 10 kHz sine, 4 VPP 90 dB

(5) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of
0x080 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested.
(6) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one
count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested.
(7) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
(8) Code transition: TLV5630 - 0x7FF to 0x800, TLV5631 - 0x7FCto 0x800, TLV5632 - 0x7F0 to 0x800.

DIGITAL INPUT TIMING REQUIREMENTS

PARAMETER MIN TYP MAX UNIT
tsu(FS-CK) Setup time, FS low before next negative SCLK edge 8 ns
Setup time, 16th
negative edge after FS low on which bit D0 is sampled before rising edge
tsu(C16-FS) 10 ns
of FS. µC mode only
tsu(FS-C17) µC mode, setup time, FS high before 17th positive SCLK. 10 ns
tsu(CK-FS) DSP mode, setup time, SLCK low before FS low. 5 ns
twL(LDAC) LDAC duration low 10 ns
twH SCLK pulse duration high 16 ns
twL SCLK pulse duration low 16 ns
tsu(FS-CK) Setup time, FS low before first negative SCLK edge 8 ns
tsu(D) Setup time, data ready before SCLK falling edge 8 ns
th(D) Hold time, data held valid after SCLK falling edge 5 ns
twH(FS) FS duration high 10 ns
twL(FS) FS duration low 10 ns
See AC
ts Settling time
specs

5
TLV5630
TLV5631
TLV5632 www.ti.com
SLAS269E – MAY 2000 – REVISED JUNE 2005

TYPICAL CHARACTERISTICS

OUTPUT LOAD REGULATION OUTPUT LOAD REGULATION

1 1
VDD = 3 V, VDD = 5 V,
0.9 Vref = 1 V, 0.9 Vref = 2 V,
Zero Scale Zero Scale
0.8 0.8
Fast Fast
VO − Output Voltage − V

VO − Output Voltage − V
0.7 0.7

0.6 0.6

0.5 0.5

0.4 0.4

0.3 0.3

0.2 0.2

0.1 0.1
Slow Slow
0 0
0 0.5 1 1.5 2 0 0.5 1 1.5 2
Sinking Current − mA Sinking Current − mA

Figure 1. Figure 2.

OUTPUT LOAD REGULATION OUTPUT LOAD REGULATION

2.06 4.12
VDD = 3 V, VDD = 5 V,
Vref = 1 V, Vref = 2 V,
2.055 4.11 Full Scale
Full Scale Fast
Slow
VO − Output Voltage − V
VO − Output Voltage − V

4.1
2.05 Fast Slow
4.09
2.045
4.08
2.04
4.07

2.035
4.06

2.03
4.05

2.025 4.04
−0.05 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4
Sourcing Current − mA Sourcing Current − mA

Figure 3. Figure 4.

6
 TLV5630
TLV5631
www.ti.com
TLV5632
SLAS269E – MAY 2000 – REVISED JUNE 2005

TYPICAL CHARACTERISTICS (continued)

TLV5630 INTEGRAL NONLINEARITY
vs
CODE
INL − Integral Nonlinearity − LSB 4
3
2
1
0
−1
−2
−3
−4
0 1024 2048 3072 4096
Code
Figure 5.

TLV5630 DIFFERENTIAL NONLINEARITY

vs
CODE
DNL − Differential Nonlinearity − LSB

1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0 1024 2048 3072 4096
Code
Figure 6.

TLV5631 INTEGRAL NONLINEARITY

vs
CODE
2.0
INL − Integral Nonlinearity − LSB

1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0 256 512 768 1024
Code
Figure 7.

7
TLV5630
TLV5631
TLV5632 www.ti.com
SLAS269E – MAY 2000 – REVISED JUNE 2005

TYPICAL CHARACTERISTICS (continued)

TLV5631 DIFFERENTIAL NONLINEARITY
vs
CODE
DNL − Differential Nonlinearity − LSB
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0 256 512 768 1024
Code
Figure 8.

TLV5632 INTEGRAL NONLINEARITY

vs
CODE
0.5
INL − Integral Nonlinearity − LSB

0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0 50 100 150 200 250
Code
Figure 9.

TLV5632 DIFFERENTIAL NONLINEARITY

vs
CODE
DNL − Differential Nonlinearity − LSB

0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0 50 100 150 200 250
Code
Figure 10.

8
 TLV5630
TLV5631
www.ti.com
TLV5632
SLAS269E – MAY 2000 – REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

twH
twL

SCLK X 1 2 3 4 16 17 X

th(D)
tsu(D)

DIN X D15 D14 D13 D12 D1 D0 X

† † † † † †
DOUT X D15 D14 D13 D12 D1 D0 X

tsu(FS - CK) tsu(FS - C17)

twH(FS) tsu(C16 - FS)
FS
(µC mode)
tsu(CK - FS)
twL(FS)
FS X
(DSP Mode)

† Previous input data

Figure 11. Serial Interface Timing

twL(LDAC)

LDAC

ts ±0.5 LSB

OUTx

Figure 12. Output Timing

9
TLV5630
TLV5631
TLV5632 www.ti.com
SLAS269E – MAY 2000 – REVISED JUNE 2005

APPLICATION INFORMATION

GENERAL FUNCTION
The TLV5630/31/32 are 8-channel, single-supply DACs, based on a resistor string architecture. They consist of a
serial interface, a speed and power-down control logic, an internal reference, a resistor string, and a rail-to-rail
output buffer.
The output voltage (full scale determined by reference) for each channel is given by:

2REF CODE [V]

0x1000
where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF for
the TLV5630, 0x000 to 0xFFC for the TLV5631, and 0x000 to 0xFF0 for the TLV5632.

POWER ON RESET (POR)

The built-in power-on-reset circuit controls the output voltage after power up. On power up, all latches including
the preset register are set to zero, but the DAC outputs are only set to zero if the LDAC is low. The DAC outputs
may have a small offset error produced by the output buffer. The registers remains at zero until a valid write
sequence is made to the DAC, changing the DAC register data. This is useful in applications where it is
important to know the state of the outputs of the DAC after power up. All digital inputs must be logic low until the
digital and analog supplies are applied. Any logic high voltages applied to the logic input pins when power is not
applied to AVDD and DVDD, may power the device logic circuit through the overvoltage protection diode causing
an undesired operation. When separate analog (AVDD) and digital (DVDD) supplies are used, AVDD must come up
first before DVDD, to ensure that the power-on-reset circuit operates correctly.

SERIAL INTERFACE
A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling
edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC
holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to
transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an
asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.
For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.
DSP Mode:

SCLK

FS

DIN X D15 D14 D1 D0 E15 E14 E1 E0 X X X F15 F15

µC Mode:

SCLK

FS

DIN X D15 D14 D1 D0 X E15 E14 E1 E0 X X F15 F15

10
 TLV5630
TLV5631
www.ti.com
TLV5632
SLAS269E – MAY 2000 – REVISED JUNE 2005

APPLICATION INFORMATION (continued)

Difference between DSP mode (MODE = N.C. or 0) and µC (MODE = 1) mode:
• In µC mode, FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before
the 16th falling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS.
• In DSP mode, FS needs to stay low for 20 ns and can go high before the 16th falling clock edge.
• In DSP mode there needs to be one falling SCLK edge before FS goes low to start the write (DIN) cycle.
This extra falling SCLK edge has to happen at least 5 ns before FS goes low, tsu(CK-FS) ≥ 5 ns.
• In µC mode, the extra falling SCLK edge is not necessary. However, if it does happen, the extra negative
SCLK edge is not allowed to occur within 10 ns after FS goes HIGH to finish the WRITE cycle (tsu(FS-C17)).

SERIAL CLOCK FREQUENCY AND UPDATE RATE

The maximum serial clock frequency is given by:

f  1  30 MHz
sclkmax t
t
whmin wlmin
The maximum update rate is:

f  1  1.95 MHz
updatemax  whmin
twlmin
16 t

Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
DAC has to be considered also.

DATA FORMAT
The 16-bit data word consists of two parts:
• Address bits (D15…D12)
• Data bits (D11…D0)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A3 A2 A1 A0 Data

Ax: Address bits. See table.

REGISTER MAP
A3 A2 A1 A0 FUNCTION
0 0 0 0 DAC A
0 0 0 1 DAC B
0 0 1 0 DAC C
0 0 1 1 DAC D
0 1 0 0 DAC E
0 1 0 1 DAC F
0 1 1 0 DAC G
0 1 1 1 DAC H
1 0 0 0 CTRL0
1 0 0 1 CTRL1
1 0 1 0 Preset
1 0 1 1 Reserved
1 1 0 0 DAC A and B
1 1 0 1 DAC C and D
1 1 1 0 DAC E and F
1 1 1 1 DAC G and H

11
TLV5630
TLV5631
TLV5632 www.ti.com
SLAS269E – MAY 2000 – REVISED JUNE 2005

DAC A-H AND TWO-CHANNEL REGISTERS

Writing to DAC A-H sets the output voltage of channel A-H. It is possible to automatically generate the
complement of one channel by writing to one of the four two-channel registers (DAC A and B etc.).
The TLV5630 decodes all 12 data bits. The TLV5631 decodes D11 to D2 (D1 and D0 are ignored). The TLV5632
decodes D11 to D4 (D3 to D0 are ignored).

PRESET
The outputs of the DAC channels can be driven simultaneously to a predefined value stored in the preset register
by driving the PRE input pin low and asserting the LDAC input pin. The preset register is cleared (set to zero) by
the POR circuit after power up. Therefore, it must be written with a predefined value before asserting the PRE
pin low, unless zero is the desired preset value. The PRE input is asynchronous to the clock.
CTRL0
BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X X X X X X PD DO R1 R0 IM
Default X X X X X X X 0 0 0 0 0

PD : Full device power down 0 = normal 1 = power down

DO : DOUT enable 0 = disabled 1 = enabled
R1:0 : Reference select bits 0 = external 1 = external, 2 = internal 1 V, 3 = internal 2 V
IM : Input mode 0 = straight binary 1 = twos complement
X : Reserved

If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. That makes it possible to
daisy-chain multiple DACs on one serial bus.
CTRL1
BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X X X PGH PEF PCD PAB SGH SEF SCD SAB
Default X X X X 0 0 0 0 0 0 0 0

PXY : Power Down DACXY 0 = normal 1 = power down

SXY : Speed DACXY 0 = slow 1 = fast
XY : DAC pair AB, CD, EF or GH

In power-down mode, the amplifiers of the selected DAC pair are disabled and the total power consumption of
the device is significantly reduced. Power-down mode of a specific DAC pair can be selected by setting the PXY
bit within the data word to 1.
There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting SXY to 1 and
slow mode is selected by setting SXY to 0.

12
 TLV5630
TLV5631
www.ti.com
TLV5632
SLAS269E – MAY 2000 – REVISED JUNE 2005

REFERENCE
The DAC reference can be sourced internally or externally by programming bits D2 (R1) and D1 (R0) of the
CTRL0 register (address = 08h). If an external source of reference is applied to the REF pin, the device must be
configured to accept the external reference source by setting R1 and R0 to 00 or 01. If R1 and R0 is set to select
for internal reference, a voltage of 1.024 V (if R1 and R0 = 10) or 2.048 V (if R1 and R0 = 11) is available. The
internal reference can source up to 1 mA, therefore. it can be used as an external system reference. A
decoupling capacitor must be connected to the REF pin if internal reference is selected to ensure output stability.
A 1 µF to 10 µF capacitor in parallel to a 100 pF capacitor should be sufficient, see Figure 13.
V(REF)

Pin 16
REF TLV56xx

10 mF 100 pF

Figure 13. Reference Pin Decoupling Connection

BUFFERED AMPLIFIER
The DAC outputs are buffered by an amplifier with a gain of two, which are configurable as Class A (fast mode)
or Class AB (slow or low-power mode). The output buffers have near rail-to-rail output with short-circuit
protection, and can reliably drive a 2-kΩ load with a 100-pF load capacitance.

13
 PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TLV5630IDW ACTIVE SOIC DW 20 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5630IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5630IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5630IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5630IPW ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5630IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5630IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5630IPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5631IDW ACTIVE SOIC DW 20 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5631IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5631IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5631IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5631IPW ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5631IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5631IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5631IPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5632IDW ACTIVE SOIC DW 20 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5632IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5632IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5632IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5632IPW ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5632IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5632IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV5632IPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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