DATA SHEET

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Single Supply Dual

Operational Amplifiers PDIP−8
N, AN, VN SUFFIX
8 CASE 626

LM258, LM358, LM358A, 1

LM358E, LM2904, LM2904A,
LM2904E, LM2904V, NCV2904 8
SOIC−8
D, VD SUFFIX
CASE 751
Utilizing the circuit designs perfected for Quad Operational 1
Amplifiers, these dual operational amplifiers feature low power
drain, a common mode input voltage range extending to ground/V EE,
and single supply or split supply operation. The LM358 series is Micro8™
8
equivalent to one−half of an LM324. DMR2 SUFFIX
CASE 846A
These amplifiers have several distinct advantages over standard 1
operational amplifier types in single supply applications. They can
operate at supply voltages as low as 3.0 V or as high as 32 V, with
PIN CONNECTIONS
quiescent currents about one−fifth of those associated with the Output A 1 8 VCC
MC1741 (on a per amplifier basis). The common mode input range
2 7 Output B
Inputs A −
+
includes the negative supply, thereby eliminating the necessity for 3 – 6 Inputs B
external biasing components in many applications. The output VEE/Gnd + 5
4
voltage range also includes the negative power supply voltage. (Top View)

Features
 Short Circuit Protected Outputs ORDERING INFORMATION
See detailed ordering and shipping information on
 True Differential Input Stage page 10 of this data sheet.
 Single Supply Operation: 3.0 V to 32 V
 Low Input Bias Currents DEVICE MARKING INFORMATION
 Internally Compensated See general marking information in the device
marking section on page 11 of this data sheet.
 Common Mode Range Extends to Negative Supply
 Single and Split Supply Operation
 ESD Clamps on the Inputs Increase Ruggedness of the
Device without Affecting Operation
 NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements;
AEC−Q100 Qualified and PPAP Capable
 These Devices are Pb−Free, Halogen Free/BFR Free and are
RoHS Compliant

 Semiconductor Components Industries, LLC,

2016
1 Publication Order Number:

August, 2021 − Rev. 34 LM358/D

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

3.0 V to
VCC(max) VCC VCC

1.5 V to VCC(max)
1 1

2 2
1.5 V to VEE(max)
VEE
VEE/Gnd
Single Supply Split Supplies
Figure 1.

Bias Circuitry
Common to
Outpu Both
t Amplifiers
VCC
Q1
5 Q2
Q1 Q1
6 4 2
Q1
3
40
Q1 k
9
5.0 Q1
pF Q2
2 4
2 Q2
5 3

Q1 Q20
8
Input
s Q1
Q 1
Q1 Q21 9
7 Q2
Q Q
6 7 5
Q Q Q 2.4
2 5 Q Q1 1 k
Q Q Q2 8 0
3 4 6 2.0
k
VEE/Gnd

Figure 2. Representative Schematic Diagram

(One−Half of Circuit Shown)

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 LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

MAXIMUM RATINGS (TA = +25C, unless otherwise noted.)

Rating Symbol Value Unit
Power Supply Vdc
Voltages Single VCC 32
Supply VCC, 16
Split Supplies VEE
Input Differential Voltage Range (Note 1) VIDR 32 Vdc
Input Common Mode Voltage Range VICR −0.3 to 32 Vdc
Output Short Circuit Duration tSC Continuous
Junction Temperature TJ 150 C
Thermal Resistance, Junction−to−Air (Note 2) Case RθJA 238 C/W
846A 212
Case 161
751
Case 626
Storage Temperature Range Tstg −65 to +150 C
Operating Ambient Temperature Range TA C
LM25 −25 to +85
8 LM358, LM358A, 0 to +70
LM358E LM2904, −40 to +105
LM2904A, LM2904E −40 to +125
LM2904V, NCV2904
(Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded,
device functionality should not be assumed, damage may occur and reliability may be affected.
1. Split Power Supplies.
2. All RθJA measurements made on evaluation board with 1 oz. copper traces of minimum pad size. All device outputs were
active.
3. NCV2904 is qualified for automotive use.

ESD RATINGS
Rating HBM MM Unit
ESD Protection at any Pin (Human Body Model − HBM, Machine Model −
MM) NCV2904 (Note 3) 2000 200 V
LM358E, LM2904E 2000 200
LM358DG/DR2G, 250 100 V
LM2904DG/DR2G 2000 200
All Other Devices V

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 LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25C, unless otherwise noted.)
LM258 LM358, LM358E LM358A
Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VIO mV
VCC = 5.0 V to 30 V, VIC = 0 V to VCC −1.7
V,
VO 1.4 V, RS = 0 Ω
TA = 25C – 2.0 5.0 – 2.0 7.0 – 2.0 3.0
TA = Thigh (Note 4) – – 7.0 – – 9.0 – – 5.0
TA = Tlow (Note 4) – – 7.0 – – 9.0 – – 5.0
Average Temperature Coefficient of Input ΔVIO/ΔT – 7.0 – – 7.0 – – 7.0 – µV/C
Offset Voltage
TA = Thigh to Tlow (Note 4)
Input Offset Current IIO – 3.0 30 – 5.0 50 – 5.0 30 nA
TA = Thigh to Tlow (Note – – 100 – – 150 – – 75
4) Input Bias Current IIB – −45 −150 – −45 −250 – −45 −100
TA = Thigh to Tlow (Note 4) – −50 −300 – −50 −500 – −50 −200
Average Temperature Coefficient of Input ΔIIO/ΔT – 10 – – 10 – – 10 – pA/C
Offset Current
TA = Thigh to Tlow (Note 4)
Input Common Mode Voltage Range VICR 0 – 28.3 0 – 28.3 0 – 28.5 V
(Note 5), VCC = 30 V
VCC = 30 V, TA = Thigh to Tlow 0 – 28 0 – 28 0 – 28
Differential Input Voltage Range VIDR – – VCC – – VCC – – VCC V
Large Signal Open Loop Voltage Gain AVOL V/mV
RL = 2.0 kΩ, VCC = 15 V, For Large VO 50 100 – 25 100 – 25 100 –
Swing, TA = Thigh to Tlow (Note 4) 25 – – 15 – – 15 – –
Channel Separation CS – −120 – – −120 – – −120 – dB
1.0 kHz  f  20 kHz, Input Referenced
Common Mode CMR 70 85 – 65 70 – 65 70 – dB
Rejection RS  10 kΩ
Power Supply Rejection PSR 65 100 – 65 100 – 65 100 – dB
Output Voltage−High VOH V
Limit TA = Thigh to Tlow
(Note 4) 3.3 3.5 – 3.3 3.5 – 3.3 3.5 –
VCC = 5.0 V, RL = 2.0 kΩ, TA = 26 – – 26 – – 26 – –
25C VCC = 30 V, RL = 2.0 kΩ 27 28 – 27 28 – 27 28 –
VCC = 30 V, RL = 10 kΩ
Output Voltage−Low VOL – 5.0 20 – 5.0 20 – 5.0 20 mV
Limit VCC = 5.0 V, RL =
10 kΩ,
TA = Thigh to Tlow (Note 4)
Output Source Current IO + mA
VID = +1.0 V, VCC = 15 V 20 40 – 20 40 – 20 40 –
TA = Thigh to Tlow (LM358A Only) 10 – –
Output Sink Current IO −
VID = −1.0 V, VCC = 15 V 10 20 – 10 20 – 10 20 – m
TA = Thigh to Tlow (LM358A 5.0 – – A
Only) VID = −1.0 V, VO = 12 50 – 12 50 – 12 50 – m
200 mV A
µA
Output Short Circuit to Ground (Note 6) ISC – 40 60 – 40 60 – 40 60 mA
Power Supply Current (Total ICC mA
Device) TA = Thigh to Tlow (Note
4) – 1.5 3.0 – 1.5 3.0 – 1.5 2.0
VCC = 30 V, VO = 0 V, RL =  – 0.7 1.2 – 0.7 1.2 – 0.7 1.2
VCC = 5 V, VO = 0 V, RL = 
4. LM258: Tlow = −25C, Thigh = +85C LM358, LM358A, LM358E: Tlow = 0C, Thigh =
+70C LM2904/A/E: Tlow = −40C, Thigh = +105C LM2904V & NCV2904: Tlow = −40C, Thigh =
+125C
NCV2904 is qualified for automotive use.
5. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3
V. The upper end of the common mode voltage range is VCC − 1.7 V.
6. Short circuits from the output to VCC can cause excessive heating and eventual destruction. Destructive dissipation can
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LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904
result from
simultaneous shorts on all amplifiers.

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 LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = Gnd, TA = 25C, unless otherwise noted.)
LM2904/LM2904E LM2904A LM2904V, NCV2904
Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VIO mV
VCC = 5.0 V to 30 V, VIC = 0 V to VCC −1.7 V,
VO 1.4 V, RS = 0 Ω
TA = 25C – 2.0 7.0 – 2.0 7.0 – – 7.0
TA = Thigh (Note 7) – – 10 – – 10 – – 13
TA = Tlow (Note 7) – – 10 – – 10 – – 10
Average Temperature Coefficient of Input ΔVIO/ΔT – 7.0 – – 7.0 – – 7.0 – µV/C
Offset Voltage
TA = Thigh to Tlow (Note 7)
Input Offset Current IIO – 5.0 50 – 5.0 50 – 5.0 50 nA
TA = Thigh to Tlow (Note – 45 200 – 45 200 – 45 200
7) Input Bias Current IIB – −45 −250 – −45 −100 – −45 −250
TA = Thigh to Tlow (Note 7) – −50 −500 – −50 −250 – −50 −500
Average Temperature Coefficient of Input ΔIIO/ΔT – 10 – – 10 – – 10 – pA/C
Offset Current
TA = Thigh to Tlow (Note 7)
Input Common Mode Voltage Range VICR 0 – 28.3 0 – 28.3 0 – 28.3 V
(Note 8), VCC = 30 V
VCC = 30 V, TA = Thigh to Tlow 0 – 28 0 – 28 0 – 28
Differential Input Voltage Range VIDR – – VCC – – VCC – – VCC V
Large Signal Open Loop Voltage Gain AVOL V/mV
RL = 2.0 kΩ, VCC = 15 V, For Large VO 25 100 – 25 100 – 25 100 –
Swing, TA = Thigh to Tlow (Note 7) 15 – – 15 – – 15 – –
Channel Separation CS – −120 – – −120 – – −12 – dB
1.0 kHz  f  20 kHz, Input Referenced 0
Common Mode CMR 50 70 – 50 70 – 50 70 – dB
Rejection RS  10 kΩ
Power Supply Rejection PSR 50 100 – 50 100 – 50 100 – dB
Output Voltage−High VOH V
Limit TA = Thigh to Tlow
(Note 7) 3.3 3.5 – 3.3 3.5 – 3.3 3.5 –
VCC = 5.0 V, RL = 2.0 kΩ, TA = 26 – – 26 – – 26 – –
25C VCC = 30 V, RL = 2.0 kΩ 27 28 – 27 28 – 27 28 –
VCC = 30 V, RL = 10 kΩ
Output Voltage−Low VOL – 5.0 20 – 5.0 20 – 5.0 20 mV
Limit VCC = 5.0 V, RL =
10 kΩ,
TA = Thigh to Tlow (Note 7)
Output Source Current IO + 20 40 – 20 40 – 20 40 – mA
VID = +1.0 V, VCC = 15 V
Output Sink Current IO −
VID = −1.0 V, VCC = 15 10 20 – 10 20 – 10 20 – mA
V VID = −1.0 V, VO = – – – – – – – – – µA
200 mV
Output Short Circuit to Ground (Note 9) ISC – 40 60 – 40 60 – 40 60 mA
Power Supply Current (Total ICC mA
Device) TA = Thigh to Tlow (Note
7) – 1.5 3.0 – 1.5 3.0 – 1.5 3.0
VCC = 30 V, VO = 0 V, RL =  – 0.7 1.2 – 0.7 1.2 – 0.7 1.2
VCC = 5 V, VO = 0 V, RL = 
7. LM258: Tlow = −25C, Thigh = +85C LM358, LM358A, LM358E: Tlow = 0C, Thigh =
+70C LM2904/A/E: Tlow = −40C, Thigh = +105C LM2904V & NCV2904: Tlow = −40C, Thigh =
+125C
NCV2904 is qualified for automotive use.
8. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3
V. The upper end of the common mode voltage range is VCC − 1.7 V.
9. Short circuits from the output to VCC can cause excessive heating and eventual destruction. Destructive dissipation can
result from
simultaneous shorts on all amplifiers.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise
noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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 LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

CIRCUIT DESCRIPTION

The LM358 series is made using two internally VCC = 15

compensated, two−stage operational amplifiers. The first Vdc RL =
stage of each consists of differential input devices Q20 2.0 kΩ TA
= 25C
and Q18 with input buffer transistors Q21 and Q17 and
the differential to single ended converter Q3 and Q4. The
first stage performs not only the first stage gain function

V/DIV
but also performs the level shifting and transconductance

1.0
reduction functions. By reducing the transconductance, a
smaller compensation capacitor (only 5.0 pF) can be
employed, thus saving chip area. The transconductance
reduction is accomplished by splitting the collectors of
Q20 and Q18. Another feature of this input stage is that
the input common mode range can include the negative 5.0 µs/DIV
supply or ground, in single supply operation, without
Figure 3. Large Signal Voltage
saturating either the input devices or the differential to Follower Response
single−ended converter. The second stage consists of a
standard current source load amplifier stage.
Each amplifier is biased from an internal−voltage
regulator which has a low temperature coefficient thus
giving each amplifier good temperature characteristics as
well as excellent power supply rejection.

20
120
18 VCC = 15
AVOL, OPEN LOOP VOLTAGE GAIN

16 100 V VEE =
Gnd TA =
VI , INPUT VOLTAGE

14 80 25C
12
60
10
Negative
8.0 40
Positive
(V)

6.0
20
4.0
2.0 0
(dB)

0 -20
0 2.0 4.0 6.0 8.0 10 12 14 16 18 1.0 10 100 1.0 k 10 k 100 k 1.0
20
M f, FREQUENCY (Hz)
VCC/VEE, POWER SUPPLY VOLTAGES (V)

Figure 4. Input Voltage Range Figure 5. Large−Signal Open Loop Voltage Gain

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 LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

14
550
VCC = 30
VOR, OUTPUT VOLTAGE RANGE (Vpp
12 RL = 2.0 V VEE =
kΩ VCC = 500
Inpu Gnd TA =
10 15 V VEE 450 25C CL =
t

VO, OUTPUT VOLTAGE

= Gnd 50 pF
Gain = -100
8.0 400
RI = 1.0 kΩ Outpu
RF = 100 t
350
6.0 kΩ
300
4.0

(mV)
250
2.0
200
0
)

0
1.0 10 100 0 1.0 2.0 3.0 4.0 5.0 6.0
1000
7.0 8.0 t, TIME (µs)
f, FREQUENCY (kHz)

Figure 6. Large−Signal Frequency Response Figure 7. Small Signal Voltage Follower

Pulse Response (Noninverting)

2.4
ICC , POWER SUPPLY CURRENT (mA)

2.1 TA =
25C RL
1.8 =∞ 90
IIB, INPUT BIAS CURRENT

1.5
1.2

0.9 80
0.6
(nA)

0.3
0
0 5.0 10 15 20 25 30 35 70
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
VCC, POWER SUPPLY VOLTAGE (V) VCC, POWER SUPPLY VOLTAGE (V)

Figure 8. Power Supply Current versus

Power Supply Voltage Figure 9. Input Bias Current versus
Supply Voltage

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 LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

50
R1 k

VCC
VCC R2 5.0
-
1/2 10 k k VCC
LM358 -
MC1403 + VO Vref 1/2
2.5 LM358 VO
V + 1
1 fo =2 u RC
Vref = 2 VCC
For: fo = 1.0 kHz
R1
R R = 16
VO = 2.5 V (1 + ) R kΩ C C C = 0.01
R2 µF

Figure 10. Voltage Reference Figure 11. Wien Bridge Oscillator

e1

+ Hysteresis
1
C R R2
1/2
R VOH
LM358
- R1 VO
Vre +
eo 1/2
- f
LM358
a 1/2 - VO
R1 R1 VOL
LM358 Vi
+ VinL VinH
b R1 Vref
R1 1 VinL = R1 + (VOL - Vref)+
R
e2 - C Vref R2
1/2
LM358 R R1
+ VinH = (VOH - Vref) + Vref
R1 + R2
eo = C (1 + a + b) (e2
R1
- e 1) H =R1 + R2 (VOH - VOL)

Figure 12. High Impedance Differential Amplifier Figure 13. Comparator with Hysteresis

1
R fo =
2
R 100
u
k 1
Vi C1 R2 C C R1 = Vref =2 VCC
n -
1/2 R C
QR
R2
R1
= TBP
LM358 -
+ 1/2 100 k R3 = TN R2
-
LM358 C1 = 10 C
1/2
+ LM358
Vref + For: = 1.0 kHz
Bandpass Vref f = 10
o
Q
Vref R1 R3 LM358 TBP = 1
Output
+ TN = 1
R2 - C1
1/2
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LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904
Notch Output 160 kΩ
RC = = 0.001 µF
R1 = 1.6
Vref Where TBP = Center Frequency MΩ R2 =
: Gain TN = Passband 1.6 MΩ R3
Notch Gain = 1.6 MΩ

Figure 14. Bi−Quad Filter

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 LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

VCC
C R3
R1 C
Vin -
1/2
LM358 VO
+ CO
R2
CO = 10
C
Vre
1
f Vref = 2 VCC

Given: fo = center frequency

A(fo) = gain at center

frequency Choose value fo, C

Then: Q
1 R3 =
Vref = Triangle R2 u fo C
2 Wave
300 R3
VCC Vref Output R1 =
+ 2
1/ k A(fo)
2 R3
+
LM358 1/2 R1 R3
- 75 R2 =4Q2 R1 -R3
LM358
k 100 Squar
- Qo fo
R1 k e For less than 10% error from operational <
Wave 0.1 BW
C
Vref Outpu
amplifier. Where fo and BW are
t
Rf expressed in Hz.
R2 R1 If source impedance varies, filter may be preceded with
R1 + if, R3 =
f C=
R R2 + voltage follower buffer to stabilize filter parameters.
4 CRf R1 R1

Figure 15. Function Generator Figure 16. Multiple Feedback Bandpass Filter

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 LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

ORDERING INFORMATION

Device Operating Temperature Range Package Shipping†

LM358ADR2G 2500 / Tape & Reel
LM358DG SOIC−8 98 Units / Rail
(Pb−Free)
LM358DR2G 2500 / Tape & Reel
LM358EDR2G SOIC−8 2500 / Tape & Reel
0C to +70C (Pb−Free)
LM358DMR2G Micro8 4000 / Tape & Reel
(Pb−Fre
e)
LM358NG PDIP−8 50 Units / Rail
(Pb−Free)
LM258DG SOIC−8 98 Units / Rail
LM258DR2G (Pb−Free) 2500 / Tape & Reel
LM258DMR2G Micro8 4000 / Tape & Reel
−25C to +85C (Pb−Fre
e)
LM258NG PDIP−8 50 Units / Rail
(Pb−Free)
LM2904DG SOIC−8 98 Units / Rail
LM2904DR2G (Pb−Free) 2500 / Tape & Reel
LM2904EDR2G SOIC−8 2500 / Tape & Reel
(Pb−Free)
LM2904DMR2G Micro8 2500 / Tape & Reel
(Pb−Fre
e)
−40C to +105C
LM2904NG PDIP−8 50 Units / Rail
(Pb−Free)
LM2904ADMG Micro8 4000 / Tape & Reel
LM2904ADMR2G (Pb−Fre 4000 / Tape & Reel
e)
LM2904ANG PDIP−8 50 Units / Rail
(Pb−Free)
LM2904VDG SOIC−8 98 Units / Rail
LM2904VDR2G (Pb−Free) 2500 / Tape & Reel
LM2904VDMR2G Micro8 4000 / Tape & Reel
(Pb−Fre
e)
LM2904VNG −40C to +125C PDIP−8 50 Units / Rail
(Pb−Free)
NCV2904DR2G* SOIC−8 2500 / Tape & Reel
(Pb−Free)
NCV2904DMR2G* Micro8 4000 / Tape & Reel
(Pb−Fre
e)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable.

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LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

MARKING DIAGRAMS

PDIP−8 PDIP−8 PDIP−8

N SUFFIX AN SUFFIX VN SUFFIX
CASE 626 CASE 626 CASE 626
8 8 8 8

LMx58N LM2904 LM2904A LM2904V

AWL N N N
AWL AWL AWL
YYWWG YYWWG YYWW YYWWG
G
1 1 1 1

SOIC−8 SOIC−8
D SUFFIX VD SUFFIX
CASE 751 CASE 751
8 8 8 8
LMx5 LM358 2904 2904 *
8 ALYW ALY V
ALYW A W ALYW
1 1 1 1
8 8
358E 2904E
ALYW ALYW
A ▪
1 ▪ 1

Micro8
DMR2 SUFFIX
CASE 846A
8 8 8 8

x58 2904 904 904 *

AYW AYW A V
▪ ▪ AYW AYW
▪ ▪ ▪ ▪
1 ▪ 1
1
x = 2 or 3 *This diagram also applies to NCV2904
1
A = Assembly
Location WL, L =
Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free
Package
▪ = Pb−Free Package − (Note: Microdot may be in either location)

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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

PDIP−8
CASE
626−05
ISSUE P DATE 22 APR 2015

SCALE 1:1
NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE
PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE
8 5 GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
E1 PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW
1 4 DATUM PLANE H WITH THE LEADS CONSTRAINED
PERPENDICULAR TO DATUM C.
NOTE 8 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH
THE LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF
b2 B END VIEW THE LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR
SQUARE CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A A1 0.015 −−−− 0.38 −−−
NOTE 3 A2 0.115 0.195 2.92 4.95
b 0.014 0.022 0.35 0.56
L b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING D1 0.005 −−−− 0.13 −−−
E 0.300 0.325 7.62 8.26
PLANE
A1 E1 0.240 0.280 6.10 7.11
C M e 0.100 BSC 2.54 BSC
D1 eB −−−− 0.430 −−− 10.92
L 0.115 0.150 2.92 3.81
e eB M −−−− 10  −−− 10 

8X b END VIEW
SIDE VIEW 0.010 M C M B M NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN XXXX = Specific Device
3. DC − IN Code A = XXXXXXXX
Assembly
4. AC IN X
5. GROUND Location
6. OUTPUT WL AW
= Wafer Lot
7. AUXILIARY YY = Year L
8. VCC
WW = WorkYYWW
Week
G = Pb−Free Package
*This information is generic. Please
refer to device data sheet for actual
part marking. Pb−Free indicator,
“G” or microdot “ ▪”, may or may
not be present.

Electronic versions are uncontrolled except when accessed directly from the Document
DOCUMENT NUMBER: 98ASB42420B Repository. Printed versions are uncontrolled except when stamped “CONTROLLED
COPY” in red.

DESCRIPTION: PDIP−8 PAGE 1 OF 1

ON Semiconductor are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States
ON Semiconductor reserves
and the right
and/or othertocountries.
make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

 Semiconductor Components Industries, LLC, www.onsemi.co

2019 m
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−8 NB
8 CASE 751−07
1 ISSUE AK
SCALE 1:1 DATE 16 FEB 2011

NOTES:
1. DIMENSIONING AND TOLERANCING
−X− PER ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT
INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
8 5 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.25 (0.010) Y DAMBAR PROTRUSION. ALLOWABLE
B S M
DAMBAR PROTRUSION SHALL BE 0.127
1 M (0.005) TOTAL IN EXCESS OF THE D
4 DIMENSION AT MAXIMUM MATERIAL
−Y− K CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

0.25 (0.010) M Z YG S X S MILLIMETERS INCHES

DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 ° B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 J 0.19 0.25 0.007 0.010
M K 0.40 1.27 0.016 0.050
H D (0.004) J M 0° 8° 0 ° 8 °
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXX XXXX XXXXX XXXXX
X X XAYWW X
1.52 ALYW ALYW AYWW
0.06 X ▪
1 1 1 1
0
IC IC Discrete Discrete
(Pb−Free) (Pb−Free)
7.0 4.0
0.27 0.15 XXXXX = Specific Device XXXXXX = Specific Device
5 5 Code A = Assembly Code A = Assembly
Location Location
L = Wafer Lot Y = Year
Y = Year WW = Work Week
W = Work Week ▪ = Pb−Free Package
▪ = Pb−Free Package
1.27
0.6 0 *This information is generic. Please
0.024 0.05 refer to device data sheet for actual
part marking. Pb−Free indicator, “G”
mm or microdot “▪”, may or may not be
SCALE
inche present. Some products may not
6:1 (s follow the Generic Marking.
)
*For additional information on our Pb−Free strategy and
soldering details, please download the ON
Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document
DOCUMENT NUMBER: 98ASB42564B Repository. Printed versions are uncontrolled except when stamped “CONTROLLED
COPY” in red.

DESCRIPTION: SOIC−8 NB PAGE 1 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other
the right to make changes without
countries. further
onsemi notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its
reserves
products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically
 Semiconductor Components Industries, LLC, www.onsemi.co
disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent
2019
rights nor the rights of others. m
 SOIC−8 NB
CASE
751−07
ISSUE AK DATE 16 FEB
2011
STYLE STYLE 2: STYLE 3: STYLE 4:
1:
PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1 PIN 1. ANODE
2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1 2. ANODE
3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2 3. ANODE
4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2 4. ANODE
5. EMITTER 5. BASE, #2 5. GATE, #2 5. ANODE
6. BASE 6. EMITTER, #2 6. SOURCE, #2 6. ANODE
7. BASE 7. BASE, #1 7. GATE, #1 7. ANODE
8. EMITTER 8. EMITTER, #1 8. SOURCE, #1 8. COMMON CATHODE
STYLE STYLE 6: STYLE 7: STYLE 8:
5:
PIN 1. DRAIN PIN 1. SOURCE PIN 1. INPUT PIN 1. COLLECTOR, DIE #1
2. DRAIN 2. DRAIN 2. EXTERNAL BYPASS 2. BASE, #1
3. DRAIN 3. DRAIN 3. THIRD STAGE SOURCE 3. BASE, #2
4. DRAIN 4. SOURCE 4. GROUND 4. COLLECTOR, #2
5. GATE 5. SOURCE 5. DRAIN 5. COLLECTOR, #2
6. GATE 6. GATE 6. GATE 3 6. EMITTER, #2
7. SOURCE 7. GATE 7. SECOND STAGE Vd 7. EMITTER, #1
8. SOURCE 8. SOURCE 8. FIRST STAGE Vd 8. COLLECTOR, #1

STYLE 9: STYLE 10: STYLE 11: STYLE 12:

PIN 1. EMITTER, PIN 1. GROUND PIN 1. SOURCE 1 PIN 1. SOURCE
COMMON 2. BIAS 1 2. GATE 1 2. SOURCE
2. COLLECTOR, DIE 3. OUTPUT 3. SOURCE 2 3. SOURCE
#1 4. GROUND 4. GATE 2 4. GATE
3. COLLECTOR, DIE 5. GROUND 5. DRAIN 2 5. DRAIN
#2 6. BIAS 2 6. DRAIN 2 6. DRAIN
4. EMITTER, 7. INPUT 7. DRAIN 1 7. DRAIN
COMMON 8. GROUND 8. DRAIN 1 8. DRAIN
5. EMITTER,
COMMON STYLE 14: STYLE 15: STYLE 16:
6. BASE, DIE #2 PIN 1. N−SOURCE PIN 1. ANODE 1 PIN 1. EMITTER, DIE #1
7. BASE, DIE #1 2. N−GATE 2. ANODE 1 2. BASE, DIE #1
8. EMITTER, 3. P−SOURCE 3. ANODE 1 3. EMITTER, DIE #2
COMMON 4. P−GATE 4. ANODE 1 4. BASE, DIE #2
5. P−DRAIN 5. CATHODE, COMMON 5. COLLECTOR, DIE #2
STYLE 13: 6. P−DRAIN 6. CATHODE, COMMON 6. COLLECTOR, DIE #2
PIN 1. N.C. 7. N−DRAIN 7. CATHODE, COMMON 7. COLLECTOR, DIE #1
2. SOURCE 8. N−DRAIN 8. CATHODE, COMMON 8. COLLECTOR, DIE #1
3. SOURCE
4. GATE STYLE 18: STYLE 19: STYLE 20:
5. DRAIN PIN 1. ANODE PIN 1. SOURCE 1 PIN 1. SOURCE (N)
6. DRAIN 2. ANODE 2. GATE 1 2. GATE (N)
7. DRAIN 3. SOURCE 3. SOURCE 2 3. SOURCE (P)
8. DRAIN 4. GATE 4. GATE 2 4. GATE (P)
5. DRAIN 5. DRAIN 2 5. DRAIN
STYLE 17: 6. DRAIN 6. MIRROR 2 6. DRAIN
PIN 1. VCC 7. CATHODE 7. DRAIN 1 7. DRAIN
2. V2OUT 8. CATHODE 8. MIRROR 1 8. DRAIN
3. V1OUT
4. TXE STYLE 22: STYLE 23: STYLE 24:
5. RXE PIN 1. I/O LINE 1 PIN 1. LINE 1 IN PIN 1. BASE
6. VEE 2. COMMON 2. COMMON 2. EMITTER
7. GND CATHODE/VCC ANODE/GND 3. COLLECTOR/ANODE
8. ACC 3. COMMON 3. COMMON 4. COLLECTOR/ANODE
CATHODE/VCC ANODE/GND 5. CATHODE
STYLE 21: 4. I/O LINE 3 4. LINE 2 IN 6. CATHODE
PIN 1. CATHODE 1 5. COMMON 5. LINE 2 OUT 7. COLLECTOR/ANODE
2. CATHODE 2 ANODE/GND 6. COMMON 8. COLLECTOR/ANODE
3. CATHODE 3 6. I/O LINE 4 ANODE/GND
4. CATHODE 4 7. I/O LINE 5 7. COMMON STYLE 28:
5. CATHODE 5 8. COMMON ANODE/GND PIN 1. SW_TO_GND
6. COMMON ANODE ANODE/GND 8. LINE 1 OUT 2. DASIC_OFF
7. COMMON ANODE 3. DASIC_SW_DET
8. CATHODE 6 STYLE 26: STYLE 27: 4. GND
PIN 1. GND PIN 1. ILIMIT 5. V_MON
STYLE 25: 2. dv/dt 2. OVLO 6. VBULK
PIN 1. VIN 3. ENABLE 3. UVLO 7. VBULK
2. N/C 4. ILIMIT 4. INPUT+ 8. VIN
3. REXT 5. SOURCE 5. SOURCE
4. GND 6. SOURCE 6. SOURCE
5. IOUT 7. SOURCE 7. SOURCE
6. IOUT 8. VCC 8. DRAIN
7. IOUT
8. IOUT STYLE 30:
PIN 1. DRAIN 1
STYLE 29: 2. DRAIN 1
PIN 1. BASE, DIE #1 3. GATE 2
2. EMITTER, #1 4. SOURCE 2
3. BASE, #2 5. SOURCE 1/DRAIN 2
4. EMITTER, #2 6. SOURCE 1/DRAIN 2
5. COLLECTOR, #2 7. SOURCE 1/DRAIN 2
6. COLLECTOR, #2 8. GATE 1
7. COLLECTOR, #1
8. COLLECTOR, #1

Electronic versions are uncontrolled except when accessed directly from the Document
DOCUMENT NUMBER:98ASB42564B Repository. Printed versions are uncontrolled except when stamped “CONTROLLED
COPY” in red.

 Semiconductor Components Industries, LLC, www.onsemi.co

2019 m
 DESCRIPTION:SOIC−8 NB PAGE 2 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other
the right to make changes without
countries. further
onsemi notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its
reserves
products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent
rights nor the rights of others.

 Semiconductor Components Industries, LLC, www.onsemi.co

2019 m
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1

GENERIC
MARKING DIAGRAM*
8

XXXX
AYW▪
▪
1
XXXX = Specific Device
Code A = Assembly
Location
Y = Year
W = Work Week
▪ = Pb−Free Package STYLE 1:
STYLE 2: STYLE 3:
PIN 1. SOURCE
(Note: Microdot may be in either PIN 1. SOURCE PIN 1. N-SOURCE
2. SOURCE
1 2. N-GATE
3. SOURCE
2. GATE 1 3. P-SOURCE
location) 4. GATE
3. SOURCE 2 4. P-GATE
5. DRAIN
*This information is generic. Please 4. GATE 2 5. P-DRAIN
6. DRAIN
5. DRAIN 2 6. P-DRAIN
refer to 7. DRAIN
6. DRAIN 2 7. N-DRAIN
device data sheet for actual part 8. DRAIN
7. DRAIN 1 8. N-DRAIN
marking. Pb−Free indicator, “G” or 8. DRAIN 1
microdot “▪”, may or may not be
present. Some products may not
follow the Generic Marking.

DOCUMENT NUMBER: Electronic versions are uncontrolled except when accessed directly from the Document
98ASB14087C Repository. Printed versions are uncontrolled except when stamped “CONTROLLED
DESCRIPTION: COPY” in red.
MICRO8
PAGE 1 OF 1

 Semiconductor Components Industries, LLC, www.onsemi.co

2019 m
 ON Semiconductor are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States
ON Semiconductor reserves
and the right
and/or othertocountries.
make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

 Semiconductor Components Industries, LLC, www.onsemi.co

2019 m
 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba
and/or subsidiaries“onsemi”
in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and
or its affiliates
other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi
reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and
onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of
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