Delta University for Science and Technology

Faculty of Engineering

ECE 113
Advanced Electronics
1 Introduction
Walid A. Raslan
Assistant Professor
Communications and Computers Engineering Dept.,
Delta University for Science and Technology
Hello!
I am Walid Raslan
Assistant Professor
Electronics and Communications Engineering Dept.,
Delta University for Science and Technology
You can find me at:
Walid.raslan@gmail.com
Whatsapp: 01225841034

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Content

◎ 1.1 Course Objectives

◎ 1.2 Intended Learning Outcomes (ILOs)
◎ 1.3 Contents
◎ 1.4 Student Assessment Methods
◎ 1.5 List of References
1.1 Course Objectives

Course Objectives: -

The aim of this course is to provide students with: -

1. Learn how to analyze BJT and FET Circuits.

2. Develop the student ability to solve BJT and FET amplifier circuits.
3. Learn how to design, analyze and test multi-stage amplifiers.
4. Enrich the student ability to implement different electronic circuits using BJT and
FET.
5. Measure the performance of any electronic circuit under specific input for a specific

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Competencies : -
on completing this course, students will able to:

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Learning outcomes “LOs”

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1.3 Contents Week Topics
1 Configurations of BJT
2 DC biasing of BJTs
3 BJT TRANSISTOR MODELING
4 BJT AC Analysis
5 BJT AC Analysis
6 Cascade Amplifiers
7 Field-Effect Transistors
8 Mid Term Exam
9 FET Biasing
10 FET Amplifiers
11 Operational Amplifiers
12 Op-Amp Applications
13 Power Amplifiers
14 Final Exam

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1.4 Student Assessment Methods

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1.5 List of References

• Thomas L. Floyd, “Electronic Devices, Global Edition”, 10th edition,

Pearson, 2018.
• R. L. Boylestad and L. Nashelsky, "Electronic devices and circuit
theory", 11th edition Pearson Prentice Hall, 2015.
• Adel Sedra and K.C. Smith, “Microelectronic Circuits”, 5th Edition,
Oxford University Press, International Version, 2014.

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 Delta University for Science and Technology
Faculty of Engineering

ECE 113
Advanced Electronics
1 DC Biasing—BJTs
INTRODUCTION

◎ The analysis or design of any electronic amplifier

therefore has two components: a DC and an AC
portion.
◎ The dc level of operation of a transistor is controlled
by a number of factors, including the range of possible
operating points on the device characteristics.
 Biasing
Biasing: The DC voltages applied to a transistor in
order to turn it on so that it can amplify the AC signal.
important basic relationships for a transistor:

❑ In fact, once the analysis of the first few networks is

clearly understood, the path toward the solution of the
networks to follow will begin to become quite apparent.
❑ In most instances the base current IB is the first
quantity to be determined. Once IB is known, the
relationships of VBE , IC and IE can be applied to find
the remaining quantities of interest.
 Operating Point
The DC input establishes an operating or quiescent point called the Q-point.

✓ The biasing circuit can be designed to set the device

operation at any of these points or others within the
active region.

✓ The maximum ratings are indicated on the

characteristics by a horizontal line for the maximum
collector current ICmax and a vertical line at the
Active
maximum collector-to-emitter voltage VCEmax.

✓ The maximum power constraint is defined by the

curve Pcmax

✓ The cutoff region, defined by IB ≤ 0µA,

✓ the saturation region, defined by VCE ≤ VCEsat

 Operating Point
If no bias were used, the device would initially be completely off, resulting in a Q-point
at A—namely, zero current through the device (and zero voltage across it).

Active
 Three States of Operation
• Active or Linear Region Operation
✓ Base–Emitter junction is forward biased
✓ Base–Collector junction is reverse biased

• Cutoff Region Operation

Base–Emitter junction is reverse biased

• Saturation Region Operation

Base–Emitter junction is forward biased
Base–Collector junction is forward biased
 DC Biasing Circuits

1. Fixed-bias Configuration
2. Emitter-bias Configuration
3. Voltage-divider Bias Configuration
4. Collector Feedback Configuration
5. Emitter-follower Configuration
 DC Biasing Circuits

1. Fixed-bias Configuration
2. Emitter-bias Configuration
3. Voltage-divider Bias Configuration
4. Collector Feedback Configuration
5. Emitter-follower Configuration
 1- FIXED-BIAS CONFIGURATION
Even though the network employs an npn transistor, the equations and
calculations apply equally well to a pnp transistor configuration merely
by changing all current directions and voltage polarities.
 1- FIXED-BIAS CONFIGURATION
Forward Bias of Base-Emitter
Base-Emitter Loop
From Kirchhoff’s voltage law:

+VCC – IBRB – VBE = 0

Solving for base current:

VCC − VBE
IB =
RB
 1- FIXED-BIAS CONFIGURATION
Collector-Emitter Loop
Collector current: I C = I B

➢ The base current is controlled by the level of RB.

➢ IC is related to IB by a constant β.
➢ The magnitude of IC is not a function of the RC.

➢ Change RC to any level and it will not affect the

level of IB or IC as long as we remain in the active
region of the device.
 1- FIXED-BIAS CONFIGURATION
Collector-Emitter Loop
From Kirchhoff’s voltage law:

The level of RC will determine the magnitude of

VCE, which is an important parameter.
Base-Emitter Loop +VCC – IBRB – VBE = 0

VCC − VBE
IB =
RB
Collector-Emitter Loop

with the negative sign revealing that the junction is

reversed-biased, as it should be for linear amplification
 Transistor Saturation Level
When the transistor is operating in saturation, current through the transistor
is at its maximum possible value.
 Load Line Analysis
➢Define the possible range of Q-points
➢ how the actual Q-point is determined
Output equation that relates the variables IC and
VCE
 Load Line Analysis
The end points of the load line are:

Icsat
IC = VCC / RC
VCE = 0 V
VCEcutoff
VCE = VCC
IC = 0 mA

The Q-point is the operating point:

• where the value of RB sets the value of IB

• that sets the values of VCE and IC
 Circuit Values Affect the Q-Point
Change in IB change the Q - point
 Circuit Values Affect the Q-Point
If VCC is held fixed and RC changed, the load
line will shift as shown in Fig.
 Circuit Values Affect the Q-Point
If IB is held fixed, the Q-point will move as shown in the same figure. If
RC is fixed and VCC varied, the load line shifts as shown in Fig.
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 DC Biasing Circuits

1. Fixed-bias Configuration
2. Emitter-bias Configuration
3. Voltage-divider Bias Configuration
4. Collector Feedback Configuration
5. Emitter-follower Configuration
 2. Emitter-bias Configuration

Adding a resistor (RE) to the

emitter circuit stabilizes the
bias circuit.
 2. Emitter-bias Configuration
Base-Emitter Loop
From Kirchhoff’s voltage law:
+VCC - I B R B - VBE - I E R E = 0

VCC - I B R B - ( + 1)I B R E = 0

Solving for IB:

VCC - VBE
IB =
R B + ( + 1)R E
 2. Emitter-bias Configuration
Collector-Emitter Loop
From Kirchhoff’s voltage law:

I R +V +I R −V =0
E E CE C C CC

Since IE  IC:
VCE = VCC – I C (R C + R E )

Also:
VE = I E R E
VC = VCE + VE = VCC - I C R C
VB = VCC – I R R B = VBE + VE
 Solution
Base-Emitter Loop +VCC - I B R B - VBE - I E R E = 0

Collector-Emitter Loop
Solution
 Saturation Level

VCE = VCC – I C (R C + R E )
The endpoints can be determined from the load line.
ICsat:
VCEcutoff:
VCE = 0 V
VCE = VCC
VCC
I C = 0 mA IC =
RC + RE
 Improved Biased Stability

Stability refers to a circuit condition in which the currents

and voltages will remain fairly constant over a wide range
of temperatures and transistor Beta () values.

Adding RE to the emitter

improves the stability of a
transistor.
Fixed Bias Emitter-Stabilized Bias MORE Stable
 DC Biasing Circuits

1. Fixed-bias circuit

2. Emitter-stabilized bias circuit

3. Voltage divider bias circuit
4. Collector-emitter loop

5. DC bias with voltage feedback

Voltage Divider Bias

This is a very stable bias circuit.

The currents and voltages are

nearly independent of any variations
in .
 Approximate Analysis
Where IB << I1 and I1  I2 :
R 2 VCC
VB =
R1 + R 2
Where RE > 10R2:
VE
IE =
RE
VE = VB − VBE
From Kirchhoff’s voltage law:

VCE = VCC − I C R C − I E R E
IE  IC
VCE = V CC −I C (R C + R E )

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 Voltage Divider Bias Analysis
Transistor Saturation Level

V CC
I Csat = I Cmax =
RC + RE

Load Line Analysis

Cutoff: Saturation:

VCE = VCC VCC

IC =
I C = 0mA RC + RE
VCE = 0V

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Exact Analysis

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Exact Analysis

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 DC Biasing Circuits

1. Fixed-bias circuit

2. Emitter-stabilized bias circuit

3. Voltage divider bias circuit
4. DC bias with voltage feedback

5. Collector-emitter loop
 DC Bias with Voltage Feedback

Another way to improve the

stability of a bias circuit is to
add a feedback path from
collector to base.

In this bias circuit the Q-point

is only slightly dependent on
the transistor beta, .

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 Base-Emitter Loop
From Kirchhoff’s voltage law:
VCC – I C R C – I B R B – VBE – I E R E = 0

Where IB << IC:

I' = I + I  I
C C B C

Knowing IC = IB and IE  IC, the loop equation becomes:

VCC –  I B R C − I B R B − VBE −  I B R E = 0

Solving for IB:

VCC − VBE
IB =
R B + (R C + R E )

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 Collector-Emitter Loop

Applying Kirchoff’s voltage law:

IE + VCE + I’CRC – VCC = 0

Since IC  IC and IC = IB:

IC(RC + RE) + VCE – VCC =0

Solving for VCE:

VCE = VCC – IC(RC + RE)

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Transistor Saturation Level
V CC
I Csat = I Cmax =
RC + RE

Load Line Analysis

Cutoff: Saturation:

V
VCE = VCC I = CC
C R +R
I C = 0 mA C E
VCE = 0 V

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 DC Biasing Circuits

1. Fixed-bias circuit

2. Emitter-stabilized bias circuit

3. Voltage divider bias circuit
4. DC bias with voltage feedback

5. Emitter-follower Configuration
Emitter-follower Configuration

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 PNP Transistors

The analysis for pnp transistor biasing circuits is the same

as that for npn transistor circuits. The only difference is
that the currents are flowing in the opposite direction.

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PNP Transistors

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 DESIGN OPERATIONS
Understanding circuit design requires knowledge of analysis and synthesis.
• Analysis focuses on solving for currents and voltages in a given circuit.
• Design involves specifying currents/voltages and determining necessary
elements.
• Basic laws such as Ohm’s law and Kirchhoff’s laws are essential for circuit
design.
• Theoretical resistor values are adjusted to standard commercial values in
designs.
• Ohm’s Law for resistance calculation: R = V / I
• This principle helps determine resistance values from voltage and current
specifications.

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Assignment

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Thanks!
Any questions?

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