JCT

COLLEGE OF ENGINNERING AND TECHNOLOGY

(AUTONOMOUS INSTITUTION)

DEPARTMENT OF
ELECTRICAL & ELECTRONICS ENGINEERING

SIXTH SEMESTER

EE3022 – VLSI DESIGN

INTEGRATED LABORATORY RECORD

NAME :
SEMESTER / YEAR :
BRANCH :
REGISTER NUMBER :
 JCT COLLEGE OF ENGINEERING & TECHNOLOGY
PICHANUR, COIMBATORE-641105

DEPARTMENT: ELECTRICAL AND ELECTRONICS

ENGINEERING

This is to certify that this

(lab name) record work done by Mr/Ms

For the course B.E

(branch) during

(year/semester) of academic Year 20 -20 in bonafide.

Date Staff in charge

REGISTER NUMBER:
This record is submitted for Semester B.E Practical Examination ofAnna
University conducted on

Internal Examiner External Examiner

 JCT COLLEGE OF ENGINEERING AND TECHNOLOGY
(AUTONOMOUS INSTITUTION)
PICHANUR, COIMBATORE – 641105

VISION AND MISSION - INSTITUTE

VISION

To emerge as a Premier Institute for developing industry ready Engineers

with competency, initiative and character to meet the challenges in global environment.

MISSION

 To impart state-of-the-art engineering and professional education through strong

theoretical basics and hands on training to students in their choice of field.
 To serve our students by teaching them leadership, entrepreneurship, teamwork,
values, quality, ethics and respect for others.
 To provide opportunities for long-term interaction with academia and industry.
 To create new knowledge through innovation and research.

VISION AND MISSION - DEPARTMENT

VISION

Emerging as a Center of Excellence in Electrical and Electronics Engineering

education for studies and research.

MISSION

 To create state-of art facilities for teaching, learning, laboratory practices and research.

 To develop competent engineers through value addition programs, products incubation,

interactive seminars, communication programs, group discussions, trainings, etc.
 To initiate collaborative relationships with Industries and Institutions for real-life experiences.
 JCT COLLEGE OF ENGINEERING AND TECHNOLOGY
(AUTONOMOUS INSTITUTION)
PICHANUR, COIMBATORE – 641105
PROGRAM EDUCATIONAL OBJECTIVES
PEO1: Graduates shall have successful career in industry or have motivation for higher
education or research.
PEO2: Graduates shall apply their knowledge of Electrical and Electronics Engineering and
work as part of a team on multidisciplinary projects.
PEO3: Graduates shall have lifelong learning skills, professional ethics and good
communication capabilities along with entrepreneur skills and leadership, so that they can
succeed in their life.
PROGRAM SPECIFIC OUTCOMES (PSO)
PSO1: Have abilities to apply their knowledge in the domain of Electronics, Electrical
Drives, Power Generation and Transmission, Power Electronics and Control system for the
benefits of the society and the Nation.
PSO2: Have abilities to successfully qualify in national level competitive examinations
for higher studies and employment.
PROGRAM OUTCOMES (POs)

1. Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals and an engineering specialization to the solution of complex engineering
problems.
2. Problem Analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. DESIGN / FORMULA USED / Development of solutions: Design solutions for
complex engineering problems and Design system components or processes that meet the
specified needs with appropriate consideration for the public health and safety, and the
cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research- based knowledge
and research methods including DESIGN / FORMULA USED of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual and as a member or
leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for and have the preparation and ability to
engage in independent and lifelong learning in the broadest context of technological change.
 JCT COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF EEE
(AUTONOMOUS INSTITUTION)
PICHANUR, COIMBATORE – 641105

INSTRUCTION TO THE STUDENTS

1. Students have to go to respective lab classes according to the lab time table.
2. They have to wear the shoes & the prescribed uniform.

3. They have to know about the procedure of the experiment before start doing the experiment.
It will be checked by the staff members.
4. After the viva, they have to get the indent slip from stores and get the required apparatus.

5. They have to give the circuit connections by involving themselves in their batch.
6. They have to take readings in proper manner without any error and get verified from the staff.
7. They have to submit their completed previous experiment record at the time of entering into
the laboratory.
8. After completing the experiment, they have to return all the apparatus to the stores and get
back the indent slip.
9. Strict discipline is solicited inside the laboratory.

EE3022 – VLSI DESIGN INTEGRATED LABORATORY

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EE3022 – VLSI DESIGN INTEGRATED LABORATORY

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SYLLABUS
EE3022 VLSI DESIGN LTPC
2023
COURSE OBJECTIVES:
The main objectives of this course are to:
 To explain the basic concepts of CMOS and
 To introduce the IC fabrication methods
 To introduce the Reconfigurable Processor technologies
 To introduce the basics of analog VLSI design and its importance.
 To learn about the programming of Programmable device using Hardware description
Language.
LIST OF EXPERIMENTS
1. Laboratory exercise: Use any FPGA Board /IDE/open source package/
platform to give hands on training on CMOS design/ reconfigurable processor
based applications.
a) CMOS logic circuit simulation using any open source software package
b) Experiments : structural and behavioral modeling based Verilog HDL programs
c) Experiment: Combinational and sequential Digital logic implementation with
FPGA.
d) Implementation of carry look ahead adder with FPGA
e) Implementation of ALU with FPGA
2. Assignment: Low Power VLSI.
3. FPGA based Mini project.

TOTAL: 30 PERIODS
COURSE OUTCOMES:
At the end of the course, the student should have the:
CO1: Develop CMOS design techniques
CO2: Learn and build IC fabrication
CO3: Explain the need of reconfigurable computing with PLDs.
CO4: Design and development of reprogrammable FPGA.
CO5: Illustrate and develop HDL computational processes with improved design strategies
CONTENT BEYOND SYLLABUS
1. Study Of Synthesize Tools
2. Study of Place And Root For FPGA

EE3022 – VLSI DESIGN INTEGRATED LABORATORY

 DEPARTMENT OF EEE
JCT COLLEGE OF ENGINEERING AND TECHNOLOGY
(AUTONOMOUS INSTITUTION)
PICHANUR, COIMBATORE – 641105

CYCLE PLAN

CYCLE – I

1. Laboratory exercise: Use any FPGA Board /IDE/open source package/ platform to give
hands on training on CMOS design/ reconfigurable processor based applications.

a) CMOS logic circuit simulation using any open source software package

b) Experiments : structural and behavioral modeling based Verilog HDL programs

c) Experiment: Combinational and sequential Digital logic implementation with FPGA.

d) Implementation of carry look ahead adder with FPGA

e) Implementation of ALU with FPGA

2. Study Of Synthesize Tools

3. Study of Place And Root For FPGA

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INDEX

EXP. NO DATE TITLE OF THE EXPERIMENT PAGE NO

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EE3022 – VLSI DESIGN INTEGRATED LABORATORY

 DEPARTMENT OF EEE
Steps to use Xilinx tool:
Start the Xilinx Project Navigator by using the desktop shortcut or by using the

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EXP NO: 1 a) CMOS logic circuit simulation using any open

source software package

DATE:

AIM:
To study simulation tools using Xilinx software tool.

TOOLS REQUIRED: Software:

Xilinx ISE Design Suite

PROCEDURE:
1. Now start the Xilinx ISE Design Suite
2. Go to file and click new project
3. Enter the project name and click next
4. Select the family name is Spartan 3E, speed is -4 and simulator is verilog click next and
click Finish.
5. Click new source.
6. Select verilog module and type file name and click next.
7. Assign input and output port and click next.
8. Finally the report is shown click finish.
9. Type the program save and click synthesis.
10. To see the output wave form change the source from implementation to simulation and
click simulator behavior model in ISim simulator.
11. Give values to the input variables and then click run
12. In wave window, click run icon and you can see corresponding output.

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 In the create new source window select source type as verilog module give file name

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RESULT:

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EXP NO : 1 b)
Experiments: structural and behavioural modeling
based verilog HDL programs
DATE:

AIM:
To write a verilog program for basic logic gates to synthesize and simulate using Xilinx
software tool.

TOOLS REQUIRED: Software:

Xilinx ISE Design Suite

PROCEDURE:
1. Click on the Xilinx ISE Design Suite or Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on
the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed by using ISIM Simulator.

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RTL SCHEMATIC

OUTPUT WAVEFORM

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BEHAVIORAL
module andgate(a,b,y);
input a,b;
output y;
reg y;
always @(a,b) begin
y=a&b;
end
endmodule

STRUCTURAL
Module and gate(a,b,y);
input a,b;
output y;
and a1(y,a,b);
endmodule

RESULT:

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EXP NO : 1 c) Experiment: Combinational and sequential Digital

logic implementation with FPGA

DATE:

AIM:
To write a verilog program for Combinational and sequential Digital logic
implementation with FPGA to synthesize and simulate using Xilinx software tool.

TOOLS REQUIRED: Software:

Xilinx ISE Design Suite

PROCEDURE:

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RTL SCHEMATIC

OUTPUT WAVEFORM

PLACE & ROUTE

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PROGRAM
Combinational Circuits: Full adder
module FADD1
( input a,b,cin,
output sum,carry
);
assign sum = a ^ b ^cin;
assign carry = (a & b) | (cin & b) | (a & cin);
endmodule

Sequential Circuit: Shift Register

module us(a,s,clk,p);
input [3:0]a;
input [1:0]s;
input clk;
output reg [3:0]p;
initial
p<=4'b0110;
always@(posedge clk)
begin
case (s)
2'b00:
begin
p[3]<=p[3];
p[2]<=p[2];
p[1]<=p[1];
p[0]<=p[0];
end
2'b01:
begin
p[3]<=p[0];
p[2]<=p[3];
p[1]<=p[2];
p[0]<=p[1];
end
2'b10:
begin
p[0]<=p[3];
p[1]<=p[0];
p[2]<=p[1];
p[3]<=p[2];
end
2'b11:
begin
p[0]<=a[0];
p[1]<=a[1];
p[2]<=a[2];
p[3]<=a[3];
end
endcase
end
endmodule

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RTL SCHEMATIC

OUTPUT WAVEFORM

PLACE & ROUTE

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RESULT:

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EXP NO : 1 d)
Implementation of carry look ahead adder with FPGA

DATE:

AIM:

To design and implement Carry look ahead Adder in FPGA using Xilinx project
navigator.

TOOLS REQUIRED: Software:

Xilinx ISE Design Suite

PROCEDURE

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RTL SCHEMATIC

OUTPUT WAVEFORM

PLACE & ROUTE

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PROGRAM
module CarryLookAheadAdder(
input [3:0]A, B,
input Cin,
output [3:0] S,
output Cout
);
wire [3:0] Ci; // Carry intermediate for intermediate computation

assign Ci[0] = Cin;

assign Ci[1] = (A[0] & B[0]) | ((A[0]^B[0]) & Ci[0]);
//assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1]) & Ci[1]); expands to
assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])));
//assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2]) & Ci[2]); expands to
assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2]) & ((A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) |
((A[0]^B[0]) & Ci[0])))));
//assign Cout = (A[3] & B[3]) | ((A[3]^B[3]) & Ci[3]); expands to
assign Cout = (A[3] & B[3])|((A[3]^B[3]) & ((A[2] & B[2])|((A[2]^B[2]) & ((A[1] & B[1]) |
((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])))))));

assign S = A^B^Ci;
endmodule

RESULT:

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EXP NO : 1 e)
Implementation of ALU with FPGA

DATE:

AIM:

To design and implement ALU in FPGA using Xilinx project navigator.

TOOLS REQUIRED: Software:

Xilinx ISE Design Suite

PROCEDURE:

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RTL SCHEMATIC

OUTPUT WAVEFORM

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Program:
module ALU(a, b, opcode, rslt, rslt_mul);
input [3:0] a, b;
input [2:0] opcode;
output [3:0] rslt;
output [7:0] rslt_mul;
wire [3:0] a, b; //inputs are wire
wire [2:0] opcode;
reg [3:0] rslt; //outputs are reg
reg [7:0] rslt_mul;
//define operation codes
parameter add_op = 3'b000,
sub_op = 3'b001,
mul_op = 3'b010,
div_op = 3'b011,
and_op = 3'b100,
or_op = 3'b101,
xor_op = 3'b110,
xnor_op = 3'b111;
//perform the operations
always @(a or b or opcode)
begin
case (opcode)
add_op : rslt = a + b;
sub_op : rslt = a - b;
mul_op : rslt_mul = a * b;
and_op : rslt = a & b;
or_op : rslt = a | b;
xor_op : rslt = a ^ b;
xnor_op: rslt = a ^~ b;
default: rslt = 8'b0000_0000;
endcase
end
endmodule

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PLACE & ROUTE

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RESULT:

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EXP NO: 02
Study Of Synthesize Tools
DATE:

AIM:
To study synthesize tools using Xilinx software tool.

TOOLS REQUIRED: Software:

Xilinx ISE Design Suite

THEORY:
Synthesis is an automatic method of converting a higher level abstraction to a lower
level abstraction. The synthesis tool convert Register Transfer Level (RTL) description to gate level
netlists. These gate level netlists consist of interconnected gate level macro cells. These gate level
netlists currently can be optimized for area, speed etc., The analyzed design is synthesized to a
library of components, typically gates, latches, or flipflops. Hierarchical designs are synthesized in
bottom up fashion, that is lower level components are synthesized before higher level components.
Once the design is synthesized we have a gate level netlist.
This gate level netlist can be simulated. Delay for the individual components are available as
part of the description of the component libraries. Timing accurate simulation is not possible at this
point because the actual timing characteristics is determined by the physical placement of the design
within the FPGA chip. However, the functional simulation that is possible at this point is quite a bit
more accurate than simulation based on user specified delays. After run the synthesize in process
window then full adder model is converted to netlist file.
To convert the RTL to gates, three steps typically occur:
 The RTL description is translated to an unoptimized boolean description usually
consisting of primitive gates such as AND and OR gates, flip-flop, and latches. This is a
functionally correct but completely unoptimized description.
 Boolean optimization algorithms are executed on this boolean equivalent description to
produce an optimized boolean equivalent description.
 This optimized boolean equivalent description is mapped to actual logic gate by making
use of a technology library of the target process.

PROCEDURE:
1. Now start the Xilinx ISE Design Suite 12.1
2. Go to file and click new project
3. Enter the project name and click next
4. Select the family name is Spartan 3E, speed is -4 and simulator is verilog click next and click
Finish.
5. Click new source.
6. Select verilog module and type file name and click next.

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7. Assign input and output port and click next.

8. Finally the report is shown click finish.
9. Type the program save and click synthesis.
10. Go to synthesis View RTL schematic

RESULT:

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EXP NO : 03 PLACE AND ROOT FOR FPGAS

DATE:

AIM:
To study place and root and back annotation for FPGAs synthesize tools using Xilinx
software tool.

TOOLS REQUIRED: Software:

Xilinx ISE Design Suite

THEORY:
To map this Full adder design onto the FPGA. The primitive hardware elements that are
available in Xilinx xc3s500e chip, namely lookup tables and positive-edge-triggered flip-flops are
organized as a two dimensional array of CLBs. The net list from synthesize is composed of
gates, latches, and flip-flops. It is necessary to assign CLB to net list primitives. This is the
process of mapping a design. For example gates will be assigned to look-up tables. This process
effectively translates the gate level netlist produce by the synthesize compiler into a netlist of
FPGA primitive hardware components. Each elements of this new netlist corresponds to a
hardware primitive in the FPGA Chip. The mapped design produces identifies the set of FPGA
hardware primitives and their interconnection.
The next step is to assign each of the components in the netlist to a equivalent physical
primitives on the FPGA chip. Once this assignment or placement is made the interconnection
between the components in the netlist must be made within the chip. This will require routing
signals through the switch matrix and other inter connect resources available on FPGA Chip. This
Place and route layout was generated from Xilinx ISE Floor planner. After place and route the
design can be simulated to validate the design. At this point timing is more accurate because the
propagation delays along routed signals and through CLBs can be more accurately estimated.
This is particularly important for designs that are operating under tight timing tolerance.
To convert the RTL to gates, three steps typically occur:
 The RTL description is translated to an unoptimized boolean description usually
consisting of primitive gates such as AND and OR gates, flip-flop, and latches.
This is a functionally correct but completely unoptimized description.
 Boolean optimization algorithms are executed on this boolean equivalent
description to produce an optimized boolean equivalent description.
 This optimized boolean equivalent description is mapped to actual logic gate by
making use of a technology library of the target process

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PROCEDURE:
1. Now start the Xilinx ISE Design Suite
2. Go to file and click new project
3. Enter the project name and click next
4. Select the family name is Spartan 3E, speed is -4 and simulator is verilog click next and click Finish.
5. Click new source.
6. Select verilog module and type file name and click next.
7. Assign input and output port and click next.
8. Finally the report is shown click finish.
9. Types the program saves and clicks synthesis.

10.Choose Implementation user constraints I/O pin planning (plan ahead) pre- synthesis, type the
input /output port.

RESULT:

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