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H Tree

The document outlines the process of creating a flexible H-tree for a 45nm technology node using the Innovus tool, detailing the multi-tap clock tree synthesis (CTS) flow. It includes sections on loading pre-CTS databases, synthesizing the flexible H-tree, debugging the clock tree, and generating various reports related to clock tree metrics and skew groups. Key components such as HTAP cells, clock buffers, and the overall clock tree structure are also discussed to ensure efficient clock distribution in the design.

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nivsingh101
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422 views21 pages

H Tree

The document outlines the process of creating a flexible H-tree for a 45nm technology node using the Innovus tool, detailing the multi-tap clock tree synthesis (CTS) flow. It includes sections on loading pre-CTS databases, synthesizing the flexible H-tree, debugging the clock tree, and generating various reports related to clock tree metrics and skew groups. Key components such as HTAP cells, clock buffers, and the overall clock tree structure are also discussed to ensure efficient clock distribution in the design.

Uploaded by

nivsingh101
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Creating Flexible HTree

Technology node :45nm

Tool: Innovus Presented By: Gunda Vinod


Contents
• Flexible H-Tree with multi-tap CTS flow
• Load Pre-CTS DB
• Clock tree Spec
• Cmds for creating Flex H Tree
• Synthesize flex H tree
• Clock Tree Debugger
• CTS nets
• HTAP cells
• Clock Buffers
• Clock Tree Structure
• Clock Tree Report
• Skew Groups Report
• TimeDesign Summary
Flexible H-tree with multi-tap CTS flow

Pre-CTS DB

create_ccopt_clock_tree_spec

create_route_type ……-shield_net …
Set_route_type ….-net_type top …

set_ccopt_property target_max_tran
– net_type top

create_ccopt_flexible_htree …..

Synthesize_ccopt_flexible_htrees …

ccopt_design
Load Pre-CTS DB

Design Information
Clock tree Spec
Cmds for creating Flex H tree
Synthesize Flex H tree

Synthesizing starts H-Tree Metrics

Wire length & Vias info before detail routing Wire length & Vias info after detail routing
Clock Tree Debugger
• A clock tree debugger displays information about the clock tree, including clock skew, insertion
delay, buffer placement, and timing constraints.

Without Unit Delay With Unit Delay


CTS nets

CTS Top nets CTS Trunk nets


CTS nets Ctd.
• These are the CTS leaf nets that connects from the trunk nets to the sink pin of all the
sequential cells.

CTS Leaf nets


HTAP Cells
• These are the 64 HTAP Cells (CLK Buffers) that placed in the design as we created 8x8 grid .

8x8 Grid
Clock Buffers
• Clock buffers are specifically designed for clock
distribution.
• Clock buffers are designed to have a high fanout,
meaning they can drive many outputs without
signal degradation.
• Clock Buffers have the equal rise and fall times,
offers High Drive Strength and less delay
compared to normal buffers.
• This is the Clock Buffers Placement in the Design.
• In the design that white color dots denotes the
Clock Buffers.

Count of Buffers and Clock Buffers


Clock Tree Structure
• Clock Tree Structures denotes how the clock tree is distributed in overall design.
• Clock Tree Structure contains details such as the maximum number of levels, the number of flip-
flops, and the HTAP cell that drives the most sink pins.
Clock Trees Report .

• Details about the clock tree are provided in the clock tree report, including the nets' length, number of
buffers, area, and capacitance, number of sink pins, total net capacitance, maximum leaf fanout, maximum
length of each HTAP cell, and source to sink resistance.
Clock Trees Report Ctd.
Clock Trees Report Ctd.
Clock Trees Report Ctd.
Skew groups report

After Synthesizing Clock Tree or Before Clock Tree Optimization


Skew groups report Ctd.

After Optimizing Clock Tree


TimeDesign Summary

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