Digital Fundamentals (DF)

GTU # 3130704

Unit-1
Fundamentals of
Digital systems and
Logic families
✓ Outline
Looping
• Number Systems
o Binary, Octal, Decimal, Hexa-decimal, Binary arithmetic operations
• Binary Codes
o Basic codes, Error detecting and correcting codes
• Boolean Algebra
• Logic Gates
o AND, OR, NOT, NAND, NOR, EX-OR, EX-NOR
• Logic Family Terminology
o TTL, Schottky TTL, CMOS logic, Tri-state logic
Number System
Section - 1
Common Number Systems

System Base Symbols Used by Humans? Used in Computers?

Decimal 10 0, 1, … 9 Yes No
Binary 2 0, 1 No Yes
Octal 8 0, 1, … 7 No No
Hexa- 0, 1, … 9,
decimal 16 No No
A, B, … F
Conversion among Bases
Possibilities

Decimal Octal

Binary Hexadecimal

Example

2510 = 110012 = 318 = 1916

Base
Decimal to Binary
Technique
Divide by two, keep track of the remainder
The remainders read from bottom to top give the equivalent binary integer number.
Example - 1 Example - 2
12510 = ?2 2 125 1
0.687510 = ?2 integer fraction
2 62 0
2 31 1 0.6875 x 2 = 1.3750 1 + 0.3750
2 15 1 0.3750 x 2 = 0.7500 0 + 0.7500
2 7 1 0.7500 x 2 = 1.5000 1 + 0.5000
2 3 1 0.5000 x 2 = 1.0000 1 + 0.0000
2 1 1
0 0.687510 = 0.10112
12510 = 11111012
Binary to Decimal
Technique
Multiply each bit by 2n, where n is the “weight” of the bit
The weight is the position of the bit, starting from 0 on the right. Finally, Add the results.
Example - 1 Example - 2
1010112 = ?10 11.112 = ?10
1 0 1 0 1 1 1 1 . 1 1

1 x 25 + 0 x 24 + 1 x 23 + 0 x 22 + 1 x 21 + 1 x 20 1 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2
32 + 0 + 8 + 0 + 2 + 1 2 + 1 + 0.5 + 0.25

1010112 = 4310 11.112 = 3.7510

Decimal to Octal
Technique
Divide by eight, keep track of the remainder
The remainders read from bottom to top give the equivalent octal integer number.
Example - 1 Example - 2
12510 = ?8 0.687510 = ?8
8 125 5 integer fraction
8 15 7
0.6875 x 8 = 5.5000 5 + 0.5000
8 1 1
0.5000 x 8 = 4.0000 4 + 0.0000
0

12510 = 1758 0.687510 = 0.548

Octal to Decimal
Technique
Multiply each digit by 8n, where n is the “weight” of the digit
The weight is the position of the digit, starting from 0 on the right. Finally, Add the results.
Example - 1 Example - 2
7248 = ?10 43.258 = ?10
7 2 4 4 3 . 2 5

7 x 82 + 2 x 81 + 4 x 80 4 x 81 + 3 x 80 + 2 x 8-1 + 5 x 8-2
448 + 16 + 4 32 + 3 + 0.25 + 0.0781

7248 = 46810 43.258 = 35.328110

Decimal to Hexa-Decimal
Technique
Divide by sixteen, keep track of the remainder
The remainders read from bottom to top give the equivalent hexadecimal integer number.
Example - 1 Example - 2
123410 = ?16 0.0312510 = ?16
16 1234 2 integer fraction
16 77 13=D
0.03125 x 16 = 0.5000 0 + 0.5000
16 4 4
0.5000 x 16 = 8.0000 8 + 0.0000
0

123410 = 4D216 0.0312510 = 0.0816

Hexa-Decimal to Decimal
Technique
Multiply each digit by 16n, where n is the “weight” of the digit
The weight is the position of the digit, starting from 0 on the right. Finally, Add the results.
Example - 1 Example - 2
ABC16 = ?10 43.2516 = ?10
A B C 4 3 . 2 5

A x 162 + B x 161 + C x 160 4 x 161 + 3 x 160 + 2 x 16-1 + 5 x 16-2

10 x 162 + 11 x 161 + 12 x 160 64 + 3 + 0.125 + 0.0195
2560 + 176 + 12

ABC16 = 274810 43.2516 = 67.144510

Octal to Binary
Technique
Convert each octal digit to a 3-bit equivalent binary representation
Example Octal Binary
7058 = ?2 0 000
7 0 5 1 001
2 010
3 011
111 000 101
4 100
7058 = 1110001012 5 101
6 110
7 111
Binary to Octal
Technique
From given fractional point, group bits in threes to right and group bits in threes to left
If, left with less than 3 bits at the end then stuff 0s to make it group of three
Convert to octal digits
Example
1011010.1112 = ?8
001 011 010 . 111

1 3 2 7

10110101112 =132.78
Hexa-Decimal to Binary
Technique
Convert each hexadecimal digit to a 4-bit equivalent binary representation
Example Hexa-Decimal Binary Hexa-Decimal Binary
10AF16 = ?2 0 0000 8 1000
1 0001 9 1001
1 0 A F
2 0010 A 1010
3 0011 B 1011
0001 0000 1010 1111 4 0100 C 1100
5 0101 D 1101
10AF16 = 10000101011112
6 0110 E 1110
7 0111 F 1111
Binary to Hexa-Decimal
Technique
From given fractional point, group bits in fours to right and group bits in fours to left
If, left with less than 4 bits at the end then stuff 0s to make it group of four
Convert to hexadecimal digits
Example
101101.01112 = ?16

0010 1101 . 0111

2 D 7

10110101112 = 2D.716
Octal to Hexa-Decimal
Technique
Convert Octal to Binary
From given fractional point, group bits in fours to right and group bits in fours to left
Convert Binary to Hexa-Decimal
Example
10768 = ?16
1 0 7 6

001 000 111 110

0010 0011 1110

2 3 E
10768 = 23E16
Hexa-Decimal to Octal
Technique
Convert Hexa-Decimal to Binary
From given fractional point, group bits in threes to right and group bits in threes to left
Convert Binary to Octal
Example
1F0C16 = ?8
1 F 0 C

0001 1111 0000 1100

000 001 111 100 001 100

0 1 7 4 1 4
1F0C16 = 174148
Binary Addition & Subtraction
Rules for binary addition Rules for binary subtraction
0+0=0 0–0=0
0+1=1 1–1=0
1+0=1 1–0=1
1 + 1 = 10 i.e. 0 0 – 1 = 1, with
with a carry of 1 a borrow 1
1 1 1 1 1 1
0 1 10 1 1 10
1 1 0 1 . 1 0 1 1 0 1 0 . 0 1 10

+ 0 1 1 1 . 0 1 1 - 0 1 1 1 . 1 1 1

1 0 1 0 1 . 0 0 0 0 0 1 0 . 0 1 1
Binary Multiplication & Division
Multiplication Division
10111 110 1 0 1 1 0 1 0 1 1 1 . 1
x 000
10011
1 0 11
1 0 1 1 1 110
1010
1 0 1 1 1 110
0 0 0 0 0 1001
0 0 0 0 0 110
11 0
1 0 1 1 1 110
1 1 0 1 1 0 1 0 1 000
Signed Binary Numbers
Two ways of representing signed numbers:
1) Sign-magnitude form, 2) Complement form.
Most of computers use complement form for negative number notation.
1’s complement and 2’s complement are two different methods in this type.
1’s Complement
1’s complement of a binary number is obtained by subtracting each digit of that binary
number from 1.
Example

1 1 1 1 1 1 1 . 1 1

- 1 1 0 1 - 1 0 1 . 0 1

0 0 1 0 0 1 0 . 1 0
(1’s complement of 1101) (1’s complement of 101.01)

Shortcut: Invert the numbers from 0 to 1 and 1 to 0

2’s Complement
2’s complement of a binary number is obtained by adding 1 to its 1’s complement.
Example

1 1 1 1 1 1 1 . 1 1

- 1 1 0 0 - 1 0 1 . 0 1

0 0 1 1 0 1 0 . 1 0

+ 1 + 1

0 1 0 0 0 1 0 . 1 1
(2’s complement of 1100) (2’s complement of 101.01)
Shortcut: Starting from right side, all bits are same till first 1 occurs and
then invert rest of the bits
Representation of negative number in 2’s complement form
Express -65.5 in 12 bit 2’s complement form.

2 65 1 0.5 x 2 = 1.0
2 32 0 So, result in 12-bit binary is as follows:
2 16 0 65.510 = 01000001.10002
2 8 0 For negative number, we have to
2 4 0 convert this into 2’s complement form

2 2 0 -65.510 = 10111110.10002
2 1 1
0
Accuracy in Binary Number Conversion
Accuracy in Binary Number Conversion
9’s Complement
9’s complement of a decimal number is obtained by subtracting each digit of that decimal
number from 9.
Example

9 9 9 9 9 9 9 . 9 9

- 3 4 6 5 - 7 8 2 . 5 4

6 5 3 4 2 1 7 . 4 5
(9’s complement of 3465) (9’s complement of 782.54)
10’s Complement
10’s complement of a decimal number is obtained by adding 1 to its 9’s complement.
Example

9 9 9 9 9 9 9 . 9 9

- 3 4 6 5 - 7 8 2 . 5 4

6 5 3 4 2 1 7 . 4 5

+ 1 + 1

6 5 3 5 2 1 7 . 4 6
(10’s complement of 3465) (10’s complement of 782.54)
Subtraction using 9’s complement & 10’s complement
Using 9’s complement
Obtain 9’s complement of subtrahend
Add the result to minuend and call it intermediate result
If carry is generated then answer is positive and add the carry to Least Significant Digit (LSD)
If there is no carry then answer is negative and take 9’s complement of intermediate result and place
negative sign to the result.

Using 10’s complement

Obtain 10’s complement of subtrahend
Add the result to minuend
If carry is generated then answer is positive, ignore carry and result itself is answer
If there is no carry then answer is negative and take 10’s complement of intermediate result and place
negative sign to the result.
Subtraction using 9’s complement (Examples)
Example -
1745.81 – 436.62

7 4 5 . 8 1 7 4 5 . 8 1
9’s complement
- 4 3 6 . 6 2 + 5 6 3 . 3 7

3 0 9 . 1 9 1 3 0 9 . 1 8
+ 1

3 0 9 . 1 9
Subtraction using 9’s complement (Examples)
Example - 2
436.62 - 745.81

4 3 6 . 6 2 4 3 6 . 6 2
9’s complement
- 7 4 5 . 8 1 + 2 5 4 . 1 8

- 3 0 9 . 1 9 6 9 0 . 8 0
9’s complement

- 3 0 9 . 1 9

As carry is not generated, so take 9’s

complement of the intermediate
result and add ‘ – ‘ sign to the result
Subtraction using 10’s complement (Examples)
Example - 1
745.81 – 436.62

7 4 5 . 8 1 7 4 5 . 8 1
10’s complement
- 4 3 6 . 6 2 + 5 6 3 . 3 8

3 0 9 . 1 9 1 3 0 9 . 1 9

Ignore the carry

Subtraction using 10’s complement (Examples)
Example - 2
436.62 - 745.81

4 3 6 . 6 2 4 3 6 . 6 2
10’s complement
- 7 4 5 . 8 1 + 2 5 4 . 1 9

- 3 0 9 . 1 9 6 9 0 . 8 1
10’s complement

- 3 0 9 . 1 9

As carry is not generated, so take 10’s

complement of the intermediate result
and add ‘ – ‘ sign to the result
Subtraction using 1’s complement & 2’s complement
Using 1’s complement
Obtain 1’s complement of subtrahend
Add the result to minuend and call it intermediate result
If carry is generated then answer is positive and add the carry to Least Significant Digit (LSD)
If there is no carry then answer is negative and take 1’s complement of intermediate result and place
negative sign to the result.

Using 2’s complement

Obtain 2’s complement of subtrahend
Add the result to minuend
If carry is generated then answer is positive, ignore carry and result itself is answer
If there is no carry then answer is negative and take 2’s complement of intermediate result and place
negative sign to the result.
Subtraction using 1’s complement (Examples)
Example - 1
68.75 – 27.50

6 8.7 5 0 1 0 0 0 1 0 0. 1 1 0 0
1’s complement
- 2 7.50 + 1 1 1 0 0 1 0 0. 0 1 1 1

+ 4 1.25 1 0 0 1 0 1 0 0 1. 0 0 1 1
+1

0 0 1 0 1 0 0 1. 0 1 0 0
Subtraction using 1’s complement (Examples)
Example - 2
43.25 - 89.75

4 3.2 5 0 0 1 0 1 0 1 1. 0 1 0 0
1’s complement
- 8 9.75 + 1 0 1 0 0 1 1 0. 0 0 1 1

- 4 6.50 1 1 0 1 0 0 0 1. 0 1 1 1
1’s complement

0 0 1 0 1 1 1 0. 1 0 0 0

As carry is not generated, so take 1’s

complement of the intermediate
result and add ‘ – ‘ sign to the result
Subtraction using 2’s complement (Examples)
Example - 1
68.75 – 27.50

6 8.7 5 0 1 0 0 0 1 0 0. 1 1 0 0
2’s complement
- 2 7.50 + 1 1 1 0 0 1 0 0. 1 0 0 0

+ 4 1.25 1 0 0 1 0 1 0 0 1. 0 1 0 0

Ignore Carry bit

0 0 1 0 1 0 0 1. 0 1 0 0
Subtraction using 2’s complement (Examples)
Example - 2
43.25 - 89.75

4 3.2 5 0 0 1 0 1 0 1 1. 0 1 0 0
2’s complement
- 8 9.75 + 1 0 1 0 0 1 1 0. 0 1 0 0

- 4 6.50 1 1 0 1 0 0 0 1. 1 0 0 0
2’s complement

0 0 1 0 1 1 1 0. 1 0 0 0

As carry is not generated, so take 2’s

complement of the intermediate
result and add ‘ – ‘ sign to the result
Binary Codes
Section - 2
8421 BCD Code (Natural BCD Code)
Each decimal digit, 0 through 9, is coded by 4-bit binary number
8, 4, 2 and 1 weights are attached to each bit
BCD code is weighted code
1010, 1011, 1100, 1101, 1110 and 1111 are illegal codes
Less efficient than pure binary
Arithmetic operations are more complex than in pure binary
Example

Decimal 1 4

BCD 0001 0100

Binary 1110
Binary Codes

Decimal Binary BCD Decimal Binary BCD

0 0 0000 8 1000 1000

1 1 0001 9 1001 1001
2 10 0010 10 1010 0001 0000
3 11 0011 11 1011 0001 0001
4 100 0100 12 1100 0001 0010
5 101 0101 13 1101 0001 0011
6 110 0110 14 1110 0001 0100
7 111 0111 15 1111 0001 0101
BCD Addition
Example - 1

1 1 1
2 5 0 0 1 0 0 1 0 1

+ 1 3 + 0 0 0 1 0 0 1 1

3 8 0 0 1 1 1 0 0 0

No carry, no illegal code. So, this is

the correct sum.

Rule: If there is an illegal code or carry is generated as a result of addition,

then add 0110 to particular that 4 bits of result.
BCD Addition
Example - 2
1 111
679.6 0110 0111 1001 .0110
+ 536.8 + 0101 0011 0110 .1000

1216.4 1011 1010 1111 .1110 All are illegal codes

+0110 +0110 +0110 +.0110 Add 0110 to each

10001 10000 10101 1.0100 Propagate carry

+1 +1 +1 +1
0001 0010 0001 0110 .0100 Corrected sum
BCD Subtraction
Example - 1

3 8 0 0 1 1 1 0 0 0

- 1 5 - 0 0 0 1 0 1 0 1

2 3 0 0 1 0 0 0 1 1

No borrow. So, this is the correct

difference.

Rule: If one 4-bit group needs to take borrow from neighbor, then subtract
0110 from the group which is receiving borrow.
BCD Subtraction
Example - 2

206.7 0010 0000 0110 .0111

- 147.8 - 0001 0100 0111 .1000
58.9 0000 1011 1110 .1111 Borrows are present
-0110 -0110 -.0110 Subtract 0110

0101 1000 .1001 Corrected difference

Excess Three (XS-3) Code
Excess Three Code = 8421 BCD + 0011(3)
XS-3 code is non-weighted BCD code
Also known as self complementing code
0000, 0001, 0010, 1101, 1110 and 1111 are illegal codes
Example

Decimal 1 4

BCD 0001 0100

XS-3 0100 0111
XS-3 Addition
Example
247.6 0101 0111 1010 .1001
+ 359.4 + 0110 1000 1100 .0111
Rule: Add 0011 to
607.0 1011 1111 10110 1.0000 Carry generated
group which
+1 +1 Propagate carry generated carry and
1011 10000 0111 .0000 Subtract 0011 to
group which do not
+1 generated carry
1100 0000 0111 .0000
- 0011 +0011 +0011 +.0011
Corrected Sum in
1001 0011 1010 .0011 XS-3
XS-3 Subtraction
Example

57.6 1000 1010 .1001

Rule: Subtract 0011 to
- 27.8 - 0101 1010 .1011 group which generated
29.8 0010 1111 .1110 borrow and Add 0011
to group which do not
+0011 -0011 -.0011 generated borrow
0101 1100 .1011
Gray Code
Only one bit changes between each pair of successive code words (Unit distance code).
Gray code is a reflected code.
Gray codes are designed recursively using following rules:
1-bit Gray code has two code words, 0 and 1.
The first 2n code words of an (n+1)-bit Gray code equal the code words of n-bit gray code, written in order
with a leading 0 appended.
The last 2n code words of an (n+1)-bit Gray code equal the code words of n-bit gray code, but written in
reverse order with a leading 1 appended.
 Gray Code
Decimal 4-bit Binary
1-bit 2-bit 3-bit 4-bit
0 00 000 0000 0 0000
1 01 001 0001 1 0001
11 011 0011 2 0010
10 010 0010 3 0011
110 0110 4 0100
111 0111 5 0101
101 0101 6 0110
100 0100 7 0111
1100 8 1000
1101 9 1001
1111 10 1010
1110 11 1011
1010 12 1100
1011 13 1101
1001 14 1110
1000 15 1111
Binary to Gray and Gray to Binary Conversion
Conversion of n-bit Binary number (B) to Gray Code (G) is as follows:

Example: Convert (1001)2 to Gray Code.

Binary 1 0 0 1

Gray 1 1 0 1
Gray to Binary Conversion
Conversion of n-bit Gray Code (G) to Binary Number (B) is as
follows:

Example: Convert Gray code 1101 to Binary.

Gray 1 1 0 1

Binary 1 0 0 1
Error-Detecting Codes
Noise can alter or distort the data in transmission.
The 1s may get changed to 0s and 0s to 1s.
Because digital systems must be accurate to the digit, errors can pose a serious problem.
Single bit error should be detect & correct by different schemes.
Parity, Check Sums and Block Parity are few examples of error detecting code.
Parity
Parity bit is the simplest technique.
There are two types of parity – Odd parity and Even parity.
For odd parity, the parity is set to a 0 or a 1 at the transmitter such that the total number of
1 bits in the word including the parity bit is an odd number.
For even parity, the parity is set to a 0 or a 1 at the transmitter such that the total number of
1 bits in the word including the parity bit is an even number.
For example, 0110 binary number has “1” as Odd parity and “0” as Even parity.
Detect a single-bit error but can not detect two or more errors within the same word.
In any practical system, there is always a finite probability of the occurrence of single error.
E.g. In an even-parity scheme, code 10111001 is erroneous because number of 1s is odd(5),
while code 11110110 is error free because number of 1s is even(6).
Check Sums
Simple parity can not detect two errors within the same word.
Added to the sum of the previously transmitted words
At the transmission, the check sum up to that time is sent to the receiver.
The receiver can check its sum with the transmitted sum.
If the two sums are the same, then no errors were detected at the receiver end.
If there is an error, the receiving location can ask for retransmission of the entire data.
This type of transmission is used in teleprocessing system.
Block Parity

01011011 0 01011011 0 01011011 0

10010101 1 10010101 1 10010101 1
01101110 0 01100110 0 01101110 0
11010011 0 11010011 0 10000011 0
10001101 1 10001101 1 10001101 1
01110111 1 01110111 1 01110111 1
Parity Row 01110110 0 01110110 0 01110110 0

Parity Column
Error Correcting Code
7-bit Hamming Code is widely used error How to detect error?
correcting code, containing 4 bits of data Example: Received data = 1001001
and 3 bits of even parity.
P1 P2 D 3 P4 D 5 D 6 D 7 = 1 0 0 1 0 0 1
Pattern: P1 P2 D3 P4 D5 D6 D7
P1 D3 D5 D7 = 1 0 0 1 (No Error)
Group - 1: P1D3D5D7
P2 D3 D6 D7 = 0 0 0 1 (Error)
Group - 2: P2D3D6D7
P4 D5 D6 D7 = 1 0 0 1 (No Error)
Group - 3: P4D5D6D7
The error word is 0 1 0 = 210.
Example: Data = 1101
Complement the 2nd bit (from left).
P 1 P 2 D 3 P 4 D 5 D 6 D7 = P 1 P 2 1 P 4 1 0 1
Correct code is 1 1 0 1 0 0 1
P 1 D3 D5 D7 = 1 1 1 1
P 2 D3 D6 D7 = 0 1 0 1
P 4 D5 D6 D7 = 0 1 0 1
7-bit Hamming Code is 1 0 1 0 1 0 1
Boolean Algebra
Section - 3
Boolean Algebra Laws
Boolean Algebra Laws

Break the line change the sign

 L.H.S. R.H.S.

A B C A+B+C
0 0 0 0 1 1 1 1 1
0 0 1 1 0 1 1 0 0
0 1 0 1 0 1 0 1 0
0 1 1 1 0 1 0 0 0
1 0 0 1 0 0 1 1 0
1 0 1 1 0 0 1 0 0
1 1 0 1 0 0 0 1 0
1 1 1 1 0 0 0 0 0
From truth table, it is clearly visible that L.H.S. = R.H.S. Hence, the
complement of a
sum of variables is equal to the product of their individual complements.
 L.H.S. R.H.S.

A B C AB
0 0 0 C 1 1 1 1 1
0 0 1 0 1 1 1 0 1
0 1 0 0 1 1 0 1 1
0 1 1 0 1 1 0 0 1
1 0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 0 1
1 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 0 0
1
From truth table, it is clearly visible that L.H.S. = R.H.S. Hence, the
complement of a
product of variables is equal to the sum of their individual complements.
Reducing Boolean Expression (Example – 1)

(Distributive law)
(Distributive law)
(A.A = A)

(1 + A = 1)
Reducing Boolean Expression (Example – 2)

(De-Morgan’s law)
(De-Morgan’s law)
(Distributive law)
(Distributive law)
(A.A’ = 0)
(Distributive law)
(A.A’ = 0)
Logic Gates
Section - 4
Logic Gates
Most basic logical unit of the digital system is gate circuit.
Types of gate circuits are as follows
1. AND Gate
2. OR Gate
3. NOT Gate (Inverter)
4. NOR Gate
5. NAND Gate
6. XOR Gate
7. XNOR Gate
1. AND Gate
AND Gate has an output which is normally at logic level “0” and only goes “HIGH” to a logic
level “1” when ALL of its inputs are at logic level “1”

2-input AND Gate Truth Table Logic Notation

A A B C
B C
0 0 0
0 1 0
1 0 0
1 1 1
2. OR Gate
OR Gate or Inclusive-OR gate has an output which is normally at logic level “0” and only goes
“HIGH” to a logic level “1” when one or more of its inputs are at logic level “1”.

2-input OR Gate Truth Table Logic Notation

A A B C
B C
0 0 0
0 1 1
1 0 1
1 1 1
3. NOT (Inverter) Gate
? NOT gate has an output which is always opposite to input level.

Inverter Gate Truth Table Logic Notation

A C A C
0 1
1 0
4. NOR Gate
NOR Gate is an OR gate followed by an inverter.
NOR Gate has an output which is normally at logic level “1” and only goes “LOW” to a logic
level “0” when one or more of its inputs are at logic level “1”.

2-input NOR Gate Truth Table Logic Notation

A A B C
C
B 0 0 1
0 1 0
1 0 0
1 1 0
5. NAND Gate
NAND Gate is an AND gate followed by an inverter.
NAND Gate has an output which is normally at logic level “1” and only goes “LOW” to a logic
level “0” when ALL inputs are at logic level “1”.

2-input NAND Gate Truth Table Logic Notation

A A B C
C
B 0 0 1
0 1 1
1 0 1
1 1 0
6. Exclusive-OR (X-OR) Gate
? X-OR gate that has 1 state when one and only one of its two inputs assumes a logic 1 state
and has 0 state when all of its input are same.
? Also known as anti-coincidence gate or inequality detector.

2-input XOR Gate Truth Table Logic Notation

A A B C
C
B 0 0 0
0 1 1
1 0 1
1 1 0
7. Exclusive-NOR (X-NOR) Gate
X-NOR gate that has 1 state when all of its input are same and has 0 state when one of its
input has 0 state and other input is 1 state.
Also known as coincidence gate or equality detector.

2-input XNOR Gate Truth Table Logic Notation

A A B C
B C
0 0 1
0 1 0
1 0 0
1 1 1
NAND as Universal Gate

(AB)’ ((AB)’)’ =
A A’ A AB
B
NOT using NAND AND using NAND

A’
A
(A’B’)’ = (A+B)
B
B’
OR using NAND
NOR as Universal Gate
(A+B)’ ((A+B)’)’ = A+B
A
A A’
B
NOT using NOR OR using NOR

A’
A
(A’+B’)’ = AB
B
B’
AND using NOR
Logic Families
Section - 5
Digital IC Specification
Threshold voltage
It is defined as that voltage at the input of a gate which causes a change in the state of the output from
one logic level to the other.
Propagation Delay
A pulse through a gate takes a certain amount of time to propagate from input to output. This interval of
time is known as the propagation delay of gate.
Power dissipation
The power dissipation, PD, of a logic gate is the power required by the gate to operate with 50% duty cycle
at a specified frequency and is expressed in milliwatts.
Fan-in
The fan-in of a logic gate is defined as the number of inputs that the gate is designed to handle.
Fan-out
The fan-out (also called the loading factor) of a logic gate is defined as the maximum number of standard
loads that the output of the gate can drive without impairing its normal operation.
Digital IC Specification
Voltage & Current parameters
VIH(min), VOH(min), VIL(max), VOL(max), IIH, IOH, IIL, IOL
Noise Margin
The noise immunity of a logic circuit refers to the circuit’s ability to tolerate noise voltages at its inputs.
A quantitative measure of noise immunity is called noise margin.
Operating Temperatures
The IC gates and other circuits are temperature sensitive being semiconductor devices.
However, they are designed to operate satisfactorily over a specified range of temperature.
Speed power products
A common means for measuring and comparing the overall performance of an IC family is the speed
power product, which is obtained by multiplying the gate propagation delay by the gate power
dissipation.
TTL v/s CMOS v/s ECL

Characteristic TTL CMOS ECL

Power Input Moderate Low Moderate-High
Frequency limit High Moderate Very high
Circuit density Moderate-hig High-very Moderate
h high
Circuit types per family High High Moderate
Logic Propagation Power Noise Fan-in Fan-out Cost
Family delay time dissipation per Margin (V)
(ns) gate (mW)
TTL 9 10 0.4 8 10 Low
CMOS <50 0.01 5 10 50 Low
ECL 1 50 0.25 5 10 High
Transistor-Transistor Logic (TTL)
Dependence on transistors alone to perform basic logic operations.
Most popular logic family.
Most widely useful bipolar digital IC family.
The TTL uses transistors operating in saturated mode.
It is the fastest of the saturated logic families.
Good speed, low manufacturing cost, wide range of circuits, and the availability in SSI and
MSI are its merits.
Schottky TTL
When a transistor is saturated, excess charge carries will be stored in the base region and
they must be removed before the transistor can be turned off.
So, owing to storage time delay, the speed is reduced.
The Schottky TTL series reduces this storage time delay by not allowing the transistor to go
into full saturation.
This is accomplished by using a Schottky barrier diode(SBD) between the base and the
collector of each transistor.
More than three times the switching speed of standard TTL, at the expense of approximately
doubling the power consumption.
Tri-state TTL
It utilizes the advantage of the high speed of operation of the totem-pole configuration and
wire ANDing of the open-collector configuration.
It is called the tri-state TTL, because it allows three possible output states: HIGH, LOW, and
HIGH Impedance (Hi-Z).
In the Hi-Z state, both the transistors in the totem-pole arrangement are turned off, so that
the output terminal is a HIGH impedance to ground or Vcc.
In fact, the output is an open or floating terminal, that is, neither a LOW nor a HIGH.