Manav Rachna International Institute of Research and Studies

(Deemed to be University)
School of Engineering & Technology
Department of Electronics and Communication Engineering

Ref. No.: MRIIRS/SET/ECE/STC/2023/01

CIRCULAR

Subject: Internship on VLSI Design

(8TH JUNE- 2ND JULY 2023)

Electronics and communication Engineering Department MRIIRS has conducted a training

on VLSI Designing for the students of ECE & EEE ,5th sem. Please find following the
Program details:

Title: “SUMMER INTERNSHIP ON VLSI DESIGN”

Date of conduct: 8 th June- 2nd July 2023

Time: 8 AM -2:50 PM
Target Audience: Students of ECE, EEE (5TH SEM)
Venue: AF-25, second floor A block, MRIIRS, Faridabad
Coordinators: Dr. Pratima Mehta, Associate Professor ECE, SET, MRIIRS

Dr. Abhiruchi Passi

HOD, ECE, Deptt,
MRIIRS

To: Dr. Pratima Mehta, Associate Professor, ECE Deptt, SET, MRIIRS

Copy to: All HoD, MRIIRS– Please attend the STC as scheduled above.
All Deans For kind information
Director (IQAC) For kind information
PVCs, MRIIRS For kind information
PS to VC-MRIIRS For kind information
 Manav Rachna International Institute of Research and Studies
(Deemed to be University)
School of Engineering & Technology
Department of Electronics and Communication Engineering

Ref. No.: MRIIRS/SET/ECE/STC/2023/01

REPORT OF SUMMER INTERNSHIP

SUBJECT: VLSI DESIGN TRAINING

BY-

- Manmath prasad
Panda- BMM-01

- Sahil Sharma
-BEE-01
- Neha Sharma
-BEE-06
- Shivangi
Sharma -
BEC-25174
(Maharishi
Dayanand
University
Rohtak) Manav Rachna International Institute of
- Ayushi Nagrota Research and Studies
- BEC-L1 (Deemed to be University)
School of Engineering & Technology
Department of Electronics and Communication Engineering
Acknowledgment

We would like to express my deepest gratitude to all the individuals and

organizations that made my summer internship in VLSI design a valuable and
enriching experience.
First and foremost, we want to extend my heartfelt thanks to Dr Pratima Ma’am
and Dr Anand sir, our internship supervisor, whose guidance and mentorship
were instrumental in helping me develop a strong foundation in VLSI design.
Your expertise and patience were invaluable, and we have learned a great deal
under your tutelage.
We are grateful to MRIIRS for facilitating this internship opportunity and for
their ongoing support in my educational journey. The knowledge and skills we
have gained during this internship will undoubtedly benefit my academic and
career pursuits in VLSI design.
We want to express my appreciation to my family and friends for their
unwavering support and encouragement throughout this internship. Your belief
in my abilities has been a constant source of motivation.
Last but not least, we want to thank all the industry professionals and
researchers whose work has been a constant source of inspiration. The VLSI
design community continues to drive innovation, and we are excited to be a part
of it.
This internship has been an incredible learning experience, and we are deeply
thankful for the opportunities and support we have received., we look forward
to applying the knowledge and skills we’ve acquired to make a positive impact
in the field of VLSI design.
Sincerely,
Sahil Sharma, Manmath Panda, Neha sharma, Shivangi Sherma, Ayushi Nagrota

K-Map
A pictorial method that is utilised to minimise various
Boolean expressions without using the Boolean algebra
theorems along with the equation manipulations.

 K-Map for 3 variables

 K-Map for 3 variables

 K-Map for 4 variables

Combinational circuits

A circuit in which the output depends on the present

combination of inputs. Combinational circuits are made
up of logic gates. The output of each logic gate is
determined by its logic function

MULTIPLEXER: A device that selects between several analog or digital

input signals and forwards the selected input to a single output line.

 4x1 Multiplexer Block diagram

 4 TO 1 MULTIPLEXER TRUTH TABLE

S0 S1 A0 A1 A2 A3 Y(Output)
0 0 0 X X X 0
0 0 1 X X X 1
0 1 X 0 X X 0
0 1 X 1 X X 1
 1 0 X X 0 X 0
1 0 X X 1 X 1
1 1 X X X 0 0
1 1 X X X 1 1

 4 TO 1 MULTIPLEXER CIRCUIT
DIAGRAM

DEMULTIPLEXER: A demultiplexer, sometimes abbreviated

dmux, is a circuit that has one input and more than one
output. It is used when a circuit intends to send a signal to
one of many devices.

 1x4 De-Multiplexer Block Diagram

 1x4 De-Multiplexer Truth Table

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

 1x4 De-Multiplexer Circuit Diagram

Half Adder
Half adder is a combinational arithmetic
circuit that adds two numbers and produces a
sum bit (s) and carry bit (c) both as output.
 Half adder Block & Circuit Diagram
  Half adder Truth table

Inputs Outputs

A B S (Sum) C (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Full Adder
A full adder is a digital circuit that performs
addition. A full adder adds three one-bit
binary numbers, two operands and a carry
bit.
 Full adder Block & Circuit Diagram
  Full adder Truth Table
Inputs Outputs

A B Cin S (Sum) Cout (Carry)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Encoder
An Encoder is a combinational circuit that
performs the reverse operation of a Decoder.
It has a maximum of 2^n input lines and 'n'
output lines, hence it encodes the
information from 2^n inputs into an n-bit
code. It will produce a binary code equivalent
to the input, which is active High.

 4 to 2 Encoder Block Diagram

 4 to 2 Encoder Truth Table

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

 2 to 4 Encoder Circuit Diagram

Decoder
A decoder is a circuit that changes a code
into a set of signals.

 2 to 4 Decoder Block Diagram

 2 to 4 Decoder Truth Table

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

 2 to 4 Decoder Circuit Diagram

Sequential Circuit
The sequential circuit is a special type of circuit
that has a series of inputs and outputs. The outputs
of the sequential circuits depend on both the
combination of present inputs and previous
outputs.

Flip Flops

A flip-flop is a sequential digital electronic circuit having

two stable states that can be used to store one bit of
binary data.

S-R Flip Flop

 Block diagram
 Truth Table

 Circuit Diagram

D-Flip Flop

 Block diagram
  Truth Table

 Circuit Diagram

J-K Flip Flop

 Block diagram
 Truth Table

 Circuit Diagram
T Flip Flop

 Block diagram
 Truth Table

 Circuit Diagram

STICK DIAGRAM
Layout of circuit
 VLSI design aims to translate circuit concepts onto silicon. stick
diagrams are a means of capturing topography and layer
information using simple diagrams. Stick diagrams convey layer
information through colour codes (or monochrome encoding). Acts
as an interface between symbolic circuit and the actual layout.

Red- polysilicon /(input terminal)

Blue- vdd& ground
Black- interconnection


Green – PMOS -
n difference(nmos)
Yellow- SOURCE- UPPER
p difference ( pmos)

SIDE
DRAIN
–BELOW
 NMOS - DRAIN
– ON UPPER SIDE
SOURCE- BELOW
SIDE
AIM- To draw the stick diagram layout circuit of
following-
1. NOR
2. NOT
3. {A+B+C} COMPLEMENT
4. {(A+B) C} Complement

5. (A B C) Complement

1.NOR

2. NOT
3.{A+B+C} COMPLEMENT
4.{(A+B) C} Complement
5.(A B C) Complement
 PROGRAM NO. 1

Aim: Design And gate using Verilog HDL.

Software used: Model sim 10.1b (Mentor graphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module and_2(a, b, s);
input a, b;
output s;
assign s=a&b;
End module
 PROGRAM NO. 2

Aim: Design Nand gate using Verilog HDL.

Software used: Model sim 10.1b (Mentor graphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module nand_2(a, b,s);
input a,b;
output s;
assign s=a~&b;
Endmodule

PROGRAM NO. 3

Aim: Design OR gate using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module or_2(a,b,s);
 input a,b;
output s;
assign s=a||b;
Endmodule

PROGRAM NO. 4

Aim: Design NOR gate using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module nor_2(a,b,s);
input a,b;
 output s;
assign s=a~||b;
Endmodule

PROGRAM NO. 5

Aim: Design NOT gate using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module not_2(a,b,s);
input a,b;
 output s;
assign s=a~b;
Endmodule

PROGRAM NO. 6

Aim: Design XOR gate using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module xor_2(a,b,s);
input a,b;
 output s;
assign s=a^b;
Endmodule

PROGRAM NO. 7

Aim: Design XNOR gate using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module xnor_2(a,b,s);
input a,b;
output s;
 assign s=a~^b;
Endmodule

PROGRAM NO. 8

Aim: Design half adder using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module halfadder(a,b,s,c);

input a,b;

output s,c;
 assign s=a^b;

assign c= a&b ;

Endmodule

PROGRAM NO.9

Aim: Design Full adder using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module fulladder (a,b,c,s,z);
 input a,b,c;

output s,z;

assign s=a^b^c;

assign c=a&b||a&c||b&c;

Endmodule

PROGRAM NO.10

Aim: Design SR flip flop using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram

Program:
module SR_ff(s,r,clk,rst_n,q,qbar);
input s,r,clk,rst_n;

output q,qbar;

reg q,qbar;

always@(posedge clk)

begin

if(!rst_n);

q<=0;

else

begin

case(s,r);

2'00:q<=q;

2'01:q<=0;

2'10:q<=1;

2'11:q=x;

endcase

end

end

assign qbar=~q;

Endmodule

PROGRAM NO.11

Aim: Design JK flip flop using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:
Program:
module JK_FF(q,qbar,clk,dr,j,k);

input clk,dr,j,k;

output q,qbar;

reg q,qbar;

reg t=1'b0;

always@(negedge clk or clk)

begin

if(clk)

t<=1'b0;

else

case({k,j})

2'b00:t<=t;

2'b01:t<=1'b1;

2'b10:t<=1'b0;

2'b11:t=~t;

default:t<=t;

endcase

end

always@(*)

begin

q<=t;

qbar<=~t;
end

Endmodule

PROGRAM NO.12

Aim: Design D-flip flop using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module D_FF(din,en,q);

input din,en;
output q;

reg q;

reg t=1'b0;

always@(en or din)

begin

if(en)

q<=din;

else

q<=1b’0;

End

Endmodule

PROGRAM NO.13

Aim: Design 4:1 multiplexer using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:
PROGRAM:
module mux41_beh(in,sel,out);

input[3:0]in;

input[1:0]sel;

output out;

reg out;

always@(in or sel)

begin

if(in)

case(sel)

2'b00: out<=in[0];

2'b01: out<=in[1];

2'b10: out<=in[2];

2'b11: out<=in[3];

default: out<=1'b0;

endcase

else

out<=1'b0;

end

Endmodule

Result:
 PROGRAM NO. 14

Aim: Design 2:1 decoder using Verilog HDL.

Software used: Model sim 10.1b (Mentorgraphics)

Theory: Truth Table and block diagram
Truth Table and Block Diagram:

Program:
module decoder_24(in,en,out);
input[1:0]in;

input en;

output[3:0]out;

and[0] (~in[0],~in[1],en,out[0]);

and[1](in[0],~in[1],en,out[1]);

and[2](~in[0],in[1],en,out[2]);

and[3](in[0],in[1],en,out[3]);

Endmodule