A SHORT TERM INTERNSHIP REPORT

On
“VLSI DESIGN WITH VERILOG”

submitted in partial fulfillment of the requirements for the award of the

degree of
BACHELOR OF TECHNOLOGY
in
ELECTRICAL AND ELECTRONICS ENGINEERING
By

KURUBA HEMANTH KRISHNA VARDHAN

22705A0221

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

ANNAMACHARYA INSTITUTE OF TECHNOLOGY AND SCIENCES: RAJAMPET
(AUTONOMOUS)
(Approved by AICTE, NEWDELHI & Affiliated to J.N.T. University, Anantapur)
Accredited by NBA of AICTE, NEWDELHI.
Accredited by NAAC of UGC, BANGLORE.
Rajampet, Annamayya (Dist), A.P-516126.
2024-2025
 DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING
ANNAMACHARYA INSTITUTE OF TECHNOLOGY AND SCIENCES: RAJAMPET
(AUTONOMOUS)
(Approved by AICTE, NEWDELHI & Affiliated to J.N.T.University, Anantapur),
Accredited by NBA of AICTE, NEWDELHI,
Accredited by NAAC of UGC, BANGALORE. Rajampet, Annamayya (Dist), A.P-516126.

Certificate
This is to certify that a Short term Internship entitled “VLSI DESIGN WITH
VERILOG” is a bona-fide work done by KURUBA HEMANTH KRISHNA VARDHAN
(22705A0221) of Annamacharya Institute of Technology and Sciences, Rajampet, Andhra
Pradesh, India, for partial fulfillment of the requirements for the award of degree of Bachelor
of Technology in Electrical and Electronics Engineering during the academic year 2024-
2025.

The results embodied in this thesis have not been submitted to any other University or
Institute for the award of any degree.

Internship Supervisor Head of the Department

Mr.M.RAMESH, M.Tech., (Ph.D)., Dr. M. PADMA LALITHA,M.Tech.,Ph.D.,
Assistant Professor, Professor and Head of the Department
Department of EEE, Department of EEE,
A.I.T.S,Rajampet. A.I.T.S,Rajampet.
 An Internship Report

Submitted in accordance with the requirement for the degree of Bachelor of Technology

Name of the College: Annamacharya Institute of Technology and Sciences,

Rajampet.

Department: Electrical and Electronics Engineering

Name of the Faculty Guide: Mr.M.RAMESH

Duration of the Internship: From-01-06-2024 To- 31-07-2024

Name and address of the Organization: TECHNOTRAN

Name of the Student: KURUBA HEMANTH KRISHNA VARDHAN

Degree of Study: B. Tech

Year of Study: 4th Year

Register Number: 22705A0221

Date of Submission:
 Student’s Declaration

I, KURUBA HEMANTH KRISHNA VARDHAN, a student of B. Tech Program,

Reg.No.22705A0221 of the department of Electrical & Electronics Engineering,
Annamacharya Institute of Technology and Sciences, Rajampet college do hereby declare
that I have completed the mandatory internship from 01-06-2024to 31-07-2024 in
TECHNOTRAN under the faculty Guideship of Mr.M.RAMESH, department of Electrical&
Electronics Engineering in Annamacharya Institute of Technology and Sciences, Rajampet.

(Signature and Date)

Endorsements

Faculty Guide

Head of the Department

Certificate from Organization
 VLSI DESIGN With Verilog
CONTENTS
VLSI DESIGN with Verilog

WEEK Work carried out throughout the week

Introduction to VLSI Design and Digital Circuit

1
 Basics of Boolean algebra and logic gates
 Concepts of combinational and sequential circuits
 Differences between ASICs and FPGAs in VLSI design
 Overview of the design flow in VLSI design

Purpose of HDLs and Overview of Verilog

 Role of Hardware Description Languages (HDLs) in VLSI design
2
 Overview of Verilog language
 Introduction to Verilog syntax, structure, data types, and variables

Implementing Combinational circuits in Verilog

 Implementation of Adders and Subtractors in Xilinx 14.7 ISE
3
 Module Instantiation in Verilog
 Design and Implementation of Multiplexers
 Hands-on exercises on implementing logic functions in Verilog
Conditional Statements in Verilog
 Introduction to conditional statements used in Verilog
4
 Implementing MUX using if-else conditional statements
 Designing of Demultiplexers in Xilinx 14.7 ISE using Case statements

Designing of Encoder and Decoder circuits in Verilog

 Introduction to Encoders in Digital Electronics
5
 Implementation of Decoders using Verilog
 Comparators in Digital Circuits
Multipliers, Flip-Flops, Latches and Registers
 Introduction to Multipliers in Digital circuits
6
  Flip-flops and latches including SR, D, JK flip-flops.
 Design of registers in Verilog
 Different types of Shift registers

Implementing a Small Digital Circuit using Verilog

 Assign students to implement a small digital circuit using Verilog on
Xilinx software.
7  Guide students through synthesizing and simulating their Verilog designs
using Xilinx tools.
 Conduct reviews and discussions on the implemented designs
Project Planning, Integration, and Presentation
 Initiate the final project and define project goals, scope, and objectives.
 Define system requirements and architecture for the final project.
 Set up Xilinx software tools and development environments for the final
8 project.
 Integrate, test, and debug the final project.
 Document the project implementation process and prepare for the final
presentation.
 final project presentation and submit project documentation.
INTRODUCTION TO VLSI DESIGN AND DIGITAL CIRCUIT
Introduction to VLSI:
Very Large-Scale Integration (VLSI) is the process of creating integrated circuits (ICs) by
combining thousands to millions of transistors on a single chip. This technology has enabled
the development of complex and high-performance electronic systems. VLSI design has
revolutionized the electronics industry, leading to advancements in computers,
telecommunications, and consumer electronics.
History of VLSI:
The evolution of VLSI began in the 1960s with the advent of small-scale integration (SSI)
and medium-scale integration (MSI), where hundreds of transistors were integrated onto a
single chip. The 1970s saw the introduction of large-scale integration (LSI), with thousands
of transistors. The term VLSI emerged in the 1980s as technology progressed to
accommodate millions of transistors. This era marked significant advancements in
semiconductor fabrication processes and design methodologies, leading to the sophisticated
ICs we see today.
Classification of ICs
Integrated Circuits (ICs) can be classified based on various criteria:
Based on Application:
Analog ICs: Used for processing analog signals. Examples include amplifiers and oscillators.
Digital ICs: Used for processing digital signals. Examples include microprocessors and
memory chips.
Mixed-Signal ICs: Combine analog and digital functions on a single chip.
Based on Fabrication Process:
Bipolar ICs: Utilize bipolar junction transistors. Known for high speed but higher power
consumption.
CMOS ICs: Use complementary metal-oxide-semiconductor transistors. Preferred for low
power consumption and high integration density.
BiCMOS ICs: Combine the benefits of both bipolar and CMOS technologies.
Based on Technology:
Planar Technology: Traditional IC fabrication method using planar transistors.
3D IC Technology: Uses vertical stacking of multiple layers of ICs to improve performance
and reduce footprint.
Based on Device or Transistor Count:

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SSI (Small-Scale Integration): Up to 100 transistors per chip.
MSI (Medium-Scale Integration): 100 to 1,000 transistors per chip.
LSI (Large-Scale Integration): 1,000 to 100,000 transistors per chip.
VLSI (Very Large-Scale Integration): Over 100,000 transistors per chip.
ULSI (Ultra-Large-Scale Integration): Over 1,000,000 transistors per chip.
VLSI Design Flow:
The VLSI design flow involves several steps to convert a high-level specification into a
physical IC. The primary stages include:
Specification: Define the functionality, performance, and physical requirements.
Design Entry: Create the initial design using hardware description languages (HDLs) like
VHDL or Verilog.
Functional Verification: Ensure the design meets functional specifications through simulation
and testing.
Synthesis: Convert the HDL code into a gate-level netlist.
Place and Route: Arrange the physical layout of the circuit on the chip and establish
connections.
Design for Testability (DFT): Incorporate features to facilitate testing of the final chip.
Physical Verification: Check for layout errors and ensure compliance with design rules.
Fabrication: Manufacture the IC using semiconductor fabrication processes.
Testing: Verify the functionality and performance of the fabricated IC.

VLSI Design Styles:

VLSI design can be categorized into several styles, each with its own advantages and
applications:
Full Custom Design:
Definition: The designer specifies every transistor and its connections, tailoring the design to
achieve optimal performance and efficiency.
Applications: Used in high-performance and specialized ICs like microprocessors and ASICs.
Semi-Custom VLSI Designs:
Definition: Utilizes pre-designed and pre-verified components like standard cells or gate
arrays.
Applications: Balances customization and time-to-market, suitable for a wide range of
applications including consumer electronics and automotive systems.

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Programmable ASIC Designs:
Definition: Uses configurable components like FPGAs (Field-Programmable Gate Arrays) or
CPLDs (Complex Programmable Logic Devices).
Applications: Provides flexibility and rapid prototyping, ideal for research, development, and
low-volume production.
These topics provide a comprehensive overview of VLSI, from its fundamental concepts to
its classification, design flow, and various design styles.
Basics of Boolean Algebra and Logic Gates
Boolean algebra is a mathematical framework used for analyzing and simplifying digital
circuits. It deals with binary variables and logical operations, making it fundamental to digital
electronics and VLSI design. The primary operations in Boolean algebra are AND, OR, and
NOT, which correspond to basic logic gates in digital circuits. These gates are the building
blocks of more complex digital systems, performing essential functions by manipulating
binary inputs to produce specific outputs.
Logic gates implement Boolean functions in hardware, enabling the construction of digital
circuits. Common gates include AND, OR, NOT, NAND, NOR, XOR, and XNOR, each
performing a unique logical operation. By combining these gates, designers can create
intricate circuits capable of performing complex computations and controlling digital devices.
Understanding Boolean algebra and logic gates is crucial for designing and optimizing digital
systems in VLSI.
Boolean Algebra is an algebra, which deals with binary numbers & binary variables. Hence,
it is also called as Binary Algebra or logical Algebra. A mathematician, named George Boole
had developed this algebra in 1854. The variables used in this algebra are also called as
Boolean variables.
The range of voltages corresponding to Logic ‘High’ is represented with ‘1’ and the range of
voltages corresponding to logic ‘Low’ is represented with ‘0’.
Postulates and Basic Laws of Boolean Algebra
In this section, let us discuss about the Boolean postulates and basic laws that are used in
Boolean algebra. These are useful in minimizing Boolean functions.
Boolean Postulates
Consider the binary numbers 0 and 1, Boolean variable x
and its complement x′
. Either the Boolean variable or complement of it is known as literal. The four possible
logical OR operations among these literals and binary numbers are shown below.

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 x+0=x
x+1=1
x+x=x
x + x’ = 1
Similarly, the four possible logical AND operations among those literals and binary numbers
are shown below.
x.1 = x
x.0 = 0
x.x = x
x.x’ = 0
These are the simple Boolean postulates. We can verify these postulates easily, by
substituting the Boolean variable with ‘0’ or ‘1’.
Note− The complement of complement of any Boolean variable is equal to the variable itself.
i.e., x′’=x.
Basic Laws of Boolean Algebra
Following are the three basic laws of Boolean Algebra.
 Commutative law
 Associative law
 Distributive law

Commutative Law
If any logical operation of two Boolean variables give the same result irrespective of the
order of those two variables, then that logical operation is said to be Commutative. The
logical OR & logical AND operations of two Boolean variables x & y are shown below
x+y=y+x
x.y = y.x
The symbol ‘+’ indicates logical OR operation. Similarly, the symbol ‘.’ indicates logical
AND operation and it is optional to represent. Commutative law obeys for logical OR &
logical AND operations.
Associative Law
If a logical operation of any two Boolean variables is performed first and then the same
operation is performed with the remaining variable gives the same result, then that logical
operation is said to be Associative. The logical OR & logical AND operations of three
Boolean variables x, y & z are shown below.

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 x + y+z = x+y+ z
x.y.z = x.y.z
Associative law obeys logical OR & logical AND operations.
Distributive Law
If any logical operation can be distributed to all the terms present in the Boolean function,
then that logical operation is said to be Distributive. The distribution of logical OR & logical
AND operations of three Boolean variables x, y & z are shown below.
x.y+z = x.y + x.z
x + y.z = x+y.x+z
Distributive law obeys logical OR and logical AND operations.
These are the Basic laws of Boolean algebra. We can verify these laws easily, by substituting
the Boolean variables with ‘0’ or ‘1’.
Logic gates:
Digital electronic circuits operate with voltages of two logic levels namely Logic Low and
Logic High. The range of voltages corresponding to Logic Low is represented with ‘0’.
Similarly, the range of voltages corresponding to Logic High is represented with ‘1’.
The basic digital electronic circuit that has one or more inputs and single output is known as
Logic gate. Hence, the Logic gates are the building blocks of any digital system. We can
classify these Logic gates into the following three categories.
 Basic gates
 Universal gates
 Special gates

Now, let us discuss the Logic gates come under each category one by one.
Basic Gates:
In earlier chapters, we learnt that the Boolean functions can be represented either in sum of
products form or in product of sums form based on the requirement. So, we can implement
these Boolean functions by using basic gates. The basic gates are AND, OR & NOT gates.

AND gate:
An AND gate is a digital circuit that has two or more inputs and produces an output, which is
the logical AND of all those inputs. It is optional to represent the Logical AND with the
symbol ‘.’.
The following table shows the truth table of 2-input AND gate.

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Here A, B are the inputs and Y is the output of two input AND gate. If both inputs are ‘1’,
then only the output, Y is ‘1’. For remaining combinations of inputs, the output, Y is ‘0’.
The following figure shows the symbol of an AND gate, which is having two inputs A, B and
one output, Y.

This AND gate produces an output Y𝑌, which is the logical AND of two inputs A, B.
Similarly, if there are ‘n’ inputs, then the AND gate produces an output, which is the logical
AND of all those inputs. That means, the output of AND gate will be ‘1’, when all the inputs
are ‘1’.
OR gate:
An OR gate is a digital circuit that has two or more inputs and produces an output, which is
the logical OR of all those inputs. This logical OR is represented with the symbol ‘+’.
The following table shows the truth table of 2-input OR gate.

Here A, B are the inputs and Y is the output of two input OR gate. If both inputs are ‘0’, then
only the output, Y is ‘0’. For remaining combinations of inputs, the output, Y is ‘1’.
The following figure shows the symbol of an OR gate, which is having two inputs A, B and
one output, Y.

This OR gate produces an output Y, which is the logical OR of two inputs A, B. Similarly, if

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there are ‘n’ inputs, then the OR gate produces an output, which is the logical OR of all those
inputs. That means, the output of an OR gate will be ‘1’, when at least one of those inputs is
‘1’.
NOT gate:
A NOT gate is a digital circuit that has a single input and single output. The output of NOT
gate is the logical inversion of input. Hence, the NOT gate is also called as inverter.
The following table shows the truth table of NOT gate.

Here A and Y are the input and output of NOT gate respectively. If the input, A is ‘0’, then
the output, Y is ‘1’. Similarly, if the input, A is ‘1’, then the output, Y is ‘0’.
The following figure shows the symbol of NOT gate, which is having one input, A and one
output, Y.

This NOT gate produces an output Y, which is the complement of input, A.

Universal gates:
NAND & NOR gates are called as universal gates. Because we can implement any Boolean
function, which is in sum of products form by using NAND gates alone. Similarly, we can
implement any Boolean function, which is in product of sums form by using NOR gates
alone.
NAND gate:
NAND gate is a digital circuit that has two or more inputs and produces an output, which is
the inversion of logical AND of all those inputs.
The following table shows the truth table of 2-input NAND gate.

Here A, B are the inputs and Y is the output of two input NAND gate. When both inputs are

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‘1’, the output, Y is ‘0’. If at least one of the input is zero, then the output, Y is ‘1’. This is
just opposite to that of two input AND gate operation.
The following image shows the symbol of NAND gate, which is having two inputs A, B and
one output, Y.

NAND gate operation is same as that of AND gate followed by an inverter. That’s why the
NAND gate symbol is represented like that.
NOR gate:
NOR gate is a digital circuit that has two or more inputs and produces an output, which is the
inversion of logical OR of all those inputs.
The following table shows the truth table of 2-input NOR gate

Here A, B are the inputs and Y is the output. If both inputs are ‘0’, then the output, Y is ‘1’. If
at least one of the input is ‘1’, then the output, Y is ‘0’. This is just opposite to that of two
input OR gate operation.

The following figure shows the symbol of NOR gate, which is having two inputs A, B and
one output, Y.

NOR gate operation is same as that of OR gate followed by an inverter. That’s why the NOR
gate symbol is represented like that.
Special Gates:
Ex-OR & Ex-NOR gates are called as special gates. Because, these two gates are special
cases of OR & NOR gates.
Ex-OR gate:
The full form of Ex-OR gate is Exclusive-OR gate. Its function is same as that of OR gate
except for some cases, when the inputs having even number of ones.
The following table shows the truth table of 2-input Ex-OR gate.

Here A, B are the inputs and Y is the output of two input Ex-OR gate. The truth table of Ex-

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OR gate is same as that of OR gate for first three rows. The only modification is in the fourth
row. That means, the output Yis zero instead of one, when both the inputs are one, since the
inputs having even number of ones.
Therefore, the output of Ex-OR gate is ‘1’, when only one of the two inputs is ‘1’. And it is
zero, when both inputs are the same.
Below figure shows the symbol of Ex-OR gate, which is having two inputs A, B and one
output, Y.

Ex-OR gate operation is similar to that of OR gate, except for few combinations
of inputs. That’s why the Ex-OR gate symbol is represented like that. The output of Ex-OR
gate is ‘1’, when odd number of ones present at the inputs. Hence, the output of Ex-OR gate
is also called as an odd function.
Ex-NOR gate
The full form of Ex-NOR gate is Exclusive-NOR gate. Its function is same as that of NOR
gate except for some cases, when the inputs having even number of ones.
The following table shows the truth table of 2-input Ex-NOR gate.

Here A, B are the inputs and Y is the output. The truth table of Ex-NOR gate is same as that
of NOR gate for first three rows. The only modification is in the fourth row. That means, the
output is one instead of zero, when both the inputs are one.
Therefore, the output of Ex-NOR gate is ‘1’, when both inputs are same. And it is zero, when
both the inputs are different.
The following figure shows the symbol of Ex-NOR gate, which is having two inputs A, B
and one output, Y.

Ex-NOR gate operation is similar to that of NOR gate, except for few combinations
of inputs. That’s why the Ex-NOR gate symbol is represented like that. The output of Ex-
NOR gate is ‘1’, when even number of ones present at the inputs. Hence, the output of Ex-
NOR gate is also called as an even function.
From the above truth tables of Ex-OR & Ex-NOR logic gates, we can easily notice that the
Ex-NOR operation is just the logical inversion of Ex-OR operation.
Concepts of Combinational and Sequential Circuits:
Combinational circuits are types of digital circuits where the output depends solely on the
current inputs, not on any previous inputs or states. These circuits perform specific logic
functions, such as addition or multiplexing, and are characterized by their stateless behavior.
Examples of combinational circuits include adders, multiplexers, encoders, and decoders. The
design and analysis of combinational circuits involve Boolean algebra and logic gate
manipulation to achieve the desired output for given inputs.

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Combinational circuits consist of Logic gates. These circuits operate with binary values. The
outputsof combinational circuit depends on the combination of present inputs. The following
figure shows the block diagram of combinational circuit.

This combinational circuit has ‘n’ input variables and ‘m’ outputs. Each combination of input
variables will affect the outputs𝑠.
In contrast, sequential circuits depend on both current inputs and previous states,
incorporating memory elements to store information. These circuits use flip-flops or latches
to maintain state information, allowing them to perform functions based on historical data.
Examples of sequential circuits include counters, shift registers, and finite state machines.
The behavior of sequential circuits is governed by clock signals, which synchronize state
transitions. Understanding both combinational and sequential circuits is essential for
designing robust and functional digital systems in VLSI.
The following figure shows the block diagram of sequential circuit.

This sequential circuit contains a set of inputs and outputs. The outputsof sequential circuit
depends not only on the combination of present inputs but also on the previous outputs.
Previous output is nothing but the present state. Therefore, sequential circuits contain
combinational circuits along with memory storageelements. Some sequential circuits may not
contain combinational circuits, but only memory elements.
Differences between ASICs and FPGAs in VLSI Design:
Application-Specific Integrated Circuits (ASICs) are custom-designed chips tailored for a
particular application or function. ASICs offer high performance, low power consumption,
and optimized silicon area since they are designed to meet specific requirements. However,
the design and fabrication of ASICs involve significant time and cost, making them less
suitable for applications requiring flexibility or rapid prototyping. ASICs are ideal for high-
volume production where performance and efficiency are critical.

Field-Programmable Gate Arrays (FPGAs), on the other hand, are reconfigurable chips that
can be programmed to perform various functions after manufacturing. FPGAs provide
flexibility and faster time-to-market, as they can be reprogrammed to adapt to changing
requirements or correct design errors. They are widely used for prototyping, research, and
applications needing frequent updates. While FPGAs typically consume more power and are
less optimized than ASICs, their versatility and ease of use make them valuable in many
VLSI design scenarios.
Overview of the Design Flow in VLSI Design:

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The VLSI design flow is a systematic process that transforms high-level specifications into a
physical integrated circuit. It begins with the specification phase, where the desired
functionality, performance, and constraints of the IC are defined. The design entry phase
follows, involving the creation of a high-level description of the circuit using hardware
description languages (HDLs) such as VHDL or Verilog. This high-level design is then
verified for functionality through simulations to ensure it meets the specified requirements.
Once verified, the design moves to the synthesis phase, where the HDL code is converted
into a gate-level netlist, representing the circuit in terms of logic gates. The place and route
phase follows, arranging the physical layout of the gates and interconnections on the chip.
Design for testability (DFT) techniques are incorporated to facilitate testing of the
manufactured IC. The final steps involve physical verification to check for layout errors and
compliance with design rules, fabrication to produce the IC, and testing to ensure the chip
functions correctly. This structured flow ensures a reliable and efficient transition from
concept to silicon in VLSI design.

PURPOSE OF HDLS AND OVERVIEW OF VERILOG

Role of Hardware Description Languages (HDLs) in VLSI Design:

Hardware Description Languages (HDLs) are specialized programming languages used to
describe the structure, behavior, and functionality of electronic circuits, particularly in VLSI
design. HDLs enable designers to model complex digital systems at various levels of
abstraction, from high-level functional descriptions to detailed gate-level implementations.
The primary advantage of using HDLs is their ability to simulate and verify the behavior of
digital circuits before actual hardware fabrication, thereby reducing design errors and
development time.
HDLs such as Verilog and VHDL (VHSIC Hardware Description Language) play a crucial
role in the VLSI design flow. They facilitate the creation of reusable and modular designs,
which can be easily modified and tested. These languages support concurrent execution,
which is essential for accurately modeling the parallel nature of digital circuits. Additionally,
HDLs allow for the integration of testbenches, enabling designers to simulate and validate
their designs under various conditions and scenarios.
For instance, consider the following simple Verilog module describing a 2-to-1 multiplexer:

In this example, the Verilog code specifies the functionality of a multiplexer, which selects
one of the two input signals (a or b) based on the selection input (sel) and outputs it as y.
Overview of Verilog Language:
Verilog is a widely-used HDL for modeling electronic systems, particularly in VLSI design.
It was developed in the mid-1980s and standardized as IEEE 1364 in 1995. Verilog supports
both behavioral and structural modeling, allowing designers to describe circuits at various
levels of abstraction, from high-level algorithms to detailed gate-level schematics. This
versatility makes Verilog suitable for a wide range of applications, including digital signal

Page | 11
processing, microprocessor design, and FPGA configuration.
One of the key features of Verilog is its ability to simulate the behavior of a digital circuit
before synthesis and implementation. This allows designers to verify the correctness and
performance of their designs early in the development process. Verilog also supports a rich
set of constructs for describing timing, concurrency, and synchronization, which are essential
for accurately modeling complex digital systems. Additionally, Verilog provides constructs
for specifying initial conditions, delays, and procedural code, which are useful for creating
testbenches and simulation models.
Consider the following example of a Verilog testbench for the previously defined 2-to-1
multiplexer:

This testbench initializes the inputs and applies different test vectors to verify the
multiplexer’s functionality.

Introduction to Verilog Syntax, Structure, Data Types, and Variables:

Verilog's syntax and structure are designed to resemble the C programming language, making
it relatively easy to learn for those with a background in software development. A Verilog
module, which is the basic building block of a Verilog design, consists of a module
declaration, a list of input and output ports, and internal declarations and statements that
describe the module's functionality.
The general structure of a Verilog module is as follows:

Verilog supports a variety of data types, including:

 Nets (e.g., wire): Used to represent connections between hardware elements.
 Registers (e.g., reg): Used to store values in sequential logic.
 Integers (e.g., integer): Used for arithmetic operations and loop indices.
 Real numbers (e.g., real): Used for modeling analog behavior.
Here's a table summarizing some common Verilog data types:

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Verilog also includes variables to represent inputs, outputs, and internal signals. These
variables can be scalars or vectors, and they can be assigned values using continuous
assignments or procedural blocks. For example, in the continuous assignment statement
assign y = a & b;, y is continuously driven by the logical AND of a and b.
In procedural blocks such as always or initial, variables are assigned values using procedural
assignments (=, <=). Here's an example of an always block used to describe a simple flip-
flop:

In this example, q is updated with the value of d on the rising edge of the clock (clk) or reset
to 0 on the falling edge of the reset signal. Understanding these basic concepts is essential for
effectively using Verilog in VLSI design.

IMPLEMENTING COMBINATIONAL CIRCUITS IN VERILOG

Implementation of Adders and Subtractors in Xilinx 14.7 ISE:

Implementing adders and subtractors in Xilinx 14.7 ISE involves creating Verilog modules
for these arithmetic circuits and synthesizing them using the Xilinx ISE software. The process
includes writing the Verilog code, simulating it to verify functionality, and then synthesizing
it to generate the FPGA configuration.
Step-by-Step Implementation:
Create a New Project:
Open Xilinx ISE and create a new project.
Set the project properties (e.g., target device, preferred HDL).
Verilog Code for the Adder:

Verilog Code for the Subtractor:

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Simulate the Modules:
Create a testbench to apply test vectors and verify the functionality of the adder and
subtractor.
Use the ISim simulator integrated with Xilinx ISE to run the simulation.
Synthesize the Design:
Run the synthesis process to convert the Verilog code into a netlist.
Check for any synthesis warnings or errors and resolve them.
Implement the Design:
Use the implementation tools in Xilinx ISE to place and route the design.
Generate the bitstream file for FPGA configuration.
Example Testbench for Adder:

Module Instantiation in Verilog:

Module instantiation in Verilog is the process of creating instances of a module within
another module, allowing for hierarchical design and reuse of code. This enables designers to
build complex systems by combining simpler sub-modules.
Syntax for Module Instantiation:

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Example of Module Instantiation:
Consider a simple design with a 2-to-1 multiplexer as a submodule:

Instantiate mux2to1 in a top-level module:

Table of Ports Mapping:

This hierarchical design approach simplifies complex system design and improves code
readability and reusability.
Design and Implementation of Multiplexers:
Multiplexers (MUX) are combinational circuits that select one of many inputs and direct it to
a single output based on control signals. Designing multiplexers in Verilog involves writing
the module to define the behavior and structure of the multiplexer.
module mux4to1 (
input wire [3:0] data,
input wire [1:0] sel,

Page | 15
 output wire y
);
assign y = sel[1] ? (sel[0] ? data[3] : data[2]) : (sel[0] ? data[1] : data[0]);
endmodule
Testbench for 4-to-1 Multiplexer:

Table of MUX Functionality:

The multiplexer directs the selected input to the output based on the selection lines.
Hands-on Exercises on Implementing Logic Functions in Verilog:
Hands-on exercises are crucial for mastering Verilog and understanding digital design
concepts. Implementing basic logic functions helps build a solid foundation in Verilog.
Exercise 1: Implementing an AND Gate
Write a Verilog module for a 2-input AND gate.

Testbench for AND Gate:

Page | 16
Exercise 2: Implementing a Full Adder

Write a Verilog module for a 1-bit full adder.

Testbench for Full Adder:

Table of Full Adder Functionality:

Page | 17
CONDITIONAL STATEMENTS IN VERILOG

Introduction to Conditional Statements Used in Verilog:

Conditional statements in Verilog are used to control the flow of execution based on certain
conditions. These statements are crucial for designing digital circuits that require decision-
making logic. The primary conditional statements in Verilog are if-else and case.
if-else Statements:
The if-else statement is used to execute a block of code if a specified condition is true. If the
condition is false, another block of code can be executed using the else clause. The syntax is
similar to that of traditional programming languages:
if (condition) begin
// Code to execute if condition is true
end else begin
// Code to execute if condition is false
end
Example:
always @(a or b or sel) begin
if (sel == 1) begin
y = a;
end else begin
y = b;
end
end

case Statements:
The case statement is used to select one of many blocks of code to execute based on the value
of a variable. This is particularly useful for implementing multiplexers, decoders, and state
machines.
case (expression)
value1: begin
// Code to execute for value1
end
value2: begin
// Code to execute for value2
end
default: begin
// Code to execute if no match
end

Page | 18
endcase

Example:
always @(sel or a or b or c or d) begin
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
2'b11: y = d;
default: y = 1'b0;
endcase
end

Implementing MUX Using if-else Conditional Statements

A multiplexer (MUX) can be implemented in Verilog using if-else statements to select one of
many input signals based on a control signal.

Example: 2-to-1 MUX Using if-else

module mux2to1_if (
input wire a,
input wire b,
input wire sel,
output reg y
);
always @(a or b or sel) begin
if (sel) begin
y = b;
end else begin
y = a;
end
end
endmodule

Testbench for 2-to-1 MUX:

module tb_mux2to1_if;
reg a, b, sel;
wire y;

mux2to1_if uut (
.a(a),
.b(b),
.sel(sel),
.y(y)
);
initial begin
a = 0; b = 0; sel = 0;

Page | 19
 #10 sel = 1;
#10 a = 1; sel = 0;
#10 b = 1; sel = 1;
#10 $finish;
end
endmodule

In this example, the if-else statement is used to assign the output y based on the value of the
selection input sel. If sel is 1, y is assigned the value of b; otherwise, y is assigned the value
of a.

Designing of Demultiplexers in Xilinx 14.7 ISE Using Case Statements

Demultiplexers (DEMUX) route a single input signal to one of many output lines based on
control signals. Implementing DEMUX in Verilog using case statements allows for efficient
and clear code.

Example: 1-to-4 Demultiplexer

module demux1to4 (
input wire din,
input wire [1:0] sel,
output reg [3:0] y
);
always @(din or sel) begin
case (sel)
2'b00: y = 4'b0001;
2'b01: y = 4'b0010;
2'b10: y = 4'b0100;
2'b11: y = 4'b1000;
default: y = 4'b0000;
endcase
end
endmodule

Testbench for 1-to-4 Demultiplexer:

module tb_demux1to4;
reg din;
reg [1:0] sel;
wire [3:0] y;

demux1to4 uut (
.din(din),
.sel(sel),
.y(y)
);
initial begin
din = 1;
sel = 2'b00;
#10 sel = 2'b01;
#10 sel = 2'b10;
#10 sel = 2'b11;

Page | 20
 #10 $finish;
end
endmodule

Implementing in Xilinx 14.7 ISE:

Create a New Project:

 Open Xilinx ISE and create a new project.
 Set the project properties (e.g., target device, preferred HDL).

Write the Verilog Code:

 Copy the demux1to4 module into a new Verilog file in the project.

Simulate the Design:

 Create a testbench file and simulate the demultiplexer to verify its functionality.
 Use the ISim simulator integrated with Xilinx ISE for simulation.

Synthesize the Design:

 Run the synthesis process to convert the Verilog code into a netlist.
 Check for any synthesis warnings or errors and resolve them.

Implement the Design:

 Use the implementation tools in Xilinx ISE to place and route the design.
 Generate the bitstream file for FPGA configuration.

Using case statements for demultiplexers ensures a clear mapping between the control signals
and the output lines, making the code easy to understand and maintain. This structured
approach also allows for efficient synthesis and implementation in FPGA designs.

DESIGNING OF ENCODER AND DECODER CIRCUITS IN VERILOG

Introduction to Encoders in Digital Electronics:
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to
the input, which is active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It
is optional to represent the enable signal in encoders.

4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block
diagram of 4 to 2 Encoder is shown in the following figure.

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at
the output. The Truth table of 4 to 2 encoder is shown below.

Page | 21
From Truth table, we can write the Boolean functions for each output as

A1=Y3+Y2
A0=Y3+Y1
We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure.

The above circuit diagram contains two OR gates. These OR gates encode the four inputs
with two bits.
Octal to Binary Encoder
Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to
binary encoder is nothing but 8 to 3 encoder. The block diagram of octal to binary Encoder is
shown in the following figure.

At any time, only one of these eight inputs can be ‘1’ in order to get the respective binary
code. The Truth table of octal to binary encoder is shown below.

From Truth table, we can write the Boolean functions for each output as

Page | 22
 A2=Y7+Y6+Y5+Y4
A1=Y7+Y6+Y3+Y2
A0=Y7+Y5+Y3+Y1
We can implement the above Boolean functions by using four input OR gates. The circuit
diagram of octal to binary encoder is shown in the following figure.

The above circuit diagram contains three 4-input OR gates. These OR gates encode the eight
inputs with three bits.

Drawbacks of Encoder
There is ambiguity, when all outputs of encoder are equal to zero. Because, it could be the
code corresponding to the inputs, when only least significant input is one or when all inputs
are zero.
If more than one input is active High, then the encoder produces an output, which may not be
the correct code. For example, if both Y3 and Y6 are ‘1’, then the encoder produces 111 at
the output. This is neither equivalent code corresponding to Y3, when it is ‘1’ nor the
equivalent code corresponding to Y6, when it is ‘1’.

So, to overcome these difficulties, we should assign priorities to each input of encoder. Then,
the output of encoder will be the binarycode corresponding to the active High inputs, which
has higher priority. This encoder is called as priority encoder.

Priority Encoder
A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. Here,
the input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this
case, even if more than one input is ‘1’ at the same time, the output will be the binary
code corresponding to the input, which is having higher priority.
We considered one more output, V in order to know, whether the code available at outputs is
valid or not.
If at least one input of the encoder is ‘1’, then the code available at outputs is a valid one. In
this case, the output, V will be equal to 1.
If all the inputs of encoder are ‘0’, then the code available at outputs is not a valid one. In this
case, the output, V will be equal to 0.
The Truth table of 4 to 2 priority encoder is shown below.

Page | 23
Use 4 variable K-maps for getting simplified expressions for each output.

The simplified Boolean functions are

A1=Y3+Y2
A0=Y3+Y2′Y1
Similarly, we will get the Boolean function of output, V as

V=Y3+Y2+Y1+Y0
We can implement the above Boolean functions using logic gates. The circuit diagram of 4 to
2 priority encoder is shown in the following figure.

The above circuit diagram contains two 2-input OR gates, one 4-input OR gate, one 2input
AND gate & an inverter. Here AND gate & inverter combination are used for producing a
valid code at the outputs, even when multiple inputs are equal to ‘1’ at the same time. Hence,
this circuit encodes the four inputs with two bits based on the priority assigned to each input.

Implementation of Decoders using Verilog:

Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines.
One of these outputs will be active High based on the combination of inputs present, when
the decoder is enabled. That means decoder detects a particular code. The outputs of the

Page | 24
decoder are nothing but the min terms of ‘n’ input variables lines, when it is enabled.
2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block
diagram of 2 to 4 decoder is shown in the following figure

One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’.
The Truth table of 2 to 4 decoder is shown below.

From Truth table, we can write the Boolean functions for each output as
Y3=E.A1.A0
Y2=E.A1.A0′
Y1=E.A1′.A0
Y0=E.A1′.A0′
Each output is having one product term. So, there are four product terms in total. We can
implement these four product terms by using four AND gates having three inputs each & two
inverters. The circuit diagram of 2 to 4 decoder is shown in the following figure.

Page | 25
Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input variables
A1 & A0, when enable, E is equal to one. If enable, E is zero, then all the outputs of decoder
will be equal to zero.
Similarly, 3 to 8 decoder produces eight min terms of three input variables A2, A1 & A0 and
4 to 16 decoder produces sixteen min terms of four input variables A3, A2, A1 & A0.

Comparators in Digital Circuits:

Comparators are digital circuits that compare two binary values and produce an output based
on the comparison. They are essential in a variety of applications, such as arithmetic
operations, data sorting, and decision-making processes. Comparators can be classified into
different types based on their functionality, including equality comparators and magnitude
comparators.
Types of Comparators:
Equality Comparator: Compares two binary numbers and checks if they are equal.
Magnitude Comparator: Compares the magnitude of two binary numbers and determines if
one is greater than, less than, or equal to the other.
Example: 2-bit Magnitude Comparator
A 2-bit magnitude comparator compares two 2-bit binary numbers (A and B) and produces
three outputs indicating if A is greater than, less than, or equal to B.

Verilog Code for 2-bit Magnitude Comparator

Page | 26
module comparator2bit (
input wire [1:0] a,
input wire [1:0] b,
output reg gt,
output reg lt,
output reg eq
);
always @(a or b) begin
if (a > b) begin
gt = 1;
lt = 0;
eq = 0;
end else if (a < b) begin
gt = 0;
lt = 1;
eq = 0;
end else begin
gt = 0;
lt = 0;
eq = 1;
end
end
endmodule

Testbench for 2-bit Magnitude Comparator:

module tb_comparator2bit;
reg [1:0] a, b;
wire gt, lt, eq;

comparator2bit uut (
.a(a),
.b(b),
.gt(gt),
.lt(lt),
.eq(eq)
);
initial begin
a = 2'b00; b = 2'b00; #10;
a = 2'b01; b = 2'b00; #10;
a = 2'b01; b = 2'b01; #10;
a = 2'b10; b = 2'b01; #10;
a = 2'b10; b = 2'b10; #10;
a = 2'b11; b = 2'b10; #10;
a = 2'b11; b = 2'b11; #10;
$finish;
end
endmodule

Page | 27
Encoders and decoders are fundamental digital circuits used for encoding and decoding
binary data. Encoders compress multiple input lines into fewer output lines, while decoders
expand binary inputs into multiple output lines. Comparators, on the other hand, compare
binary values and provide outputs indicating the relationship between the values.
Understanding these circuits and their implementation in Verilog is essential for digital
system design and application.

MULTIPLIERS, FLIP-FLOPS, LATCHES AND REGISTERS

Introduction to Multipliers in Digital circuits:

Multipliers are fundamental components in digital circuits, essential for performing
arithmetic operations. They are used extensively in digital signal processing, computer
graphics, and various other applications where mathematical calculations are necessary.
Multipliers take two binary numbers as input and produce their product as output.

Types of Multipliers:
Combinational Multipliers: These multipliers use combinational logic to produce the output
in a single clock cycle. They are fast but can be large and complex.
Sequential Multipliers: These use sequential logic, breaking the multiplication process into
smaller steps over multiple clock cycles. They are simpler and consume less area but are
slower than combinational multipliers.
Example: 2x2 Binary Multiplier

A 2x2 binary multiplier multiplies two 2-bit numbers, producing a 4-bit result. The truth table
below shows how the output is calculated.

In first method, cascade two latches in such a way that the first latch is enabled for every
positive clock pulse and second latch is enabled for every negative clock pulse. So that the
combination of these two latches become a flip-flop.

In second method, we can directly implement the flip-flop, which is edge sensitive. In this
chapter, let us discuss the following flip-flops using second method.

Page | 28
SR Flip-Flop
D Flip-Flop
K Flip-Flop

SR Flip-Flop
SR flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, SR latch operates with enable signal. The circuit diagram of SR flip-flop is shown
in the following figure.

This circuit has two inputs S & R and two outputs Qt & Qt’. The operation of SR flipflop is
similar to SR Latch. But, this flip-flop affects the outputs only when positive transition of the
clock signal is applied instead of active enable.
The following table shows the state table of SR flip-flop.

Here, Qt𝑡 & Qt+1𝑡+1 are present state & next state respectively. So, SR flip-flop can be used
for one of these three functions such as Hold, Reset & Set based on the input conditions,
when positive transition of clock signal is applied. The following table shows
the characteristic table of SR flip-flop.

Page | 29
By using three variable K-Map, we can get the simplified expression for next state, Qt+1. The
three variable K-Map for next state, Qt+1 is shown in the following figure.

The maximum possible groupings of adjacent ones are already shown in the figure.
Therefore, the simplified expression for next state Qt+1is

Q(t+1)=S+R′Q(t)
D Flip-Flop
D flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, D latch operates with enable signal. That means, the output of D flip-flop is
insensitive to the changes in the input, D except for active transition of the clock signal. The
circuit diagram of D flip-flop is shown in the following figure.

This circuit has single input D and two outputs Qt& Qt’. The operation of D flip-flop is
similar to D Latch. But, this flip-flop affects the outputs only when positive transition of the
clock signal is applied instead of active enable.

Page | 30
The following table shows the state table of D flip-flop.

Therefore, D flip-flop always Hold the information, which is available on data input, D of
earlier positive transition of clock signal. From the above state table, we can directly write the
next state equation as
Qt+1= D
Next state of D flip-flop is always equal to data input, D for every positive transition of the
clock signal. Hence, D flip-flops can be used in registers, shift registers and some of the
counters.
JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock
transitions or negative clock transitions. The circuit diagram of JK flip-flop is shown in the
following figure.

This circuit has two inputs J & K and two outputs Qt& Qt’. The operation of JK flip-flop is
similar to SR flip-flop. Here, we considered the inputs of SR flip-flop as S = J Qt’ and R
=KQtin order to utilize the modified SR flip-flop for 4 combinations of inputs.

The following table shows the state table of JK flip-flop.

Here, Qt & Qt+1are present state & next state respectively. So, JK flip-flop can be used for

Page | 31
one of these four functions such as Hold, Reset, Set & Complement of present state based on
the input conditions, when positive transition of clock signal is applied. The following table
shows the characteristic table of JK flip-flop.

By using three variable K-Map, we can get the simplified expression for next state,
Qt+1𝑡+1. Three variable K-Map for next state, Qt+1𝑡+1 is shown in the following figure.

The maximum possible groupings of adjacent ones are already shown in the figure.
Therefore, the simplified expression for next state Qt+1𝑡+1 is

Q(t+1)=JQ(t)′+K′Q(t)

SR Latch

SR Latch is also called as Set Reset Latch. This latch affects the outputs as long as the
enable, E is maintained at ‘1’. The circuit diagram of SR Latch is shown in the following
figure.

This circuit has two inputs S & R and two outputs Qt𝑡 & Qt𝑡’. The upper NOR gate has two

Page | 32
inputs R & complement of present state, Qt𝑡’ and produces next state, Qt+1𝑡+1 when enable,
E is ‘1’.

Similarly, the lower NOR gate has two inputs S & present state, Qt𝑡 and produces
complement of next state, Qt+1𝑡+1’ when enable, E is ‘1’.

We know that a 2-input NOR gate produces an output, which is the complement of another
input when one of the input is ‘0’. Similarly, it produces ‘0’ output, when one of the input is
‘1’.

 If S = 1, then next state Qt+1𝑡+1 will be equal to ‘1’ irrespective of present state,
Qt𝑡 values.
 If R = 1, then next state Qt+1𝑡+1 will be equal to ‘0’ irrespective of present state,
Qt𝑡 values.

At any time, only of those two inputs should be ‘1’. If both inputs are ‘1’, then the next state
Qt+1𝑡+1 value is undefined.

The following table shows the state table of SR latch.

Therefore, SR Latch performs three types of functions such as Hold, Set & Reset based on
the input conditions.

D Latch

There is one drawback of SR Latch. That is the next state value can’t be predicted when both
the inputs S & R are one. So, we can overcome this difficulty by D Latch. It is also called as
Data Latch. The circuit diagram of D Latch is shown in the following figure.

This circuit has single input D and two outputs Qt𝑡 & Qt𝑡’. D Latch is obtained from SR
Latch by placing an inverter between S amp;& R inputs and connect D input to S. That means
we eliminated the combinations of S & R are of same value.

Page | 33
  If D = 0 → S = 0 & R = 1, then next state Qt+1𝑡+1 will be equal to ‘0’ irrespective of
present state, Qt𝑡 values. This is corresponding to the second row of SR Latch state
table.
 If D = 1 → S = 1 & R = 0, then next state Qt+1𝑡+1 will be equal to ‘1’ irrespective of
present state, Qt𝑡 values. This is corresponding to the third row of SR Latch state
table.

The following table shows the state table of D latch.

Therefore, D Latch Hold the information that is available on data input, D. That means the
output of D Latch is sensitive to the changes in the input, D as long as the enable is High.

Different types of Shift registers:

The group of flip-flops, which are used to hold store the binary data is known as register.

If the register is capable of shifting bits either towards right hand side or towards left hand
side is known as shift register. An ‘N’ bit shift register contains ‘N’ flip-flops. Following are
the four types of shift registers based on applying inputs and accessing of outputs.

 Serial In − Serial Out shift register

 Serial In − Parallel Out shift register
 Parallel In − Serial Out shift register
 Parallel In − Parallel Out shift register
AD

Serial In − Serial Out SISO Shift Register

The shift register, which allows serial input and produces serial output is known as Serial In –
Serial Out SISO shift register. The block diagram of 3-bit SISO shift register is shown in the
following figure.

This block diagram consists of three D flip-flops, which are cascaded. That means, output of
one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are

Page | 34
synchronous with each other since, the same clock signal is applied to each one.

In this shift register, we can send the bits serially from the input of left most D flip-flop.
Hence, this input is also called as serial input. For every positive edge triggering of clock
signal, the data shifts from one stage to the next. So, we can receive the bits serially from the
output of right most D flip-flop. Hence, this output is also called as serial output.

Example

Let us see the working of 3-bit SISO shift register by sending the binary information “011”
from LSB to MSB serially at the input.

Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000. We can
understand the working of 3-bit SISO shift register from the following table.

The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000. Here, the
serial output is coming from Q0. So, the LSB 1 is received at 3rd positive edge of clock and
the MSB 0is received at 5th positive edge of clock.

Therefore, the 3-bit SISO shift register requires five clock pulses in order to produce the valid
output. Similarly, the N-bit SISO shift register requires 2N-1 clock pulses in order to shift ‘N’
bit information.

Serial In - Parallel Out SIPO Shift Register

The shift register, which allows serial input and produces parallel output is known as Serial In
– Parallel Out SIPOshift register. The block diagram of 3-bit SIPO shift register is shown in
the following figure.

This circuit consists of three D flip-flops, which are cascaded. That means, output of one D
flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous
with each other since, the same clock signal is applied to each one.

Page | 35
In this shift register, we can send the bits serially from the input of left most D flip-flop.
Hence, this input is also called as serial input. For every positive edge triggering of clock
signal, the data shifts from one stage to the next. In this case, we can access the outputs of
each D flip-flop in parallel. So, we will get parallel outputs from this shift register.

Example

Let us see the working of 3-bit SIPO shift register by sending the binary information “011”
from LSB to MSB serially at the input.

Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000. Here,
Q2& Q0are MSB & LSB respectively. We can understand the working of 3-bit SIPO shift
register from the following table.

The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000. The
binary information “011” is obtained in parallel at the outputs of D flip-flops for third
positive edge of clock.

So, the 3-bit SIPO shift register requires three clock pulses in order to produce the valid
output. Similarly, the N-bit SIPO shift register requires N clock pulses in order to shift ‘N’ bit
information.

Parallel In − Serial Out PISO Shift Register

The shift register, which allows parallel input and produces serial output is known as Parallel
In − Serial Out PISOshift register. The block diagram of 3-bit PISO shift register is shown in
the following figure.

Page | 36
This circuit consists of three D flip-flops, which are cascaded. That means, output of one D
flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous
with each other since, the same clock signal is applied to each one.

In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset
Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage
to the next. So, we will get the serial output from the right most D flip-flop.

Example

Let us see the working of 3-bit PISO shift register by applying the binary
information “011” in parallel through preset inputs.

Since the preset inputs are applied before positive edge of Clock, the initial status of the D
flip-flops from leftmost to rightmost will be Q2Q1Q0=011. We can understand the working
of 3-bit PISO shift register from the following table.

Here, the serial output is coming from Q0𝑄0. So, the LSB 11 is received before applying
positive edge of clock and the MSB 00 is received at 2 nd positive edge of clock.

Therefore, the 3-bit PISO shift register requires two clock pulses in order to produce the valid
output. Similarly, the N-bit PISO shift register requires N-1 clock pulses in order to shift
‘N’ bit information.AD

Page | 37
Parallel In - Parallel Out PIPO Shift Register

The shift register, which allows parallel input and produces parallel output is known as
Parallel In − Parallel Out PIPOshift register. The block diagram of 3-bit PIPO shift register
is shown in the following figure.

This circuit consists of three D flip-flops, which are cascaded. That means, output of one D
flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous
with each other since, the same clock signal is applied to each one.

In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset
Enable to 1. We can apply the parallel inputs through preset or clear. These two are
asynchronous inputs. That means, the flip-flops produce the corresponding outputs, based on
the values of asynchronous inputs. In this case, the effect of outputs is independent of clock
transition. So, we will get the parallel outputs from each D flip-flop.

Example

Let us see the working of 3-bit PIPO shift register by applying the binary
information “011” in parallel through preset inputs.

Since the preset inputs are applied before positive edge of Clock, the initial status of the D
flip-flops from leftmost to rightmost will be Q2Q1Q0=011. So, the binary
information “011” is obtained in parallel at the outputs of D flip-flops before applying
positive edge of clock.

Therefore, the 3-bit PIPO shift register requires zero clock pulses in order to produce the
valid output. Similarly, the N-bit PIPO shift register doesn’t require any clock pulse in
order to shift ‘N’ bit information.

Page | 38
IMPLEMENTING A SMALL DIGITAL CIRCUIT USING VERILOG

Step-by-Step Guide to Implementing a 4-bit Binary Adder in Verilog Using Xilinx ISE:

Step 1: Setting Up the Project

Open Xilinx ISE:
Launch Xilinx ISE software.
Create a new project: File -> New Project.
Enter a project name, location, and specify it as an HDL project. Click Next.

Set the Project Properties:

Select the appropriate FPGA family, device, and package. For example, select Spartan-6,
XC6SLX9, TQG144.
Click Next and Finish to create the project.

Step 2: Writing Verilog Code

Add Verilog Source Files:
Right-click on the project name in the Hierarchy pane and select New Source.
Choose Verilog Module and name it adder4bit. Click Next.
Define the module with inputs a, b, cin and outputs sum, cout. Click Next and then Finish.

Design Module (adder4bit.v):

Verilog code for the 4-bit binary adder:
module adder4bit (
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] sum,
output cout
);
assign {cout, sum} = a + b + cin;
endmodule

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Testbench File:
Right-click on the project name and select New Source.
Choose Verilog Test Fixture and name it tb_adder4bit. Click Next.
Select adder4bit as the module to associate with the test fixture. Click Next and Finish.
Testbench Module (tb_adder4bit.v):
Verilog code for the testbench:
`timescale 1ns / 1ps
module tb_adder4bit;
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire cout;
adder4bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize inputs
a = 4'b0000; b = 4'b0000; cin = 0;
#10; // Wait for 10 ns

// Apply test vectors

a = 4'b0101; b = 4'b0011; cin = 0;
#10;
a = 4'b1111; b = 4'b0001; cin = 1;
#10;
a = 4'b1001; b = 4'b0110; cin = 0;
#10;

// End simulation
$finish;

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 end
endmodule

Step 3: Simulating the Design

Run Simulation:
Select the testbench file (tb_adder4bit.v).
Right-click and select Simulate Behavioral Model.

Verify Waveforms:
The ISim simulator will launch.
Observe the simulation waveforms to verify that the outputs (sum and cout) match the
expected values for the given inputs (a, b, and cin).

Step 4: Synthesizing the Design

Run Synthesis:
Select the main module (adder4bit.v).
Right-click and select Synthesize - XST.
Check the synthesis report for any warnings or errors.

Optimize Design:
If necessary, optimize the design parameters based on the synthesis report to meet the target
device specifications.

Step 5: Implementing the Design

Run Implementation:
After synthesis, right-click on the module and select Implement Design.

Generate Bitstream:
After implementation, right-click on the module and select Generate Programming File.
This will create a bitstream file for programming the FPGA.

Step 6: Documenting the Project

Example Verilog Code and Testbench

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adder4bit.v
module adder4bit (
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] sum,
output cout
);
assign {cout, sum} = a + b + cin;
endmodule

tb_adder4bit.v
`timescale 1ns / 1ps
module tb_adder4bit;
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire cout;
adder4bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize inputs
a = 4'b0000; b = 4'b0000; cin = 0;
#10; // Wait for 10 ns

// Apply test vectors

a = 4'b0101; b = 4'b0011; cin = 0;
#10;
a = 4'b1111; b = 4'b0001; cin = 1;

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 #10;
a = 4'b1001; b = 4'b0110; cin = 0;
#10;
// End simulation
$finish;
end
endmodule
This guide provides a detailed approach to implementing a 4-bit binary adder using Verilog
and Xilinx ISE, from writing the code to simulating and synthesizing the design.

Introduction to Counters
Synchronous Counters:
Synchronous counters are digital circuits in which all flip-flops are clocked simultaneously
by a common clock signal. Each flip-flop in a synchronous counter is triggered at the same
time, which eliminates the propagation delay that occurs in asynchronous counters. This
synchronized operation ensures that the output changes state simultaneously, making
synchronous counters faster and more reliable in high-speed applications. Synchronous
counters can be designed to count in binary, decimal, or any arbitrary sequence.

Example: 4-bit Synchronous Binary Counter

module synchronous_counter (
input clk,
input reset,
output reg [3:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 4'b0000;
else
count <= count + 1;
end
endmodule

Page | 43
Asynchronous Counters
Asynchronous counters, also known as ripple counters, are digital circuits where each flip-
flop is triggered by the output of the preceding flip-flop, rather than a common clock signal.
The first flip-flop is triggered by the external clock, and subsequent flip-flops are triggered by
the previous flip-flop's output. This design leads to a propagation delay, as each flip-flop
must wait for the previous one to toggle before it can change state. Asynchronous counters
are simpler and require fewer components but are slower and less accurate than synchronous
counters due to the accumulated delays.

Example: 4-bit Asynchronous Binary Counter

module asynchronous_counter (
input clk,
input reset,
output reg [3:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 4'b0000;
else begin
count[0] <= ~count[0];
count[1] <= count[0] ? ~count[1] : count[1];
count[2] <= (count[0] & count[1]) ? ~count[2] : count[2];
count[3] <= (count[0] & count[1] & count[2]) ? ~count[3] : count[3];
end
end
endmodule

Finite State Machine (FSM)

Mealy State Machine
A Mealy state machine is a type of finite state machine where the output depends on both the
current state and the current inputs. This characteristic allows for quicker reactions to input

Page | 44
changes, as the output can change immediately in response to an input signal without waiting
for a state transition. Mealy machines are typically used in applications where the output
needs to respond rapidly to input changes.

Example: Mealy FSM for Sequence Detector

module mealy_fsm (
input clk,
input reset,
input in,
output reg out
);
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

always @(posedge clk or posedge reset) begin

if (reset)
state <= S0;
else
state <= next_state;
end

always @(state or in) begin

case (state)
S0: begin
if (in) next_state = S1;
else next_state = S0;
out = 0;
end
S1: begin
if (in) next_state = S2;
else next_state = S0;
out = 0;
end
S2: begin

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 if (in) next_state = S2;
else next_state = S0;
out = 1;
end
default: begin
next_state = S0;
out = 0;
end
endcase
end
endmodule

Moore State Machine

A Moore state machine is a type of finite state machine where the output depends solely on
the current state, not on the input. This characteristic simplifies the design and often makes
the FSM more robust, as outputs change only during state transitions. Moore machines are
typically used in applications where output stability and predictability are more important
than responsiveness to input changes.

Example: Moore FSM for Sequence Detector

module moore_fsm (
input clk,
input reset,
input in,
output reg out
);
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;

always @(posedge clk or posedge reset) begin

if (reset)
state <= S0;
else
state <= next_state;

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 end
always @(state or in) begin
case (state)
S0: begin
if (in) next_state = S1;
else next_state = S0;
out = 0;
end
S1: begin
if (in) next_state = S2;
else next_state = S0;
out = 0;
end
S2: begin
if (in) next_state = S3;
else next_state = S0;
out = 0;
end
S3: begin
if (in) next_state = S3;
else next_state = S0;
out = 1;
end
default: begin
next_state = S0;
out = 0;
end
endcase
end
endmodule

ASM Charts
Algorithmic State Machine (ASM) charts are graphical representations of state machines,
providing a clear and concise way to design and visualize the operation of complex sequential

Page | 47
circuits. An ASM chart consists of three primary components: state boxes, decision boxes,
and conditional output boxes.

State Boxes: Represent states in the FSM. Each state box lists the state name and any actions
that occur while in that state.
Decision Boxes: Represent decision points based on input conditions. Each decision box
branches to different states or outputs depending on the input values.
Conditional Output Boxes: Represent actions that occur based on specific conditions while
transitioning between states.
ASM charts help in the systematic design of FSMs by clearly showing the sequence of states
and transitions based on inputs and conditions. They are especially useful for designing
complex state machines where textual descriptions might become cumbersome.

Example ASM Chart for a Simple Sequence Detector:

State S0:
Output: out = 0
If in = 0 -> State S0
If in = 1 -> State S1

State S1:
Output: out = 0
If in = 0 -> State S0
If in = 1 -> State S2

State S2:
Output: out = 1
If in = 0 -> State S0
If in = 1 -> State S2
In this example, the ASM chart helps visualize the states and transitions of a simple sequence
detector FSM.

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CONCLUSION
The VLSI Design with Verilog project provided an immersive, hands-on experience in digital
circuit design and FPGA implementation. Through a series of structured tasks, participants
gained a comprehensive understanding of fundamental VLSI concepts and practical skills in
using Verilog for hardware description. The project covered essential topics such as
designing basic digital circuits, writing Verilog code, simulating and synthesizing designs
using Xilinx ISE, and optimizing hardware implementations for FPGA.

Key achievements of this project include:

Understanding VLSI Basics: Participants learned the core principles of VLSI design,
including Boolean algebra, logic gates, combinational and sequential circuits, and the
differences between ASICs and FPGAs.
Proficiency in Verilog: Participants developed proficiency in Verilog, including its syntax,
data types, conditional statements, and module instantiation. They also practiced designing
various digital circuits such as adders, subtractors, multiplexers, encoders, and decoders.
Practical Implementation: The hands-on exercises in Xilinx ISE allowed participants to
synthesize, simulate, and verify their designs. This practical implementation reinforced
theoretical knowledge and provided insight into the real-world applications of VLSI design.
Collaborative Learning: Conducting reviews and discussions on implemented designs
fostered a collaborative learning environment. Peer feedback and guidance helped refine the
designs and broaden the understanding of best practices in digital circuit design.

Inferences & Recommendations:

Inferences
Several important inferences can be drawn from this project:
Importance of Simulation and Verification: Simulation and verification are critical steps in
the VLSI design process. They ensure that the design functions correctly before proceeding to
synthesis and implementation, thereby reducing the likelihood of costly errors in later stages.
Optimization Trade-offs: The project highlighted the trade-offs involved in optimizing
VLSI designs. Participants learned to balance factors such as speed, area, and power
consumption to achieve the best overall design performance for the target application.

Page | 49
Skill Development: The project significantly enhanced participants' technical skills in digital
design and programming with Verilog. These skills are essential for pursuing careers in VLSI
design and related fields.
Real-World Relevance: The project demonstrated the real-world relevance of VLSI design
principles and tools. By working on practical implementations, participants gained insight
into how digital circuits are designed and tested in the industry.

Recommendations
Based on the experiences and outcomes of this project, several recommendations can be
made for future iterations and for those pursuing further expertise in VLSI design:
Expanded Project Scope: Future projects could include more complex design challenges,
such as designing complete subsystems or integrating multiple modules. This would provide
a deeper understanding of system-level design and integration.
Advanced Topics: Incorporate advanced topics such as low-power design techniques, timing
analysis, and verification methodologies like formal verification and functional coverage.
These areas are crucial for modern VLSI design.
Tool Diversification: Encourage exploration of other industry-standard tools and platforms,
such as Synopsys, Cadence, and ModelSim, in addition to Xilinx ISE. This diversification
will broaden the toolset and adaptability in the industry.
Industry Collaboration: Establish collaborations with industry partners to provide real-
world projects and exposure to current trends and challenges in VLSI design. This could
include guest lectures, workshops, and internships.
Capstone Projects: Implement capstone projects where participants design and implement a
complete digital system, from specification to FPGA implementation. This comprehensive
experience would synthesize their learning and demonstrate their capabilities to potential
employers.
Soft Skills Development: Emphasize the development of soft skills such as teamwork,
communication, and project management. These skills are vital for successful collaboration
in professional settings.
In conclusion, the VLSI Design with Verilog project has been a valuable learning experience,
equipping participants with essential skills and knowledge for a career in digital design and
VLSI. By building on this foundation with continued learning and practical application,
participants can advance their expertise and make significant contributions to the field of
VLSI design.AD

Page | 50
 LITERATURE SURVEY

The Proposed ALU Architecture performs the addition, Subtraction and

multiplication operations and additionally decoder and multiplexer is combined.
Adder, Subtractor and multiplier of various designs have already addressed and
worked on by numerous authors in a literature of reversible designs with the aim
of creating the large optimal and better performance circuits [7-10].

In the year 2011[7], S. Sultana optimised this 8-bit Adder/Subtractor

architecture. They used twenty-fivereversible logic gates, seventeen trash
outputs, and seventythree quantum rate while designing this circuit.

An improved 4-bit Adder/Subtractor [8] circuit was put out in the 2013
publication by, Shefali Mamataj. 8reversible gates with a mix of Feynman and
DKG gates were used in that design. 11 trash output signals were produced by
this design.in 2015, Harpreet Singh [9] suggested a novel reversible logic gate
under the moniker WG gate. This paper presents the construction of a
comprehensive Adder/Subtractor circuit utilising with a one gate and two trash
outputs and a quantum rate of seven. In [10] the adder/subtractor design is
proposed usingreversible gates. The author concluded as the design have a 2n
trash outputs and seven n quantum rates.

In 2018 [11], the HNG gate based 8 bit and 4 bit array multiplier is proposed.
The author proposed the multiplier design using HNG gate based Ripple Carry
Adder and the multiplier design have a 28 gates, 5249 nW power, 231 µm2area.

In 2017 [12], the sixteen bit reversible arithmetical and logical unit is design by
the author Swaminathan. The ALU design contains adder and subtractor and the
multiplexer is used as a control unit. The design is reduced the power 0.312mw
to 0.261mw and delay 2.266ns to 1.907ns and the ALU design parameters are
compared with irreversible ALU design.

In 2021[13], the novel ALU design is provided by the author

BehrouzSafaiezadeh using quantum dot cellular automata. The proposed design
performs 6 Arithmetic
operations and 10 logical operations. The design is reduced the area 0.92 µm2
to 0.62 µm2and Quantum rate 21 to 16 compared to other existing designs and
Vedic multiplier design[14] is designed using Quantum Dot cellular automata.

In 2011 [15], the author approach the two different ALU designs and
comparison of the ALU parameters also provided. The Quantum rate is reduced

Page | 51
compared to the other existing designs.

PHOTOS&VIDEOLINKS

Link:https://internships.technotran.in

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