VLSI CIRCUIT DE

~- SIGN LABORATORY (ECELiG PC20) 2024

Exp ~o: 6

Title - Study of CMOS Sequential Circuit using Pspice\TCAD

Objective:

I. Design a OFF
2. Observer its transient response
Tools used:

Personal Computer

Tanner Tools v 16.2

• Schematic-Edit (S-Edit)

• Wave- Edit (W-Edit)

• Tanner Spice (T-Spice)

Theory:

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state
information. A flipcflop is a bi stable multi vibrator. It is the basic storage element in sequential logic. Flip-
flops and latches are a fundamental building block of digital electronics systems used in computers,
communications, and many other types of systems.
Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state,
and such a circuit is described as sequential logic . When used in a finite-state machine, the output and next
state depend not only on its current input, but also. on its current state (and hence, previous inputs). It can
also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference
timing signal.
Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the
simple ones are commonly called latches. The word latch is mainly used for storage elements, while clocked
devices are described asjlip-jlops. A latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is,
when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type
(posi ti ve go ing or negative going) of clock edge.
In seque ntial logic circuits the output signals ts determined by the current inputs as well as the
previously app li ed input variables. Fig. I shows a sequential circuit consisting of a combinational

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 2024
VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20)

circuit and a memory block in the feedback loop. All basic latches, flip-flops. registers and memory
elements used in digital systems fall into this category.

OVT1
A
OUT2
8 Comt,lnallonal
C Logic
I---
~

.....-

---- Memorf
.___

~--- ···--· -----· --

Fig.I.Sequential circuit consisting of a combinational logic block and a memory

(~)

Fig.2. Classification of logic circuits based on their temporal behaviour

SR Flip-Flop: Fig.3 shows a SR latch using two NAND2 gates. The state of the circuit can be
changed by pulling the set input or reset input to zero. The gate level schematic and the corresponding
block diagram representation of the NAND-based SR latch are shown in Fig.3.Note that a
NANO-based SR latch responds to an active low input signals. The truth table of the NAND
SR latch is also shown in Fig.3. The same approach used in the timing analysis of the NOR-based
SR-latches can be applied to NAND-based SR-latches.

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VLSI CIRCUIT DESIG N LABO RATORY [ECEUGPC20) 2024

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:~ s

·=§=·
A
SAIAICh
~

~\l A

~~ s
0
0
R
0
I
o..•• o.. ••
1
1
I
0
Operation
not a llowcd
set

~
I 0 0 I reset
I I 0.. 0.. ho ld

r~ Fig.3.Circuit, Block Diagram & Truth Table of SR Latch

r$ s

~
~ R

r'
rl Fig.4.Circuit of SR Flip-Flop

r·> Voo

~
~~=,
Q
Q

~
r,-;.
,-~ Fig.S.Circ uit of CMOS SR Flip-Flop

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 VLSI CIRCUIT DESIGN LABORATORY [ECEliGPC20) 2024

A CMOS SR latch built with two 2-input !\A~D gates is shown at figure.

The basic memory cell comprised of two back-to-back C.\1OS inverters is seen. The circuit responds to
active low Sand R inputs. Ifs goes too (while R = I). Q goes high, pulling Q' low and the latch enters Set
state S=0, Q == I (if R == I). Jf R goes to 0 (while S == J), Q' goes high, Jf R goes to O (while S = I),o· goes
Hold state requires bolh Sand R 10 be high_
high, pulling Q low and the latch is Reset R=0, Q' == I (if S = I).
S == R =0 if not allowed, as it would result in an indeterminate state.

Fig.6. Timing diagram of CMOS SR Flip-Flop

From fig.4 NOR-based SR latch with a clock added. The latch is responsive to inputs S and R only when
CLK is high. When CLK is low, the latch retains its current state. Timing diagram shows the level-sensitive
nature of the clocked SR latch. When S goes high during positive CLK, on leading CLK edge after changes
in S & R during CLK low time. A positive glitch in S while CLK is high, When R goes high during positive
CLK.

JK Flip-Flop: All simple and clocked SR latch circuits examined to this point suffer from the common
problem of having a not-allowed input combination i.e. their state becomes indeterminate when
both S and R are activated at the same time. This problem can be overcome by adding two
feedback lines from the outputs to the inputs, resulting in the JK latch. Fig.7 shows an all NANO
implementation of the JK latch with active high inputs, and the corresponding block diagram representation.
Tht: J and K inputs in this circuit correspond to the set and reset inputs of the basic SR latch. When the
clock is active, the latch can be set with the input combination (J=" I ", K="0"), and it can be
reset with the input combination (J="0", K=" I"). If both inputs are equal tologic"0", the latch preserves its
current state. If both inputs are equal to logic " !"during the active clock phase, the latch simply
switches it,; state due 10 the feedback . Thus, the JK latch does not have a not-allowed input
combination. As in other clocked latch circuits, the JK latch will hold its current state when CLK=''0".
Thi: opi.:ration of the clocked JK latch is summarized in Table. I

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~
J

I~
K

[w K

r~ Fig.7. NAND implementation ofthc .JK Flip-Flop

I'1~ J
0
K
0
Q.
0
I
Q.
I
0
s
I
I
R
I
I
Q....
0
I
Q... ,
I
I
Opamoa
Hold

0 I 0 I I I 0 l Reset

~ I 0 0
I 0
I 0
I 0
l
0
l 0
0
I
Set

~~3
I 0 I I l
I I 0
I
I
0
0
I
I
0
I
0
0
l
Toggle
I
~
-- -- ~ -

Table.I. Truth Table of the JK Flip-Flop

~
r' CK
I

~
~~ 0 a

r,~ J

r-w
1r-: Fig.8.Circuit of CMOS JK Flip-Flop

1---
r:-:-.;
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VLSI CIRCUIT DE 2024
- SIG N LABORATORY (ECE UGPC20)

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· .
D. Flip-Flop Cir CUI·1:- D- Iatch stores a logic level. Th is is often called 1-b.11 register or del~y li1 J>-- llop. Ii has
Smgle data input D and two outputs: Q and Q. A D-latch is implemented, at the gate level by simply

f\l utilizing a NOR-based S-R latch, connecting D to input S. and connect

When CLK goes high, Dis transmitted to output Q (and o· to Q' ).When
ing D' to input R with an inverter.
CLK goes low, the latch retains its

h previous state. The gate leve l representation of the D-latch is si mply obtaine
d by modifying the docked
output Q assumes the value of

,~
~
NOR-based SR latch circuit. It can be seen from Fig. that the
the input D when the clock is active (i.e. for CK=··1 '} When the
output wiJI simply preserve its state. Thus, the CK input acts as
clock signal goes to zero. the
an enable signal which allows data

1~ to be accepted into the D-latch .

~
D
Q

~
I Q

~
~
~
rr, Fig.9. NOR implem entatio n of the D Flip-Flop

Voo

,,~
~
D

r1-~ flg. JO.Circ uit of C.\10S D flip-flo p

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~ 2024
VLSI CIRCUIT DESIGN LABORATORY (EC EUGPC20)

'1
~
Procedure:

1. Open S-Edit window.

~ 2. Go to File ➔ New ➔ New design

~
3. Go to Cell ➔ New View
4. Add libraries file to the New Cell.

~ 5. Instance the devices by using appropriate library files .

6. Save the design and setup the simulation.

~ 7. Run design and observe waveforms.

I" Tanner Spice Code:

~J

'J
r~
********* Simulation Settings - General Section*********

.include "E:\Tanner Model Files\Tanner\tanner models\ami0S.md"

r~
,,
~
*************** Subcircuits *****************

.subckt cmos_inverter_invl In Out Gnd Vdd

MNMOS_ 1 Out In Gnd 0 NMOS W=2.Su L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

,~,~
r~~ MPMOS_l Out In Vdd Vdd PMOS W=Su L=250n AS=4.Sp PS=l 1.8u AD=4 .Sp PD= l 1.8u

.ends

,~ .subckt \!AN D2 AB Out Gnd Vdd

rr MNMOS_ I Out/\ N_ l 0 NMOS W=2u L=2 50n AS=l.8p PS=S.8u AD=l.8p PD= S.8u

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~ VLSI CIRCUIT DES IGN LABORATORY (ECEUG PC20) 2024

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~
~
\il\~tOS_2 N_ l B Gnd 0 NMOS W=2u L=250n AS= l.8p PS=S. 8u AD- I.Sp PD=S.8u

MPMOS_ l Out A Vdd Vdd PMOS W=2.Su L=250n AS=2.25p PS=6.8u /\D=2.25 p PD=6.8u

MPMOS_:! Out B Vdd Vdd PMOS W=2. 5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

~ .ends

~
~ ***** Top Level *****

f'l Xinvl - I D N- 3 Gnd Vdd cmos-inverter- invl

X1\AND2_ 1 D CLK N_ l Gnd Vdd NAND2

~ XNAND2_2 N_ I QB Q Gnd Vdd NAND2

~ Xl\AND2_3 CLK N_3 N_2 Gnd Vdd NAND2

rw
,~ X~AND2_4 Q N_2 QB Gnd Vdd NAND2

VVI Vdd Gnd DC 5

r'r-·l VV2 CLK Gnd PULSE(0 5 0 In In 5.5n 13n)

VV3 D Gnd PULSE(0 5 In In In 4n !On)

r~ ~
~
.PRINT V(CLK)

.PRINT V(D)

.PR.INT V(Q)

.PRINT V(QB)

t~
f~
,-1•
u+uo o Simulati on Settings - Analysis Section*********
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• • •• • • ••

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 2024
VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20)

Exp No: 7

Title - Study ofRing Oscillator

Objective:

1. Design a 3 stage oscillator

2. Observe its oscillation frequency
Tools used:

Personal Computer

Tanner Tools v 16.2

• Schematic-Edit (S-Edit)
• Wave- Edit (W-Edit)
• Tanner Spice (T-Spice)
Procedure:

I. Open S-Edit window.

2. Go to File ➔ New ➔ New design
3. Go to Cell ➔ New View
4. Add libraries file to the New Cell.
S. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.

-l
r~
I

r-~
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I ..
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''I' VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20) 2024

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Schematic Diagram:
~
~
11
~
"v
"}
Fig. Three Stage Ring Oscillator Circuit

Tanner Spice Code: '

********* Simulation Settings - General Section*** ******

.include "E:\Tanner Model Files\Tanner\tanner models\ami0S.md"

************** * Subcircuits *****************

.subckt cmos_inverter_in vl In Out Gnd Vdd

\INMOS_ l Out In Gnd 0 NMOS W=2.Su L=250n AS=2.25p PS=6.8u AD=2.2Sp PD=6 .8u

MPMOS_ l Out In Vdd Vdd PMOS W=Su L=250n AS=4.S p PS=l 1.8u AD=4.Sp PD= t I. Su

.ends

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~ VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20) :!024

t\i ..... Top Level • •• 0

,~
j\l
Xinvl _ l N_3 N_ I Gnd Vdd cmos_inverte r_invl

Xinvl _2 N_ l N_2 Gnd Vdd cmos_inverter_invl

r~ Xinv I _3 N_2 N_3 Gnd Vd<l cmos_inverter_inv 1

'"
VV l Vdd Gnd DC S

r~ .PRINT V(N_3)

~
********* Simulation Settings - Analysis Section *********
~
.tran IOp Sn UIC
.,. ._~
,-..~
********* Simulation Settings - Additional SPICE Commands *********
r--~
I
r-~ .end

r-1) Output responses:

-~ Discussion
1 J Oscillation frequency, f = l/(2*n*tp)
i"-~ \ =number of stage

I """- Tp= propagation delay

~
I
~
I
~
I
I
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VLSI CIRCUIT DESIG N LABORATORY [ECEUGPC20) 2024

Exp No: 8

Title - Programming Technique using VHDL

Objective: To Design Full Adder and JK fliJrflop Using VHDL & Implementation Using FPGA

Tools used:

Personal Computer

Xilinx ISE I0.1

Theory:

Electronic design automation (EDA or ECAD) is a category of software tools for designing electronic
systems such as printed circuit boards and integrated circuits. The tools work together in a design flow that
chip designers use to design and analyze entire semiconductor chips.

IDesign-CAD-Foundry Interfaces I
Proprietary Design Tools
and Libraries

Design : Chip
Foundry i-..:::'------ ----1Cente r : Users
I

Back-end Front-end
CAD Tools CAD Tools

CAD Tools
' - - - - - ~ Vendor 1 - - - - - - - - '

Fig.I. Design-CAD-Foundry Interfaces

HDL is a formal language that is used to design, synthesize, simulate, and model logic circuits. There are
two popular HDL languages: VHDL and Verilog. VHDL is mostly used by academics, whereas Verilog is
used by Industry personnel. Both VHDL and Verilog are IEEE (Institute of Electrical and Electronic
Engineers) standards.

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VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20) 2024

In 1986, VHDL was proposed as an IEEE standard. It went through a number of revisions and changes until
it was adopted as the IEEE 1076 standard in December 1987.

VHDL is an acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High
Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system
at many levels of abstraction ranging from the algorithmic level to the gate level. The digital system can also
be described hierarchically. Timing can also be explicitly modelled in the same description.

The VHDL language can be regarded as an integrated merger. The language has the following basic
constructs:

Sequential language

+
Concurrent language

Net-list language

Timing specifications

Waveform generation language

n
VHDL

The hardwure abstraction has two views:

• External
• lntemul
To des<.: ri bc an entity VHDL provides five different types of primary constructs, called Design Units. They
arc

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~1.sl CTru)JIT DESI.Qi UBO?.ATOZ'I (ECaGK'lfJ}

I . &.tity ~

2. Arclri1tacre bod-1

3. Conf~ ~

4. Padagt: dtclaratioo

An entity is modelled using an entity declaration and at least one arclritecrure body. The emi1y dedautioo
dticribes the external tli...""W of the emity. for aamp)e. the input and ompci signal names.

Etrtity

A VHDL entity specifies the name of the entity. ihe ports of the entity, and entily-relared infomlation. All
designs are created using one or more entities.

Let's take a look at a simple entity example:

ENTITY mux IS

PORT (a, b, c, d: N BIT;

sO, s l: IN BIT;

x: OUT BIT);

E~Dmux;

The architecture body contains the internal description of the entity, for example, as a set of interconnected
compom.-nts that represents the structure of the entity. Architecture contain5 the statements that model the
behaviour of the entity. Each style of representation can be specified in a different architecture body or
mixed within a single architecture body. There are four different VHDL modelling styles of the architecture:

• Structural
• Behavioural
• Dataflow
• \-f ixed

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VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20) 2024

Architectures

ARCHITECTURE dataflow OF mux IS

SIGNAL select: fNTEGER;

BEGfN

select<= 0 WHEN s0= '0' AND sl= '0' ELSE

I WHEN s0= 'I' AND sl= '0' ELSE

2 WHEN sO= '0' AND sl= 'I' ELSE

3·
'
X <= a AFTER 0.5 NS WHEN select= 0 ELSE

b AFTER 0.5 NS WHEN select= 1 ELSE

c AFTER 0.5 NS WHEN select= 2 ELSE

a AFTER 0.5 NS;

END dataflow;

The keyword ARCHITECTURE signifies that this statement describes architecture for an entity. The
architecture name is DAT AFLOW.

A configuration declaration is used to create a configuration for an entity. It specifies the binding of one
architecture body from the many architecture bodies that may be associated with the entity. It may also
specify the bindings of components used in the selected architecture body to other entities. An entity may
have any number of different configurations.

A package declaration encapsulates a set of related declarations such as type declarations, subtype
declarations, and subprogram declarations that can be shared across two or more design units.

A package body contains the definitions of subprograms declared in a package declaration.

r
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VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC 20) 2024

Circuits / Block Diagram:-

Entity
Hardware Model
abstraction )
of a dig~al
system

Architecture bodies

Fig.2. An entity and its model

IHDL-Based Design Flow I

!
Spcc1fica11oos + Constrwnts

Code Organi=alion Choice

Behavioral Description in HDL

Archilft•ctural Choicr

RT- Level Description in HDL

u,gic lmplt!mmlution Choice

Ga~Nerlist

Plaumttnl and Rau.ting Choictt

'
Fig.3. HDL based Design Flow

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 2024
VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20)

Design AmlysiJ

Design Spccific.ition

t-- - ---vesi·gn lmplemCDtation using HD1~---- ,

Syn1bcsis

Simublion

Tlll1ing Analysis

Place& Roule

Extrac1ion

Vcrifica1ion

Fig.4.Digital design flow

This is a very crucial step in digital design where the design functionality

is stated. This step involved stating in definite terms the performance of the chip. Hardware Description
Language is used to run the simulations.

Synthesis-It forms the fundamentals of Logic Synthesis using EDA tools. Standard Cell Library is the
collection of such building blocks which comprises

most of the digital designs. After the RTL simulation, the HDL, code is taken as input by Synthesis Tool and
converted to Gate level. At this stage that the digital design becomes dependent on the fabrication process.
At the end of this stage, we have the logic circuit i.e. in terms of gates and memories. The output of
synthesis is a gate level netlist.

Simulation-After the netlist is generated as part of synthesis, this netlist is simulated to verify the
fi.mctionality of this gate level implementation of design.

Timing Analysis- RTL and Gate Level simulation doesn't take into account the physical time delay in
signal propagation from one device to another and through the device. This time delay is dependent on the
fabrication process adopted.

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'
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VLSI CIRCUIT DESIGN LABORATORY [ECEUGPC20)
2024

implemented at semiconductor layout b ·cl.

Place & Route-This is the actual stage where the design
~ Semiconductor layout has to follow certain design rules
to lay devices at semiconductor level.

tic capacitances and resistances associated with

Extraction- Once the layout is made; there always is parasi
/l the design.Due to these factors it becomes very much
important to extract these devices from layout and

check the design for performance and functionality.

I& Verification- Verification would either be the tape out
stage of the chip or the stage where design is again
modification. It verifies the extracted view of the chip
~ taken back through the same flow for optimization or
for performance and functionality.
J',J

~ Procedure:

rams >Engineering Software >

~
Start ISE from the Start menu by selecting Start >Prog

r~ Xilinx !SE I0.1 >Project Navigator.

Creating a New Project

rJ A project in ISE is a collection of all files necessary

To create a new project:
to create and download a design to the selected devic
e.

re) I. Select File > New Project.

t name 'CJRCUIT' in the Project name fie ld. You
rcJ 2. In the New Project Wizard dialog box, enter the projec
can browse to the desired directory using the browse
button next to the Project Location field.

r~ 3. Use the pull-down arrow to select HDL from the Top-L

evel Module Type field. Click Next.

dialog box, use the pull-down arrow to select the

r:~ 4. In the New Project Wizard Device and Design Flow

Value for each Property Name. Click in the field

Change the values as follows :

• Device Family: Spartan3

to access the pull down list.

• Devin:: xc3•;5 U

• Pac b gc: FCi 32U

• Sp,cd Grad, : -4

• Synth esi~ Tool: XST (VI IO U Verilo g)

• Simulatur: ISi: Si111ul ator (VIID U Verilo g)

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~ VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20) 2024

~
~
• Preferred Language: VHDL

Click Next

~ 5. This will open a New Project dialog box. Click on 'New Source' to create a new source to be added to the
project.
~ 6. In the New Source dialog box select VHDL Module from the list. Name the file as ADDER in the File

~ Name field. Verify that the Add to project check box is selected.

Next write the ports name a, b, c, sum and carry and select the direction (in or out).
~ Click Next! Then Finish!

~ Select Yes

~
Click Next.

Click Next.
~ Finish it.

t) Write the expressions of sum and carry inside the ADDER.vhd file in between begin and end
Behavioral.Expressions are:
eJ sum <= a xor b xor c;

carry <= (a and b) or (band c) or (c and a);

Save the file

Next go to the Source and select Sources for Implementation> select the file ADDER-Behavioral.

Next go to the Processes below and run the Check Syntax, View Synthesis report and View RTL Schematic
simultaneously.

Show the RTL (Resistor-Transistor Logic) Schematic

Show the internal logic ckt. by double clicking on the block.

Show the logic diagram of carry.

For simulation go to the Project> New Source

Select Test Bench Waveform and give a tile name as like test. Then click Next

3 Click !\ext.

3
DEPARTM ENT OF ELECTRON ICS AND COMMUNICATION ENGINEERING
~ ALIAH UNIVERSITI
IIA/27, New Town, Kolkata - 700 160
53
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~ VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20) 2024

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Finish it.

As full adder is a combinational circuit for this select the Combinational (or internal clock).

~ Finish it

~ Select the inputs (a ,b, c) according to the truth table of the adder ckt. and Save it.

~
For check output go to the source and select Sources for Behavioral Simulation and select the test bench
waveform file test(test.tbw).

~ Next go to the Processes below and run the Simulation Behavioral Module.

~
Check the output waveform of full adder ckt.

For hardware implementation go to the Project > New Source

~ Select Implementation Constraints File and give file name as like test. Click Next

eJ Click Finish

For write the port code go to the source and select Sources for Implementation and select the user
)J constraints file test.ucf(test.ucf).

For generate a text file run the Edit Constraints(Text) under the Processes.
)_J
Write the ucf on the text file. The codes are:

NET "a" LOC = "P21";

NET "b" LOC = "P27";

NET "c" LOC = "P29";

NET "sum" LOC = "P20";

> NET "carry" LOC = "P26";

-3 Save it

Next go to the Processes and run the Implement Design

1\cxt run the Generate Programming File

ls;c xt run the Configure Target Device. Before run the Configure Target Device always keep power on of
thl:
3 Hardware kit.

3
DEPARTM ENT OF ELEC IRONICS /\ND COMMUNICATION ENGINEERING
ALIAH UNIVERSITY
IIA/ 27, New [own, Kolkat a / 00 160
54
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~ VLSI CIRCUIT DESIGN LABORATORY (ECEUGPC20) 2024

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Finish it.

There will be opened two Assign New Configuration File window. Close the first window.

~ Next open the adder.bit file on the second window of the Assign New Configuration File.

~ Select the device or processor which has been connected to the hardware. Here it is FPGA, xc3s50.

~
Next Apply > OK

Wright click on the Processor name (xc3s50) and run the Program
(; It will show the Program Succeeded

~ Schematic Diagram:

~
q

t) CLK

)J K

Re set _ b a r

Fig : Schematic

VHDL Code:

library IEEE;

use IEEE.STD_LOGIC_l 164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jkOipOop is

Port ( j .k,clk, reset_bar: in std_logic ;

q : inout std_logic);

enJ jktl ipOup:

DEPART MENT OF ELECT RONICS AND CO MMUN ICATION ENGI NEERING

AL IAH UN IVERSITY
IIA/27, New fa wn , Kolka t a - 700 160
55
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~ VLSI CIRCUIT DESIGN LABORATORY lECEUG PC20) 2024

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architecture Behavioral of jkflipflop is

begin

~ process(clkj,k,reset_bar)

11 begin

~
if(reset_bar='O') then q<='O';

elsif (clk'event and elk=' I') then

!J if j='O' and k=' I' then q<='O';

~ elsif j=' I' and k='O' then q<=' I ';

elsifj='l' and k=' l' then q<=not q;

~ end if;

~ end if;

end process;
•J
end Behavioral;
~

Output responses:

Discussion

Dl_.>/\K l M[N r or EL(( rHONICS /IND COMMUNIC/ITION ( NGIN((RING

11' I/\H lJN IVERSI fY
IIA/21 rJew I own, i<ol.Jta /00 160
5£,

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