Ministry of Higher Education

Nile Higher Institute For ‫وزاره التعليم العالي‬

Engineering & Technology ‫معهد النيل العالي للهندسة والتكنولوجيا‬
Communication & Electronics ‫قسم هندسة االتصاالت وااللكترونيات‬
Department

Academic Year: 2024-2025

Second Semester

Integrated Circuit Design

Report

Power dissipation in digital circuits

DR: Rehab Mahmoud

Eng: Heba Salah

Group Members

Ahmed Mohamed Ismail 200037

Ahmed Samir Soliman 200096
Mohamed Gamal Abd Elgwad 200049
Ahmed Desoky Gaffer 180149
Mohamed Ashraf Sadat Zater 200044
Ministry of Higher Education
Nile Higher Institute For ‫وزاره التعليم العالي‬
Engineering & Technology ‫معهد النيل العالي للهندسة والتكنولوجيا‬
Communication & Electronics ‫قسم هندسة االتصاالت وااللكترونيات‬
Department

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1. Introduction

Power dissipation in digital circuits has become a critical concern, especially with
the growth of portable electronics, high-performance computing, and ultra-dense
integrated circuits. As technology scales down and operating frequencies increase,
managing power consumption is vital for battery life, heat management, and
overall system reliability.
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2. Types of Power Dissipation in Digital Circuits

Digital circuits mainly consume power in the following forms:

2.1 Dynamic Power

Dynamic power is consumed when the circuit switches states (0 to 1 or 1 to 0). It

includes:

Switching Power (Capacitive Load): Power consumed to charge and discharge the
load capacitance during transitions. It is calculated as:

P_{dynamic} = \alpha C_L V_{dd}^2 f

= activity factor

= load capacitance

= supply voltage

= clock frequency

Short-Circuit Power: Occurs during input transitions when both NMOS and PMOS
transistors are momentarily conducting, allowing current to flow directly from the
Ministry of Higher Education
Nile Higher Institute For ‫وزاره التعليم العالي‬
Engineering & Technology ‫معهد النيل العالي للهندسة والتكنولوجيا‬
Communication & Electronics ‫قسم هندسة االتصاالت وااللكترونيات‬
Department

supply to ground.

2.2 Static (Leakage) Power

This is the power consumed even when the circuit is not switching. It arises due to:

Subthreshold Leakage: Current that leaks through a transistor even when it is

turned off, increasing with technology scaling and lower threshold voltages.

Gate Oxide Leakage: Caused by electron tunneling through ultra-thin gate oxides
in modern transistors.

Junction Leakage: Leakage current from reverse-biased diodes formed between the
source/drain and substrate.

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3. Sources of Power Dissipation

The main contributors to power dissipation in digital circuits are:

1. Dynamic Switching Activity, which is heavily influenced by the clock

frequency, supply voltage, and how often transistors switch states.

2. Short-Circuit Current, which results from both PMOS and NMOS transistors
being briefly on at the same time during logic transitions.

3. Leakage Currents, especially prominent in submicron technologies, caused by

subthreshold conduction, gate tunneling effects, and reverse-biased diode leakage.

4. Power Lost in Interconnects, due to parasitic capacitances that require charging

and discharging during signal transitions.

5. Clock Networks, which consume a large portion of the total dynamic power due
to their high activity rate and wide reach across the chip.
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Ministry of Higher Education
Nile Higher Institute For ‫وزاره التعليم العالي‬
Engineering & Technology ‫معهد النيل العالي للهندسة والتكنولوجيا‬
Communication & Electronics ‫قسم هندسة االتصاالت وااللكترونيات‬
Department

4. Power Analysis in CMOS Circuits

CMOS technology is preferred for its low static power consumption. However, as
transistors shrink and operating frequencies rise, both dynamic and leakage power

become significant.

4.1 Power in a CMOS Inverter

When a CMOS inverter switches states, dynamic power is consumed due to

charging and discharging of the output node. Although static power was negligible
in older technologies, it has become a major concern in modern nanoscale devices
due to increased leakage.

4.2 Effect of Technology Scaling

As supply voltage decreases to save power, transistor threshold voltages also

decrease, leading to a significant rise in leakage power. This creates a trade-off
between dynamic power savings and increased static power.
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5. Techniques for Power Reduction

5.1 Circuit-Level Techniques

Transistor Sizing: Adjusting the size of transistors to balance speed and

capacitance.

Voltage Scaling: Reducing supply voltage to decrease dynamic power

quadratically.

Power Gating: Turning off power to unused circuit blocks to eliminate leakage.

5.2 Logic-Level Techniques

Clock Gating: Disabling the clock signal to inactive parts of the circuit.
Ministry of Higher Education
Nile Higher Institute For ‫وزاره التعليم العالي‬
Engineering & Technology ‫معهد النيل العالي للهندسة والتكنولوجيا‬
Communication & Electronics ‫قسم هندسة االتصاالت وااللكترونيات‬
Department

Operand Isolation: Preventing unnecessary switching in logic blocks.

Multi-Threshold CMOS (MTCMOS): Using high-threshold transistors in non-

critical paths to reduce leakage.

5.3 Architectural Techniques

Dynamic Voltage and Frequency Scaling (DVFS): Adjusting voltage and

frequency based on workload.

Parallelism and Pipelining: Processing data in parallel or in stages to reduce the

need for high frequencies.

Adaptive Body Biasing: Dynamically changing transistor threshold voltages using

body biasing.

5.4 Physical Design Techniques

Optimized Placement and Routing: Reducing wire length and capacitance.

Use of Low-Capacitance Materials: Minimizing dynamic power due to

interconnect charging.

3D Integration: Stacking dies vertically to shorten interconnects and lower power.

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6. Power Estimation and Tools

Power estimation can be done at various stages:

At the RTL level, using early power estimation tools.

At the gate level, using precise tools like Synopsys PrimeTime PX or Cadence
Voltus.

Thermal analysis is also crucial to ensure the heat generated by power

consumption can be effectively dissipated.
Ministry of Higher Education
Nile Higher Institute For ‫وزاره التعليم العالي‬
Engineering & Technology ‫معهد النيل العالي للهندسة والتكنولوجيا‬
Communication & Electronics ‫قسم هندسة االتصاالت وااللكترونيات‬
Department

7. Case Study: Power Consumption in a 5nm Mobile Processor

In a modern 5nm mobile SoC, total power consumption can reach around 3 watts.
Of this, approximately 70% is dynamic power, 25% is leakage power, and 25% of
the dynamic portion comes from the clock distribution network. The chip utilizes
DVFS, aggressive power gating, and deep sleep modes to manage energy
consumption efficiently.

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8. Conclusion

Power dissipation is a key design challenge in digital circuits. With advanced

technologies increasing performance demands and reducing transistor sizes,
managing both dynamic and leakage power is critical. Through a combination of
circuit-level, architectural, and physical design techniques, significant power
savings can be achieved while maintaining performance and reliability.