Aim: Study of BPSK transmitter & receiver using suitable hardware setup/kit.

Objective : To study concept of BPSK Generation and Reception

Apparatus: 1. PSK Generator / Receiver kit Kashtronica
2. DSO, Dual Channel, CRO60 MHz

Theory:
BPSK (also sometimes called PRK, Phase Reversal Keying, or 2PSK) is the simplest form of phase
shift keying (PSK). It uses two phases which are separated by 180° and so can also be termed 2-
PSK. It does not particularly matter exactly where the constellation points are positioned, and in
this figure they are shown on the real axis, at 0° and 180°. This modulation is the most robust of all
the PSKs since it takes the highest level of noise or distortion to make the demodulator reach an
incorrect decision. It is, however, only able to modulate at 1 bit/symbol (as seen in the figure) and
so is unsuitable for high data-rate applications.
In the presence of an arbitrary phase-shift introduced by the communications channel, the
demodulator is unable to tell which constellation point is which. As a result, the data is often
differentially encoded prior to modulation.

BPSK is functionally equivalent to 2-QAM modulation.

This yields two phases, 0 and π. In the specific form, binary data is often conveyed with the following
signals:

for binary "0"

 for binary "1

Where fc is the frequency of the carrier-wave.

Hence, the signal-space can be represented by the single basis function

where 1 is represented by and 0 is represented by . This assignment is, of course,

arbitrary.

This use of this basis function is shown at the end of the next section in a signal timing diagram.
The topmost signal is a BPSK-modulated cosine wave that the BPSK modulator would produce.
The bit-stream that causes this output is shown above the signal (the other parts of this figure are
relevant only to QPSK).

BIT ERROR RATE

The bit error rate (BER) of BPSK in AWGN can be calculated as:

or
Since there is only one bit per symbol, this is also the symbol error rate.Sometimes this is known as
quaternary PSK, quadriphase PSK, 4-PSK, or 4-QAM. (Although the root concepts of QPSK and 4-QAM are
different, the resulting modulated radio waves are exactly the same.) QPSK uses four points on the
constellation diagram, equispaced around a circle. With four phases, QPSK can encode two bits per symbol,
shown in the diagram with gray coding to minimize the bit error rate (BER) — sometimes misperceived as
twice the BER of BPSK.

The mathematical analysis shows that QPSK can be used either to double the data rate compared witha
BPSK system while maintaining the same bandwidth of the signal, or to maintain the data-rate of
BPSK but halving the bandwidth needed. In this latter case, the BER of QPSK is exactly the same as
the BER of BPSK - and deciding differently is a common confusion when considering or describing
QPSK.
Given that radio communication channels are allocated by agencies such as the Federal
Communication Commission giving a prescribed (maximum) bandwidth, the advantage of QPSK
over BPSK becomes evident: QPSK transmits twice the data rate in a given bandwidth compared to
BPSK - at the same BER. The engineering penalty that is paid is that QPSK transmitters and receivers
are more complicated than the ones for BPSK. However, with modern electronics technology, the
penalty in cost is very moderate.
As with BPSK, there are phase ambiguity problems at the receiving end, and differentially encoded
QPSK is often used in practice. The following diagram is BPSK receiver

Procedure:-

1] Connect O/P of pattern Gen to OR Gate.

2] Connect O/P of OR gate to I/P of transmitter i.e.(i/p of MULT. Block).
3] Connect O/P of MULT Block i.e. BPSK O/P to I/P of 1496 Sq. ckt. 4]
Connect O/P of 1496 Sq. ckt to I/P of B.P. Filter.
5] Connect O/P of BP Filter to I/P of %2 N/W.
6] Connect O/P of %2 N/W to I/P1 of phase comparator.
7] Connect BPSK O/P to I/P2 of phase comparator.
8] Switch on the power supply.
9] Observe Signal‘s at different test points together with I/P bit pattern.
10] Observe filter O/P & COMP. Block O/P. The O/P of COMP. Block is receiver detected O/P.

Conclusion:
Aim: Study of Baseband receiver performance in presence of Noise using suitable
hardware setup/kit.

Objective:To study a matched filter and its error probability calculation.

Apparatus: Matched Filter kit, Connecting probes.

THEORY: Data transmission system using binary encoding transmits sequence of 1,

0. these bits may be represented in number of ways. In PSK system we transmit in
phase sine wave for logic 1 & 180 degree out of phase wave for logic 0. When this
data is received it is corrupted by noise & there is finite probability that receiver will
make an error in determining logic 1 & logic 0. To reduce the probability of error
we use the concept of co-relaters or matched filter as optimum filter. In matched filter
we integrate input data for one bit period. At the end of integration if output is more
than certain level we come to know that bit is logic 1 or logic 0. It is instructive to
note that integrator filters signal & noise such that signal voltage varies linearly with
time & noise increases more slowly.
In the circuit 8-bit data is given to parallel to serial converter. Bit duration of
this data can be varied by basic clock output. Signal coming out of parallel to serial
converter is fed to PSK Generator. Amplitude of output of PSK Generator can be
varied by using nearby pot. Now we have not used any filter after PSK gen. so noise
generated by multiplication process is there with the desired PSK signal. Now this
PSK signal is fed to the receiver.
Output of filter is fed to serial to parallel converter. Output of receiver can be
observed on LED‘s provided on the panel.

Procedure:
1. Switch on the power supply.
2. Observe clock output on CRO & connect it to i/p of control block.
3. Set bit pattern as 00100101 using dip switch. ―1‖on the switch is LSB.
When s/w is to on position o/p is ―1‖.
4. Observe o/p of p/s block on CRO Measure bit period by varying pot
nearby clock. Make bit period maximum.
5. Connect o/p of p/s block to i/p of PSK gen. Observe o/p of PSK gen.
6. Keep pot nearby PAK gen. to such a position that o/p of PAK gen. will
be 500 mVp-p in amplitude
7. Observe the o/p of noise gen. o/p & set min. amplitude (i.e. 0V).
8. Connect o/p of noise gen. to i/p2 of adder block & PSK generator O/P
to i/p 1 adderblock.
 9. Connect O/P of adder block to i/p of matched filter observe the o/p of matched
filter
10. Keep S/W above receiver latch to LE
11. Observe O/P on LEDs the same data should be at o/p.
12. Now go on varying clock frequency slowly increase the level, every
time measure the bit period. Observe at what bit period 1st error comes.
Also observe that if you increase amplitude of PSK gen. error vanishes.
13. By keeping pot of amplitude of PSK generator to lowest position & by
varying clock period measure no. of errors vs bit period. To observe
stable readings make switch
14. above receiver latch to ground position. For particular bit period take
no of readings by moving this s/w from LE to ground.
15. Plot the graph of bit period Vs error probability.
16. In 8 bits if one bit is in error then error probability is 12.5%. If we
increase no. of bits more accurate results are obtained
Conclusion:
Aim: Study of Error Control Coding using suitable hardware setup/kit.

Objective: To study hamming Code for error detection and Correction.

Apparatus: Digital Multimeter, SB 224 Error Detection Kit (Make: SINCOM)

Theory: Error Detection and Correction

In mathematics, computer science, telecommunication, and information theory, error detection and
correction has great practical importance in maintaining data (information) integrity across noisy
channels and less-than-reliable storage media.

Definitions of error detection and error correction:

• Error detection is the ability to detect the presence of errors caused by noise or other impairments
during transmission from the transmitter to the receiver.

• Error correction is the additional ability to reconstruct the original, error-free data. There are two
basic ways to design the channel code and protocol for an error correcting system:

• Automatic repeat-request (ARQ): The transmitter sends the data and also an error detection code,
which the receiver uses to check for errors, and requests retransmission of erroneous data. In many
cases, the request is implicit; the receiver sends an acknowledgement (ACK) of correctly received
data, and the transmitter re-sends anything not acknowledged within a reasonable period of time.

• Forward error correction (FEC): The transmitter encodes the data with an error correcting code
(ECC) and sends the coded message. The receiver never sends any messages back to the
transmitter. The receiver decodes what it receives into the "most likely" data. The codes are
designed so that it would take an "unreasonable" amount of noise to trick the receiver into
misinterpreting the data.

It is possible to combine the two, so that minor errors are corrected without retransmission, and
major errors are detected and a retransmission requested. The combination is called hybrid
automatic repeat-request.

Error detection schemes

In telecommunication, a redundancy check is extra data added to a message for the purposes of
error detection. Several schemes exist to achieve error detection, and generally they are quite
simple. All error detection codes (which include all error-detection-and-correction codes) transmit
more bits than were in the original data. Most codes are "systematic": the transmitter sends a fixed
number of original data bits, followed by fixed number of check bits (usually referred to as
redundancy in the literature) which are derived from the data bits by some deterministic algorithm.
The receiver applies the same algorithm to the received data bits and compares its output to the
received check bits; if the values do not match, an error has occurred at some point during the
transmission. In a system that uses a "nonsystematic" code, such as some raptor codes, data bits are
transformed into at least as many code bits, and the transmitter sends only the code bits.

Parity schemes
A parity bit is an error detection mechanism that can only detect an odd number of errors. The
stream of data is broken up into blocks of bits, and the number of 1 bits is counted. Then, a "parity
bit" is set (or cleared) if the number of one bits is odd (or even). (This scheme is called even parity;
odd parity can also be used.) If the tested blocks overlap, then the parity bits can be used to isolate
the error, and even correct it if the error affects a single bit: this is the principle behind the
Hamming code.

There is a limitation to parity schemes. A parity bit is only guaranteed to detect an odd number of
bit errors (one, three, five, and so on). If even numbers of bits (two, four, six and so on) are flipped,
the parity bit appears to be correct, even though the data is corrupt.

Hamming distance based checks

If we want to detect d bit errors in an n bit word we can map every n bit word into a bigger n+d+1
bit word so that the minimum Hamming distance between each valid mapping is d+1. This way, if
one receives a n+d+1 word that doesn't match any word in the mapping (with a Hamming distance
x <= d+1 from any word in the mapping) it can successfully detect it as an erroneous word. Even
more, d or fewer errors will never transform a valid word into another, because the Hamming
distance between each valid word is at least d+1, and such errors only lead to invalid words that are
detected correctly. Given a stream of m*n bits, we can detect x <= d bit errors successfully using
the above method on every n bit word. In fact, we can detect a maximum of m*d errors if every n
word is transmitted with maximum d errors.

Error correction: Automatic repeat request

Automatic Repeat-request (ARQ) is an error control method for data transmission which makes use
of error detection codes, acknowledgment and/or negative acknowledgement messages and
timeouts to achieve reliable data transmission. An acknowledgment is a message sent by the
receiver to the transmitter to indicate that it has correctly received a data frame. Usually, when the
transmitter does not receive the acknowledgment before the timeout occurs (i.e. within a reasonable
amount of time after sending the data frame), it retransmits the frame until it is either correctly
received or the error persists beyond a predetermined number of retransmissions.

A few types of ARQ protocols are Stop-and-wait ARQ, Go-Back-N ARQ and Selective Repeat
ARQ. Hybrid ARQ is a combination of ARQ and forward error correction.
Error-correcting code

An error-correcting code (ECC) or forward error correction (FEC) code is redundant data that is
added to the message on the sender side. If the number of errors is within the capability of the code
being used, the receiver can use the extra information to discover the locations of the errors and
correct them. Since the receiver does not have to ask the sender for retransmission of the data, a
back-channel is not necessary in forward error correction, so it is suitable for simplex
communication such as broadcasting. Error correcting codes are used in computer data storage, for
example CDs, DVDs and in dynamic RAM. It is also used in digital transmission, especially
wireless communication, since wireless communication without FEC often would suffer from
packet-error rates close to 100%, and conventional automatic repeat request error control would
yield a very low good put.

Hamming Code - Error Detection and Error Correction

 The hamming code technique, which is an error-detection and error-correction technique, was
proposed by R.W. Hamming. Whenever a data packet is transmitted over a network, there are
possibilities that the data bits may get lost or damaged during transmission.

Let's understand the Hamming code concept with an example: Let's say you have received a 7-bit
Hamming code which is 1011011.

First, let us talk about the redundant bits. The redundant bits are some extra binary bits that are not
part of the original data, but they are generated & added to the original data bit. All this is done to
ensure that the data bits don't get damaged and if they do, we can recover them.

Now the question arises, how do we determine the number of redundant bits to be added? We use
the formula, 2r >= m+r+1; where r = redundant bit & m = data bit.

From the formula we can make out that there are 4 data bits and 3 redundancy bits, referring to the
received 7-bit hamming code.

Hamming Code: Error Detection

As we go through the example, the first step is to identify the bit position of the data & all the bit
positions which are powers of 2 are marked as parity bits (e.g. 1, 2, 4, 8, etc.). The following image
will help in visualizing the received hamming code of 7 bits.

First, we need to detect whether there are any errors in this received hamming code.

Step 1: For checking parity bit P1, use check one and skip one method, which means, starting from P1 and
then skip P2, take D3 then skip P4 then take D5, and then skip D6 and take D7, this way we will have the
following bits,

As we can observe the total number of bits are odd so we will write the value of parity bit as P1 =
1. This means error is there.

Step 2: Check for P2 but while checking for P2, we will use check two and skip two method,
which will give us the following data bits. But remember since we are checking for P2, so we have
to start our count from P2 (P1 should not be considered).

As we can observe that the number of 1's are even, then we will write the value of P2 = 0. This
means there is no error.
 Step 3: Check for P4 but while checking for P4, we will use check four and skip four methods,
which will give us the following data bits. But remember since we are checking for P4, so we have
started our count from P4(P1 & P2 should not be considered).

As we can observe that the number of 1's are odd, then we will write the value of P4 = 1. This means
the error is there.

So, from the above parity analysis, P1 & P4 are not equal to 0, so we can clearly say that the received
hamming code has errors. The parity P0, P1, and P2 is obtained by following equation

P0 = D1 D2 D4

P1 = D1 D3 D4

P2 = D2 D3 D4

Hamming Code: Error Correction

Since we found that received code has an error, so now we must correct them. To correct the errors,
use the following steps: Now the error word E will be:

Now we have to determine the decimal value of this error word 101 which is 5 (22 *1 + 21 * 0 + 20
*1 = 5). We get E = 5, which states that the error is in the fifth data bit. To correct it, just invert the
fifth data bit. So the correct data will be:

Procedure:

1. Study the circuit provided on the Front panel of Kit.

2. Switch on power supply.
3. Apply I/P Data to Data Transmitter.
4. Convert parity and data O/P of data transmitter to data receiver.
5. Create error in data bit by error switcher given on kit.
6. Observe the data bit before correction and after correction.

Conclusion:
Aim: Study of DSSS transmitter and receiver using suitable hardware setup/kit.

Objective: To study direct sequence spread spectrum BPSK modulation and

demodulation technique.

Apparatus:
Sr. No. Apparatus Range
1. DSSS kit
2. DSO Dual Channel, 60 MHz

Theory: Spread Spectrum techniques were and are still used in military applications,
because of their high security, and their less susceptibility to interference from other
parties. In this technique, multiple users share the same bandwidth, without
significantly interfering with each other. The spreading waveform is controlled by a
Pseudo-Noise (PN) sequence, which is a binary random sequence. This PN is then
multiplied with the original baseband signal, which has a lower frequency, which
yields a spread waveform that has a noise like properties. In the receiver, the opposite
happens, when the pass band signal is first demodulated, and then despreads using the
same PN waveform. An important factor here is the synchronization between the two
generated sequences. In this report, I will try to illustrate the design process of such a
system, and then come up with a full circuit design.
Pseudo Noise (PN)
As we mentioned earlier, PN is the key factor in DS-SS systems. A Pseudo
Noise or Pseudorandom sequence is a binary sequence with an autocorrelation that
resembles, over a period, the autocorrelation of a random binary sequence. It is
generated using a Shift Register, and a Combinational Logic circuit as its feedback.
The Logic Circuit determines the PN words. In this design i used the so-called
Maximum–Length PN sequence. It is a sequence of period 2m. 1 generated by a linear
feedback shift register, which has feedback logic of only modulo–2 adders (XOR
Gates). Some properties of the Maximum–Length sequences are:
In each period of a maximum– length sequence, the number of 1s is always
one more thanthe number of 0s. This is called the Balance property.
Block Diagram:

DS-SS Transmitter and Receiver block diagram

PROCEDURE:

1) Switch on the power supply.

2) Observe o/p of PN sequence generator, P1, P2, on CRO. i.e. P1 = 10000, P2 = 10100.
3) Connect o/p of PN sequence generator to PN sequence i/p of transmitter multiplier
block.
4) Connect either P1 or P2 to pattern i/p of transmitter multiplier block.
5) Observe o/p of transmitter multiplier block which looks like random signal.
6) Connect o/p of transmitter multiplier block to i/p of PSK transmitter.
7) Observe o/p of PSK transmitter block together with carrier of PSK transmitter
on XY modeof CRO. You can observe two cross lines corresponding to 0
&180 phases i.e. BPSK signal.
8) Connect PSK transmitter o/p to i/p of 1496 squaring circuits & i/p2 of PSK
receiver
9) Observe o/p of 1496 squaring circuits & o/p of band pass filter. Adjust it
properly using pot provided near B.P. filter section.
10) Connect o/p frequency divider to i/p 1 of PSK receiver.
11) Observe o/p of PSK receiver & o/p of filter & comparator.
12) Connect o/p of filter & comparator to receiver multiplier block & also connect
PN sequence to receiver multiplier block.
13) Observe o/p of receiver multiplier block which is our transmitted pattern.

Conclusion:
Aim-To study of random processes. Find various statistical properties of random process

Objectives-To study various statistical properties of random process.

Apparatus-Matlab software,PC

Theory-

Random Process

 A random process is a collection of time functions or signals corresponding to various

outcomes of a random experiment.
 The random process represents the mathematical model of these random signals.
 A random process (or stochastic process) is a collection of random variables (functions)
indexed by time.
 The random process can be denoted by X(t,s) or X(t), where s is the sample point of the
random experiment and t is the time.
 These random signals play a fundamental role in the fields of communications, signal
processing, control systems, and many other engineering disciplines.

Statistical Properties of Random process

Mean:

The mean function of a random process is the expected value of the process.
Auto-correlation-

Autocorrelation of a random process X(t) is defined as the correlation of the random process X(t)
with itself (hence the word auto) at different points in time.

Figure 1-Random process at different points in time .

Auto-covariance

Autocovariance of a random process X(t) is defined as the covariance of the random process X(t)
with itself (hence the word auto) at different points in time.

Conclusion-
Aim: Simulation Study of performance of BPSK receiver in presence of noise.

Objective : Simulation Study of performance of BPSK receiver in presence of noise

Apparatus:1. MATLAB Software 2. PC

Theory:

Binary Phase Shift Keying (BPSK)

The first modulation considered is binary phase shift keying. Binary Phase-shift keying (BPSK)
is a digital modulation scheme that conveys data by changing, or modulating, two different phase
s of a reference signal (the carrier wave). The constellation points chosen are usually positioned
with uniform angular spacing around a circle. In this scheme during every bit duration, denoted
by T, one of two phases of the carrier is transmitted. These two phases are 180 degrees apart.
This makes these two waveforms antipodal. Any binary modulation where the two signals are
antipodal gives the minimum error probability (for fixed energy) over any other set of binary
signals. The error probability can only be made smaller (for fixed energy per bit) by allowing
more than two waveforms for transmitting information.

BPSK is a simple but significant carrier modulation scheme. The two time-limited energy signals
s1(t) and s2(t) are defined based on a single basis function ϕ1(t) as:

Generation of BPSK: Consider a sinusoidal carrier. If it is modulated by a bi-polar bit stream

according to the scheme illustrated in Figure 6.1 below, its polarity will be reversed every time

the bit stream changes polarity. This, for a sine wave, is equivalent to a phase reversal (shift).

The information about the bit stream is contained in the changes of phase of the transmitted
signal. A synchronous demodulator would be sensitive to these phase reversals.

Bit error rate (BER) of a communication system is defined as the ratio of number of error bits
andtotal number of bits transmitted during a specific period. It is the likelihood that a single error
bit will occur within received bits, independent of rate of transmission. There are many ways of
reducing BER. Here, we focus on channel coding techniques.
% Simulation Study of performance of BPSK receiver in presence of noise
% Simulation parameters
numBits = 1000; % Number of bits
SNRdB = 0:2:20; % Range of SNR values in dB
ber = zeros(size(SNRdB));

% Loop over SNR values

for i = 1:length(SNRdB)
% Generate random bits
bits = randi([0, 1], 1, numBits);

% BPSK modulation
bpskSignal = 2 * bits - 1;

% Add Gaussian noise

snrLinear = 10^(SNRdB(i) / 10); % Convert SNR from dB to linear scale
noise = sqrt(1 / (2 * snrLinear)) * randn(1, numBits);
receivedSignal = bpskSignal + noise;

% BPSK demodulation
DemodulatedBits = (receivedSignal > 0);

% Calculate BER
ber(i) = sum(bits ~= demodulatedBits) / numBits;
end

% Plot BER vs SNR

figure;
semilogy(SNRdB, ber, 'o-');
xlabel('SNR (dB)');
ylabel('Bit Error Rate (BER)');
title('BPSK Receiver Performance in Noise');
grid on;

Conclusion:
Aim: Study of CDMA Techniques

Objective: To study code division multiple access

Apparatus:Matlab Software

Theory:
Code Division Multiple Access (CDMA) is a sort of multiplexing that facilitates various signals
to occupy a single transmission channel. It optimizes the use of available bandwidth. The
technology is commonly used in ultra-high-frequency (UHF) cellular telephone systems, bands
ranging between the 800-MHz and 1.9-GHz.Code Division Multiple Access system is very
different from time and frequency multiplexing. In this system, a user has access to the whole
bandwidth for the entire duration. The basic principle is that different CDMA codes are used to
distinguish among the different users.Techniques generally used are direct sequence spread
spectrum modulation (DS-CDMA), frequency hopping or mixed CDMA detection (JDCDMA).
Here, a signal is generated which extends over a wide bandwidth. A code called spreading
code is used to perform this action. Using a group of codes, which are orthogonal to each other,
it is possible to select a signal with a given code in the presence of many other signals with
different orthogonal codes.

How Does CDMA Work?

CDMA allows up to 61 concurrent users in a 1.2288 MHz channel by processing each voice
packet with two PN codes. There are 64 Walsh codes available to differentiate between calls and
theoretical limits. Operational limits and quality issues will reduce the maximum number of calls
somewhat lower than this value.In fact, many different "signals" baseband with different
spreading codes can be modulated on the same carrier to allow many different users to be
supported. Using different orthogonal codes, interference between the signals is minimal.
Conversely, when signals are received from several mobile stations, the base station is capable of
isolating each as they have different orthogonal spreading codes.
The following figure shows the technicality of the CDMA system. During the propagation, we
mixed the signals of all users, but by that you use the same code as the code that was used at the
time of sending the receiving side. You can take out only the signal of each user.

The factors deciding the CDMA capacity are −

 Processing Gain
 Signal to Noise Ratio
 Voice Activity Factor
 Frequency Reuse Efficiency

Capacity in CDMA is soft, CDMA has all users on each frequency and users are separated by
code. This means, CDMA operates in the presence of noise and interference.In addition,
neighboring cells use the same frequencies, which means no re-use. So, CDMA capacity
calculations should be very simple. No code channel in a cell, multiplied by no cell. But it is not
that simple. Although not available code channels are 64, it may not be possible to use a single
time, since the CDMA frequency is the same.

Conclusion:

______________________________________________________________________________
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Aim: Simulation study of Source Coding technique.

Objectives:To obtain Shanno-fano code and Huffman code

Apparatus:Matlab Software,PC

Theory:
 Shannon Fano Coding
Shannon Fano Coding is directed towards construction of reasonably efficient
separate binary codes.

Let [x] be the message to be transmitted and [p] be their corresponding

probabilities. The messages are first written in descending order of their probabilities. The
message set then is partitioned into the most equiprobable subsets[x1] and [x2]. A 0 is
assigned to each message contained in one subset and ‗a‘ is assigned to each message in
other subset. The same procedure is repeated for subsets [x1] and [x2] i.e, [x1] will be
partitioned into 2 subsets [x11] and [x12] and [x2] will be partitioned into [x21] and
[x22]. The code words in [x11] will start with 00, [x12] will start with 01, and [x21] with
10, and so on.

 Huffman Coding
Huffman Coding uses the principal as that of Shannon Fano algorithm. This type of
coding makes average no. of digits per message equal to entropy. The messages are
arranged in accordance to their decreasing probability. The 2 digit message of lowest
probability is assigned binary 0 and 1.

The two probabilities are added & sum is placed in the last stage just that the
probability are decreasing in order. Again 0 and 1 are assigned to last 2 probabilities this
goes on till the final stage. The code is taken in reverse order by linking for a part icular
level.

Algorithm
 Shannon Fano Coding

1. Enter the number of messages.

2. Enter probability of each message.

3. Sort the message in decreasing order of probability.

4. Partition the message into two halves and continue till one element in the subset
5. Assign code for each partition block.
6. Calculate efficiency using the formula
7. Stop.

.
Huffman Coding:
1. Start

2. Enter the no. of messages and the value of probabilities

3. Arrange in ascending order.

4. Go on adding min 2 probabilities and also assign binary values to each level 0

5. Continue this till all probabilities are finished

6. Start linking the binary levels so that code is generated.

7. Print the code accordingly in sequence.

% Write a MATLAB CODE for Huffman Source Coding Method.

clc;
clear all;
close all;
sig=1:4;
Symbols=[1 2 3 4];
P=[0.1 0.3 0.4 0.2];
dict = huffmandict(Symbols,P);
temp=dict;
for i=1: length(temp)
temp {i,2}= num2str(temp{i,2});
end
disp(temp);
hcode= huffmanenco(sig,dict) dhsig= huffmandeco(hcode, dict)

Output

[1] '0 0 1'

[2] '0 1'
[3] '1'
[4] '0 0 0'

hcode =

0 0 1 0 1 1 0 0 0

dhsig =

1 2 3 4
Conclusion:
Aim: Simulation Study of cyclic codes.

Objectives- Simulation Study of cyclic codes.

APPARATUS-1. MATLAB Software 2. PC

Theory-

Cyclic Code is known to be a subclass of linear block codes where cyclic shift in the bits
of the codeword results in another codeword. It is quite important as it offers easy
implementation and thus finds applications in various systems.
Cyclic codes are widely used in satellite communication as the information sent digitally
is encoded and decoded using cyclic coding. These are error-correcting codes where the actual
information is sent over the channel by combining with the parity bits.Cyclic codes are known to
be a crucial subcategory of linear coding technique because these offers efficient encoding and
decoding schemes using a shift register. These are used in error correction as they can check for
double or burst errors. Various other important codes like, Reed Solomon, Golay, Hamming,
BCH, etc. can be represented using cyclic codes.Basically, a shift register and a modulo-2 adder
are the two crucial elements considered as building blocks of cyclic encoding. Using a shift
register, encoding can be efficiently performed. The fundamental elements of shift registers are
flip flops (that acts as a storage unit) and input-output. While the other i.e., a binary adder has
two inputs and one output.
% Simulation Study of cyclic codes.
clc;
clear all;
k=input(‘Enter the length of Msg word’);
n= input(‘Enter the length of Codeword’);
m=input(‘Enter the Msg word’);
G=cyclpoly(n,k,‘max’)
gx=poly2sym(G)
C=encode(m,n,k,‘cyclic’,G)
D=decode(C,n,k,‘cyclic’,G)

Output:

Enter the length of Msg word4

Enter the length of Codeword7

Enter the Msg word [1 0 1 0]

G=[ 1 1 0 1]

gx=x^3+x^2+1

C=0 0 1 1 0 1 0

D=1 0 1 0

Conclusion: