Bipin Tripathi Kumaon Institute

of Technology

Computer Organization
and Architecture Lab File
(2024-2025)

Submitted To: Submitted By:

Dr. Kapil Chaudhary Anuj Kumar
B. Tech CSE (II Year)
Roll No. - 230180101004
 Experiment 1: Ripple Carry Adder
Objective: To understand the operation of a ripple carry adder, specifically how the carry ripples through the adder.

1. Examining the behaviour of the working module to understand how the carry ripples through the adder
stages

2. To design a ripple carry adder using full adders to mimic the behaviour of the working module

3. The adder will add two 4 bit numbers

Examining behaviour of ripple carry adder for the working module and the module designed by the student as part
of the experiment (refer to the circuit diagram)

Loading data in the ripple carry adder (refer to procedure tab for pin numbers)

 each unit of adder will add single bits of the two numbers along with the carry from the previous adder

 load the two input numbers in the adder units as:

 A(A3 A2 A1 A0): A3=1, A2=1, A1=1, A0=1

 B(B3 B2 B1 B0): B3=0, B2=0, B1=0, B0=1

Examining the rippling of carry behaviour:

 check output sum:

 sum(S3 S2 S1 S0): S3=0, S2=0, S1=0, S0=0

 check output carry:

 cout=1

 check intermediate carry bit of all the unit adders which will be 1

 probing the carry port can be done by verifying the colour of the wire coming out of the port

Recommended learning activities for the experiment:

Leaning activities are designed in two stages, a basic stage and an advanced stage. Accomplishment of each stage can
be self-evaluated through the given set of quiz questions consisting of multiple type and subjective type questions. In
the basic stage, it is recommended to perform the experiment firstly, on the given encapsulated working module,
secondly, on the module designed by the student, having gone through the theory, objective and producer. By
performing the experiment on the working module, students can only observe the input-output behaviour. Whereas,
performing experiments on the designed module, students can do circuit analysis, error analysis in addition with the
input-output behaviour. It is recommended to perform the experiments following the given guideline to check
behaviour and test plans along with their own circuit analysis. Then students are recommended to move on to the
advanced stage. The advanced stage includes the accomplishment of the given assignments which will provide
deeper understanding of the topic with innovative circuit design experience. At any time, students can mature their
knowledge base by further reading the references provided for the experiment.

Colour configuration of wire for 5 valued logic supported by the simulator:

 if value is UNKNOWN, wire colour= maroon

 if value is TRUE, wire colour= blue

 if value is FALSE, wire colour= black

 if value is HI IMPEDENCE, wire colour= green

 if value is INVALID, wire colour= orange

Test plan:

1. Set one input to zero(0) and check the output.

2. Set one input to all one and another as 0001 in ripple carry adder. Check the output and how the carry
ripples.

3. Check the ripple carry adder with input carry with two arbitrary input.

Use Display units for checking output. Try to use minimum number of components to build. The pin configuration of
the canned components are shown when mouse hovered over a component.

Assignment Statements:

1. Create a half adder circuit using only logic gates and test it by giving proper input.

2. Create a full adder circuit using only logic gates and test it by giving proper input.

3. Create a full adder circuit using half adder and test it by giving proper input.

4. Create a 4-bit ripple carry adder circuit using half adders and full adders and test it by giving proper input.

Theory:

Design of Ripple Carry Adders:

Arithmetic operations like addition, subtraction, multiplication, division are basic operations to be implemented in
digital computers using basic gates like AND, OR, NOR, NAND etc. Among all the arithmetic operations if we can
implement addition then it is easy to perform multiplication (by repeated addition), subtraction (by negating one
operand) or division (repeated subtraction).

Half Adders can be used to add two one bit binary numbers. It is also possible to create a logical circuit using multiple
full adders to add N-bit binary numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This
kind of adder is a Ripple Carry Adder, since each carry bit "ripples" to the next full adder. The first (and only the first)
full adder may be replaced by a half adder. The block diagram of 4-bit Ripple Carry Adder is shown here below –

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is
relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate
delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a
32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 31 * 2(for carry
propagation) + 3(for sum) = 65 gate delays.

Design Issues:

The corresponding Boolean expressions are given here to construct a ripple carry adder. In the half adder circuit the
sum and carry bits are defined as

Sum = A ⊕ B

Carry = AB

In the full adder circuit the Sum and Carry output is defined by inputs A, B and Carrying as
Sum = ABC + ABC + ABC + ABC

Carry = ABC + ABC + ABC + ABC

Having these we could design the circuit. But we first check to see if there are any logically equivalent statements
that would lead to a more structured equivalent circuit.

With a little algebraic manipulation, one can see that

Sum = ABC + ABC + ABC + ABC

= (AB + AB) C + (AB + AB) C

= (A ⊕ B) C + (A ⊕ B) C

=A⊕B⊕C

Carry = ABC + ABC + ABC + ABC

= AB + (AB + AB) C

= AB + (A ⊕ B) C

Procedure

Assignment Statements:

 Create a half adder circuit using only logic gates and test it by giving proper input.

 Create a full adder circuit using only logic gates and test it by giving proper input.

 Create a full adder circuit using half adder and test it by giving proper input.

 Create a 4-bit ripple carry adder circuit using half adders and full adders and test it by giving proper input.

Circuit diagram of Ripple Carry Adder:

Experiment 2: Implement and test a two-input AND Gate using VHDL code
Objective: To implement and test a two-input AND gate using VHDL code.

Theory: AND gate logic

 An AND gate is used to perform logical Multiplication of binary input. The Output state of the AND gate will
be high(1) if both the input are high(1), else the output state will be low(0) if any of the input is low(0).
 The Boolean Expression or logic for the AND gate is the logical multiplication of inputs denoted by a full stop
or single dot as
 The truth table for the AND gate is:

A B Y (Output)
0 0 0
0 1 0
1 0 0
1 1 1

VHDL Code:

The code for designing the AND gate in VHDL:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity AND_Gate is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC);

end AND_Gate;

architecture Behavioral of AND_Gate is

begin

Y <= A and B;

end Behavioral;

Testbench Code:

To test the functionality of the AND gate, a testbench is used. The testbench generates different combinations of
input values (A, B) and checks the corresponding output (Y).
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity TB_AND_Gate is

end TB_AND_Gate;

architecture testbench of TB_AND_Gate is

signal A, B, Y : STD_LOGIC;

begin

-- Instantiate the AND Gate

UUT: entity work.AND_Gate port map (A => A, B => B, Y => Y);

 -- Stimulus process

process

begin

-- Test Case 1: 0 AND 0

A <= '0'; B <= '0';

wait for 100 ns;

-- Test Case 2: 0 AND 1

A <= '0'; B <= '1';

wait for 100 ns;

-- Test Case 3: 1 AND 0

A <= '1'; B <= '0';

wait for 100 ns;

-- Test Case 4: 1 AND 1

A <= '1'; B <= '1';

wait for 100 ns;

-- End simulation

wait;

end process;

end testbench;

Output:
 Experiment 3: Carry Look Ahead Adder
Objective: It computes the carries parallelly thus greatly speeding up the computation.

1. understanding behaviour of carry lookahead adder from module designed by the student as part of the
experiment

2. understanding the concept of reducing computation time with respect of ripple carry adder by using carry
generate and propagate functions

3. the adder will add two 4 bit numbers

Examining behaviour of carry lookahead adder for the module designed by the student as part of the experiment
(refer to the circuit diagram)

Loading data in the carry lookahead adder (refer to procedure tab for further detail and experiment manual for pin
numbers)

Load the two input numbers in the adder units as:

 1111 and 0001

Examining the carry generate and propagate function behaviour:

 check output sum 0000

 check final output carry 1

 check intermediate carry bit and sum bit of the unit adders and verify the values of carry generate and
propagate function (refer to theory)

 probing the any port can be done by verifying the colour of the wire coming out of the port

Recommended learning activities for the experiment:

Leaning activities are designed in two stages, a basic stage and an advanced stage. Accomplishment of each stage can
be self-evaluated through the given set of quiz questions consisting of multiple type and subjective type questions. In
the basic stage, it is recommended to perform the experiment firstly, on the given encapsulated working module,
secondly, on the module designed by the student, having gone through the theory, objective and producer. By
performing the experiment on the working module, students can only observe the input-output behaviour. Whereas,
performing experiments on the designed module, students can do circuit analysis, error analysis in addition with the
input-output behaviour. It is recommended to perform the experiments following the given guideline to check
behaviour and test plans along with their own circuit analysis. Then students are recommended to move on to the
advanced stage. The advanced stage includes the accomplishment of the given assignments which will provide
deeper understanding of the topic with innovative circuit design experience. At any time, students can mature their
knowledge base by further reading the references provided for the experiment.

Colour configuration of wire for 5 valued logic supported by the simulator:

 if value is UNKNOWN, wire colour= maroon

 if value is TRUE, wire colour= blue
 if value is FALSE, wire colour= black
 if value is HI IMPEDENCE, wire colour= green
 if value is INVALID, wire colour= orange

Test plan:

1. Set one input to zero(0) and check the output.

2. Set one input to all one and another as 0001 in carry lookahead adder.
 3. Check the carry lookahead adder with two arbitrary input. Check the output and show the carry propagator
and generator output for every bit.

Use Display units for checking output. Try to use minimum number of components to build. The pin configuration of
the canned components are shown when mouse hovered over a component.

Assignment Statements:

1. Design a 4-bit carry lookahead adder circuit using half adders and full adders and test it by giving proper
input.

2. Design a 16-bit carry lookahead adder circuit using half adders and full adders and test it by giving proper
input.

Theory:

Design of Carry Lookahead Adders:

To reduce the computation time, there are faster ways to add two binary numbers by using carry lookahead adders.
They work by creating two signals P and G known to be Carry Propagator and Carry Generator. The carry propagator
is propagated to the next level whereas the carry generator is used to generate the output carry, regardless of input
carry. The block diagram of a 4-bit Carry Lookahead Adder is shown here below –

The number of gate levels for the carry propagation can be found from the circuit of full adder. The signal from input
carry Cin to output carry Cout requires an AND gate and an OR gate, which constitutes two gate levels. So if there are
four full adders in the parallel adder, the output carry C5 would have 2 X 4 = 8 gate levels from C1 to C5. For an n-bit
parallel adder, there are 2n gate levels to propagate through.

Design Issues:

The corresponding Boolean expressions are given here to construct a carry lookahead adder. In the carry-lookahead
circuit we ned to generate the two signals carry propagator(P) and carry generator(G),

The output sum and carry can be expressed as

Having these we could design the circuit. We can now write the Boolean function for the carry output of each stage
and substitute for each Ci its value from the previous equations:

Procedure

Assignment Statements:

1. Design a 4-bit carry lookahead adder circuit using half adders and full adders and test it by giving proper
input.

2. Design a 16-bit carry lookahead adder circuit using half adders and full adders and test it by giving proper
input.

Circuit diagram of Carry Lookahead Adder:

 Experiment 4: Implement and test a Shift Register using VHDL code
Objective: To implement and test a Shift Register using VHDL code.

Theory: Shift Register

A shift register is a sequential logic circuit used to store and shift data. It consists of a series of flip-flops, where the
output of one flip-flop is connected to the input of the next. Shift registers are widely used in digital circuits for
temporary data storage, data transfer, and serial-to-parallel conversion.

Types of Shift Registers:

1. Serial-In Serial-Out (SISO): Data is shifted in and out sequentially.

2. Serial-In Parallel-Out (SIPO): Data is shifted in serially and outputted in parallel.

3. Parallel-In Serial-Out (PISO): Data is loaded in parallel and shifted out serially.

4. Parallel-In Parallel-Out (PIPO): Data is loaded and outputted in parallel.

For this experiment, we will implement a 4-bit Serial-In Serial-Out (SISO) Shift Register.

Truth Table for a 4-bit SISO Shift Register:

Clock Cycle Input (SI) Output (Q3) Output (Q2) Output (Q1) Output (Q0)
0 X 0 0 0 0
1 1 0 0 0 1
2 0 0 0 1 0
3 1 0 1 0 1
4 1 1 0 1 0

VHDL Code for 4-bit Serial-In Serial-Out Shift Register

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Shift_Register is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

shift : in STD_LOGIC; -- 0 for right shift, 1 for left shift

data_in : in STD_LOGIC;

q : out STD_LOGIC_VECTOR(3 downto 0));

end Shift_Register;

architecture Behavioral of Shift_Register is

signal temp_reg : STD_LOGIC_VECTOR(3 downto 0) := "0000";

begin

process(clk, reset)

begin
 if reset = '1' then

temp_reg <= "0000"; -- Reset register to 0

elsif rising_edge(clk) then

if shift = '1' then

-- Left shift: Insert data_in at LSB, shift left

temp_reg <= temp_reg(2 downto 0) & data_in;

else

-- Right shift: Insert data_in at MSB, shift right

temp_reg <= data_in & temp_reg(3 downto 1);

end if;

end if;

end process;

q <= temp_reg; -- Output the register value

end Behavioral;

Testbench Code :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Shift_Register_TB is

end Shift_Register_TB;

architecture TB of Shift_Register_TB is

signal clk : STD_LOGIC := '0';

signal reset : STD_LOGIC := '0';

signal shift : STD_LOGIC := '0';

signal data_in : STD_LOGIC := '0';

signal q : STD_LOGIC_VECTOR(3 downto 0);

constant clk_period : time := 10 ns; -- Define clock period

begin

-- Instantiate the Shift Register

uut: entity work.Shift_Register port map (

 clk => clk,

reset => reset,

shift => shift,

data_in => data_in,

q => q

);

-- Clock process

clk_process: process

begin

while now < 200 ns loop

clk <= '0';

wait for clk_period / 2;

clk <= '1';

wait for clk_period / 2;

end loop;

wait;

end process;

-- Stimulus process

stim_process: process

begin

-- Reset the shift register

reset <= '1';

wait for clk_period;

reset <= '0';

-- Right shift operations (shift = 0)

shift <= '0';

data_in <= '1'; wait for clk_period;

data_in <= '0'; wait for clk_period;

data_in <= '1'; wait for clk_period;

data_in <= '1'; wait for clk_period;

 -- Left shift operations (shift = 1)

shift <= '1';

data_in <= '0'; wait for clk_period;

data_in <= '1'; wait for clk_period;

data_in <= '0'; wait for clk_period;

data_in <= '1'; wait for clk_period;

wait;

end process;

end TB;
 Experiment 5: Wallace Tree Adder
Objective: This is an adder with less height.

1. understanding behaviour of wallace tree adder from module designed by the student as part of the
experiment and the working module as well

2. understanding the concept of reducing gate delay by using tree of adders instead of using cascaded full
adders

3. the adder will add three 4-bit numbers

Examining behaviour of wallace tree adder for the module designed by the student as part of the experiment
(refer to the circuit diagram)

Loading data in the carry lookahead adder (refer to procedure tab for further detail and experiment manual for pin
numbers)

 load the three input numbers in the adder units as:

o 1111, 0001 and 1110

Examining the behaviour:

 check output sum 1110

 check final output carry 1

 check intermediate carry bit and sum bit of the unit adders (refer to theory and circuit diagram)

 probing the any port can be done by verifying the color of the wire coming out of the port

 color configuration of wire for 5 valued logic supported by the simulator:

- if value is UNKNOWN, wire color= maroon

- if value is TRUE, wire color= blue

- if value is FALSE, wire color= black

- if value is HI IMPEDENCE, wire color= green

- if value is INVALID, wire color= orange

Examining behaviour of given wallace tree adder for the workng module:

Loading data in the wallace tree adder (refer to procedure tab for further detail and experiment manual for pin
numbers) as:

 load the three input numbers as:

- A (A3 A2 A1 A0): A3=1, A2=1, A1=1, A0=1

- B (B3 B2 B1 B0): B3=0, B2=0, B1=0, B0=1

- C (C3 C2 C1 C0): C3=1, C2=1, C1=1, C0=0

Examining the behaviour:

 check output sum:

- sum (S3 S2 S1 S0): S3=1, S2=1, S1=1, S0=0

  check output carry:

- cout=1

Recommended learning activities for the experiment:

Leaning activities are designed in two stages, a basic stage and an advanced stage. Accomplishment of each stage can
be self-evaluated through the given set of quiz questions consisting of multiple type and subjective type questions. In
the basic stage, it is recommended to perform the experiment firstly, on the given encapsulated working module,
secondly, on the module designed by the student, having gone through the theory, objective and procuder. By
performing the experiment on the working module, students can only observe the input-output behavior. Whereas,
performing experiments on the designed module, students can do circuit analysis, error analysis in addition with the
input-output behavior. It is recommended to perform the experiments following the given guideline to check
behavior and test plans along with their own circuit analysis. Then students are recommended to move on to the
advanced stage. The advanced stage includes the accomplishment of the given assignments which will provide
deeper understanding of the topic with innovative circuit design experience. At any time, students can mature their
knowledge base by further reading the references provided for the experiment.

 color configuration of wire for 5 valued logic supported by the simulator:

- if value is UNKNOWN, wire color= maroon

- if value is TRUE, wire color = blue

- if value is FALSE, wire color = black

- if value is HI IMPEDENCE, wire color = green

- if value is INVALID, wire color = orange

Test Plan: Take three 4-bits number. Give proper inputs to check the identity, commutativity, associativity of addition
operation with interchanging input values, setting zero (0) to one input.

Use Display units for checking output. Try to use minimum number of components to build. The pin configuration of
the canned components are shown when mouse hovered over a component.

Theory:

Design of Wallace Tree Adders: There are many cases where it is desired to add more than two numbers together.
The straightforward way of adding together m numbers (all n bits wide) is to add the first two, then add that sum to
the next using cascading full adders. This requires a total of m − 1 additions, for a total gate delay of O(m lg n)
(assuming lookahead carry adders). Instead, a tree of adders can be formed, taking only O(lg m · lg n) gate delays.

A Wallace tree adder adds together n bits to produce a sum of log2n bits.

The design of a Wallace tree adder to add seven bits (W7) is illustrated below:
An adder tree to add three 4-bit numbers is shown below:

An adder tree (interconnections incomplete) to add five 4-bit numbers is shown below:

The above block diagrams can be used to design different Wallace tree adder.

Procedure

Assignment Statements : You are required to build the following Wallace tree adders

 Adder to add seven bits

 Adder to add three 4-bit numbers

 Adder to add five 4-bit numbers

 Adder to add seven 4-bit numbers

Circuit diagram of Wallace Tree Adder:
 Experiment 6: Synthesis of Flip Flops
Objective

1. To understand the basic concepts of flip-flops as elementary units of sequential circuits

2. To understand what is race around condition and why does it occur in JK flip-flop

3. To know how the race around condition which occurs in JK flip-flop is avoided

4. To understand what kind of problems may occur in master slave JK flip-flop

5. To know the need for master slave JK flip-flop with asynchronous preset and clear

Theory

Synthesis of Flip Flops: Till now the experiments are based only on the combinational circuits where output at any
instance depends only on the current input. Most of components of digital logic consists combinational circuits but
they likely to have memory elements too. Those type of circuits are known to be sequential circuits. In a sequential
circuit the present output is not only determined by the present input but also depends on the past output. flip-flops
are the simplest kind of sequential circuits. A flip-flop can maintain a binary state identity which means it can act as
1-bit memory cell. There are different kind of flip-flops depending on the number of inputs or the way the inputs
affect the states.

Basic flip-flop: A basic flip-flop circuit can be constructed using two cross-coupled NAND/NOR gates shown below.
Each flip-flop has two outputs, Q and Q', and two inputs, set and reset. When the set input goes to 1 the Q output
goes to 1 and the Q' goes to 1 when reset goes to 1. But when both set, reset are 1, both Q, Q' outputs go to 0 for
basic flip-flop circuit with NOR gates. In basic flip-flop circuit with NAND gates, when both input go to 0, both outputs
go to 0 violating the fact that the outputs of the flip-flop have to be complement of each other.

There are various different kind of flip-flops. Some of the common flip-flops are: R-S flip-flop, D flip-flop, J-K flip-
flop, T flip-flop etc.

1. Clocked RS flip-flop: The basic flip-flop is modified by adding some gates to the inputs so that the flip-flop
changes state only when the clock pulse is 1. The truth table for this type of flip-flop is shown below. If R is
high then reset state occurs and when S=1 then set state. However, if both the inputs are 1 then it violates
normal operation of flip-flop.
 2. JK flip-flop: JK flip-flop is a refinement of RS flip-flop where the indeterminate state of RS type is defined.
Input J and K are respectively the set and reset inputs of the flip-flop. When both the inputs are high then the
output of the flip-flop switches to its complemented state. A clocked JK flip-flop is shown below.

3. D flip-flop: The D flip-flop is used to transfer data to the flip-flop. It is basically the JK flip-flop where the the K
input is inverted. The circuit diagram of the D flip-flop is shown below:

4. T flip-flop: The T or "toggle" flip-flop changes its output on each clock edge. The truth table as follows:

Components Required:

To build any gate level flip-flop, we need :

1. Logic Gates.

2. Wires to connect.

Circuit Diagram of SR Flip Flop:

Circuit Diagram of JK Flip Flop:

Circuit Diagram of D Flip Flop:

Circuit Diagram of T Flip Flop:

 Experiment 7: Registers and Counters
Objective of Designing Registers:

1. To understand the shifting of data

2. To examine the behavior of different modes of data input and data output (serial-in serial-out, serial-in
parallel-out, parallel-in serial out, parallel-in parallel-out)

3. To make use of shift register in data transfer

4. Developing skills in the designing and testing of sequential logic circuits

5. Developing skills in analysing timing signals

Objective of Designing Counters:

1. Understanding the concept of counting upto certain limiting value and returning back to the start state from
final state

2. Understanding the generation of timing sequences to control operations in a digital system

3. Developing skills in the design and testing of counters for given timing sequences

4. Developing skills in generating timing signals

Theory

Design of Registers and Counters:

In a sequential circuit the present output is determined by both the present input and the past output. In order to
receive the past output some kind of memory element can be used. The memory element commonly used in the
sequential circuits are time-delay devices. The block diagram of the sequential circuit-

A circuit with flip-flops is considered a sequential circuit even in the absence of combinational logic. Circuits that
include flip-flops are usually classified by the function they perform. Two such circuits are registers and counters:

1. Register is a group of flip-flops. Its basic function is to hold information within a digital system so as to make
it available to the logic units during the computing process.

2. Counter is essentially a register that goes through a predetermined sequence of states.

Types of Registers:

 4-bit Serial-in Serial-out

4 bit serial-in serial-out register accepts digital data serially that is one bit at the time on one line. It produces
the stored information on its output also in serial form. This is a shift register, as the binary number is
"Shifted" one bit at time from one flip flop to the next.

 4-bit Serial-in Parallel-out

In serial-in parallel-out register the data are loaded serially and read out in parallel.
  4-bit Parallel-in Serial-out

In parallel-in serial out register the bits are entered simultaneously into their respective stages on parallel-
lines, rather than on a bit-by-bit basis on one line as with serial data inputs and output is read out out
parallelly.

 4-bit Parallel-in Parallel-out

In parallel-in parallel out register the data is loaded in parallel and shifted out serially.

Types of Counters:

 4-bit Synchronous Binary Counter

A counter is a sequential circuit that moves through a predefined sequence of states upon applying of clock
pulses. The sequence of states may follow the binary number sequence or an arbitrary manner (no
sequence). The simplest example of a counter is the binary counter which follows the binary number
sequence. An n-bit binary counter contains n flip-flops and can count binary numbers from 0 to (2n -1) (up
counter which is incremental, if it counts decrementally it is then down counter).

 4-bit Synchronous Ring Counter

If the output of a shift register is fed back to the input. a ring counter results. The data pattern contained
within the shift register will recirculate as long as clock pulses are applied. logic diagram of synchronous ring
counter-

 4-bit Synchronous Johnson Counter

If the complement output of a ring counter is fed back to the input instead of the true output, a Johnson
counter results. This "reversed" feedback connection has a profound effect upon the behavior of the
otherwise similar circuits. Recirculating a single 1 around a ring counter divides the input clock by a factor
equal to the number of stages. Whereas, a Johnson counter divides by a factor equal to twice the number of
stages.

Design Issues:

The four different types of flip-flops are supplied here. One can easily build any register or counter using those flip-
flop and different logic gates. But the clock input is under development, so it is not possible now to build any register
or counter completely.

Components:
To build any register or counters, we need:
1. Flip-Flops.
2. Logic Gates.
3. Wires to connect. In case of counters the number of flip-flops depends on the number of different states in
the counter.

Circuit 4-bit shift register (SISO):

 Experiment 8: Design of Combinational Multipliers
Objective of 4 bit carry lookahead adder:

To show that it is possible to construct a 4x4 combinational multiplier from an array of AND gates, half-adders and
full-adders.
1. understanding behaviour of combinational multiplier from module designed by the student as part of the
experiment
2. understanding the scheme implemented for the multiplication which is as follows (along with the logic
diagram bellow):
o it can be designed by unrolling the multiplier loop
o instead of handling the carry out of partial product summation bit, the carry out can be sent to the
next bit of the next step
o this scheme of handling the carry is called carry save addition
3. The multiplier will multiply two 4-bit numbers

Theory
Design of Combinational Multipliers
Combinational Multipliers do multiplication of two unsigned binary numbers. Each bit of the multiplier is multiplied
against the multiplicand, the product is aligned according to the position of the bit within the multiplier, and the
resulting products are then summed to form the final result. Main advantage of binary multiplication is that the
generation of intermediate products are simple: if the multiplier bit is a 1, the product is an appropriately shifted
copy of the multiplicand; if the multiplier bit is a 0, the product is simply 0.
The design of a combinational multiplier to multiply two 4-bit binary number is illustrated below:

If two n-bit numbers are multiplied then the output will be less than or equals to 2n bits.
Some features of the multiplication scheme:
 it can be designed by unrolling the multiplier loop
 instead of handling the carry out of partial product summation bit, the carry out can be sent to the next bit
of the next step
 this scheme of handling the carry is called carry save addition
 this scheme is more regular and modular
Logic diagram:

Components Needed:
To build a Combinational Multiplier, we need:
1. 16 2-input AND Gates
2. 4 half adders
3. 8 full adders
4. Display unit to show the outputs.
5. Wires to connect.

Circuit Diagram of Combinational Multiplier:

 Experiment 9 : Open Car Door beep System
Objective: To design a vhdl code to beep depending upon the number of doors open.

VHDL code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity DoorBeepSystem is

Port ( door : in STD_LOGIC_VECTOR(3 downto 0);

beep1 : out STD_LOGIC;

beep2 : out STD_LOGIC;

beep3 : out STD_LOGIC );

end DoorBeepSystem;

architecture Behavioral of DoorBeepSystem is

signal count : STD_LOGIC_VECTOR(2 downto 0);

begin

process(door)

variable sum : integer := 0;

begin

sum := 0;

for i in 0 to 3 loop

if door(i) = '1' then

sum := sum + 1;

end if;

end loop;

count <= std_logic_vector(to_unsigned(sum, 3));

-- Reset all beeps

beep1 <= '0';

beep2 <= '0';

 beep3 <= '0';

case count is

when "001" =>

beep1 <= '1'; -- 1 door open

when "010" =>

beep2 <= '1'; -- 2 doors open

when others =>

if unsigned(count) > "010" then

beep3 <= '1'; -- 3 or 4 doors open

end if;

end case;

end process;

end Behavioral;

Testbench:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity DoorBeepSystem_tb is

end DoorBeepSystem_tb;

architecture test of DoorBeepSystem_tb is

component DoorBeepSystem

Port ( door : in STD_LOGIC_VECTOR(3 downto 0);

beep1 : out STD_LOGIC;

beep2 : out STD_LOGIC;

beep3 : out STD_LOGIC );

end component;

signal door : STD_LOGIC_VECTOR(3 downto 0) := "0000";

signal beep1 : STD_LOGIC;

signal beep2 : STD_LOGIC;

signal beep3 : STD_LOGIC;

begin

uut: DoorBeepSystem
 port map (

door => door,

beep1 => beep1,

beep2 => beep2,

beep3 => beep3

);

stim_proc: process

begin

-- 0 doors open

door <= "0000"; wait for 10 ns;

-- 1 door open

door <= "0001"; wait for 10 ns;

-- 2 doors open

door <= "0011"; wait for 10 ns;

-- 3 doors open

door <= "0111"; wait for 10 ns;

-- 4 doors open

door <= "1111"; wait for 10 ns;

-- Alternate doors open

door <= "0101"; wait for 10 ns;

-- Random pattern

door <= "1010"; wait for 10 ns;

wait;

end process;

end test;