Solutions Chapter 7
7.2. In modern FETs, the gate is usually degenerately doped silicon, whose Fermi
level is essentially at the bottom of the conduction band edge (for an NFET) or at
the top of the valence band edge (for a PFET).
a) Draw an energy band diagram similar to Figure 7.5b, except making the
transistor a PFET.
b) Suppose the device is an NFET, but the gate is made of metal (as was done
in the early days). Draw the energy band diagram. Take M<S.
The energy band diagram is:
7.3. For the transistor of Figure P7.1, by how much should the gate voltage be
changed to produce inversion? Threshold? Assume half the applied voltage appears
across the oxide and half across the semiconductor. If the device in the figure is at
equilibrium, is this an enhancement or a depletion FET?
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We need to bend the bands in the Si by an additional 0.1 eV to just invert
the surface, meaning the gate voltage should be increased by
20.1=0.2V. To produce threshold, the surface should be inverted by 0.3
eV, requiring another 0.3eV of band bending or 0.6V. Thus the change in
gate voltage required to reach threshold if 0.6+0.2=0.8V. As no channel
exists at equilibrium, this is an enhancement device.
7.6. Consider two silicon MOSFETs, one n channel and the other p channel, with
substrate dopings of 1016cm-3. The NMOS has an n+ gate and the PMOS has a p+
gate, both doped to 1019cm-3. Find the built-in voltage Vbi for each, and draw the
energy band diagram. Neglect the band-gap narrowing effects discussed in Chapter
2.
For the NMOS, we construct the energy band diagram, keeping in mind
that the substrate is p-type and that since both the gate and substrate are
silicon, they have the same electron affinity . We find the location of the
Fermi level with respect to the valence band edge from
For the poly side, we take the Fermi level to be at the conduction band
edge since the material is degenerately doped.
The energy band diagram is
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and the built-in voltage is
For the PMOS,
The energy band diagram is
and the built-in voltage= (4.05+1.12)- 4.05-0.21=0.91eV.
7.7. In the MOS process, structures like the gate of a transistor are used to make
capacitors as well. If the oxide thickness is 4 nm, what area is needed to achieve a
capacitance of 1 pF? The permittivity of silicon dioxide is 3.90.
The capacitance per unit area is
So the area required to obtain 1 pF is
.
This corresponds to a square about 11 m on a side.
7.11. An enhancement NFET with the characteristics in Table 7.1 has a threshold
voltage of VT=1V, a channel length of 1 m and a width of 5 m. Considering
velocity saturation, with vsat=5 x 106 cm/s, find the current ID for
a) VGS=0 V, VDS= 1V
Here VG<VT, so the device is below threshold, so the current is essentially
zero.
b) VGS=2V, VDS=1 V
From Equation (7.68),
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Thus we are above saturation (VDS>VDSsat), and from Equation (7.67),
Alternately, using Equation (7.69)
c) VGS=3V, VDS=1 V
This is greater than our VDS, so now the device is not saturated. The
current is
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