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HDL Report 1

The document contains multiple HDL (Hardware Description Language) modules that define various digital logic circuits, including NOR gates, Boolean expressions, a full adder/subtractor, and a BCD to excess-3 converter. Each module specifies inputs and outputs, along with the logic operations performed. The document also includes test benches for verifying the functionality of the circuits.

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Mohamed Ahmed
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9 views6 pages

HDL Report 1

The document contains multiple HDL (Hardware Description Language) modules that define various digital logic circuits, including NOR gates, Boolean expressions, a full adder/subtractor, and a BCD to excess-3 converter. Each module specifies inputs and outputs, along with the logic operations performed. The document also includes test benches for verifying the functionality of the circuits.

Uploaded by

Mohamed Ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Mohamed Ahmed Hammouda

HDL Report 1

W1

1 – 3.31 e W2
W1_bar

W2_bar

W3

module ex3.31e_gate_level ( F , A ,B , C , D , E_bar ) ;

output F ;

input A ,B , C , D , E_bar ;

wire (w1 , w2 , w1_bar , w2_bar , w3 ) ;

nor (w1 , A , B ) ;

nor ( w2 , C , D ) ;

not (w1_bar , w1) ;

not (w2_bar,w2) ;

not (w3 , E_bar ) ;

and ( F , w1_bar , w2_bar, w3 ) ;

endmodule

2 – 3.32f

module ex3.32f_bolean_expression (F , A , B , C , D ) ;

output F ;

input A , B , C , D ;

assign F = ( (A&~B ) | (~A&B) ) & ( C | ~D) ;

endmodule
3 – 3.34

module ex3.34_bolean_expression (Out_1, Out_2 , Out_3 , A , B , C , D ) ; // Rest of code

output F ; A=0;B=0;C=0;D=0;

input A , B , C , D ; #10 D = 1 ; // 0001

assign Out_1 = ( A | ~B) &(~ C) & (C | D ) ; #20 C= 1 ; D = 0 ; // 0010

assign Out_2 = ( ( ~C &D ) | (B&C&D) | ( C&~D) ) & (~A | B) ; #30 D = 1 ; // 0011

assign Out_3 = ( ( (A&B) | C ) & D ) | ( ~B&C ) ; #40 B = 1 ; C = 0 ; D = 0 ; // 0100

endmodule #50 D = 1 ; // 0101

// test bench #60 C = 1 ; D = 0 ; // 0110

module t_Fig 3.34_bolean_expres; #70 D = 1 ; // 0111

wire x , y , z , w #80 A = 1 ; B = 0 ; C = 0 ; D = 0 ; // 1000

reg A , B , C , D #90 D = 1 ; // 1001

Fig 3.34_bolean_expression test (A , B , C , D , Out_1, Out_2 , Out_3); end

initial initial # 100 $finish ;

begin endmodule

4 – 3.36a
5 – 3.37

primitive ex3.37 (Y , A , B , C , D ) ;

output Y ;

input A , B , C , D ;

table

// A B C D : Y

0 0 0 0 : 0 ;

0 0 0 1 : 0 ;

0 0 1 0 : 0 ;

0 0 1 1 : 0 ;

0 1 0 0 : 0 ;

0 1 0 1 : 0 ;

0 1 1 0: : 0 ;

0 1 1 1: : 1 ;

1 0 0 0 : 0 ;

1 0 0 1 : 0 ;

1 0 1 0 : 0 ;

1 0 1 1 : 1 ;

1 1 0 0 : 0 ;

1 1 0 1 : 1;

1 1 1 0 : 1;

1 1 1 1 : 1 ;

endtable

endprimitive
6 – 4.37

module ex4.37_full_adder_subtractor (

output [3 : 0} Sum_diff ,

output C_out ,

input [3 : 0 ] A,B,
G4 G3 G2 G1
input M

);

wire [3 : 0 ] B_xor_M ;

xor

G1 ( B_xor_M[0] , B[0] , M) ,

G2 ( B_xor_M[1] , B[1] , M) ,

G3 ( B_xor_M[2] , B[2] , M) ,
G1
G4 ( B_xor_M[3] , B[3] , M) ;

assign{ C_out , Sum_diff} = A + B_xor_M + M ;

endmodule
7– 4.42

module ex4.42_BCD_to_excess_3 ( x , y , z , w , A , B , C , D ) ;

output x , y , z , w ;

input A , B , C , D ;

wire CD , C_or_D , C_or_D__bar , B _bar , w1 , w2 , w3 ;


G9
and

G1 ( CD , C , D ) ,
G1
G2 (w1 , C_or_D__bar , B ) , G5

G3 ( w2 , , C_or_D , B_bar ) , G10


G6
G4 (w3 , C_or_D , B) ;

or w1
G2

G5 (y ,CD , C_or_D__bar ) , G7

G6 (C_or_D , C , D) , G11 w2
B_bar G3

G7 (x , w1 , w2) ,

G8 (w , w3 , A) ; G4
W3
not G8

G9 (z , D) ,

G10 ( C_or_D__bar , C_or_D ) ,

G11 (B_bar , B) ;

endmodule

module ex42_b ( x , y , z , w , A , B , C , D ) ;

output x , y , z , w ;

input A , B , C , D ;

assign z = ~D ;

assign y = (C &D) | ( (~C) & (~D) ) ;

assign x = (~B&C) | (~B&D) | (B&~C&D) ;

assign w = A | (B&C )| (B&D ) ;

endmodule

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