Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 1
AIM:
Simulate the frequency and transient response of a first-order RC circuit.

SOFTWARE USED: MULTISIM

THEORY:
The RC circuit shown in Fig. 1 is a low pass filter having a 3-dB cut-off frequency, f c

where 𝑓 =

Figure 1 RC Circuit under consideration

Figure 2Output of frequency analysis for the RC circuit

A capacitor can store an electrical charge and energy. The voltage across the capacitor is related to the
charge by the equation V=Q/C for steady-state values, or expressed as an instantaneous value dv=dq/C

We will study the transient response of the RC circuit, which is the response to a sudden change in
voltage.

In this experiment, we apply a pulse waveform to the RC circuit to analyze the transient response of the circuit.
The pulse-width relative to a circuit’s time constant determines how it is affected by an RC circuit.

Time Constant (τ): A measure of time required for certain changes in voltages and currents in RC and
RL circuits. Generally, when the elapsed time exceeds five-time constants (5τ) after switching has
occurred, the currents and voltages have reached their final value, which is also called a steady-state
response.

The time constant of an RC circuit is the product of equivalent capacitance and the Thévenin resistance
as viewed from the terminals of the equivalent capacitor.
Analogue Electronics Lab 15B17EC471

τ = RC (1)

A Pulse is a voltage or current that changes from one level to the other and back again. If a waveform’s
high time equals its low time, it is called a square wave. The length of each cycle of a pulse train is
termed it's period (T).

The pulse width (tp) of an ideal square wave is equal to half the period. The relation between pulse
width and frequency is then given by,

𝑓= (2)

From Kirchoff’s laws, it can be shown that the charging voltage VC (t) across the capacitor is given by:
𝑉 (𝑡) = 𝑉 1 − 𝑒 , 𝑡≥0 (3)
Where, V is the applied source voltage to the circuit for t ≥ 0. τ =RC is the time constant.
The response curve, showing capacitor charging for Series RC circuit to a step input with
time axis normalized by τ is shown in Fig. 3.

Figure 3Voltage across capacitor during charging

The discharge voltage for the capacitor is given by:

𝑉 (𝑡) = 𝑉 𝑒 , 𝑡 ≥ 0 (4)

Where Vois the initial voltage stored in the capacitor at t = 0, and τ=RC is time constant. The response
curve is a decaying exponential as shown in Fig. 4.

Figure 4Voltage across capacitor during discharging

Analogue Electronics Lab 15B17EC471

Figure 5RC circuit for Transient Analysis

Figure 6Transient response for the RC circuit with tp = 0.5τ

Figure 7Transient response for the RC circuit tp = 5τ

Figure 8Transient response for the RC circuit tp = 15τ

PROCEDURE:
Frequency response

1. Apply 1V ac voltage at the input using a function generator.

2. Plot output voltage magnitude (in dB) versus frequency.
3. Calculate Cut-off frequency.
Analogue Electronics Lab 15B17EC471

Transient Response

1. Set up the circuit shown in Fig. 5 with the component values R = 1 kΩ and C =1 µF.
2. Use a pulse voltage signal and apply it as the input voltage to the circuit as shown in Fig. 5.
3. Observe the input square wave on channel 1 and output, across the capacitor, on channel 2 of the
CRO. Set the volt/div same for both the channels.
4. Observe the response of the circuit for the following three cases and record the results.
a) tp>> 5τ: Set the frequency of the function generator output such that the capacitor has enough
time to fully charge and discharge during each cycle of the square wave. So Let t p = 15τ and
accordingly set the function generator frequency. Determine the time constant from the
waveforms obtained on the CRO. (At t= τ, Vc(t) =0.63Vo )
b) tp = 5τ: Set the frequency such that tp = 5τ. Since the pulse width is exactly 5τ, the capacitor
should just be able to fully charge and discharge during each pulse cycle. From the figure
determine τ.
c) tp<< 5τ: In this case, the capacitor does not have time to charge significantly before it is switched to
discharge and vice versa. Let tp = 0.5τ in this case and set the frequency accordingly.

RESULT:
Cur-off Frequency=

PRECAUTIONS:

LEARNING OUTCOMES:
Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 2
AIM:
Implement a discrete BJT circuit on breadboard to check the dependence of β dc on the collector bias
current

APPARATUS REQUIRED:
S.No Apparatus Quantity
1 Multimeter 2
2 DC Regulated Power Supply 1
3 Bread Board 1

COMPONENT REQUIRED:

S.No Apparatus Specifications Quantity

1 Transistor BC547 1
2 Potentiometer 100k 1

THEORY:

XMM1

XMM2

VCC
10 V
50% Q1

VBB Potentiometer
1V Key = A BC547BP
100kΩ

Figure 9 Circuit Diagram

Analogue Electronics Lab 15B17EC471

350

300

250

200

β
150

100

50

0
0 10 20 30 40 50 60
Ic (mA)

Figure 10 βdc Dependence on IC

In the above graph, we can see that with increasing collector current βdc is becoming saturated. Thus,
to operate at the maximum value of βdc (i.e. βdc = 330) at VCE =10V BJT must be biased at IC=9.9
mA. Since increasing the bias current of the transistor increases power dissipation, it is clear from the
graph that the choice of collector current IC is a trade-off between current gain βdc and power
dissipation.

PROCEDURE:
1. Complete the circuit as shown in figure.
2. Vary the resistance variable to change the IB value and note corresponding IC through the
transistor.

OBSERVATION TABLE:

IB (mA) IC (mA) βdc= IC/ IB

RESULT:
PRECAUTIONS:
LEARNING OUTCOMES:
Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 3
AIM:
Implement and compare BJT based biasing techniques such as voltage divider, collector to base bias
and fixed bias for DC “Q- point” stability on breadboard.

APPARATUS REQUIRED:
S.No Apparatus Specifications Quantity
1 DC Regulated Power Supply 1
2 Bread Board 1
3 Multimeter 1

COMPONENTS REQUIRED:
S.No Apparatus Specifications Quantity
1 Resistor 1K 2
2 Resistor 470k,225k,11k,100Ω 1
3 Transistor SL100 3

THEORY:
CASE (A): Base Biasing (Fixed Biasing)

CIRCUIT DIAGRAM:

Figure 11 Schematic Diagram of Fixed Biasing

Given

Supply Voltage (VCC) = 12 V Collector

Current (IC) = 4mA Collector Resistance

(RC) = 1KΩ Base Resistance (RB) = 470

KΩ
Analogue Electronics Lab 15B17EC471

Now, we have to calculate the output voltage (VCE) and other current and voltages across
resistors and then compare the variation of the values with other biasing techniques.

CASE (B): Collector-Base Biasing

CIRCUIT DIAGRAM:

Figure 12 Schematic Diagram of Collector-Base Biasing

Given

Supply Voltage (VCC) = 12 V Collector

Current (IC) = 4mA Collector Resistance

(RC) = 1KΩ Base Resistance (Rf) = 225

KΩ

Now, we have to calculate the output voltage (VCE) and other current and voltages across
resistors and then compare the variation of the values with other biasing techniques.

CASE (C): Voltage Divider Biasing

CIRCUIT DIAGRAM:

Figure 13 Schematic Diagram of Voltage Divider Biasing

Analogue Electronics Lab 15B17EC471

Given

Supply Voltage (VCC) = 12V Voltage

Gain (Av) = 10 Collector Current (IC)

=4mA

In this case, first, we have to find out the values of the resistors R 1 and R2.

PROCEDURE:

Voltage gain is defined as- Av = RC

/ (RE + re)

Since Av is given to be 10, So we

can write

Av = RC/(RE) ---(Equation-1)

=> RC = 10 RE

Let

RE = 100 Ω

=> RC = 1 KΩ

The max. value of collector current (ICmax) can be calculated as ICmax =

VCC / (RC + RE)

=>ICmax = 10.91 mA

So we can design the circuit for IC = 4mA.

Now, the voltage drop across RC (VRC) = (1 KΩ) * (4mA)

= 4V

and the voltage drop across RE (VRE) = (100 Ω) * (4mA)

= 0.4V

So, VCE = 12 – (4 + 0.4) V = 7.6V

Potential difference between the base and the ground = (VBE + VRE)

= (0.6 + 0.4)V = 1V
Analogue Electronics Lab 15B17EC471

So, the potential drop across R2 (VR2) = 1V R2 / (R1 +

R2) * VCC = 1V

=>R1=11*R2 ---(Equation-2)

The input impedance Zi is given as- Zi = β*RE

Let β = 150 (typical)

=> Zi = 150*100 Ω

=> Zi = 15 KΩ

Since IB is assumed to be negligible, so most of the part of the current, passing through the resistor
R1, flows through R2.

=> Zi is much higher than R2. In general, R2< Zi / 10

So, here R2< 1.5 KΩ Let us take

R2 = 1 KΩ

=> R1 = 11 KΩ

So, we choose the values of R1 and R2 as R1 = 11

KΩ

R2 = 1 KΩ
Now, we have to calculate the output voltage (VCE) and other current and voltages across
resistors and then compare the variation of the values with other biasing techniques.

OBSERVATION TABLE:

CASE (A): Base Biasing (Fixed Biasing)

VCE VRc R c* Ic VRb R b* Ib β

CASE (B): Collector-Base Biasing

VCE VRc R c* Ic VRf Rf* Ib β

Analogue Electronics Lab 15B17EC471

CASE (C): Voltage Divider Biasing

VCE VRc Rc* Ic VRe Re* Ie Ib β

* measured value of the resistance

RESULT:

PRECAUTIONS:

LEARNING OUTCOMES:
Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 4
AIM:
Implement the single-stage CE amplifier circuit on breadboard to determine the instantaneous node
voltages and branch currents for triangular input Vi = 1.6V (p-p) using a discrete transistor. Also,
determine the maximum amplitude of Vi whichis allowed to be used in the amplifier.

APPARATUS REQUIRED:
S.No Apparatus Quantity
1 CRO 1
2 DC Regulated PowerSupply 1
3 Bread Board 1
4 Multimeter 1
5 Function Generator 1

COMPONENT REQUIRED:

S.No Apparatus Specifications Quantity

1 Transistor BC547 1
2 Resistor 3k, 100k 1

THEORY:

All types of transistor amplifiers operate using AC signal input which alternates between a positive and
a negative value. Biasing is very important in amplifier design as it establishes the operating point of
the transistor amplifier ready to receive signals, thereby reducing any distortion of the output signal.

An NPN or PNP transistor works as an amplifier only if it is in the active mode of operation. In cut-off
and saturation mode, it works as a switch. So if we apply small voltage signals at the input then we get
an amplified version at the output of BJT when it is in the active region. For the computation of
amplification, we divide the analysis of the circuit in two parts dc analysis. The total output is the sum
of the two responses individually. The amplification process is used to amplify the low-quality signal
like the voice signal at the receiver side to amplify. Voltage Gain is the ratio of the amplitudes of output
to that of the input voltage signal represented by A V.

𝑣
𝐴 =
𝑣
Analogue Electronics Lab 15B17EC471

Figure 14 Discrete transistor amplifier with triangular input signal

Applying KVL in emitter loop

−𝑉 +𝑅 𝐼 +𝑉 =0

𝑉 =𝑅 𝐼 +𝑉

Fig. 2 shows the input signal (a triangular wave) with 1.6 (p-p V) 1000Hz along with corresponding
output signal. From the Fig. 2, it is clear that output waveform is clipped from the top. There can be
two possibility of the clipped output. First, the Q-point is not in the mid of the active region. Second,
the input signal does not satisfy the small signal characteristics for BJT.

Figure 15 Traingular input signal and corresponding output signal

Figure 16 Undistorted output Signal

Analogue Electronics Lab 15B17EC471

PROCEDURE:
Now vary (decrease) the amplitude of triangular input signal to get the undistorted output signal (shown
in Fig. 3) and hence determine the maximum amplitude of V i which is allowed to be used in the given
amplifier circuit.

RESULT:
PRECAUTIONS:
LEARNING OUTCOMES:
Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 5
AIM:
Implement a single stage BJT amplifier on breadboard for given specifications (f L=10 kHz).

APPARATUS REQUIRED:

S. No. Apparatus Quantity

1 DC Regulator Power Supply 1
2 Bread Board 1
3 Function Generator 1
4 Multi Meter 1

COMPONENT REQUIRED:

S.No. Apparatus Specifications Quantity

1 Resistor - -

2 Capacitor - -

3 Transistor BC547 2

THEORY:
Single Stage Amplifier means an amplifier which has only one amplifying stage or having only one
transistor to amplify the signal. Potential divider bias circuit is based on CE configuration which has
high voltage gain (Av), high current gain (Ai). This configuration is used for the audio frequency
range.

Given:

Supply Voltage (VCC) = 12 V

Voltage Gain (Av) = 10
Collector Current (IC) = 2mA
Step 1: DC analysis
Analogue Electronics Lab 15B17EC471

Figure 17 Amplifier Circuit for DC Analysis

The maximum value of collector current (ICmax) can be calculated as

ICmax= VCC / (RC + RE)
As ICmax= 2 Ic
4mA=12/ (RC + RE)
(RC + RE) = 3 kΩ (eq. 1)

Figure 18 Voltage drop across collector and source resistance

As per potential drop shown in above figure

RC = 4 R E
Putting the value in eq. 1
5 RE = 3000
RE = 600Ω
RC =2.4 kΩ
Potential at nod A= Ve+0.6
=(Ie*Re) + 0.7
=(Ic*600)+ 0.7
Analogue Electronics Lab 15B17EC471

=(2mA*600)+0.7
=1.2+0.7 = 1.9V
Now 1.9 = 12 * (R2 / (R1 + R2) (eq. 2)
The input impedance Zi is given as-
Zi = β*RE
Let β = 150 (typical)
=> Zi = 150*600 Ω
=> Zi =90 kΩ
Since IB is assumed to be negligible, so most of the part of the current, passing through the resistor
R1, flows through R2.
=> Zi is much higher than R2.
In general, R2 < Zi / 10
So, here R2 < 9 kΩ
Let us take R2 =6.8 kΩ
Putting this value in (eq. 2)
=> R1 = 36.14 kΩ
So, we choose the values of R1 and R2 as
R1 = 36.14 kΩ
R2 =6.8 kΩ
Step2: AC Analysis
Voltage gain is defined as-
Av = RC / (RE + re)
re = Vth/Ic = 26mV/2mA = 13Ω

100 = 2.4K / (RE + 13)

RE = 227 Ω
As per DC analysis RE = 600Ω
So we have to reduce the value of RE to 227 for the desired gain
To make the 600Ω, 227Ω fo Ac analysis we will connect two resistance in series and capacitor in
parallel with the same resistance RE = 600Ω as shown in figure
Analogue Electronics Lab 15B17EC471

Figure 19 Emitter resistance distribution

Calculation of the value of Bypass capacitor Now we consider the frequency at which we require
the desired gain 10.
Let the frequency is 10 kHz.
Xc=1 / 2 * π f C
C= 1/ 2*3.14*10k*7Ω
C=2.27 uF
Calculation of Coupling Capacitor:

Figure 20 Equivalent Circuit for Cc1 calculation

Figure 21 Equivalent Circuit for Cc2 calculation

Figure 22 Complete Amplifier Circuit

Analogue Electronics Lab 15B17EC471

RESULT:

PRECAUTIONS:

LEARNING OUTCOMES:
Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 6
AIM:
Implement/simulate the frequency response of the Common source amplifier using N- channel
MOSFET. Determinea) Upper, lower 3-dB frequency b) Bandwidth

SOFTWARE USED: MULTISIM

THEORY:

Figure 23 Circuit Diagram of CS amplifier

For the CS amplifier shown in fig. 1 let us assume single-source resistance Rsig=10K, a load resistance
RL=50K and a bypass coupling capacitor of 10uF. The targeted specification for the CS Amplifier is a
mid-band gain Am=10 V/V and maximum power consumption of P=1.5 mW.
With a 3.3 V power supply; the drain current of MOSFET must be limited to
ID=P/VDD=1.5mW/3.3V=0.45mA to meet the power consumption specification.
RD is calculated based on the desired voltage gain:
|Av|=gm(RD||RL||ro)=10V/V==> RD~=4.2 kΩ
Where gm=3.0 mA/V and ro=22.2 kΩ. Hence the output bias voltage is
Vo= VDD-IDRD=1.39 V. An Rs= (Vo- VDD/3)/ID=630 Ω is needed to bias the MOSFET at VDS=VDD/3.
Finally, resistors RG1=2 MΩ and RG2=1.3 MΩ are chosen to set the gate bias voltage at
VG=IDRS+VOV+Vtn~=1.29 V. Using large values for these gate resistors ensures that both their power
consumptions and the loading effect on the input signal source are negligible.

PROCEDURE:

1. Perform a bias-point simulation to verify that the MOSFET is properly biased in the saturation
region and the dc voltage and currents are within the desired specifications.
2. Apply a 1-V AC voltage at the input.
Analogue Electronics Lab 15B17EC471

3. Perform an AC analysis simulation and plot the output voltage magnitude (in dB) versus
frequency.
4. Measure the mid-band gain Am and the 3- dB frequencies fL and fH

OBSERVATION TABLE:
a) Upper, lower 3-dB frequency
b) Bandwidth:

RESULT:

PRECAUTIONS:

LEARNING OUTCOMES:
Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 7
AIM:
Design and implement a basic BJT current mirror on breadboard using a discrete transistor for
reference current of 1mA

APPARATUS REQUIRED:

S. No. Apparatus Quantity

1 CRO 1
2 DC Regulator PowerSupply Bread 1
3 Board 1
4 Function Generator 1
5 Multi Meter 1

COMPONENT REQUIRED:

S. No. Apparatus Specifications Quantity

1 Resistor 4.7k 1
2 Potentiometer 5k 1
3 Transistor Q2N3904 1

THEORY:
Figure 1 shows the basic current mirror. It is consisting of two matched transistors with their base and
emitter connected together. The transistor in the circuit is transformed into a diode by short-
circuiting the collector and the base of Q1 & Q2.

Figure 24 Current Mirror Circuit

In the current mirror circuit, reference current to the mirror IREF is determined by a Resistor R
which is connected to the positive power supply V CC. The current IREF is given by

𝑉
−𝑉
𝐼 = (1)
𝑅
The output current is taken from the collector of Q2. The transistor Q2 must be kept active all
the time by keeping its collector voltage higher than that of the base.
Consider the following assumptions for current mirror:

-The two transistors are perfectly matched

Analogue Electronics Lab 15B17EC471

-Finite  and Early effects are neglected.

I REF  I C 1  I B 1  I B 2
  1 I B1  I B1  I B 2
 (  1  1) I B 1  I B 2 (If both the transisto r are matched then I B1  I B2 )
 (  1  1) I B 2  I B 2
 (  1 2 ) I B 2
1  2
 IC2
2
2
IC 2  I
 1  2 REF
If  1   2   then
1
IC 2  I REF (2)
1 2


If β is very high then the output mirror current will be equal to the input reference current

I O  I C 2  I REF . (3)

The circuit will operate as a constant current mirror as long as Q 2 remains in the active region, or
VCB  VBE .

CURRENT GAIN and ACCURACY

The current gain is the ratio of the output current to the input current. For ideal current mirror,
with identical transistors, the current gain is unity (neglecting the early effect). The practical
current mirror has a ratio close to unity.

PROCEDURE:
1) Build the circuit shown in Fig. 1 using the transistor Q2N3904.
2) Set Vcc = 20V,
3) Calculate the value of R for given Io.
4) Use the DMM to measure the DC voltages across RL for at least 5 different values of
RL.

OBSERVATION TABLE:
Rref = ……
Iref = …….

S. No. RL IL
Analogue Electronics Lab 15B17EC471

RESULTS:

PRECAUTIONS:

LEARNING OUTCOMES:
Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 8
AIM:
Implement/simulate a Wilson current mirror of 1mA. and determine the output resistance and current
gain error

APPARATUS REQUIRED:

S. No. Apparatus Quantity

1 CRO 1
2 DC Regulator PowerSupply Bread 1
3 Board 1
4 Function Generator 1
5 Multi Meter 1

COMPONENT REQUIRED:

S. No. Apparatus Specifications Quantity

1 Resistor 4.7k 1
2 Potentiometer 5k 1
3 Transistor Q2N3904 1

THEORY:
Fig. shows the Wilson current mirror. It is consisting of three matched transistors.

In the current mirror circuit, reference current to the mirror IREF is determined by a Resistor
RREF which is connected to the positive power supply V CC. The current IREF is given by

𝑉
−𝑉
𝐼 =
𝑅
The output current is taken from the collector of Q3.
The following assumptions have been considered for current mirror:
 The three transistors are perfectly matched
Analogue Electronics Lab 15B17EC471

 Early effects are neglected.

The characteristics and the behavior of the current mirror will be determined according to the
followings:
 Current gain accuracy.
 Output resistance.

Clearly the Wilson current mirror which uses an additional current amplifier at the output is much
better that the simple current source.

We shall explain in brief one of the above points which are relevant to our experimental procedures.

CURRENT - GAIN ACCURACY AND OUTPUT RESISTANCE

The current gain is the ratio of the output current to the input current. For ideal current mirror,
with identical transistors, the current gain is unity (neglecting the early effect). The practical
current mirror has a ratio close to unity.

PROCEDURE:
5) Build the circuit shown in fig. using the transistor Q2N3904.
6) Set Vcc = 20V,
7) Calculate the value of R for given Io.
8) Use the DMM to measure the DC voltages across RL for at least 5 different values of
RL.

OBSERVATION TABLE:
Rref = ……
Iref = …….

S. No. RL IL

RESULTS:

PRECAUTIONS:

LEARNING OUTCOMES:
Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 9
AIM:
Implement/simulate a single-stage differential amplifier and determine the following:
a) Frequency response of differential gain Ad.
b) Frequency response of common-mode gain ACM.
c) Common Mode Rejection Ratio (CMRR).

APPARATUS REQUIRED:

S. No. Apparatus Quantity

1 CRO 1
2 DC Regulator PowerSupply Bread 1
3 Board 1
4 Function Generator 1
5 Multi Meter 1

COMPONENT REQUIRED:

S. No. Apparatus Specifications Quantity

1 Resistor 20K, 20K, 3K, 2.3K, 15.7K, 3K, 28.6K 1 Each
2 Transistor Q2N3904 11
3 Transistor Q2N3905 1

THEORY:
UsingEquationof transistorQ9forthecircuitshowninfig.1

28.6(2Ic/β + IC ) =0.7 V

We get the collector current through Q9 to be 0.5mA. Then we see that transistor Q 3 conduct
.5mA and transistor Q6 conducts 2mA. The current shows transistor Q3 feeds the differential pair
(Q1, Q2) with .5 mA. Thus each of Q1 and Q2 will be biased at .25mA. The collector of Q1 and Q2 will
be at (+15- 0.25*20) =+10V.
Analogue Electronics Lab 15B17EC471

Fig. 1

Fig.2

Proceeding to the second differential stage formed by Q4 and Q5, we find the voltage at their emitter
to be (+10-0.7)=9.3V. This differential pair is biased by the current source transistor Q6 which
supply a current of 2 mA thus Q4 and Q5 will each be biased at 1mA. We can now calculate the
voltage at collector of Q5 as (+15-1*3) = +12V. This will cause the voltage at the emitter of PNP
transistor Q7 to be (+15-12.7)/2.3=1mA.
Analogue Electronics Lab 15B17EC471

The collector current of Q7, 1mA cause the voltage at the collector to be (-15+1*15.7)=+0.7
V. The emitter of Q8 will be 0.7 V below the base thus output terminal will be at 0 Volt.
Finally the emitter current of Q8 can be calculated to be[0-(-15)]/3=5mA.

The upper limit on the input common mode voltage is determined by the voltage at which Q1
and Q2 leave the active mode and enter saturation. These will happen if the input voltage exceeds the
collector voltage which is +10 V by about .4V thus the upper limit of the common mode is +10.4 V.
The lower limit of the input common mode range is determined by the voltage at which Q3
leaves the active mode and thus ceases to act as a constant current source. This will happen if the
collector voltage of Q3 goes below the voltage at its base which is -14.3 volt by more than .4 V.
It follows that the input common mode voltage should not go lower than (-14.7+.7)=-14V.

Figures 3, 4 and 5 shows the large-signal differential transfer characteristics, frequency response
and common mode transfer characteristics respectively for multistage differentialamplifier.

Fig. 3
Analogue Electronics Lab 15B17EC471

Fig. 4

Fig. 5

PROCEDURE:

Part A
1. Perform a DC analysis with the differential voltage input Vd (shown in fig. 2
swept over the range –VEE to +VCC.
2. Plot the corresponding output voltage Vout. The slope of the
characteristics corresponds to the differentials gain of the amplifier.
Analogue Electronics Lab 15B17EC471

Part B

1) Set the differential input voltage Vd to be a 1-V ac signal (with 0-V dc level).
2) Perform AC analysissimulation.
3) Plot the output voltage magnitude |Vout| versus frequency.
4) Calculate fH.

Part C

Perform a DC analysis simulation with the input common mode voltage swept over the range –
VEE to VCC while maintaining Vd constant at –Vos in order to cancel the output offset voltage.
1) Draw the graph between Vout and VCM.
2) Find the input common mode range.

OBSERVATION TABLE:

PART A: Large signal differential transfer characteristic

S. No. Vd(V) Vo(V)

PART B: Midband gain =

fH=

PART C: Large signal common mode transfer characteristics.

S. No. VCM(V) Vo(V)

RESULT:

PRECAUTIONS:

LEARNING OUTCOMES:

ECE, JIIT 31
Analogue Electronics Lab 15B17EC471

EXPERIMENT NO. 10
AIM: Implement and validate applicability of Op-Amp on breadboard using 741 IC in different
applications (Integrator and Differentiator)

APPARATUS AND COMPONENTS REQUIRED:

SL NO. Apparatus and components required Quantity

1. CRO 01
2. Function Generator 01
3. Capacitor 0.1µf, 0.01µf,1nf 01
4. Resistance 10k, 22k 02
5. IC741 01

THEORY:
Integrator: A circuit in which the output voltage is the integration of the input voltage is called an
integrator.
In the practical integrator to reduce the error voltage at the output, a resistor R F is connected
across the feedback capacitor CF. Thus, RF limits the low-frequency gain and hence minimizes the
variations in the output voltage

Figure 25 Frequency Response of Integrator

ECE, JIIT 32
Analogue Electronics Lab 15B17EC471

The frequency response of the integrator is shown in the fig. 2.1. f b is the frequency at which the
gain is 0 dB and is given by
fb = 1/2π R1Cf.

In this fig. there is some relative operating frequency, and for frequencies from f to
fa the gain RF/R1 is constant. However, after fa the gain decreases at a rate of 20 dB/decade.
In other words, between fa and fb the circuit of fig. 2.1 acts as an integrator. The gain-
limiting frequency fa is given by

fa = 1/2π RfCf.

Normally fa<fb. From the above equation, we can calculate Rf by assuming fa & Cf.
This is very important frequency. It tells us where the useful integration range starts.

If fin < fa - circuit acts like a simple inverting amplifier and no integration results,

If fin = fa - integration takes place with only 50% accuracy results,

If fin = 10fa - integration takes place with 99% accuracy results.

In the circuit diagram of Integrator, the values are calculated by assuming fa as 50

Hz. Hence the input frequency is to be taken as 500Hz to get 99% accuracy results.

ECE, JIIT 33
Analogue Electronics Lab 15B17EC471

INTEGRATOR:

EXPECTED WAVEFORM

PROCEDURE:
1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply sine wave at the input terminals of the circuit using function Generator.
4. Connect channel-1 of CRO at the input terminals and channel-2 at the
output terminals.
5. Observe the output of the circuit on the CRO which is a cosine wave (90o phase
shifted from the sine wave input) and note down the position, the amplitude and
the time period of Vin & Vo.
6. Now apply the square wave as input signal.
7. Observe the output of the circuit on the CRO which is a triangular wave and
note down the position, the amplitude and the time period of Vin & Vo.
8. Plot the output voltages corresponding to sine and square wave inputs.

ECE, JIIT 34
Analogue Electronics Lab 15B17EC471

DIFFERENTIATOR:

As the name suggests, the circuit performs the mathematical operation of

differentiation, i.e. the output voltage is the derivative of the input voltage.

Both the stability and the high-frequency noise problems can be corrected by the
addition of two components: R1 and Cf, as shown in the circuit diagram. This circuit is a
practical differentiator.

The input signal will be differentiated properly if the time period T of the input
signal is larger than or equal to RfC1. That is, T>= RfC1
Differentiator can be designed by implementing the following steps.

1. Select fa equal to the highest frequency of the input signal to be differentiated.

2. Then, assuming a value of C1<1 µF , calculate the value of Rf
3. Calculate the values of R1and Cf so that R1C1=RfCf.

ECE, JIIT 35
Analogue Electronics Lab 15B17EC471

PROCEDURE:

1. Connect the components/equipment as shown in the circuit diagram.

2. Switch ON the power supply.
3. Apply sine wave at the input terminals of the circuit using function Generator.
4. Connect channel-1 of CRO at the input terminals and channel-2 at the
output Terminals.
5. Observe the output of the circuit on the CRO which is a cosine wave (90o phase
Shifted from the sine wave input) and note down the position, the amplitude
and the time period of Vin & Vo.
6. Now apply the square wave as input signal.
7. Observe the output of the circuit on the CRO which is a spike wave and note
down the position, the amplitude and the time period of Vin & Vo.
8. Plot the output voltages corresponding to sine and square wave inputs.

EXPECTED WAVEFORM

RESULT:

LEARNING OUTCOME

ECE, JIIT 36