DESIGN AND ANALYSIS OF INNOVATIVE RF

MIXERS AND PHASE CONTROL CIRCUITS

HU ZIJIE

(M.Eng., Huazhong University of Science and Technology, China)

(B.Eng., Harbin Institute of Technology, China)

A THESIS SUBMITTED
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
NATIONAL UNIVERSITY OF SINGAPORE
2013
Dedicated to My Beloved Parents
 DECLARATION

I hereby declare that this thesis is my original work and it has been written by me in its

entirety. I have duly acknowledged all the sources of information which have been used in

the thesis.

This thesis has also not been submitted for any degree in any university previously.

_____________________________

Hu Zijie

4 November 2013
 Acknowledgements

First of all, I would like to express my deepest appreciation to my supervisor,

assistant professor Dr. Koenraad Mouthaan, who has led me into the interesting world of

microwave circuit design, and given me full support for my research and study. He has

continually provided me with patient guidance, invaluable advice and the opportunity to

improve my academic and engineering skills. His scientific attitude influences me a lot,

especially on forming my own style of research methodology, and helps me to

systematically and thoroughly look into problems. I believe what I have learnt from him

will always lead me ahead. I also want to thank my co-supervisor, associate Professor

Chen Xudong, for his encouragement on my research and discussion of the related topics.

I would also like to express my appreciation to other faculty staff in the NUS

Microwave & RF group: Prof Leong Mook Seng, Prof Yeo Swee Ping, Prof Yeo Tat Dr.

Hui Hon Tat, for their generous support and encouragement throughout the course of my

Ph.D. studies.

Thanks also to several students from the lab for their generous assistance with my

research-related problems and for being good partners in various physical exercises. First,

and foremost I would like to thank Tang Xinyi, Azadeh Taslimi, Chen Ying, and Lu

Xiaoming for their never-ending willingness to give time for assistance and discussions

regarding the designs and measurements over the four years we spent together in the lab.

I'd like to thank my other friends in the lab, namely Nan Lan, Dalpatadu K Radike

i
Samantha, Hu Feng, Ji Yuancheng, Ray Fang Hongzhao, Winson Lim, Zhong Zheng, for

their encouragement and assistance over these years. I will always remember my friends

for all the fun we had and will definitely miss the hot-pots and Japanese food buffet get-

together, squash matches, and mahjong.

I am truly grateful to Madam Lee Siew Choo, Madam Guo Lin, and Mr. Sing Cheng

Hiong, for their help in the fabrication and the measurement of microwave circuits during

the past four years.

Last but not least, I thank my parents, who always unconditionally support me and

love me. They are the source of my strength and I will forever be grateful.

ii
 Table of Contents

Abstract vii

List of Figures ix

List of Tables xiv

List of Abbreviations xv

Chapter 1 Introduction 1

1.1 Motivation 1

1.2 Scope and Thesis Overview 6

1.3 List of Publications 10

Chapter 2 Literature Review 12

2.1 Wireless Communication System Architecture 12

2.1.1 Superheterodyne Architecture2. 12

2.1.2 Direct-Conversion Architecture 13

2.2 Mixer Circuit Review 17

2.2.1 Overview of Fundamental Mixers 17

2.2.2 Subharmonic Mixers 25

2.2.3 Image-Rejection Mixers 29

2.2.4 Mixer Performance Parameters 31

iii
Chapter 3 Design and Stability Analysis of a Low Voltage Subharmonic Cascode

FET Mixer 39

3.1 Introduction 39

3.2 Fundamental Mixer Using Cascode FET Cell 41

3.2.1 Principle of Mixing Process 42

3.2.2 Circuit Analysis 44

3.3 Proposed SHM based on the conventional cascode FET cell 46

3.3.1 Mixer Configuration 46

3.3.2 Analysis of Mixing Principle 49

3.3.3 Discrete Design Verification and Discussion 51

3.4 Stability Analysis on the Proposed Class-B SHM 55

3.4.1 Large Signal Stability Analysis 55

3.4.2 Odd-Mode Equivalent Circuit Analysis 59

3.4.3 Experiments and Stabilization Technique 67

3.4.4 Summary 70

3.5 Conclusions and Recommendations 70

Chapter 4 1-10 GHz RF and Wideband IF CMOS Gilbert Mixer with Cross-

Coupled Feedback 72

4.1 Introduction 72

4.2 Design Considerations of the Proposed Wideband Mixer 75

4.2.1 The Cross-Coupled Common Gate RF Stage 76

4.2.2 Conversion Gain Flattening Technique 81

iv
 4.2.3 Wideband Active Baluns for the LO Port and IF Port 84

4.3 Chip Implementation and Measurement Results 89

4.4 Conclusions and Recommendations 96

Chapter 5 CMOS Wideband Vector-Sum Phase Shifter with Over 400° Phase

Control Range 98

5.1 Introduction 98

5.2 Wideband VGA with Linear-in-magnitude Controlled Gain 101

5.2.1 Design Considerations of the Proposed VGA 102

5.2.2 Circuit Implementation and Experimental Results 106

5.2.3 Conclusions 109

5.3 Wideband Phase-reversible VGA with Linearly Controlled Gain 110

5.3.1 Motivation 110

5.3.2 Design Considerations of the Phase-reversible VGA 112

5.3.3 Measurement Results and Discussion 123

5.3.4 Conclusions 128

5.4 A 2-16 GHz Vector-Sum Phase Shifter with Over 400 Phase Range 129

5.4.1 Introduction 129

5.4.2 System Overview 131

5.4.3 Design Considerations of Circuit Blocks 134

5.4.4 Measurement Results 146

5.4.5 Conclusions 153

Chapter 6 Conclusions and Recommendations 155

v
 6.1 Summary 155

6.2 Review of Contributions 156

6.3 Recommendations 159

References 161

vi
 Abstract

Exciting new opportunities are envisioned for wireless communication circuits that

are capable of operating at higher frequencies with wider bandwidth. However, the higher

frequencies and wideband operations lead to numerous design challenges in microwave

and millimeter-wave integrated circuits (ICs) that are not present or not significant at

lower frequencies or narrower bandwidths. This thesis aims to propose and realize

innovative circuit topologies and techniques in order to overcome above-mentioned

design challenges in key building blocks of RF front-ends.

Subharmonic mixers are employed in superheterodyne systems as a method of

reducing the local oscillator frequency, which eases the need for high frequency local

oscillator (LO). Moreover, the large-signal stability is another key issue for any RF active

mixer design as the mixer is a strongly nonlinear device, which has rarely been

investigated previously. Therefore, this thesis first explores and investigates the design

and stability analysis of a 2× subharmonic mixer. Here, a novel biasing scheme is

proposed to realize a low voltage subharmonic cascode FET mixer with relaxed LO

power requirements. A systematic stability analysis is subsequently performed on the

proposed subharmonic mixer, which successfully predicts and eliminates the potential

parametric oscillations. The feasibility of the technique is demonstrated in a discrete

design as a proof of concept.

vii
 To address design issues of mixers with both wide-RF and wide-IF bandwidths, a

new Gilbert-cell mixer is proposed, together with on-chip active LO and IF baluns.

Wideband techniques are proposed to simultaneously improve the RF and IF bandwidths,

conversion gain, as well as the input- and output-matching. The monolithic microwave

integrated circuit (MMIC) proof of concept is realized in a standard 0.13-µm CMOS

process. The RF bandwidth from 1 to 10 GHz is achieved with a conversion gain of

5.5±2.5 dB, while a conversion gain variation less than 2 dB is measured throughout the

IF bandwidth from 100 MHz to 1 GHz.

The RF phase shifter, used for beam-steering in phased array systems, is preferable

to provide 360° phase shifting and maintain a constant amplitude within a certain

bandwidth. In previous works of the 360°vector-sum phase shifter, the fully differential

topology is typically adopted, which requires an input balun, switches and a digital-to-

analog converter (DAC). In this thesis, a novel and simple scheme is proposed based on

the phase-reversible variable gain amplifier (VGA), in order to realize the single-ended

360ºvector-sum phase shifter. Furthermore, a compact DC control circuit is proposed to

accomplish a continuously adjustable output phase. A wideband prototype is

implemented in a standard 0.13-µm CMOS process, which successfully realizes a

continuously adjustable phase control range of more than 400ºwith only one DC control

voltage. The CMOS prototype exhibits a measured 3-dB bandwidth of 2-16 GHz, and the

average insertion loss amounts from -5 to -2 dB, associated with all measured states. To

the best of the authors' knowledge, it is the first full-360ºphase shifter demonstrated in

CMOS technology using the single-ended configuration without switches.

viii
 LIST OF FIGURES

1.1 Block diagram of a phased array receiver.

1.2 Block diagram for the vector-sum phase shifter.

2.1 Block diagram of a superheterodyne receiver.

2.2 Block diagram of a direct-conversion receiver.

2.3 LO self-mixing paths.

2.4 Basic structure of a diode mixer.

2.5 Conventional topology of a Gilbert-cell mixer [35].

2.6 Output spectrum of Gilbert-cell mixer.

2.7 Circuit diagram of Gilbert-cell mixer with current bleeding technique.

2.8 Gilbert cell mixer with inductive degenerated transconductors.

2.9 Basic subharmonic mixer circuit used in [49], [51].

2.10 Subharmonic mixer circuit proposed in [50].

2.11 Image rejection architectures: (a) Hartley. (b) Weaver.

2.12 Graphical illustration of linearity parameters.

3.1 Circuit schematic of the single-end cascode FET mixer.

3.2 Transconductance of the lower FET gm(Vd1s1) with LO superimposed.

3.3 Source follower equivalent circuit.

3.4 Proposed balanced SHM based on cascode FET cell.

3.5 The conventional and proposed biasing indicated on the I/V curve.

3.6 Operation of frequency-doubling circuit.

ix
3.7 Proposed SHM circuit and auxiliary generator to detect oscillations (matching

networks and interconnects not shown).

3.8 Input admittance Y(f) at node C with PLO = -6 dBm. The oscillation frequency is

around 4.12 GHz.

3.9 Oscillation frequency versus LO power.

3.10 Circuit diagram for determining the large-signal gm. (a) gm1. (b) gm2.

3.11 Large-signal gm1 and gm2 versus PLO.

3.12 Odd-mode equivalent circuit used for stability analysis.

3.13 Circuit model for deriving input admittance Yleft.

3.14 (a) Calculated c. (b) Calculated Re(Yleft).

3.15 Equivalent circuit for deriving input admittance Yright.

3.16 (a) Calculated Re(Yleft). (b) Calculated Re(Yleft)+ Re(Yright).

3.17 Fabricated SHM with a size of 6 × 6 cm2.

3.18 Spectrum measurement of the oscillation at PLO = -3 dBm.

3.19 The proposed SHM with the damping resistor Rdamp (matching and biasing

networks not shown).

3.20 Re(Y(f)) versus resistance Rdamp.

4.1 Schematic of a conventional Gilbert-cell mixer.

4.2 Block diagram of the proposed mixer.

4.3 Circuit schematic of the proposed mixer core.

4.4 Simulated frequency response of the proposed Gilbert mixer.

4.5 Parasitic capacitance compensated by the interstage inductor at the dominant pole.

x
4.6 Conversion gain frequency response with different inductor models.

4.7 Circuits diagram of the cascode CG and CS balun.

4.8 (a) Simulated phase and gain imbalance of the adopted active balun. (b)

Simulated voltage gains of the two branches.

4.9 Proposed D-to-S converter.

4.10 Microphotograph of the mixer chip (core size: 0.7 × 0.4 mm2).

4.11 Measured and simulated reflection coefficient at RF, LO and IF port.

4.12 Measured conversion gain as a function of the LO power.

4.13 Measured conversion gain versus RF frequency at various IF frequencies.

4.14 Measured port-to-port isolation (LO-to-RF and LO-to-IF) with an LO power of 0

dBm.

4.15 Measured IP1-dB of the proposed mixer for a fixed IF frequency of 200 MHz.

4.16 Measured IIP3 of the proposed mixer for a fixed IF frequency of 200 MHz.

4.17 Measured SSB noise figure versus RF frequency.

5.1 Block diagram of the vector-sum phase shifter.

5.2 Schematic diagram of the proposed VGA (DC biasing and decoupling capacitors

are not shown).

5.3 (a) Traditional Cherry-Hooper amplifier. (b) Proposed buffer stage based on the

modified Cherry-Hooper amplifier.

5.4 Chip micrograph of the VGA.

5.5 Measured |S21| for various control voltages VCTL.

5.6 Magnitude and phase of S21 versus control voltage VCTL.

xi
5.7 Measured |S11| and |S22|.

5.8 Typical architecture of the full 360ºphase shifter [91].

5.9 (a) Block diagram of a full 360º vector-sum phase shifter using the phase-

reversible VGA. (b) Vector diagram of the full-360ºphase control.

5.10 Block diagram of the proposed phase-invertible VGA.

5.11 Schematic diagram of the differential multiplier.

5.12 Schematic diagram of the DC control generator.

5.13 Simulated voltage transfer curve of the DC control circuit.

5.14 Simulated small-signal voltage gain versus the DC control voltage VCTL.

5.15 Simulated phase of the differential voltage gain versus VCTL.

5.16 Schematic diagram of: (a) conventional inductive peaking circuit. (b) peaking

circuit with common-mode suppression.

5.17 Typical layout of the differential center-tapped inductor.

5.18 Schematic diagram of the output buffer.

5.19 Microphotograph of the proposed phase-invertible VGA.

5.20 Simulated and measured |S21|.

5.21 Simulated and measured |S11| and |S22|.

5.22 Measured transmission phase versus control voltage VCTL.

5.23 Equivalent transmission phase versus VCTL.

5.24 Magnitude of S21 versus control voltage VCTL.

5.25 Block diagram of the proposed 360ºvector-sum phase shifter using the phase-

reversible VGA.

xii
5.26 Locus of the output vector with the presence of small common-mode component.

5.27 The current-reuse resistive shunt feedback stage for I/Q path.

5.28 Simulated |S11| and small-signal voltage gain.

5.29 Conventional two-staged folding circuit [108].

5.30 Schematic diagram of the proposed sine-cosine generator.

5.31 Simulated voltage transfer curves of the DC sine-cosine generator.

5.32 Schematic diagram of (a) I-path VGA. (b) Q-path VGA.

5.33 Simulated gain control curves of both I- and Q-path.

5.34 Schematic diagram of the differential summing circuit.

5.35 Simulated small-signal voltage gain at 3 GHz.

5.36 Simulated CMRR versus frequency of the stages after the VGA.

5.37 Simplified schematic of the output buffer stage.

5.38 Microphotographs of: (a) the proposed vector-sum phase shifter. (b) DC control

generator.

5.39 |S11| and |S22| versus frequency.

5.40 Simulated and measured |S21|.

5.41 Measured and simulated RMS amplitude error versus frequency.

5.42 Measured relative phase shift versus frequency.

5.43 Measured and simulated RMS phase error versus frequency.

5.44 Measured input-referred P1-dB versus frequency.

xiii
 LIST OF TABLES

3.1 Performance Summary.

3.2 Reference Table.

4.1 Performance Summary and Reference Table.

5.1 Design Values of Wideband VGA.

5.2 Design Values of Phase-reversible VGA.

5.3 Design Values of Output Buffer.

5.4 Performance Summary of The Proposed Phase-Reversible VGA.

5.5 Comparison Table.

5.6 Design Values of The Proposed Vector-Sum Phase Shifter.

5.7 Performance Summary and Comparison Table.

xiv
 LIST OF ABBREVIATIONS

f Frequency in Hz

ω Frequency in rad/s

fT, ωT Unity current gain frequency, transistor cutoff frequency

fmax, ωmax Maximum frequency of oscillation

fRF Frequency of the radio frequency signal

fLO Frequency of the local oscillator signal

fIF Frequency of the intermediate frequency signal

gm Transconductance

rg Series gate resistance

µn Electron Mobility

AC Alternating Current

ADS Advanced Design System (software from Agilent)

BiCMOS A process with both bipolar and CMOS transistors

BPF Band-Pass Filter

CMOS Complementary Metal-Oxide-Semiconductor

CG Common-Gate

Cgs Parasitic gate-source capacitance

Cgd Parasitic gate-drain capacitance

Cox Gate oxide capacitance

DAC Digital-to-Analog Converter

DC Direct Current

DSB Double Sideband

xv
EM Electromagnetic

FCC Federal Communications Commission

FET Field-Effect Transistor

FOM Figure of Merit

GaAs Gallium arsenide

GSG Ground-Signal-Ground

HEMT High Electron Mobility Transistor

IF Intermediate Frequency

IIP3 3rd Order Input Intercept Point

IMD Intermodulation Distortion

IMD3 3rd Order Intermodulation Distortion

InP Indium Phosphide

IP1-dB Input referred 1 dB Compression Point

IP3 3rd Order Intercept Point

IRR Image Rejection Ratio

LNA Low Noise Amplifier

LPF Low-Pass Filter

LO Local Oscillator

MIM Metal-Insulator-Metal

MMIC Monolithic Microwave Integrated Circuit

MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor

NF Noise Figure

OIP3 Output 3rd Order Intercept Point

OP1-dB Output referred 1-dB Compression Point

xvi
P1-dB 1-dB Compression Point

PA Power Amplifier

PCB Printed Circuit Board

PLL Phase-Locked Loop

Q Quality factor

RF Radio Frequency

RFIC Radio-Frequency Integrated Circuit

RMS Root-Mean-Square

SAW Surface Acoustic Wave

SDR Software-Defined Radio

SHM Subharmonic Mixer

SiGe Silicon germanium

SoC System-on-Chip

SSB Single Sideband

UWB Ultra-Wideband

VCO Voltage-Controlled Oscillator

VGA Variable Gain Amplifier

Vth FET threshold voltage

W Transistor gate width

WLAN Wireless Local Area Network

L Transistor gate length

xvii
Chapter 1

Introduction

1.1 Motivation

The trend towards faster and more robust wireless communications as well as

extended functionality has provided a direct impetus for the development of RF front-end

circuits and systems. At the same time, the demand for increasing data rates through

wireless communication channels necessitates RF front-end systems capable of handling

signals occupying larger bandwidths at higher frequencies. Thus, the primary motivation

of this thesis is to demonstrate innovative RF front-end circuits especially catering to

microwave and wideband applications.

In addition to the need to increase the performance of wireless communication

systems, the desire to reduce costs is universal as well. Over the past 20 years there has

been a tremendous interest in the use of CMOS technology for RF and microwave

circuits (often referred to as RF CMOS). There are significant benefits that can be

derived from the use of CMOS for RF circuits. Since the predominant technology used

for digital circuitry is CMOS there is a natural desire to use CMOS technology for RF

circuits as well. By combining the RF circuitry with the digital processing circuitry on the

1
same substrate, significant cost savings can potentially be realized. Moreover, it is also

desirable to use CMOS for RF and microwave applications because generally it is much

less expensive than other technologies, such as GaAs, GaN and InGaP processes [1]-[3].

However, there are significant challenges when using CMOS for RF circuit

implementations. Prior to the 1990s there was very little work in the area of RF CMOS

because the transistors could not meet the performance requirement at high frequencies.

Through continuous refinement and downscaling of the technology, CMOS now has the

capability of operating in the microwave and millimeter-wave frequency range. Two

common figures of merit for the high frequency performance of transistors are ωT and

ωmax, which are the frequencies at which the current and power gain, respectively, equal

to unity and are given by [1]:

gm
ωT = (1.1)
Cgs +Cgd

1 ωT
ωmax = (1.2)
2 R g Cgd

where gm is the transconductance of the transistor, Rg is the series gate resistance, and Cgs

and Cgd denote the parasitic gate-source and gate-drain capacitances, respectively. When

the transistor is scaled, the parasitic capacitances decrease, which leads to an increase in

ωT and ωmax, and improved high frequency performance. A cutoff frequency of over 400

GHz achieved with CMOS 45 nm silicon-on-insulator (SOI) technology is reported in [4].

It can be expected that with this extremely high cutoff frequency, the application of

2
CMOS technology in the microwave and millimeter-wave range will continue to grow for

some time into the future. For all of the MMICs demonstrated in this thesis, standard

CMOS 0.13-µm technology is used.

Besides providing wide bandwidth and facilitating high frequency operation, modern

wireless networks also tend to cover vast areas to serve the demands of today’s

ubiquitous and media-oriented communications [5]. As physical limits such as multipath

in urban areas, and fixed bandwidth regulations, constrain this development, new

concepts have been developed to exploit the potential as much as possible. One of these

concepts is multiple-input multiple output systems (MIMO), where multiple antennas are

employed to transmit and receive independent data streams, raising the spectral efficiency

in the presence of multipath effects [6]. Another approach uses phased arrays (also

known as adaptive antennas) to raise the signal-to-noise ratio of a given channel with

multipath or interferers by means of beam steering and spatial diversity, which also

enables the system to use more sophisticated data modulation schemes to increase the

achievable data rates [7], [8].

In the last decades, phased array antennas were only feasible for defense applications

as they require a large amount of expensive RF components [9]. In recent years the

fabrication cost has reduced dramatically due to improvements in low-cost CMOS

semiconductor technology, which has become the technology of choice for many RF

applications. This enables phased arrays for commercial applications including radar,

sensors and communications [10]-[12]. Fig. 1.1 shows the architecture of a phased array

3
receiver, in which phase shifters are employed as electronic beam-steering elements [13].

Different active antenna paths are combined after being adjusted in amplitude and phase.

Single-pole double-throw (SPDT) switches can be used to switch between the antenna

input signal and a calibration signal. Passive attenuators or variable-gain low-noise

amplifiers are used to set the required signal amplitude [14]. For this application, the

relatively low-cost CMOS process is an excellent candidate to realize phase shifter

MMICs [15].

Antenna
Vector 1
Adaptive
SPDT
Variable-Gain Phase Combiner
LNA Shifter
Calibration

Antenna Vector 2 LO

Variable-Gain Phase
SPDT
Shifter ADC
LNA
Calibration Baseband

RF control unit

Antenna Vector 3

Variable-Gain Phase
SPDT
LNA Shifter
Calibration

Fig. 1.1 Block diagram of a phased array receiver [9].

Moreover, advanced phased array systems with a limited number of elements and

very low side lobes require phase shifters of high resolutions [16]. The high phase

resolution is very difficult to achieve with digital phase shifters, such as all pass networks

[17], [18], true-time-delay circuits [19], LC-based circuits [20]-[23], and others [24]-[25],

due to accumulating phase errors. The vector-sum phase shifter, which applies a variable

4
and adjustable phase shift to an arbitrary RF signal over a finite bandwidth, is able to

provide a phase shift of full 360°with high resolution at microwave frequencies since

they have excellent amplitude and phase balance over a wide band [26]. The block

diagram of a vector-sum phase shifter is shown in Fig. 1.2.

sin(ωt) CI•sin(ωt)
VGA
I vector

+
Vin Quadrature Vout
Splitter

cos(ωt)
VGA
Q vector CQ•cos(ωt)

Fig. 1.2 Block diagram of the vector-sum phase shifter.

The typical architecture of a vector-sum phase shifter consists of two variable gain

amplifiers (VGAs), quadrature networks and summing circuits, all of which can be

integrated compactly in almost any IC technology. Hence, the vector-sum phase shifter is

feasible under the given constraints of CMOS IC design. By properly weighting and

combining signal paths with predefined phase offsets (usually 90°), vector-sum phase

shifters can cover a phase shift of full 360°and can provide a flat gain. The output of the

vector-sum phase shifter is given by,

Vout  CI  sin  ωt   CQ  cos  ωt 

 M  cos  θ   sin  ωt   M  sin  θ   cos  ωt  (1.3)
 M  sin  ωt  θ 

5
where CI = cos(θ) is the controllable in-phase gain and CQ = sin(θ) is the quadrature gain.

Assuming the polarity of controllable gain CI and CQ can be reversed, the phase of the

output vector Vout can therefore be continuously tuned for a full 360°. In particular, VGAs

used to weight the amplitude of those paths, are desired to provide a linear gain control

curve to avoid complicated lookup tables. Additionally, the transmission phase deviation

across the assumed gain range is preferably zero, especially for VGAs used in the vector-

sum phase shifter.

The performance, size and cost of vector sum phase shifters enable improved

systems solutions. However, design challenges, such as bandwidth and phase control

range are also introduced with the vector-sum phase shifters. Therefore, new circuits

targeted for wideband operation need to be investigated to address these issues, which is

another motivation for this thesis.

1.2 Scope and Thesis Overview

The principle of this thesis is to propose and realize innovative circuit topologies and

techniques in order to overcome issues in advanced RF front-ends mentioned previously.

More specifically, the circuit blocks and their corresponding design challenges covered in

this thesis are briefly introduced below.

A special type of mixer, the subharmonic mixer (SHM), typically requiring half of

the LO frequency of the conventional mixer, has unique advantages in terms of easing the

design difficulty of high frequency local oscillators and reducing the LO leakage to other

6
ports, and therefore can address some of the issues discussed above regarding high-

frequency wireless communication devices, and is one focus of this thesis.

In the case of wideband mixers, the RF bandwidth is an important parameter as it

determines the spectral coverage of the RF band with a proper adjustment of the LO

frequency for the fixed IF, while the IF bandwidth is also an important parameter as it

limits the spectral width of sub-channels in ultra-wideband (UWB) systems. Therefore

the study of wideband techniques, which could enhance both RF and IF bandwidths, is

the second focus of this thesis.

As discussed in Section 1.1, VGAs are critical components in the vector-sum phase

shifter, whose bandwidth constrains the bandwidth of the whole circuit. Furthermore, for

many applications, such as the automatic gain control in Wireless Local Area Network

(WLAN) receivers with single signal path, the variation of the transmission phase in

VGAs is not a critical issue. However, for VGAs used in the vector-sum phase shifter, the

phase variation over the controlled gain must be kept low in order to achieve high phase

control accuracy with the whole circuit. Therefore, new VGA circuits accounting for

wideband operation and low transmission phase variation, need to be investigated to

overcome the design challenges of wideband vector-sum phase shifters exhibiting low

phase error. In this thesis, the design of wideband low phase error vector-sum phase

shifters based on the proposed VGAs is the third focus.

7
 The main objectives of this thesis are as follows:

1. To propose a new biasing scheme to realize a subharmonic cascode FET mixer with

low supply voltage and relaxed LO power requirements.

2. To perform a systematic large-signal stability analysis of the proposed subharmonic

mixer and propose a stabilization method to correct the potential instabilities.

3. To propose a new wideband mixer based on the modified Gilbert-cell with an active

feedback to improve both RF and IF bandwidth.

4. To investigate and propose wideband VGAs with low phase variations, for

applications in vector-sum phase shifters.

5. To propose a wideband full-360° vector-sum phase shifter with only one control

voltage.

The proposed subharmonic mixer is demonstrated with discrete transistors and SMD

components, while the others are all demonstrated in a standard 0.13-µm CMOS

technology. The proposed circuit techniques and design solutions of the research work

presented in this thesis are all verified by experimental results. All circuit measurements

were performed at the MMIC lab of National University of Singapore (NUS). For the on-

wafer measurements, the losses and stray parasitics of the RF probes and cables were de-

embedded by proper calibrations.

In Chapter 3, a novel biasing scheme to realize a low voltage subharmonic cascode

FET mixer is presented. The proposed biasing requires a low supply voltage and

effectively enhances the generation of the second harmonic of the LO signal. The

8
implemented mixer exhibits competitive performance at a lower supply voltage compared

to conventional subharmonic mixers. Additionally, a large-signal stability analysis is

performed to predict potential parametric oscillations. Based on the stability analysis, a

practical stabilization solution is proposed to successfully eliminate the nonlinear

parametric oscillation. A PCB prototype is measured at an RF frequency of 900 MHz,

and an LO frequency of 400 MHz, with a supply of only 1 V. Note that the concept of

subharmonic mixers is more competitive and suitable for microwave and millimeter-

wave applications. However, due to funding limitations, the proposed subharmonic mixer

is not demonstrated in MMIC at millimeter-wave frequency range in our study and hence

is beyond the scope of this thesis.

In Chapter 4, a wideband CMOS 1-10 GHz mixer is proposed with the modified

Gilbert-cell topology. Employing the common-gate transconductance stage with an active

feedback, the RF bandwidth enhancement, conversion gain boosting, as well as the RF

port impedance matching are simultaneously achieved. The proposed wideband mixer

also incorporates active baluns at LO and IF ports to facilitate measurements with single-

ended equipment and to improve the port impedance matching. The proposed mixer is

implemented in a standard 0.13-µm CMOS technology. The experimental circuit

employs an optimized LO power of 0 dBm and draws 7 mA from a 1.2 V supply. The RF

bandwidth from 1 to 10 GHz is observed with a conversion gain of 5.5±2.5 dB, while the

measured mixer also shows a gain variation of 2 dB in the IF bandwidth from 100 MHz

to 1 GHz. It is noteworthy that the achieved reflection coefficients for both RF and IF

ports are better than 10 dB within the frequency range of interest, and for the LO port is

9
better than 7 dB. The measured IP1-dB, IIP3 and SSB noise figure are better than -16 dB, -

7 dB and 15 dB, respectively over the RF band of operation.

In Chapter 5, wideband techniques and issues for gain control linearity as well as

transmission phase error for VGAs are investigated. Two wideband CMOS VGAs for

vector-sum phase shifter applications are presented. The first VGA exhibits a continuous,

linear-in-magnitude gain control curve by using a programmable transconductance

multiplier. In the second VGA design, both a linear-in-magnitude gain control curve and

output phase reversal are achieved for applications in the full-360° vector-sum phase

shifters. Lastly, a 2-16 GHz CMOS vector-sum phase shifter is presented with over 400°

phase-tuning range controlled by only one DC voltage, employing the proposed

wideband phase-reversible VGA and DC control generator.

Chapter 6 summarizes the main contributions of this thesis and proposes directions

for future research.

1.3 List of Publications

Journal Papers

 Hu Zijie and Koen Mouthaan, “Design and Stability Analysis of a Low Voltage

Cascode FET Subharmonic Mixer,” IEEE Transactions on Circuits and Systems

II: Express Briefs, vol. 59, no. 3, pp. 153–157, March 2012.

10
  Hu Zijie and Koen Mouthaan, “1-10 GHz RF and Wideband IF Cross-Coupled

Gilbert Mixer in 0.13-µm CMOS,” accepted by IEEE Transactions on Circuits

and Systems II: Express Briefs.

 Hu Zijie and Koen Mouthaan, “2-16 GHz Vector-Sum Phase Shifter With 435º

Phase control Range in 0.13-µm CMOS,” submitted to IEEE Transactions on

Microwave Theory and Techniques.

Conference Papers

 Hu Zijie and Koen Mouthaan, “Systematic Stability Analysis of a Class-B

Subharmonic Mixer,” in IEEE Asia-Pacific Microwave Conference (APMC),

December 2011.

 Hu Zijie and Koen Mouthaan, “A 2-6.5 GHz CMOS Variable Gain Amplifier for

Vector-Sum Phase Shifters,” in IEEE Asia-Pacific Microwave Conference

(APMC), December 2012.

 Hu Zijie and Koen Mouthaan, “Wideband VGA in 0.13-µm CMOS with Phase

Reversal for 360º Vector-Sum Phase Shifters,” accepted for IEEE European

Microwave Conference (EuMC), 2013.

11
Chapter 2

Literature Review

2.1 Wireless Communication System Architecture

This section reviews the research on wireless communication system architectures

conducted in the past. Emphasis is placed on the receiver architectures of

superheterodyne and direct-conversion, to provide context for the work in this thesis.

2.1.1 Superheterodyne Architecture

For over 75 years the dominant receiver architecture has been the superheterodyne

architecture. Patented in the United States by Edwin Armstrong in 1920 [27], the

superheterodyne receiver method solved several problems at the time by down-

converting the received radio frequency signal to a lower intermediate frequency where

filtering and amplification could be more easily implemented.

A block diagram of a simplified superheterodyne receiver is shown in Fig. 2.1. The

signal received by the antenna is filtered using a bandpass filter (BPF) and then amplified

by a low-noise amplifier (LNA). A local oscillator (LO) signal is generated and its

frequency can be multiplied, if necessary, to the required frequency. The RF signal is

12
down-converted to a lower frequency (IF) for further processing using a mixer. After the

signal has been down-converted to IF, it is filtered and amplified. The IF filter is often

realized by an external filter (often a SAW filter), and therefore it is not possible to

design an entire system on one single chip. An I/Q demodulator is then used to convert

the signal to baseband. The demodulator uses another LO and two more mixers to

convert the signal to baseband where it goes through a low-pass filter (LPF) and is then

converted to the digital-domain via the analog-to-digital converters (ADC) where it can

be processed further. Note that subharmonic mixers could also be used in the

transmitter/receiver chain in order to lower the LO frequency.

Antenna I/Q Demodulation LPF

ADC
Fundamental or
RF BPF LNA Subharmonic Mixer IF Filter IF Amp I
LO2 To
baseband
Q
LPF
Frequency
Multiplier ADC

LO1

Fig. 2.1 Block diagram of a superheterodyne receiver.

2.1.2 Direct-Conversion Architecture

The tremendous growth in the applications of radio-frequency transceivers in the last

decade has sparked a renewed interest in the direct-conversion receiver architecture, for it

permits increased integration, lower cost, and lower power dissipation [28]. The receiver,

also referred to as zero-IF or homodyne, is shown in Fig. 2.2. This receiver architecture

13
clearly requires fewer components than the superheterodyne receiver. After the signal is

received by the antenna, it is filtered in the bandpass filter and amplified by the LNA.

The RF signal is then converted directly to baseband by mixers and an LO that has a

frequency equal to the RF carrier. Finally, the down-converted signal is low-pass filtered

and amplified before being converted to the digital domain. As a result, there is no image

frequency to reject. Most importantly, external IF filters can be eliminated, since channel

selection is achieved using on-chip low-pass filters at baseband.

Subharmonic
Antenna LPF
Mixer
ADC

RF BPF LNA I
LO To
baseband
Q

ADC

Subharmonic LPF
Mixer

Fig. 2.2 Block diagram of a direct-conversion receiver.

However, there are still challenges that must be overcome in order to use this

architecture. One of the most significant challenges is LO self-mixing, which can

seriously degrade performance through increased noise and intermodulation distortion

[29]. Since the RF carrier is directly converted to DC, any DC offsets that are created by

the mixer itself can interfere with the desired signal, however, many efficient modulation

14
formats have significant spectral content at or near DC (e.g. GMSK, QPSK, etc.).

Moreover, given that the LO is generally a strong signal, it can easily couple to various

circuits on the chip, which can result in a DC offset from the LO signal mixing with itself.

There are several possible paths for LO self-mixing, as shown in Fig. 2.3 [30]. Path 1

represents the LO signal that is coupled to the RF port of the mixer, which will then mix

with itself and produce a DC offset. Path 2 represents LO coupling to the input of the

LNA, which can be particularly problematic since it will then be amplified along with the

RF signal before entering the RF port. Path 3 in Fig. 2.3 represents the LO signal

coupling to the antenna where it is radiated, and reflections of this signal by nearby

objects are received by the antenna, as shown in Path 4. Path 4 can also represent a strong

nearby interfering signal that is received by the antenna and could couple to the LO port

and self-mix, also producing a DC offset. Whereas Paths 1 and 2 would generate static

DC offsets, the results of paths 3 and 4 would be dynamic due to the changing operating

environment. CMOS technology, in particular, is very susceptible to LO self-mixing due

to the relatively low substrate resistivity allowing energy to couple to other sub-circuits

on the chip.

To combat the LO self-mixing problem, several techniques have been suggested

such as the use of frequency doublers at the output of the LO [31] and the use of

subharmonic mixers. Subharmonic mixers are very attractive in direct-conversion

receivers since they can reduce LO self-mixing by using an LO frequency that is much

lower than the RF. Furthermore, since the frequency of the LO is reduced there can be

significant additional benefits regarding performance and ease of design.

15
 Antenna

LNA Mixer

4
Output

1
2
3

LO

Fig. 2.3 LO self-mixing paths.

The proposed subharmonic mixer in this thesis can be implemented not only in the

direct-conversion receiver, but also in several places in the superheterodyne receiver, as

mentioned above. First, any or all of the three mixers shown in Fig. 2.1 could be

subharmonic mixers. Since subharmonic mixers internally multiply the frequency of the

LO, a lower LO frequency could be used, which has several potential benefits such as

ease of design and improved oscillator phase noise. A reduction in oscillator phase noise

can ultimately result in a lower receiver noise figure and improved receiver sensitivity.

Furthermore, at very high frequencies (e.g. millimeter-wave), it may not be possible to

realize an LO at the frequency of interest with sufficient output power, and there may be

no choice but to use a subharmonic mixer or a frequency multiplier. A reduction in the

DC power consumption of the local oscillator might also be possible since it operates at a

much lower frequency when using a subharmonic mixer, which would ultimately result

in a longer battery life for portable electronics. Of course, the savings in LO power

consumption need to be compared to a fundamental mixer, taking into consideration the

additional DC power required by a subharmonic mixer.

16
2.2 Mixer Circuit Review

A mixer is a three-port device that uses a nonlinear or time-varying element to

achieve frequency conversion: translating the IF signal to a carrier frequency for

transmission and from an RF carrier back down to IF for detection. Mixers can be

categorized into two families: active and passive mixers [32]. Active mixers usually have

power gain whereas passive mixers have insertion loss. Each mixer essentially modulates

either the transconductance of an amplifier or the resistance of a switch to produce the

mixing action through a time-varying mechanism. The devices are usually modulated

with a large LO signal to maximize the conversion gain. It is noted that at millimeter-

wave frequencies it is difficult to generate large LO power. Even though the device

nonlinearity will produce mixing products even with a weak LO, the conversion gain is

too small when mixers are operated in such a fashion. Hence, the conversion gain and

noise figure requirements must be obtained at a reasonable LO power level (eg.∼0 dBm).

Also the design goal of low-noise, together with mm-wave modeling difficulties, limits

the use of complex mixer topologies.

2.2.1 Overview of Fundamental Mixers

In this section, several topologies of current state-of-the-art mixers will be reviewed.

Fundamental mixers will first be explored, followed by subharmonic mixers. The

commonly-adopted image rejection architectures are discussed lastly.

17
A. Diode Mixer

The use of diodes in mixer circuits is extensive. Recent research on diode-based

mixers generally focuses on very high-frequencies where the use of more complex

techniques (e.g. the Gilbert-cell, discussed in the next section) is not possible due to

limited high-frequency transistor performance [33], [34]. A basic configuration is shown

in Fig. 2.4. The RF and LO inputs are combined with a directional coupler or hybrid

junction, which superimposes the two input voltages to drive the diode. With the

nonlinear characteristic of the diode, an IF component is generated at the output. This

description is for application as a down-converter, but the same mixer can be used for up-

conversion since each port can be used as an input or output port. The input network

provides the optimum termination to the LO and RF signals and filters the IF signal

generated by the nonlinearity in the diode, in order to ensure minimum conversion losses

and maximum isolation between the input and output ports. It must also provide isolation

between the LO and the RF ports in order to avoid interference. Similarly, the output

network provides optimum loading for IF and stops RF and LO signals.

The practical design and realisation of the filtering structures can be problematic,

especially when the frequency of an unwanted large signal (typically the LO fundamental

or low-harmonic frequency) is very close to the input or output frequency that requires a

good match. Employing a balanced structure can suppress, or rather attenuate, an

unwanted signal, easing the design of the filtering and matching networks.

18
 OUT
LO + RF IF
filter & match filter & match

Fig. 2.4 Basic structure of a diode mixer [32].

B. Gilbert-Cell Mixer

Fig. 2.5 illustrates an active double-balanced circuit, known as the Gilbert cell mixer,

commonly employed in radio-frequency integrated circuits (RFICs) [35]. In RF

applications, the LO is applied to the upper transistors, which operate as commutating

switches (also referred to as switching stage). The lower transistors, the so-called RF

transconductance stage, generate outputs which are modulated by the LO switching

transistors. RF and LO signals are normally applied to the circuit via the corresponding

matching networks and external baluns. Similarly, the IF output requires a matching

network as well. Since the two single-balanced mixers are connected in anti-parallel, LO

terms add up to zero at the IF output, whereas the converted RF signal is doubled in the

output. This mixer thus provides a high degree of LO-IF isolation, which alleviates

filtering requirements at the output.

19
 VDD

RD RD
iif1 iif2 vIF

+
vLO i3 i4 i5 i6
- M3 M4 M5 M6

i1 i2

M1 M2
+
vRF
-

IB

Fig. 2.5 Conventional topology of a Gilbert-cell mixer [35].

Note that the current iif1 is the sum of i3 and i5, and iif2 is the sum of i4 and i6, and the

RF current i1 is the sum of i3 and i4 and the sum of i5 and i6 is equal to i2. The bias current

IB is the sum of i1 and i2. Assuming that the LO signal is large enough to make the

differential pairs act like current-steering switches, transistors M4 and M5 will be on

while M3 and M6 will be off, and vice versa [36]. Therefore, the differential RF current is

effectively multiplied by a square wave whose frequency is that of the local oscillator:

iout  iif1  iif2 =sgn(cosωLOt )  (i2  i1 )  sgn(cosωLOt )  iRF (2.1)

where sgn(ωLOt) represents a squre wave with the magnitude of 1 and frequency of fLO:

20
 -1 cosω LOt < 0
sgn(cosω LOt )= 
1 cosωLOt > 0 (2.2)

Subsequently, sgn(ωLOt) is expanded using Fourier transform, and only contains LO odd

harmonic terms, as shown in Fig. 2.6. The Fourier spectrum of sgn(ωLOt) is obtained as


sgn(cosω LO t )= A n cos nω LO t , where A n =

sin n
2  (2.3)
n =1
n
4

The RF current of the transconductance stage can be given as

iRF =gm,RFvRF cos(ωRFt ) (2.4)

where gm,RF is the transconductance of the RF input stage, i.e., gm,RF = gm,M1 = gm,M2.

Consequently, the voltage conversion gain Gc of this circuit can be found after

multiplication of sgn(ωLOt) and iRF. It is given as [37]

2 2
Gc  RD g m,RF = RD K RF I B (2.5)
 

where RD is the load resistance, IB is the tail current, and process parameter
W
K RF =nCOX ( )n is determined by the technology and the size of the RF transistors M1,
L
M2 .

fLO 3fLO 5fLO 7fLO

Fig. 2.6 Output spectrum of Gilbert-cell mixer.

21
 Unfortunately, Gilbert-cell mixers usually suffer from large power dissipation and

the need for high supply voltages because of the stacked topology (three stages: RF input,

local oscillator (LO) switching, IF load). The problem is based on the need for a large

bias current for the RF stage, which also has to pass the IF load and the switching

transistors, resulting in a voltage drop across each stage that limits the available DC

potential and output swing of the RF transconductance stage. This is obviously a major

problem in deep-submicron CMOS technologies with very low supply voltages, e.g., 1.2

V in 0.13-µm. Furthermore, a large DC current through the switching stage leads to a

deterioration of the switching action, affecting the gain, linearity, and noise performance

of the circuit [38]. In conventional Gilbert cell mixer implementations, the current

bleeding technique is generally adopted to alleviate the above-mentioned issues [39]. As

shown in Fig. 2.7, replacing the transconductance stage (MN1) by a complementary

transistor pair (MN1 and MP1), DC currents for the switching transistors (M3 and M4) are

separately controlled from the currents of the transconductance stage (MN1). The current

bleeding can enable IMN1 to be higher than (IM3 + IM4). It is noteworthy that the added

PMOS differential pair MP1-MP2 contributes to the input tranconductance as well. By

selecting the current ratio of the complementary stages to be α, the enhanced conversion

gain is given by [3]:

2  W W 
Gc’  R D  nCOX ( )n I B +  pCOX ( ) p I B  (2.6)
  L L 

where (W/L)n and (W/L)p are the aspect ratio of transistors MN1-MN2 and MP1-MP2, and

IB is the bias current. Compared to (2.5), it is obvious that the conversion gain is boosted

22
without additional DC current through the switching stage and the resistive load RD. In

[40], a wideband distributed mixer is presented incorporating the modified current-

bleeding technique, which demonstrated an effective gain enhancement. Thus, high CG

and broad bandwidth can be achieved simultaneously while maintaining excellent gain

flatness within the entire frequency band. Distributed amplification is considered a robust

technique for the design of broadband mixers due to its unique capability of providing a

large gain-bandwidth product, at the cost of large chip area.

VDD

RD RD
+ vIF -

+
vLO
- MP1 MP2
M3 M4 M5 M6

+
vRF MN1 MN2
-

IB

Fig. 2.7 Circuit diagram of Gilbert-cell mixer with current bleeding technique.

The linearity of the mixer depends on the switching stage, the transconductance stage,

and the tail current source. In [41], it was shown that imperfect switches have an effect on

the linearity of the mixer, which is roughly the sum of the intermodulation values of the

transconductors and the switches. To reduce the non-linear behavior, the switch-on

23
 VDD

RD RD
iif1 iif2 vIF

+
vLO i3 i4 i5 i6
- M3 M4 M5 M6

i1 i2
vRF+ M1 M2 vRF-

Fig. 2.8 Gilbert cell mixer with inductive degenerated transconductors.

voltage should be made low and a large LO power should be used. However, excessive

LO drive could cause a higher non-linearity because of the capacitive loading at the

switching pairs' common-source nodes [41]. Thus, a moderate LO drive ensures reliable

switching. If the switches are perfect, then the IIP3 of the mixer is determined by the

transconductors [1]. Classical linearity extension techniques employed in LNA designs

can be used here as well. One classic technique is source degeneration. In resistive

degeneration, two resistors are connected to the sources of the transconductors in series.

However, due to the limited voltage headroom and noise figure, inductive degeneration in

Fig. 2.8 is usually used instead. In [42], it was shown that inductive degeneration

increases linearity by providing some form of cancellation, which can not be achieved by

resistive and capacitive degeneration. One drawback is that inductors are large and take

24
up costly chip space. Other transconductor linearization methods such as the multi-tanh

principle [43] and the modified class AB transconductor [44]-[45] can also be used to

increase mixer linearity.

2.2.2 Subharmonic Mixers

Direct conversion receivers convert the received signal directly to baseband as

opposed to first converting to an intermediate frequency. The primary advantage to using

direct-conversion is that there is no image frequency produced, and, consequently much

simpler and inexpensive filtering can be used [28]. However, an inevitable issue in the

development of direct conversion receivers is the local oscillator (LO) leakage causing a

time-variant DC offset at the output of the receiver. While the stages within the receiver

may be DC blocked, time-varying DC offset will be coupled through the receiver and

may degrade system performance [29]. One technique to reduce LO leakage within the

receive band is to employ a mixer with an LO operating at a frequency which is close to

an integer divisor of the RF frequency. This is also referred to as a subharmonically

pumped mixer. For example, a 2 subharmonic mixer is implemented as:

fIF = fRF-2×fLO (2.7)

There have been many 2 SHMs proposed (e.g. [46]-[54]). In most cases (e.g. [46]-

[50]), modifications to the Gilbert-cell mixer were made in order to generate the double

frequency LO component to mix with the RF. One common modification to the Gilbert-

cell to enable subharmonic mixing is to use an additional level of LO switching

transistors and using quadrature LO signals rather than differential signals [49], [51]. This

25
 VDD

RD RD

vIF

90°
vLO
270°
Q7 Q8 Q9 Q10

0°
vLO
180°
Q3 Q4 Q5 Q6

Q1 Q2
+
vRF
-

IBias

Fig. 2.9 Basic subharmonic mixer circuit used in [49], [51].

circuit, shown in Fig. 2.9 with bipolar transistors, has three-levels of transistors with the 0°

and 180°LO signals applied to the gates of the middle LO-transistor level, and the 90°

and 270°LO signals applied to the gates of the top LO-transistors. This configuration

generates the doubled LO frequency signal, 2fLO, that mixes with the differential RF

signal that is applied to the gates of the bottom transistors. Since this technique requires

three levels of transistors, it generally requires a higher DC supply voltage than the basic

Gilbert-cell and its use may not be possible in low-voltage applications. The topology

shown in Fig. 2.9 was introduced in [49], where it was implemented using a Si/SiGe HBT

26
technology and using passive on-chip RC phase shifters to generate quadrature LO

signals. This circuit was designed for direct-conversion applications with an RF signal

from 1 GHz to 2 GHz and an LO frequency from 500 MHz to 1 GHz. With a DC supply

voltage of 2.5 V, the measured conversion gain was 13.5 dB with an LO power of 10

dBm, a double sideband (DSB) noise figure of 10.4 dB, and an IIP3 of 3.5 dBm.

VDD

RD RD

vIF

0°
vRF
180°
Q1 Q2 Q3 Q4

vLO0 vLO180 vLO90 vLO270

Q5 Q6 Q7 Q8

IBias

Fig. 2.10 Subharmonic mixer circuit proposed in [50].

A different modification to the Gilbert-cell to enable subharmonic mixing is

demonstrated in [50] using a 0.35 μm BiCMOS technology. This circuit, which is shown

in Fig. 2.10, uses only two levels of transistors similar to the traditional Gilbert-cell,

however, it exchanges the position of the LO and RF transistor (i.e. the LO transistors are

27
on the bottom and the RF transistors are on the top). Similar to the circuit in Fig. 2.9,

quadrature LO signals are also required for this topology. In [49], the quadrature signals

were generated on-chip from a differential LO input using RC-CR networks. The circuit

in [49] was designed for an RF signal at 1.9 GHz and an LO signal at 900 MHz (a 100

MHz IF). The measured conversion gain for this circuit was 7.5 dB and the single-

sideband (SSB) noise figure was 10 dB. The input 1-dB compression point was 8 dBm

and the IIP3 was 3 dBm. The power consumption is 24 mW. Clearly, from the preceding

discussion of 2× subharmonic mixers, the requirement of quadrature LO signals is very

common (e.g. [46]-[47], [50]-[51]). Furthermore, in [52] and [53], even octet-phase

signals of the LO were used with subharmonic mixers.

There are several circuits that have been used to realize 2× subharmonic mixers

using FETs that are not based on the Gilbert-cell. For example, in [54], the RF signal was

applied to the gate of a FET while the LO signal was applied to the bulk connection of

the FET (using CMOS 0.18-μm technology). This technique of injecting the LO signal

into the bulk of the transistor has the effect of modulating the threshold voltage and

exploiting the nonlinearity that results to realize a subharmonic mixer. The measured

conversion gain in [54] was 10.5 dB with an RF frequency of 2.1 GHz and LO frequency

of 1.025 GHz. The input 1-dB compression point was 12 dBm and the IIP3 was 3.5 dBm.

The measured noise figure (DSB) was 17.7 dB and the power consumption was 2.5 mW.

Note that the study in this thesis focuses on the active type of subharmonic mixers.

However, a review of its passive counterparts would need to be carried out, but is beyond

the scope of this thesis.

28
2.2.3 Image-Rejection Mixers

An important issue for the low-IF architecture is the image frequency problem, since

the image frequency is very close to the RF frequency. To overcome this problem, image

rejection architectures such as Hartley and Weaver architectures can be used [55], as

shown in Fig. 2.11.

(a)

(b)

Fig. 2.11 Image rejection receivers: (a) Hartley, (b) Weaver [1].

29
 In the Hartley receiver, the RF input is firstly split into I and Q paths and mixed with

quadrature LO signals. Before the two outputs are added together, a 90°phase shifter is

employed to shift the phase of one of the outputs relative to the other.

Suppose the input consists of the desired RF signal cos(ωRFt) and the image signal

cos(ωIMt), and fRF − fLO = fLO − fIM = fIF . Then the signals at points A, B and C will be:

1 1
A: cos(RF t +LOt )+cos(RF t-LOt ) + cos(LOt +IM t )+cos(LOt-IM t ) (2.8)
2 2

1 1
B: sin (RF t +LOt )+sin(RF t -LOt ) + sin (LOt +IM t )+sin(LOt -IM t ) (2.9)
2 2

1 1
C: -cos(RF t +LOt )+cos(RF t-LOt ) + -cos(LOt +IM t )-cos(LOt-IM t ) (2.10)
2 2

By adding (2.8) and (2.10), the final IF output at point D can be found as:

D: cos IF t =cos(RF t -LOt ) (2.11)

From (2.11), it is clear that the IF components caused by the image signal at the I and Q

paths cancel out. However, in practice, there is always some image signal appearing at

the output due to both the amplitude and phase mismatches of the I and Q paths. One

design challenge for the Hartley architecture is that it is difficult to generate an accurate

90° phase shift for wideband applications. To overcome this problem, the Weaver

architecture as shown in Fig. 2.11(b) can be used. Two quadrature down-conversions are

performed on the desired RF input signal and image signal in the Weaver receiver, and it

30
can also be shown that the image signal is cancelled after the subtraction. However, the

Weaver architecture suffers from the secondary image problem. To avoid the secondary

image problem, the LO frequency selections have to be constrained by the condition ωRF

= ωLO1 ± ωLO2, resulting in a much lower design flexibility. Another drawback is the

increased circuit complexity and power consumption due to the two down-conversions.

The image rejection can be quantified as a parameter named image rejection ratio

(IRR). Assuming small amplitude and phase errors, IRR can be derived as [1]:

4
IRR  (2.12)
( )2 + 2

where ε and ∆φ denote the quadrature amplitude and phase errors. It is quite difficult to

achieve much better than 0.1% of gain error and 1°of phase error, which corresponds to

an IRR of about 41 dB. Mismatch calibration can help to improve the IRR, but still does

not satisfy the requirement. Therefore, high-Q off-chip filters often have to be used to

provide some additional image suppression, which inevitably prevents monolithic

integration. Furthermore, the IRR tends to be worse at higher frequencies due to many

other high frequency coupling effects, making it extremely difficult to achieve a high IRR

at microwave and millimeter-wave frequencies.

2.2.4 Mixer Performance Parameters

In order to fully model, characterize, and benchmark a mixer, it is important to have

a thorough understanding of essential mixer performance parameters [1].

31
A. Conversion Gain

The output of a linear system only consists of those frequencies that are present at

the input. Therefore, to achieve frequency translation, mixers must be nonlinear.

Multiplication is one of the most basic nonlinearities. A mixer is fundamentally a

multiplier. The multiplication of two sinusoids gives

1 1
sin 1t sin 2t = cos (1t -2t )- cos (1t +2t ) (2.13)
2 2

which is a sum of two signals at the sum and difference frequencies.

For the conversion gain analysis, we assume that the RF signal at the mixer input is

small, and only the LO signal overdrives the mixer. In other words, the mixer behaves

linearly with respect to the RF port. Consider a single tone input,

Si =a1 sin it (2.14)

and the time-varying gain of the mixer driven by an oscillator with frequency ωo,

G=g0 +g1 sin ot +g2 sin 2ot +... (2.15)

The output of the mixer can then be expressed as

So = GSi
a1 g1 ag (2.16)
= a1 g0 sin i t + sin (i -0 )t - 1 1 sin (i +0 )t +...
2 2

The second term and third term are the signals of interest. We see that this nonlinear

circuit down-converts the RF signal to ωi-ωo as well as up-converts it to ωi+ωo. For both

32
down-conversion and up-conversion mixers, the conversion gain is g1/2. If an input tone

were present at 2ωo-ωi, it would result in a down-converted term at ωi-ωo. This is the

image that corrupts the down-converted signal in a heterodyne receiver. For a direct-

conversion receiver with ωi = ωo, the image is the signal itself. Therefore direct-

conversion receivers do not suffer from the image problem.

B. Linearity and Noise Figure

In the previous section, we assumed that the mixer behaves linearly with respect to

the RF port. In practice, however, the mixer will affect the RF signal in a nonlinear way,

such that (2.16) becomes

So = G1Si +G2 Si2 +G3 Si3 +... (2.17)

where Gn has the same form as G in (2.15). For the single tone input (2.14),

a12 a12
S i2 = - cos 2i t
2 2
(2.18)
3a13 a13
3
Si = sini t - sin 3i t
4 4

The tone at 2ωi will be down-converted to 2ωi-2ωo by the second harmonic of the LO.

This is the second harmonic of the fundamental, which is at ωi-ωo. The same principle

applies for the higher orders. Harmonic distortion is defined as:

Amplitude of the n th harmonic

HDn = (2.19)
Amplitude of the fundamental

33
In a direct-conversion receiver, time-varying DC offsets can be generated by a single

large interferer as the second-order HD product of the mixer. Intermodulation distortion

measures the amount of spurious signals generated by two input signals. It is defined as

Amplitude of the n th -order IM product

IM n = (2.20)
Amplitude of the fundamental

For two equal-amplitude input signals at ω1 and ω2, the nth-order IM product is any tone

at pω1+ qω2 where p + q =n . Consider two tones at the input of the mixer,

Si =a1 sin 1t +a 2 sin 2t (2.21)

The third-order terms at 2ω1-ω2 and 2ω2-ω1 are of particular concern since they are close

to the fundamentals at ω1 and ω2 for ω1 close to ω2. Then the downconverted third-order

IM products are simply at 2ω1-ω2-ω0 and 2ω2-ω1-ω0.

Intermodulation distortion can also be specified in terms of the amplitude of the

signals when the nth-order IM product equals the fundamental. This is called the nth-

order intercept point (IPn). IPn can be input- or output-referred (IIPn or OIPn), and it is

illustrated in Fig. 2.12 for n=3. IPn is a measure of small-signal nonlinearity since it is

found using extrapolations. A measure of large-signal nonlinearity is gain compression or

3 3
expansion. The first term a1 sin i t in (2.18) is multiplied by G3 in (2.17) to give a
4
down-converted term at ωi-ω0. This term either adds to or subtracts from the small-signal

gain of the mixer, causing gain expansion or compression. Another source of gain

compression is limiting in the circuit. Gain compression is usually specified with the 1-
34
dB compression point (P1-dB), which occurs when the gain decreases by 1 dB from the

ideal small-signal gain. Typically, the P1-dB compression point is 10~15 dB lower than the

IIP3. The output linearity (i.e., OIP3 and OP1-dB) is equal to the input linearity (i.e., IIP3

and IP1-dB) plus the conversion gain.

The noise factor of a circuit block is defined as

SNRin N s +N a (2.22)
F= =
SNRout Ns

where SNRin and SNRout are the input and output signal-to-noise ratios, respectively. Ns is

the noise power due to the source impedance, and Na is the noise power added by the

circuit. The noise factor expressed in dB is called the noise figure (NF). There are two

types of noise figure defined for mixers: single-sideband (SSB) and double-sideband

(DSB).

Fig. 2.12 Graphical illustration of linearity parameters.

35
 SSB noise figure is used when the signal is present on only one side of the LO,

unlike noise which is present at all frequencies. The mixing process folds the noise over,

doubling the total noise power at the down-converted frequency while the signal power

remains fixed. Heterodyne receivers are characterized by this type of noise figure. DSB

noise figure is used when the signal is present on both sides of the LO. If the conversion

gain is the same for both sidebands, the down-converted signal doubles in power along

with the noise, and the DSB noise figure will be 3 dB lower than the SSB noise figure.

Direct-conversion receivers are characterized by this type of noise figure.

Usually, up-conversion and down-conversion mixers have quite different

requirements for NF and linearity. The NF requirement for the up-conversion mixer is not

as important as for the down-conversion. As for the linearity requirement, output linearity

is critical for the up-conversion mixer, while input linearity is more important for the

down-conversion. Because of these different requirements, circuit topologies and design

techniques can be different for up-conversion and down-conversion mixers. For example,

inductive degeneration is often used in the Gilbert-cell down-conversion mixer to achieve

a better power and noise matching [38]. However, the inductive degeneration is not

necessary for the up-conversion mixer. To improve the output linearity of the up-

conversion mixer, positive feedback techniques could be employed, which is uncommon

for the down-conversion mixer.

C. Port-to-Port Isolations

Isolation is a measure of how much power is coupled from one port to the other in a

two-port or N-port device. The mixer can be treated as a three-port device, and the
36
coupling, leakage, and isolation through these ports can be analyzed using S-parameters.

Being a three port device, there are a number of combinations. However, we will focus

on a few that are most commonly used and have stringent specifications, such as the LO-

to-IF and LO-to-RF isolation, since nonideal mixers have severe LO signal leaking to

both input and output ports. For the direct-conversion receiver, the LO feedthrough to the

input port of the mixer causes self-mixing, which results in a DC offset at the output port.

Since the down-converted band extends to DC, the DC offset can corrupt the received

signal. In a low-IF up-converter, the LO feedthrough at the output port has a frequency

very close to the desired RF signal causing in-band spurs, which is almost impossible to

be filtered out on-chip. Double-balanced mixers are usually used to suppress the LO

leakage at lower RF frequencies. However, at microwave and millimeter-wave

frequencies, the LO feedthough is much higher due to many other coupling effects, such

as electromagnetic (EM) coupling and substrate coupling.

Port-to-port isolation is a critical parameter for a circuit because it can dramatically

affect the performance of the circuit. If the port-to-port isolation is not sufficient, external

components, such as high-order filters with sharp roll-offs and high attenuation at low

cut-off frequencies, may be required.

D. Spurious Responses

The performance of the mixer does not only degrade due to the nonlinearity,

conversion loss, and noise. There are other phenomena, which affect the overall

performance of the mixer. One such phenomenon is the occurrence of spurs. Sometimes

37
there are signals that are within the passband of the mixer, and they may be up-converted

or down-converted to the IF band where they are undesired. The undesired signals that

show up at the output of the mixer are known as spurious responses [1]. To solve these

issues, the designer has a choice of changing the input filter characteristic of the mixer, or

choosing a different IF output frequency.

38
Chapter 3

Design and Stability Analysis of a Low Voltage

Subharmonic Cascode FET Mixer

3.1 Introduction

As discussed in Chapter 2, the subharmonic mixer (SHM) could be used in either a

superheterodyne system to reduce the required LO frequency by half, or in a direct-

conversion receiver in order to reduce LO self-mixing. Additionally, the down-scaling of

CMOS, which strongly improves the RF performance of MOS devices, has resulted in a

continuous reduction of the supply voltage for each technology generation. Thus, the goal

of this work is to realize a SHM with relaxed supply voltage and LO power requirements

that can achieve a conversion gain and is compatible with a system that uses single-ended

RF signals. This work is one of the first SHMs demonstrated with measurement results

using the proposed topology. This circuit also provides the foundation for a more

advanced higher-order and higher-frequency SHM. Note that the aim of the discrete

design is to validate and demonstrate the feasibility of the proposed technique.

Implementation in an integrated circuit can drastically reduce these problems and

39
increase the frequency of operation further. Therefore, the proposed SHM operating at a

low supply voltage could be an attractive solution for frequency conversion in microwave

communication systems.

Previously reported active SHMs are mostly based on the modified Gilbert-cell in

combination with an LO frequency doubler [57], [58]. The popularity of the Gilbert-cell

stems from its good conversion gain, linearity, and high isolation. However, Gilbert-cell

based SHMs always require quadrature LO signals and a significant supply voltage,

because the stacked transistors are biased in the saturation region. In addition, some

reported Gilbert-cell based SHMs achieve low supply voltages but require much larger

LO drive powers [59], [60]. Here, we present a novel biasing scheme to realize a low-

voltage SHM based on the cascode FET cell. The proposed cascade FET SHM works in

Class-B mode which inherently enhances second-harmonic generation of the LO signal.

Hence, the proposed SHM requires a low supply voltage and low LO power, which, to

the best of our knowledge, is the first time the Class-B biasing is used to realize a cascode

FET SHM.

In the case of nonlinear circuits, large-signal stability analysis is essential in order to

predict any potential nonlinear oscillations. Generally, causes of the nonlinear oscillations

for mixers can be attributed to the increased gain at certain LO input powers together

with the internal feedback loop. Especially for mixers operating in Class-B mode, the

small-signal stability analysis is not valid because circuits are biased with zero DC

current, which ensures unconditional stability in the small-signal regime, however,

40
Class-B mixers can exhibit nonlinear parametric oscillations when driven with certain LO

powers [61]. A systematic stability analysis is performed on the proposed Class-B SHM,

which successfully predicts and eliminates the potential oscillations.

Section 3.2 firstly reviews the conventional cascode FET mixer which realizes the

fundamental mixing, with a simple discrete circuit demonstration. In Section 3.3, the

design and measurement of a Class-B SHM using cascade FET cell in discrete circuit

form is presented. In Section 3.4, a systematic stability analysis is performed on the

proposed SHM, which predicts and eliminates the potential parametric oscillations.

Finally, conclusions are stated in Section 3.5.

3.2 Fundamental Mixer Using Cascode FET Cell

Cascode FET mixers have been used successfully in many kinds of portable and

fixed radio receivers for many years. Because of this success, it was originally expected

that cascode FET mixers would become the devices of choice for most receiver

applications. Cascode FET mixers have an important advantage over single FET mixers:

the LO and RF can be applied to separate gates. Because the capacitance between the

gates is low, the mixer has good LO-to-RF isolation. Because of its high isolation, the

cascode FET mixer can be used in applications where a balanced mixer would otherwise

be needed. Cascode FET cells are also used in integrated circuits, where filters and

distributed-element hybrids may be impractical, and good LO-to-RF isolation may

otherwise be difficult to achieve.

41
3.2.1 Principle of Mixing Process

The cascode FET mixer is well-known for realizing conversion gain and reasonable

noise figure. The circuit schematic of the conventional cascode FET mixer is shown in

Figure 3.1. The RF signal is applied and matched to the lower FET gate, whereas the LO

signal is applied and matched to the upper FET gate, periodically modulating drain

voltage (floating node) of the lower transistor. An LC tank resonating at IF frequency can

be inserted as RF choke to make all LO harmonics and mixing frequencies short-circuited

except the IF.

Vdd

D
G2
vLO FET2

Vgs2
D1

vRF G1 FET1
Vgs1 S1

Fig. 3.1 Circuit schematic of the single-end cascode FET mixer.

The applied LO modulates the floating-node (D1) voltage, which is the drain of the

lower FET. Conversion gain for a cascode FET mixer is primarily due to the changing

drain-source voltage of the lower FET1, which further modulates the transconductance of

FET1. A smaller frequency conversion path in the cascode FET mixer is present due to

the modulated conductance of the FET1. The modulated drain voltage swings FET1 in and

42
out of the linear and saturated region over the LO cycle. The optimum bias point is when

the conversion transconductance is maximized with respect to a changing drain-source

voltage on FET1. This bias point can be estimated by plotting the DC transconductance of

FET1 as a function of drain-source voltage. Then the optimum bias point is where an

applied LO could modulate the transconductance the greatest. As seen in Figure 3.2, the

optimum bias for the drain voltage of FET1 would be the "knee region" on the I/V curve,

in order to have the best mixing efficiency.

70

60
Vg1=-0.1 V
50 Vg1=-0.2 V
gm (mS)

40 Vg1=-0.3 V

30

20

10

0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VD1S1 (V)

Fig. 3.2 Transconductance of the lower FET gm(Vd1s1) with LO superimposed.

As discussed in Chapter 2, the conversion gain of a Gilbert-cell mixer is set by the

transconductance stage. Device sizing, biasing, and inductive degeneration set the

transconductance value of a Gilbert mixer, but ordinarily the transconductance stage is

biased in the active region. While the cascode FET mixer has the lower FET operating in

the linear region during the majority of the LO cycle, resulting in low output resistance

43
and lower transconductance. Hence, a cascode FET mixer typically has lower conversion

gain but requires a larger LO power than a Gilbert mixer. Moreover, a cascode FET

mixer exhibits a moderately better linearity performance than that of a Gilbert mixer with

actively biased transconductance stage, owing to the higher required LO power and lower

gain.

3.2.2 Circuit Analysis

To approximately analyze the mixing principle, the simplified transistor model (i.e.

square-law current model) is employed. The square-law current model is suitable for the

circuit tendency analysis.

When FET1 works in the linear region, we have

W
I D1  μ n Cox VGS1  Vth1 VDS1 (3.1)
L

W
Where μ n , Cox are process parameters and is the aspect ratio of the transistor. That is,
L
drain current is a linear function of VDS1. And this linear relationship implies that the

path from the source to the drain can be represented by a linear resistor Ron1:
1
R on1  (3.2)
W
μ n Cox (VGS1  Vth1 )
L

Eqn. (3.1) indicates that the output current is simply the multiplication of vgs1 (RF

signal) and vds1 , which is modulated by the LO signal applied at G2. In order to find the

relationship between vds1 and vLO, FET1 is replaced by its equivalent resistance Ron1.

Therefore, the equivalent circuit of a source follower is sketched in Fig. 3.3.

44
 Vdd

G2 D
vLO
Vds1

Ron1

Fig. 3.3 Source follower equivalent circuit.

Subsequently,

vds1 g m 2 Ron1
AV   (3.3)
vLO 1  ( g m 2  g mb 2 ) Ron1

vgs1  vRF  VRF cos  ωRF t  (3.4)

vLO  VLO cos  ωLO t   (3.5)

W W
iD1  nCox vgs1vds1  nCox vgs1vds1
L L
(3.6)
W g m 2 Ron1
 nCox VRF cos  wRF t   VLO cos  wLO t  
L 1  ( g m 2  g mb 2 ) Ron1

Consequently, the conversion gain (here, a transconductance) is derived,

W g m 2 Ron1
Gc  nCox VLO (3.7)
L 1  ( g m 2  g mb 2 ) Ron1

As presented in [62]-[63], the optimum conversion gain occurs when the lower transistor

FET1 is biased in the “knee region”, where it can swing in and out of the linear and half-

45
saturated regime by the LO signal. This hard switching mode offers the optimum mixing

efficiency with the tradeoff of large LO power requirements.

3.3 Proposed SHM based on the conventional cascode FET cell

3.3.1 Mixer Configuration

Fig. 3.4 shows the schematic of the cascode FET SHM. Differential LO signals are

applied at the gates of FET1 and FET1’, while the RF signal is applied at the gates of FET2

and FET2’. Note that the function of the damping resistor Rdamp is discussed in Section 3.4.

Vdd

IF

Vg2 iout Vg2

LO+ LO-
FET1 FET1’
ids ids’

FET2 FET2’
Vg1 Vg1
Rdamp Rdamp

RF

Fig. 3.4 Proposed balanced SHM based on cascode FET cell.

46
 Here we propose a biasing scheme to implement a subharmonic mixing. The

proposed biasing is shown in Fig. 3.5, where FET1 and FET1’ are biased in the cutoff

region, and FET2 and FET2’ are biased at the origin of the I/V curve. Based on this

biasing, differential LO signals drive FET1 and FET1’ alternately on and off for each half

of the LO cycle, and FET2 swings between the cutoff and linear region. This Class-B

mode operation inherently enhances the generation of the LO second harmonic

component, which enables an effective LO frequency doubling with relaxed LO power

requirements. FET2 which is biased at the origin of the I/V curve, swings between the

cutoff and linear region for each half of the LO cycle. Therefore, FET2 exhibits a low

channel resistance Rlinear when it conducts. For the proposed SHM, the two branches are

alternatively turned on by the differential LO signals, thus it can be considered as a push-

pull Class-B amplifier with a source-degenerated resistor Rlinear, as shown in Fig. 3.6.

Additionally, FET2 and FET2’ are biased with zero drain-source voltage Vds, only one

saturated Vds1,sat is required from the DC source, which facilitates low voltage

applications. For comparison purposes, the “sweet spot” for the conventional cascode

FET mixer, in which the RF is mixed with the fundamental component of the LO signal,

is also indicated in Fig. 3.5.

In conclusion, the proposed biasing provides subharmonic mixing for low voltage

applications. In addition, there is no power dissipation in the absence of the LO signal,

due to the nature of Class-B operation.

47
 Proposed biasing
Conventional biasing

FET2
FET1
Ids

Vgs

FET2(zero Vds2) FET1(cut-off)

Vds

Fig. 3.5 The conventional and proposed biasing indicated on the I/V curve.

Vdd
iout

ids ids’
vLO+ vLO-
G1

Rlinear Rlinear

Fig. 3.6 Operation of frequency-doubling circuit.

48
3.3.2 Analysis of Mixing Principle

To gain a principle understanding of the circuit behavior, the simple square-law

model is applied for the large-signal analysis. The drain current is given by [56]

  1 
 K (Vgs - Vth )Vds - Vds2 Linear region

I ds   
2 
(3.8)
 1 K (V - V ) 2 Saturation region

2
gs th

where Vth is the threshold voltage and the parameter K is determined by the technology

and the size of the transistor.

FET1 and FET1’ provide LO pumping to FET2 and FET2’ and also operate as a

common-gate IF post-amplifier. The mixing mostly occurs in FET2 and FET2’ which

operate in the linear region [62]. The noise contributed by biasing FET2 and FET2’ in the

linear region is larger compared to biasing in the saturation region. However, the

conversion gain when biased in the linear region is much higher, which improves the

overall noise performance of the two-stage mixer [1].

For the positive half cycle of vLO+, FET1 and FET2 are turned on. According to (3.8),

the current flowing through FET2 can be approximated by

ids2  K (Vgt2 +vRF )vds2 (3.9)

where the overdrive voltage Vgt2 = Vgs2-Vth, and vRF = VRFsin(ωRFt) is the RF input signal

applied at the gate of FET2. Following (3.9), mixing occurs due to the multiplication of

vRF and vds2, while vds2 is controlled by the LO signal vLO+. FET1 works within the

49
saturation region when it conducts. Therefore, the current flowing through FET1 can be

expressed as

1 1
ids1  K (vgs1 -vth1  vLO+ -vds2 )2  K (vLO+ -vds2 ) 2 (3.10)
2 2

where vgs1= vth1 (LO switching transistors are biased in the cutoff region), and vLO+ =

VLOsin(ωLOt). Note that, the current flowing through FET1 and FET2 is equal:

ids  ids1  ids2 (3.11)

Solving Eqn. (3.9)-(3.11), the time varying drain-source current for the conducting half

cycle is obtained as

ids  K (Vgt2 +vRF ) 2  KvLO+ (Vgt2 +vRF )

(3.12)
 K (Vgt2 +vRF ) (Vgt2 +vRF )(2vLO+  Vgt2 +vRF ) vLO+  0

There are two solutions for ids, but only the solution with the minus sign is practical

because ids should equal to zero (cut-off) when there is no LO signal.

For the negative half cycle of vLO+, the opposite branch, which is driven by vLO-, is

alternately turned on and works in the same manner. Therefore, the output current which

is the sum of the two branch currents can be written as

iout  K (Vgt2 +vRF )2  K vLO (Vgt2 +vRF )

(3.13)
 K (Vgt2 +vRF ) 2 vLO (Vgt2 +vRF )  (Vgt2 +vRF ) 2 

where vLO  VLO sin(ωLO t) . Furthermore, vLO is Fourier expanded into harmonics of the

LO signal,

50
  2 4  cos  2nωLO t  
vLO  VLO     
   n 1 4n 2 - 1  (3.14)
2 4
=VLO (  cos(2ωLO t)  ...)
 3

Note that the spectrum of vLO only contains DC and even-harmonic components,

demonstrating the LO frequency doubling. Consequently, the term K vLO  vRF in (3.13)

consists of the subharmonic IF frequency (ωIF = ωRF-2ωLO) component due to the

multiplication of vLO  and vRF.

In reality, the mixing mechanism is more complicated. The assumption that FET1

and FET2 remain in the saturation region and the linear region respectively may not be

valid when the LO power reaches a certain level. Accordingly, the conversion gain

decreases at larger LO powers, because when FET2 swings into the saturation region less

mixing effect occurs. In addition, the transistors’ higher order effects, which are not

considered in the simple square-law model, may deteriorate the mixer’s performance.

3.3.3 Discrete Design Verification and Discussions

The proposed SHM is designed at an RF frequency of 900 MHz, and an LO

frequency of 400 MHz, with four ATF-36163 pHEMTs (fT = 28 GHz) on RT5880

substrate (εr = 2.2, h = 31 mils). The measurement results are obtained for the stabilized

SHM, while the stability analysis and stabilization of the proposed SHM will be

discussed in Section 3.4. The aim of the discrete design is to validate and demonstrate the

proposed biasing scheme. Through simulations it is found that at the RF frequency of 900

MHz, the parasitics of the discrete surface mount devices (SMDs) are the dominant

51
parasitics rather than the transistor package parasitics. However, at higher frequencies the

package parasitics will become more important. It is also noted that the low self-resonant

frequency (SRF) of the discrete components inhibits the design of a good matching

network at higher frequencies. Implementation in an integrated circuit can drastically

reduce these problems and increase the frequency of operation further. Therefore, this

SHM with Class-B biasing is very well suited for integrated circuit design at higher

frequencies. The bias condition is: Vdd = 1 V, Vg1 = -0.55 V (cut-off), and Vg2 = 0 V. The

large-signal stability analysis is performed with the LO drive only because the RF input

signal is assumed to be small signal.

The cascode FET mixers are measured in different modes with the same RF and IF

frequencies, which include:

Mode A (the proposed SHM): subharmonic mixing with the proposed Class-B biasing

(fLO = 400 MHz).

Mode B: subharmonic mixing with the conventional Class-A biasing (fLO = 400 MHz).

Mode C: fundamental mixing with the proposed Class-B biasing (fLO = 800 MHz).

Mode D: fundamental mixing with the conventional Class-A biasing (fLO = 800 MHz).

All DC gate voltages are applied through resistors of 5 kΩ. The drain of FET1 and FET1’

are connected to the supply voltage through a LC resonator resonant at the IF frequency

(100 MHz). Note that the balanced cascode FET mixer biased in Class-A mode also has

52
stability issues, so all the four modes are measured with the insertion of the 10 Ω

damping resistors.

TABLE 3.1
PERFORMANCE SUMMARY

Mode A Mode B Mode C Mode D

RF frequency (GHz) 0.9 0.9 0.9 0.9
LO frequency (GHz) 0.4 0.4 0.8 0.8
LO Power (dBm) -4 2 3 -7
Conversion Gain (dB) 12 8 16 20
Input P-1dB (dBm) -20 -22 -22 -24
IIP3 (dBm) -11 -15 -13 -16
SSB Noise Figure (dB) 7 11 7 7
Power (mW) 12 19 16 20
Supply Voltage (V) 1.0 1.5 1.0 1.5

Table 3.1 summarizes the measured performance for all four modes. Comparing

mode A with mode B, it can be seen that the cascode FET mixer achieves better

subharmonic mixing with the proposed biasing. The SHM in mode A exhibits 4 dB more

conversion gain with less LO power and less DC consumption than in mode B, while the

other performance parameters are comparable. The reason for the poorer performance in

mode B is attributed to the conventional Class-A biasing providing less nonlinearity to

support the subharmonic mixing. Mode C and mode D are included to demonstrate that

the proposed Class-B biasing does not support fundamental mixing. It is observed that

mode C requires higher LO power to have a similar conversion gain as in mode D.

53
 Additionally, it is well known that for low frequency applications, the fundamental

mixer exhibits superior performance compared to the subharmonic mixer, which can be

seen from the comparison of mode A with D. However, when the operating frequency

increases, the design difficulty of a high-frequency local oscillator with both high output

power and good phase noise prevents the application of fundamental mixers.

Table 3.2 summarizes the performance of previously published SHMs. SHMs

implemented in integrated circuits are demonstrated in [65]-[67] and discrete solutions

are shown in [68], [69]. The mixer in [65] requires only 1.2 V but also requires an LO

drive power of 0 dBm. The mixer shown in [66] requires a relatively low LO drive and

has good conversion gain. However, a supply voltage of 3.3 V is needed. The mixers in

[67]-[69] require 0 dBm LO power and a supply voltage of 3 V. In summary, the

proposed biasing scheme (mode A) facilitates subharmonic mixing with both low voltage

and relaxed LO power requirements. Furthermore, the proposed SHM biasing will benefit

from integrated circuit implementation for high frequency applications.

TABLE 3.2
REFERENCE TABLE
RF LO CG IIP3 NF Power Supply Circuit
Technology Year
(GHz) (dBm) (dB) (dBm) (dB) (mW) (V) Topology
0.18μm
[65] 1.9 0 2.2 -3.0 11.3 6.4 1.2 Folded mixer 2007
CMOS
2 μm HBT
[66] 5.2 -8 14.5 -5.0 21 13.2 3.3 Gilbert-cell 2007
GaInP/GaAs
[67] 1.9 0 7.5 -3.0 10 24 3.0 Gilbert-cell 0.35 μm SiGe 2001
Resistive Discrete
[68] 2.1 0 0.67 8.25 N/A N/A 3.0 2004
mixer HEMT
Cascode-FET Discrete
[69] 1.9 0 10 -1.0 8.9 180 3.0 2003
Class-A HEMT

This Cascode-FET Discrete 0.2

0.9 -4 12 -11.0 7 12.0 1.0 2011
work Class-B μm HEMT

54
3.4 Stability Analysis of the Proposed Class-B SHM

In the case of mixers operating in Class-B mode, a large-signal stability analysis is

required because mixers operate in the large signal regime. Class-B mixers can exhibit

large signal parametric oscillation which is a function of LO powers. Here, a systematic

stability analysis for predicting and correcting large signal oscillations of the proposed

Class-B subharmonic mixer is presented. First, the large-signal stability analysis

technique is applied for an initial prediction of any potential instability. The proposed

circuit is found to be stable in the small-signal regime. However, at a certain range of LO

powers, spurious oscillations occur. Secondly, in order to study the origins of the

instability, a simplified circuit analysis is performed incorporating the critical large-signal

model parameters. Based on the in-depth understanding of the origins of the instability, a

practical stabilization solution is proposed to successfully eliminate the oscillations,

while maintaining the desired performance. Simulation and experimental results are in a

good agreement.

3.4.1 Large Signal Stability Analysis

The large-signal stability analysis is applied to the balanced Class-B SHM, shown in

Fig. 3.7. Note that the large-signal stability analysis is performed with the large-signal

LO drive only because the RF input signal is assumed to be small-signal [70]. The large-

signal stability analysis relies on the calculation of the linearized admittance of circuit

nodes in the large-signal regime. The algorithm analyzing the locally linearized behavior

55
of a nonlinear circuit is known as the conversion matrix method [71], which can be

solved by any commercial HB simulator. Here, Agilent's ADS is used.

Vdd

IF
Vg1 Vg1
XA
XB
LO+ LO-
FET1 FET1’
XC
Vg2 Vg2

FET2 FET2’
XD

Auxiliary Generator
Y1
XE
Y2

vAG, fAG RF

Fig. 3.7 Proposed SHM circuit and auxiliary generator to detect oscillations (matching networks
and interconnects not shown).

The procedure to detect large-signal oscillations is as follows. In the first step, a

small-signal auxiliary voltage generator at a frequency nonharmonically related to fLO is

introduced at a circuit node of interest [72]. In the second step, the two-tone Harmonic-

Balance (HB) simulation, considering both the LO excitation and the auxiliary generator,

is carried out to obtain the linearized node’s admittance Y(f) in the large-signal regime.

56
After the two-tone HB simulation, Y(f) is given by the ratio between the observed phasor

current iAG and the introduced voltage vAG:

iAG (PLO , f AG )
Y f = (3.15)
vAG (PLO , f AG )

According to Kurokawa’s oscillation condition [71], an oscillation at a frequency fo will

occur, if

Re  Y  f o    0andIm  Y  f o    0 (3.16)

As an example, the admittance Y(f) at node C is plotted in Fig. 3.8 for PLO = -6 dBm.

Fulfillment of the oscillation startup condition at 4.124 GHz is observed. Furthermore, in

order to detect the range of LO powers where the oscillation can occur, both PLO and fAG

are swept. The detected oscillation frequency versus the LO power is shown in Fig. 3.9,

which indicates that the oscillation condition is satisfied when the LO power is in the

range of -7 dBm to -3.5 dBm, and the observed oscillation frequency varies from 4.04 to

4.18 GHz. The circuit is stable when driven with an LO power outside the above power

range.

Note that the node at which the oscillation condition is fulfilled determines the

oscillation mode [73]. At the internal nodes B, C and D, both even- and odd-mode

oscillations can be excited and at the power combining nodes A and E, only the even-

mode oscillation can be excited. In our design it is found that the oscillation condition is

satisfied only at nodes B, C, and D, and oscillations are detected at LO powers from -7

dBm to -3 dBm, as found earlier. In conclusion, only odd-mode parametric oscillations

are present in the Class-B SHM.

57
 Real (Y(f))
8 Imaginary (Y(f))

4
Y(f) (mS)

-4

-8

4.10 4.11 4.12 4.13 4.14 4.15

Frequency (GHz)

Fig. 3.8 Input admittance Y(f) at node C with PLO = -6 dBm. The oscillation frequency is around
4.12 GHz.

4.20
Osillation Frequency (GHz)

4.16

4.12

4.08

4.04

-7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5

LO power (dBm)

Fig. 3.9 Oscillation frequency versus LO power.

58
3.4.2 Odd-Mode Equivalent Circuit Analysis

To investigate the root causes of the odd-mode instability, an odd-mode equivalent

circuit analysis is necessary. First, the large-signal transconductances gm1 and gm2 versus

the input LO power are determined for FET1 and FET2. Subsequently, a simplified circuit

analysis using the large-signal gm is performed.

A. Determination of Large-Signal Transconductance

To determine the large-signal transconductance gm, the conversion matrix method

[72] is applied again. The schematic for calculating gm1 and gm2 under large-signal

conditions is shown in Fig. 3.10. Ideal circulators and ideal filters are employed to

separate incident waves a1 and a2 and reflected waves b1 and b2. The auxiliary source is

set at fag =1 Hz. After the two-tone HB simulation, in which fLO is the nonlinear tone and

fag is the small-signal tone, the S parameters at fag linearised in the large-signal regime are

computed from

b1 b b b
S11  ,S12  1 , S21  2 ,S22  2 (3.17)
a1 a2 a1 a2

After converting the S-parameters to Y-parameters, we have

gm  Re(Y21 ) (3.18)

59
 Port 1 Port 2 Port 2 Pag
Pag Pag
a2
a1 a2 b2
b1 b2
50 Ω 50 Ω 50 Ω

fag

FET1
FET1
fag fag
PLO
PLO
a1
FET2 FET2
b1
fag
50 Ω Port 1 Pag 50 Ω

(a) (b)

Fig. 3.10 Circuit diagram for determining the large-signal gm. (a) gm1. (b) gm2.

Fig. 3.11 shows the large-signal gm1 and gm2 versus LO power from -20 to 20 dBm. It is

observed that LO transistor FET1 enters into Class-A region, i.e., gm1 is larger than 0, for

LO powers from -20 dBm to around 10 dBm. Using the large-signal gm1 and gm2, a circuit

analysis will be performed to study the cause of the oscillation.

60
 30
nonlinear gm1
25 nonlinear gm2

20
(mS)

15
m
g

10

0
-20 -10 0 10 20
LO power (dBm)

Fig. 3.11 Large-signal gm1 and gm2 versus PLO.

B. Circuit Analysis of the Odd-mode Equivalent Circuit

For the odd-mode oscillation in the Class-B SHM, the signals in both branches are

180°out of phase. Thus, a virtual ground can be assumed at power combining points A

and D. One branch of the balanced circuit is chosen with virtual grounds added at nodes

A and D, as shown in Fig. 3.12. According to (3.21), the necessary oscillation condition

is:

Re  Y  f   =Re  Yleft +Yright   0 (3.19)

where Yleft and Yright are the input admittance looking towards left and right at node C.

61
 LO+
Yleft Yright
TLd
TLg
C

Fig. 3.12 Odd-mode equivalent circuit used for stability analysis.

Zparallel Ztotal
g2 i1 d2 Yleft
+
+ Cgd2 i2 i3 i4
TLg vgs2 vin
Cgs2 gm2vgs2 Cds2 rds2
-
-
s2

Fig. 3.13 Circuit model for deriving input admittance Yleft.

In order to gain insight in the high-frequency behavior of Yleft, the intrinsic model of

the ATF-36163 HEMT is applied, as shown in Fig. 3.13. The large-signal gm1 and gm2

obtained at PLO = -6 dBm are used in the following circuit analysis. The parasitic

capacitances are extracted from the small-signal analysis and assumed to be constant for

simplicity. Using KCL and KVL, Re(Yleft) is derived as

i2  i4 1
Re  Yleft     cg m2 (3.20)
Vin rds2

Zparallel ωCgd2 X TLg

c  (3.21)
Ztotal ω(Cgd2  Cgs2 )X TLg  1

62
where XTLg is the input reactance of the gate transmission line TLg, using the lossless

microstrip line model. Fig. 3.14 shows the calculated c and Re(Yleft) versus frequency. As

can be seen, Re(Yleft) is highly negative around 6.2 GHz, which is mainly due to the

resonance of the resonator formed by Cgd2, Cgs2, and TLg. Three frequency regions in Fig.

3.14(a) are indicated:

Region I: At low frequencies, the complex resonator Ztotal is capacitive with a high

reactance, while the parallel resonator Zparallel is inductive with a low reactance.

Consequently, c is negative, but the magnitude is too small to make Re(Yleft) negative.

However, c decreases with frequency, and when the frequency approaches 6.2 GHz, the

first resonant frequency of Ztotal, c becomes highly negative, and Re(Yleft) becomes highly

negative as well.

Region II: Right after the first resonance, Ztotal becomes inductive, and Zparallel remains

inductive before its resonance. As a consequence, c and Re(Yleft) are positive.

Region III: When the frequency increases further, the parallel resonator Zparallel resonates,

which gives an infinite reactance. Then c approaches 1, and Re(Yleft) is still positive.

After the second resonance, Cgs2 dominates Zparallel, which is in series with Cgd2 to give a

capacitive Ztotal. Therefore c and Re(Yleft) remain positive.

63
 18

12

c 6

-6
I II III
-12

-18
4 5 6 7 8
Freq (GHz)

(a)

1.5

1.0

0.5
) (S)
left

0.0
Re(Y

-0.5

-1.0

-1.5

-2.0
4 5 6 7 8
Freq (GHz)

(b)

Fig. 3.14 (a) Calculated c. (b) Calculated Re(Yleft).

64
 Next, we obtain the input admittance of the right side Yright. The simplified

equivalent circuit is shown in Fig. 3.15. Within the frequency range of interest, the

impedance of FET1’s gate matching network is negligible, therefore the gate terminal g1

is shorted to ground for simplicity. Applying the circuit nodal equations, the input

admittance Re(Yright) is derived as

g m1 (1  ωCds1X res )  yds1

Re(Yright )  (3.22)
(1  ωCds1X res )  X 2res yds2 1
2

where Xres is the reactance due to Cgd1 in parallel with the drain transmission line TLd,

and yds1 is the conductance of rds1. Re(Yright) is also plotted in Fig. 3.16(a). Then, an

approximation for Re(Yright) at low frequencies is

1
Re(Yright )  g m1 + (3.23)
rds1

Cgd1 TLd
g1 d1

+
vgs1
Cgs1 gm1vgs1 Cds1 rds1
- i1 i2 i3 i4
s1
Yright
+
vin
-

Fig. 3.15 Equivalent circuit for deriving input admittance Yright.

65
 To find the potential instability, the sum of Re(Yleft) and Re(Yright) is plotted in Fig.

3.16(b). It can be seen that the negative input admittance occurs at 6.2 GHz, which is

caused by the negative Re(Yleft), as discussed earlier.

100
gm1+yds1
80
) (mS )

60
right

40
Re(Y

20

-20
0 1 2 3 4 5 6 7 8 9 10
Freq (GHz)

(a)

1.5
Re(Yleft)+Re(Yright)
1.0
) (S)
right

0.5
)+Re(Y

0.0
left

-0.5
Re(Y

-1.0

-1.5
0 1 2 3 4 5 6 7 8 9 10
Freq (GHz)

(b)

Fig. 3.16 (a) Calculated Re(Yright). (b) Calculated Re(Yleft)+ Re(Yright).

66
3.4.3 Experiments and Stabilization Technique

The board photo of the designed balanced SHM is shown in Fig. 3.17. A parametric

oscillation is experimentally found in the LO power range from -6 dBm to -1 dBm. As an

example, Fig. 3.18 shows the output spectrum at PLO = -3 dBm. An oscillation around 4.2

GHz is observed, which is close to the frequency predicted by the large-signal stability

analysis of Section 3.4.1. Note that the distributed parasitic capacitance coming from the

package is comparable to the intrinsic parasitic capacitance. The discrepancy between the

measured oscillation frequency and the predicted oscillation frequency found in Section

3.4.2 is attributed to the negligence of the transistors’ package parasitics and the

nonlinear behavior of the transistors’ capacitors in the simplified circuit analysis.

IF

LO+ LO-

RF
SHM Core

Fig. 3.17 Fabricated SHM with a size of 6 ×6 cm2.

67
 From the equivalent circuit analysis of Section 3.4.2, it is found that the resonance of

the complex resonator Ztotal causes the negative admittance Yleft. An effective way to

eliminate the oscillation is to insert a damping resistor Rdamp into Ztotal to suppress the

negative admittance Yleft, as shown in Fig. 3.19. The large-signal stability analysis

discussed in Section 3.4.1, is performed again for different values of the damping resistor.

The simulated Re(Y(f)) at node C is shown in Fig. 3.20. As can be seen, a 10 Ω damping

resistor reduces the negative admittance sufficiently. It is confirmed by the experiment

that the proposed methodology has determined the suitable location and correct value of

the stabilization resistors.

Fig. 3.18 Spectrum measurement of the oscillation at PLO = -3 dBm.

68
 Vdd

IF

LO+ LO-
FET1 FET1’

FET2 FET2’

Rdamp Rdamp

RF

Fig. 3.19 The proposed SHM with the damping resistor Rdamp (matching and biasing networks
not shown).

60 Rdamp=0 Ohm
Rdamp=10 Ohm
40 Rdamp=20 Ohm
Re(Y(f)) (mS)

20

-20

-40

0 1 2 3 4 5 6 7 8 9 10
Freq (GHz)

Fig. 3.20 Re(Y(f)) versus resistance Rdamp.

69
3.4.4 Summary

A systematic stability analysis for the proposed Class-B SHM is performed in order

to detect nonlinear oscillations and to determine the root causes. To the best of our

knowledge, this is the first time the origin of the large-signal oscillation in the Class-B

SHM is analyzed incorporating the critical nonlinear circuit parameters using the

proposed circuit analysis. Finally, a practical stabilization approach successfully

eliminates the large-signal parametric oscillation. Simulation and experimental results are

in a good agreement.

3.5 Conclusions and Recommendations

A new biasing for the cascode FET mixer is proposed in order to realize a

subharmonic mixer. The proposed SHM requires a low supply voltage and reduced LO

drive power, which makes it a suitable solution for low-voltage applications. Furthermore,

a large-signal stability analysis is performed which successfully predicts and eliminates

the odd-mode parametric oscillation. Simulation and measurement results provided are in

good agreement.

Suggestions for future research in the parasitic cancellation technique are:

 When the proposed subharmonic mixer is implemented in integrated circuit, active

balun for the LO port could be used, in order to save chip area.

70
 As an advantageous candidate for frequency conversion in direct-conversion receiver,

the proposed subharmonic mixer implemented as zero-IF down-converter could be

studied.

 An increase in the order of subharmonic mixing could be investigated. For example, a

4X subharmonic mixer. However, this may be challenging using the proposed

topology since it would require splitting the LO into four phases.

 Performance improvement of the proposed subharmonic mixer could be investigated,

such as linearity, bandwidth, and power consumption.

71
Chapter 4

1-10 GHz RF and Wideband IF CMOS Gilbert

Mixer With Cross-Coupled Feedback

4.1 Introduction

Since the Federal Communications Commission (FCC) has allocated 7.5 GHz (3.1-

10.6 GHz) of unlicensed bandwidth for low-power high-data-rate wireless networks and

high-precision positioning systems, the development of wideband mixers necessarily has

received considerable attention. The emerging wideband applications, namely software-

defined radio (SDR) and ultra-wideband (UWB) standards, call for the operational

frequency range covered from 1 GHz up to about 6 GHz (SDR) or 10 GHz (UWB) [74].

And for monolithic microwave integrated circuits (MMICs), a wideband mixer catering

for multiple applications is also attractive and advantageous, in light of high data rate,

application flexibility, economies of scale, and improved inventory costs.

Owing to the continuous down-scaling and low cost requirement, deep-submicron

CMOS technologies have become the most appealing and promising candidate for radio-

frequency (RF) applications. The Gilbert-cell based mixer is a typical type of active

72
mixers, which has been widely used as the down-converter to provide the required

frequency translation in CMOS designs. This active topology is favored over its passive

counterparts due to the offered conversion gain, which relaxes gain and noise

requirements on the preceding LNA and subsequent baseband stages, respectively. To

improve the bandwidth of CMOS Gilbert-cell mixers, novel circuit techniques have been

studied extensively, such as employing LC-ladder networks [75] or transformers [76] at

the input (RF and LO) ports, and the distributed architecture with input artificial

transmission lines [37]. These techniques are considered robust for the design of

broadband mixers, at the cost of larger chip area due to the additional passive networks.

Moreover, most of the previously-published wideband mixers tend to achieve their

wideband behavior by shifting the LO frequency across the intended RF frequency range,

while exhibiting a relatively small IF bandwidth. Therefore, these mixers are wideband

RF, but narrowband IF. Indeed, the RF bandwidth is an important parameter for a mixer

as it determines the spectral coverage of the RF band with a proper adjustment of the LO

frequency for a fixed IF. The IF bandwidth is also an important parameter, as it

determines the channel bandwidth or the number of channels in UWB systems. However,

to date, only a few published mixers have demonstrated both wideband RF and wideband

IF performance [77]–[79]. Fig. 4.1 shows the schematic of a conventional Gilbert-cell

mixer [12]. As discussed in Chapter 2, the differential pair M1-M2 acts as a RF

transconductance stage translating the input RF voltage into a current. The differential

pairs M3-M4 and M5-M6 referred to as the LO commutating stage and are used as

switches for current steering.

73
 VDD

RD RD
iif1 iif2 vIF

+
vLO i3 i4 i5 i6
- M3 M4 M5 M6

i1 i2

M1 M2
+
vRF
-

IB

Fig. 4.1 Schematic of a conventional Gilbert-cell mixer.

In this chapter, we propose wideband techniques in a modified Gilbert-cell mixer, to

realize both wideband RF and wideband IF performance. To the best of our knowledge,

the proposed mixer is the first Gilbert-cell mixer using a common gate transistor with

cross-coupled feedback in the RF stage, exhibiting a flat conversion gain as well as good

input/output matching over both larger RF bandwidth and larger IF bandwidth. To

demonstrate the proposed techniques and design methodology, a standalone prototype is

designed and implemented in a standard 0.13 µm CMOS process. Layout and measured

results of the proposed CMOS wideband mixer are then presented. Compared with the

conventional distributed or LC-ladder network based wideband mixers, our proposed

74
mixer has the advantages of low-complexity of geometry, good in-band input/output

matching, broad bandwidth, and low power consumption.

Modified Gilbert Mixer

VRF+ Active VIF

Balun
VRF-

VLO+ VLO-
VLO Active
Balun

Fig. 4.2 Block diagram of the proposed mixer.

4.2 Design Considerations of the Proposed Wideband Mixer

Two key requirements for MMIC wideband mixers are good input- and output-

matching and adequate conversion gain flatness. To meet these demands, various design

aspects are discussed in the following sections, including the device size selection,

bandwidth limitation, conversion gain boosting, conversion gain flattening and circuit

realization. Fig. 4.2 illustrates the block diagram of the proposed mixer, which is divided

into three functional blocks: a mixer core based on the Gilbert-cell multiplier, an active

wideband LO balun, and an active wideband IF balun. Notably, the RF signal is

intentionally designed differentially for application in differential communication

systems, which facilitates second order distortion suppression, as well as noise reduction

75
from power supply and substrate [80]. Active baluns are designed for the LO and IF ports,

mostly for convenience of measurements, which slightly increases the overall power

consumption. All building blocks are designed and simulated using GlobalFoundries

0.13-µm CMOS process models.

VDD

RD RD
vIF+ vIF-
vLO+ M3 M4 M5 M6

vLO-
LO Stage
Interstage RF Stage

iRF+ iC2 iC1 iRF-

VDD VDD
id1 MP1 MP2 id2
C1 C2
(+) (-)
M1 MN1 MN2 M2
vRF+ (+) (-)
vRF-
RS RS

Fig. 4.3 Circuit schematic of the proposed mixer core.

4.2.1 The Cross-Coupled Common Gate RF Stage

The proposed mixer core is based on a Gilbert-cell multiplier, as shown in Fig. 4.3.

Since wideband input matching is a primary objective to ensure effective RF power

76
injection, a common gate stage with cross-coupled feedback is adopted as the RF

transconductace stage. As commonly used in wideband LNA designs, the common gate

(CG) topology features desirable properties for wideband operation, and exhibits superior

stability due to the absence of the Miller effect of Cgd. Ignoring the loading effect of the

following stages and the back-gate transconductance gmb, the input impedance of the

common gate stage is given by

1
Zin  (4.1)
g m,M1  sCgs,M1  1 / R S

where gm,M1 and Cgs,M1 are the transconductance and gate to source capacitance of the

common gate NMOS transistor M1. By selecting RS = 200 Ω and optimizing the size of

M1 for impedance matching, an input return loss larger than 10 dB can easily be achieved

up to 10 GHz.

The conversion gain of a Gilbert-cell mixer strongly depends on the load impedance

RD and the effective Gm of the RF transconductance stage. And for a given bias current,

the mixer linearity tends to degrade with increased RD, due to the excess voltage drop

across the load. Therefore, the conversion gain of the proposed mixer is determined by

the transconductance of the CG transistor gm,M1, which is restricted by the input matching,

according to (4.1). Hence, a gm-boosting technique using the concept of cross-coupled

active feedback is proposed for the RF stage. The RF stage of a Gilbert-cell mixer has

differential inputs and differential outputs, which allow the two branches to be cross-

coupled for transconductance enhancement [81]. As shown in Fig. 4.3, the proposed RF

77
stage contains two CG transistors M1 and M2 and two complementary pairs (MN1/MP1

and MN2/MP2), where the drain of each complementary pair is cross-coupled to the gate

of the other. To illustrate how the effective transconductance of the proposed RF stage

Gm,eff, is boosted, the signal polarity and current direction are labeled in Fig. 4.3. When

the differential RF signal vRF+ is in the positive half-cycle, a positive small-signal current

id1 results; whereas a negative small-signal current id2 results from the negative vRF-.

Meanwhile, the drain voltage vd1 of M1 increases and the vd2 of M2 decreases. With the

cross-coupled connection, these changes in the drain voltage of CG transistors also cause

drain current variations in the complementary pairs. For instance, the decrease of vd2,

which is also the gate-source voltage of MN2/MP2, would cause a positive iC2. Since the

small-signal output current of the RF stage iRF+ consists of two current components id1

and iC2 with the same polarity, iRF+ is enhanced, which results in an increase of Gm,eff. It is

worth noting that a positive voltage feedback is formed between node C1 and C2 due to

the cross-coupled complementary pairs MP1/MN1 and MP2/MN2, which further improves

Gm,eff.

To explain the proposed gm boosting technique further, we consider the left branch of

the RF stage where the drain voltage and current of M1 are given by

vC1 =  id1 +iC2  ZC


 (4.2)

 id1 = g m,M1vRF+

where ZC denotes the node impedance at C1, and vC1 is the small-signal voltage at node

C1. Subsequently, the current flowing into the complementary stage MP2/MN2 is derived,

78
 iC2 = -iC1
(4.3)
=(g m,MP1 +g m,MN1 )vC1

Consequently, the output current of the left branch can be expressed as:

iRF+ = id1 +iC2

g m,M1 (4.4)
= vRF+
1-(g m,MP1 +g m,MN1 )ZC

Therefore, the effective transconductance Gm,eff can be obtained,

g m,M1
G m,eff = (4.5)
1-(g m,MP1 +g m,MN1 )ZC

Compared to the transconductance gm,M1 of the CG input stage, the transconductance

enhancement factor F is found,

1
F (4.6)
1-(g m,MP1 +g m,MN1 )ZC

And the node impedance ZC is given by

1 1
ZC  R ds,M1 R ds,CP2 (4.7)
2g m,LO jωCC

where Rds,M1 and Rds,CP2 denote the drain source resistance of M1 and the complementary

pair MN2/MP2, CC is the parasitic capacitance at node C1, and the input resistance looking

into the source of the LO stage is approximated by 1/(2gm,LO). Note that the term

79
(gm,MP1+gm,MN1)ZC from (4.5) is required to remain less than 1 for any frequencies, to

ensure a stable circuit with the cross-coupled positive feedback.

It can be seen from (4.6) and (4.7), Gm,eff can be enhanced by properly designing the

transconductance of the complementary pair and the LO stage. In order to effectively

boost Gm,eff, preferably wide transistors are used for the complementary pair. However,

when the transistor width increases, the gate parasitic capacitance increases too, which

reduces the node impedance ZC at higher frequencies. Thus, a tradeoff should be made

between Gm,eff and RF bandwidth. Alternatively, reducing the width of LO transistors M3-

M6 also benefits Gm,eff boosting by increasing ZC. However, smaller LO transistors

require a larger overdrive voltage which results in a reduction of voltage headroom in the

RF stage, and therefore degrades linearity and noise performance of the mixer [3].

Cadence simulations show a very good agreement with the presented analysis, and

indicate a stable circuit, even with PVT variations. Additionally, an approximately 3 dB

increase of noise figure caused by the channel noise of the cross-coupled transistors is

also observed.

As discussed in Chapter 2, the limited voltage headroom requires heavy current

bleeding in the Gilbert-cell mixer to keep the gain high. The proposed mixer also

employs the current-reuse technique realized by the bias current difference in the

complementary transistors (MN1 and MP1). Taking the complementary pair MP1 and

MN1 as an example, increasing the aspect ratio (W/L)MP1 of the PMOS transistor or

decreasing the aspect ratio (W/L)MN1 of the NMOS transistor would allow more bias

80
current injecting into the drain of M2. The relationship between the bias currents of RF

and LO stage can be expressed as

I M2   I MP1  I MN1    I M5  I M6  (4.8)

where (IM5+IM6) refers to the bias current of the LO stage. By optimizing the size of the

complementary transistors, the bias current through the LO transistors can be reduced,

which improves the switching function, and offers better gain, linearity and noise

performance as well [82]. Reduction of the DC current through the resistive load RD also

alleviates voltage headroom limitations caused by the continuously reducing supply

voltage due to technology scaling, and therefore improves the mixer linearity and

conversion gain.

4.2.2 Conversion Gain Flattening Technique

According to (4.5), the high parasitic capacitance CC lowers Gm,eff at high

frequencies, which is mainly due to Cgs of the LO transistors and the complementary pair.

To investigate the resulting conversion gain roll-off at higher RF frequencies, Cadence

Harmonic Balance (HB) simulations are performed by sweeping both RF and LO

frequencies for a fixed IF frequency of 200 MHz. Note that the LO and IF baluns are also

included in HB simulations, which will be discussed in Section II-C. The conversion gain

frequency response of the mixer using the proposed RF stage is shown in Fig. 4.4,

indicating a 3-dB RF bandwidth of approximately 3 GHz.

81
 15
14 Original mixer + interstage inductor
Original mixer
12
11
Post-Layout Spectre Simulation

Conversion Gain (dB)

9
8
6
5
3
2
0 3 GHz
-2
-3
-5
1 2 3 4 5 6 7 8 9 10
RF Frequency (GHz)

Fig. 4.4 Simulated frequency response of the proposed Gilbert mixer.

To reduce the effect of parasitic capacitance present at the interstage node C1 and C2,

and to realize a flat conversion gain over a wider frequency range, an inductor Linter is

added between the LO and RF stage, as shown in Fig. 4.5. The parallel connection of

Cp,LO and Cp,RF is broken up and a complex resonator is formed by the total parasitic

capacitor at the source of LO transistors Cp,LO, the interstage inductor Linter, and the total

parasitic capacitor at the output node of the RF stage Cp,RF. The resulting equivalent

admittance at interstage node C1 is given by

1
YC  jωCp,RF 
1
jωLint er 
jω Cp,LO (4.9)
jω(Cp,RF  Cp,LO  ω L int er Cp,RF Cp,LO )
2


1  ω2 Lint er Cp,LO

82
Let YC equal to zero, i.e., the parasitic capacitance is compensated, then the resonating

frequency can be derived,

1
ωO  (4.10)
C C
Lint er ( p,LO p,RF )
Cp,LO  Cp,RF

That is, the interstage inductance Linter resonating with Cp,LO and Cp,RF gives the best

compensation of overall parasitic capacitance. Taken into account process limitations of

CMOS inductors, such as low-Q and low self-resonant frequency, an optimum

inductance Linter = 3.5 nH at 10 GHz is adopted. As shown in Fig. 4.4, the gain-peaking

occurs around 8.5 GHz, which effectively improves the conversion gain flatness up to 10

GHz. Cadence simulations also show that the noise performance is improved around the

gain peaking frequency. The main reason for the noise figure improvement is the part of

noise added by the circuit itself remains unchanged due to the gain peaking, while the

amplification of useful signal is enhanced.

vIF+ vIF-
vLO+
LO Stage
vLO+
Cp,LO Cp,LO

Linter Linter Interstage

Cp,RF Cp,RF

vRF+ RF Stage vRF-

Fig. 4.5 Parasitic capacitance compensated by the interstage inductor at the dominant pole.

83
 Sensitivity analysis is also investigated by Cadence corner simulations. As shown in

Fig. 4.6, the conversion gain variation is less than 1 dB, indicating the conversion gain

flatness is not sensitive to the inductance process variations.

Fig. 4.6 Conversion gain frequency response with different inductor models.

4.2.3 Wideband Active Baluns for the LO Port and IF Port

A. Single-to-Differential Balun for the LO Port

The LO signal fed into a mixer is either from an internal VCO or an external signal

source. However, a VCO with differential outputs would require higher power

consumption and complicated control voltages. Additionally, the LO signal fed into the

84
gate of the switching transistors is large-signal, and reflections due to impedance

mismatch should be avoided. For convenience of measurements, an on-chip active LO

balun with wideband matching is applied in the proposed mixer.

The cascode common gate common-source balun is adopted and designed at the LO

port [83]. As shown in Fig. 4.7, the cascode common gate topology is employed to add

phase delay to compensate the phase deviation between the two stages over a wide

bandwidth. Note that the resistor Rin =200 Ω is utilized for the RF block and input

matching, instead of using an inductor in order to save the die area. Cadence HB

simulations are performed on the designed LO balun, loaded with the gate-source

capacitance Cgs of LO transistors M3-M6. The process parameters are given by the

GlobalFoundries 0.13-µm CMOS process models (LO transistor W/L = 50/0.13, Cgs =

38.65 fF). Fig. 4.8(a) depicts the simulated phase imbalance and gain imbalance of the

adopted active balun, which shows a phase imbalance better than 6°and an amplitude

imbalance within 2.6 dB, in the frequency range from 1 to 10 GHz. Simulations also

indicate a 6-dB gain variation throughout the 1-10 GHz LO band, which slightly

increases the required LO power for the optimum conversion gain, as shown in Fig. 4.8

(b).

85
 RFout1 RFout2

CS Stage

CGCG Stage

RFin

Rin

Fig. 4.7 Circuits diagram of the cascode CG and CS balun.

3
6 Phase Imbalance
Gain Imbalance

4
Gain Imbalance (dB)
2
Phase Imbalance ( )
o

0 1

-2

0
-4

1 2 3 4 5 6 7 8 9 10
Frequency (GHz)

(a)

86
 6

CGCG
4
CS

Voltage Gain (dB) 2

-2

-4

-6
1 2 3 4 5 6 7 8 9 10
Frequency (GHz)

(b)
Fig. 4.8 (a) Simulated phase and gain imbalance of the adopted active balun. (b) Simulated

voltage gains of the two branches.

B. Differential-to-Single Balun for the IF Port

An on-chip active IF balun is also designed for matching and testing purposes. The

differential-to-single (D-to-S) amplifier of Fig. 4.9(a) is adopted, which combines a

common source amplifier with diode-connected load and a source follower [84]. Because

the output impedance of the source follower stage is inherently low, output matching and

conversion gain flatness can be achieved throughout the entire IF-band, simply by

optimizing the transistor size. Note that the source follower stage can also be utilized as a

simple output buffer for achieving wideband matching, if the output signal is required to

remain differentially.

87
 After thorough and detailed design considerations, the size of the transistor M1 is set

identical to that of the M2 for output balancing without gain and phase mismatches, and

both transistors are in saturation. Since the same current flows from the transistor M1 to

M2, the transconductance of the transistor M1 is identical to that of the M2. For the source

follower stage, shown in Fig. 4.9(b), the voltage gain can be approximated by 1, thus the

output voltage vo1 is estimated by

vo1 =vin1 (4.11)

For the CS amplifier with diode-connected load, shown in Fig. 4.8(c), the output voltage

vo2 is derived as:

1
vo2  -g m2  vin2  -vin2 (4.12)
g m1

Therefore, the single-ended output voltage Vout is given by

vout  vo1  vo2  vin1 - vin2 =v+ - v- (4.13)

Source Diode-connected
Load
M1 follower M1
M1
v+ vin1
vo2
Differential

vout
vo1
CS amplifier
M2 M2
M2
v- vin2

(a) (b) (c)

Fig. 4.9 Proposed D-to-S converter.

88
 Circuit simulations are performed on the designed IF balun combined with the mixer

core. The optimized aspect ratio of the two equally sized transistor M1 and M2 is 35

µm/0.13 µm, for considerations of flat conversion gain and good output return loss

throughout the entire IF-band.

4.3 Chip Implementation and Measurement Results

The proposed wideband mixer is fabricated in GlobalFoundries 0.13-µm CMOS

technology. The die photograph is shown in Fig. 4.10 with a chip size of 1.4 × 1.1 mm2,

in which the active area only occupies 0.28 mm2 excluding pads and DC decoupling

capacitors. The mixer characteristics are measured using on-wafer probing on RF, LO,

and IF pads, while DC pads are wire-bonded to the printed circuit board (PCB). Signal

generators are used to generate the RF and LO signals. A spectrum analyzer is used to

measure the converted signal at the IF port. An external balun is used at the RF port to

provide the differential RF signals. All losses from the balun, probes and cables are

carefully extracted for precise power calibrations. Operated with a 1.2-V supply voltage,

the measured power dissipation of the entire chip is 8.4 mW. The simulated power

consumptions of the mixer core, LO balun and IF balun are 2.55 mW, 1.6 mW and 3.05

mW, respectively.

In order to evaluate the small-signal characteristics, the S-parameter measurement is

performed using a vector network analyzer. The measured and simulated port reflection

coefficients are shown in Fig. 4.11. Due to the use of common gate transistors in the RF

stage, the measured RF input return loss is better than 10 dB from 0.6 to 12 GHz. The LO
89
port exhibits an input return loss larger than 7 dB from 1 GHz to 10 GHz, whereas the

output return loss is better than 10 dB from 0.1 to 4.4 GHz.

Active Area

0.4 mm

0.7 mm

Fig. 4.10 Microphotograph of the mixer chip (core size: 0.7 × 0.4 mm2).

0
Measured
-2
Simulated
Reflection Coefficient (dB)

-4
IF
-6
LO
-8

-10

-12
RF
-14

-16

-18
0 1 2 3 4 5 6 7 8 9 10

Frequency (GHz)

Fig. 4.11 Measured and simulated reflection coefficient at RF, LO and IF port.

90
 The conversion gain is firstly measured for a -40 dBm RF input at 3 GHz, where the

2.8 GHz LO power is swept from -10 to 5 dBm. As shown in Fig. 4.12, the measured

conversion gain is saturated when the LO power is 0 dBm, hence a 0 dBm LO power is

used to drive this mixer over the entire RF band for the sake of simplicity. The

conversion gain frequency response is subsequently measured with both RF and LO ports

swept in the frequency range from 1 GHz to 10 GHz. Fig 4.13 depicts the measured

conversion gain versus the RF frequency at a group of fixed IF frequencies up to 1 GHz.

The simulated conversion gain in Fig. 4.4 is also plotted together for comparison

purposes. The measured conversion gain is 5.5±2.5 dB throughout the whole RF band of

1 to 10 GHz, and the IF bandwidth from 100 MHz to 1 GHz is observed with a

conversion gain variation less than 2 dB. Compared with the simulated conversion gain,

the relatively large discrepancies at high frequencies are attributed to process variations

and an underestimation of parasitic effects due to the lack of EM models of interconnects.

As for the port-to-port isolation, the measured results with an LO power of 0 dBm

are presented in Fig. 4.14. The LO-to-RF isolation is generally higher than 45 dB, while

the LO leakage to the IF port is lower than -40 dB within the entire RF band. Note that all

metal connections in the Gilbert-cell core are placed as symmetrical as possible; however,

there are some inevitable crossovers between these metal connections, which deteriorate

port-to-port isolations to some extent. Some advantageous crossover structures to tackle

the RF trace intersection issues are presented in [85]-[87], which are not considered in

this study due to the relatively large area requirements.

91
 8

Conversion Gain (dB) 6

3
Measured at RF=3 GHz, IF=200 MHz
2

1
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5

LO Power (dBm)

Fig. 4.12 Measured conversion gain as a function of the LO power.

8
Conversion Gain (dB)

6 5 dB
IF@100 MHz
5 IF@200 MHz
IF@300 MHz
IF@500 MHz
4
IF@800 MHz
IF@1000 MHz
Simulated@200 MHz IF
3

2
1 2 3 4 5 6 7 8 9 10

RF frequency (GHz)

Fig. 4.13 Measured conversion gain versus RF frequency at various IF frequencies.

92
 LO-to-RF
60 LO-to-IF

Isolation (dB)

40

20

0
0 1 2 3 4 5 6 7 8 9 10
RF frequency (GHz)

Fig. 4.14 Measured port-to-port isolation (LO-to-RF and LO-to-IF) with an LO power of 0 dBm.

To evaluate the linearity of the proposed mixer, a two-tone intermodulation

distortion test is performed. The test procedure is performed over the entire RF band. In

each case, RF signals spaced 1 MHz apart are down-converted to two-tone IF of 199 and

200 MHz. Subsequently, the measured input referred 1-dB compression point (IP1-dB) and

third-order input intercept point (IIP3) as a function of RF frequency are plotted in Fig.

4.15 and Fig. 4.16, respectively. The IP1-dB is from -16 to -13 dBm and the measured IIP3

is better than -7 dBm over the entire RF band. In addition to the linearity, the noise figure

of the fabricated mixer is characterized at various RF frequencies. At a group of fixed IF

frequencies, the measured single-sideband (SSB) noise figure ranges from 11.3 to 15 dB

within the entire RF band, as shown in Fig. 4.17.

93
 -12

-13

IP1-dB (dBm) -14

-15

-16

Measured at IF=200 MHz

-17

-18
1 2 3 4 5 6 7 8 9 10
RF frequency (GHz)

Fig 4.15 Measured IP1-dB of the proposed mixer for a fixed IF frequency of 200 MHz.

-2

-3 Measured at IF=200 MHz

-4
IIP3 (dBm)

-5

-6

-7

-8
1 2 3 4 5 6 7 8 9 10
RF frequency (GHz)

Fig 4.16 Measured IIP3 of the proposed mixer for a fixed IF frequency of 200 MHz.

94
 20

IF
100 MHz
18
300 MHz
Noise Figure (dB) 500 MHz
700 MHz
16
900 MHz

14

12

10
1 2 3 4 5 6 7 8 9 10

RF frequency (GHz)

Fig 4.17 Measured SSB noise figure versus RF frequency.

The performance summary and comparison with recently published wideband

CMOS mixers is shown in Table 4.1. The reported wideband mixers are implemented

with either 0.13-µm or 0.18-µm CMOS technology and demonstrated in the similar

frequency range. Mixers in [83], and [88]-[90] are measured at a fixed IF frequency, and

therefore they are only wideband RF mixers. Compared with recently published

wideband mixers in [78], [83], [88]-[90], the mixer presented here has advantages in

terms of relatively wide RF and IF bandwidth, good input/output matching, low LO

power requirement, low power consumption, along with acceptable conversion gain, gain

flatness, linearity. As is well known, the wider IF bandwidth deteriorates the noise

performance, however, the noise figure of our proposed mixer still competes well with

the narrow-band IF mixers. Especially compared with works based on the Gilbert-cell

95
topology in [83], [89]-[90], our proposed mixer exhibits significantly better performance,

which makes the proposed mixer suitable for wideband applications.

TABLE 4.1
PERFORMANCE SUMMARY AND REFERENCE TABLE

[83] [88] [89] [90] [78] This

MTT MWCL VLSI ISCAS MTT work
RF BW (GHz)* 2-11 3.1-10.6 3.1–8.72 2.4-10.7 8.7-17.4 1-10

RF Matching BW (GHz)# 2-12 NA 3.5-8.5 NA 8.7-17.4 1-12

IF BW (GHz) IF@0.05 IF@0.264 IF@0.528 IF@0.05 DC-8.7 0.1-1

CG (dB) 6.9±1.5 9.8~14 2~6 3.3±1.5 10.5~19 5.5±2.5

PLO (dBm) -5 -3 9 -5 5 0

NF (dB) 15.5~20 14.5~19.6 6.8~7.3 NA 7~12.6 11~14.5

IIP3 (dBm) 6.5 -11 5 4~6.9 -5~-6 -7~-4

1.85
PDC (mW) 25.7 (except 10.8 14.4 40 8.4
buffer)
0.13
0.18 µm 0.13 µm 0.18 µm 0.18 µm 0.13 µm
Technology µm
CMOS CMOS CMOS CMOS CMOS
CMOS
0.28
Area (mm2) 0.4845 0.3422 1.624 0.406 1.3
(core)
Sub-
Gilbert Gilbert Gilbert Resistive Gilbert
Topology threshold
cell cell cell mixer cell
mixer
Year 2009 2008 2005 2007 2010 2012

*RF BW refers to the RF operating bandwidth.

#RF Matching BW refers to the bandwidth where RF Return Loss > 10 dB.

4.4 Conclusions and Recommendations

A wideband RF and wideband IF mixer is demonstrated in standard 0.13-µm CMOS

technology. By employing a common gate transistor with cross-coupled active feedback

96
in the RF input stage, a conversion gain of 5.5±2.5 dB and RF return loss better than 10

dB are measured over the RF band from 1 to 10 GHz. The proposed mixer also exhibits a

measured IF bandwidth from 100 MHz to 1 GHz, with a conversion gain variation less

than 2 dB, as well as an output return loss better than 10 dB. The chip draws only 7 mA

at a supply voltage of 1.2 V. The measured IP1-dB, IIP3, and SSB noise figure are better

than -16 dBm, -7 dBm, 15 dB throughout the entire RF band, respectively. To the best of

our knowledge, the proposed mixer is the first demonstration of a CMOS Gilbert mixer

exhibiting a flat conversion gain and good input/output matching over large RF and IF

bandwidths.

There are several potential directions for future work on the proposed wideband

mixer.

 For the current CMOS prototype, two interstage inductors are used to flatten the

conversion gain within the RF band. In order to save chip area and improve the self-

resonant frequency (SRF) of inductors, the feasibility of coupling the two differential

inductors to form a single transformer could be studied.

 The measured conversion gain variation in RF band of 1-10 GHz is 5 dB, which

could be improved by further investigation on wideband techniques.

 Noise figure analysis on the proposed Gilbert-cell mixer with the common gate input

stage could be conducted, to compare with the conventional Gilbert-cell mixers.

97
Chapter 5

CMOS Wideband Vector-Sum Phase Shifter

with Over 400ºPhase Control Range

5.1 Introduction

Since being proposed in the 1930s [91], the electrically scanned phased array

system has been widely used in defense and science applications. The advantages of

this all-RF architecture are its simplicity, improved system-level linearity, (no mixer,

no local oscillator (LO) and LO distortion), suppression of the spatial interferences

and improvement on the signal-to-noise ratio (SNR) [92]. For MMIC (monolithic

microwave integrated circuit) implementation of phased array systems, CMOS has

become a good candidate since its continuous down-scaling has facilitated RF and

microwave circuit implementations. Another fundamental merit is the low-cost and

ability to integrate active RF circuits, digital circuits, transmission lines, and passive

elements on a single substrate.

In the architectural view of phased arrays, phase shifting in the RF domain for

each array element has been dominant ever since they were developed [91]. The phase

shifter, used for electronic beam-steering, is required to provide 360°phase shifting

98
and maintain a constant amplitude and group delay in a certain bandwidth to

minimize the distortion of the signal processing [93]. In addition, advanced phased

array systems with a limited number of antenna paths and very low side lobes

especially depend on phase shifters with high phase resolution. To address the above-

mentioned challenges, the vector modulator-based phase shifter [93]-[97] is an

excellent topology of choice, since it is able to provide continuous and adjustable

phase shifts at microwave frequencies and is well suited for monolithic integration.

VI VOI = CI•VI
CI
I vector

+
Vin Quadrature Vout
Splitter

VQ
CQ
VGA
Q vector VOQ = CQ•VQ

Fig. 5.1 Block diagram of the vector-sum phase shifter.

The block diagram of a vector-sum phase shifter is shown in Fig. 5.1, and the

functional principle is explained as follows. A quadrature splitter produces an in-

phase signal VI = sin(ωt) and a quadrature-signal VQ = cos(ωt). The amplitude of VI,

VQ is balanced and simplified to unity for convenience. After weighting by the

variable gain amplifier (VGA) of each signal path, the two signals are combined to

obtain an adjustable output phase while exhibiting a constant magnitude. Assuming

99
the quadrature splitter and analog adder are ideal and lossless, the output Vout with the

desired phase shift Δθ can be expressed as

Vout  CI  sin  ωt   CQ  cos  ωt   M  sin  ωt  θ (5.1)

where M denotes the maximum achievable gain of the VGA, and the gains of the I-

and Q-path should be set as CI = M·cos(Δθ) and CQ = M·sin(Δθ), accordingly. The

variable gains CI and CQ should be kept as cos(θ) and sin(θ) to realize the adjustable

phase together with the constant amplitude. Note that it is highly desirable for the

variable gain to be a linear function of the control voltage. Otherwise a calibration and

tabulation procedure for compensation would be required. Additionally, the insertion

phase of the VGA should be kept as small as possible in order to reduce phase and

amplitude errors in the vector modulator.

In previous works of the 360° vector sum phase shifter, the fully differential

topology is typically adopted [93]-[97]. A balun is placed at the input port to provide

the differential input signal and therefore all the following building blocks are

designed differentially, including the quadrature coupler, VGAs and adder. The

second approach uses the single-ended phase shifter incorporating phase-reversible

VGAs, where the differential phases are obtained by the roles of transistors rather

than the passive networks, and this results in a simpler system architecture and layout

and lower power consumption. Especially, the single-ended topology is favorable

over the fully differential one for large arrays with hundreds of elements.

Along with the increasing numbers of features and communication standards that

are loaded on a single device or integrated circuit, the development of wideband

phased arrays is needed. The bandwidth of a vector-sum phase shifter mostly depends

100
on its quadrature splitter and VGA circuits. Note that the bandwidth of on-chip

quadrature splitter is smaller than its off-chip counterpart, especially when using lossy

CMOS technologies. Implemented by an off-chip 3-dB quadrature coupler, a multi-

octave bandwidth can be easily realized. Therefore, it is very important to design the

VGA considering specifications such as bandwidth, phase-reversible feasibility,

minimum control complexity, and transmission phase variations. In Section 5.2, we

present a wideband CMOS VGA with a linear-in-magnitude gain control

characteristic. Based on the proposed wideband technique, Section 5.3 proposes a

CMOS wideband phase-reversible VGA, which exhibits a phase-reversible and linear-

in-magnitude controlled gain with only one control voltage. Lastly, a wideband

vector-sum phase shifter with over 400° phase range is demonstrated in 0.13-µm

CMOS technology employing the proposed phase-reversible VGA, as discussed in

Section 5.4.

5.2 Wideband VGA with Linear-in-magnitude Controlled Gain

Targeted for wideband vector-sum phase shifter applications, the VGA poses

challenging requirements on bandwidth, tuning range, transmission phase variations

within the control voltage range, etc. Here, we propose a wideband linear-in-

magnitude controlled VGA with reduced transmission phase error. Implemented in a

standard 0.13-µm CMOS process, the proposed VGA achieves a 3-dB bandwidth

from 2 to 6.5 GHz and good in-band input/output matching, which is the widest

bandwidth reported in CMOS technology for phase shifter applications, according to

the best of our knowledge.

101
5.2.1 Design Considerations of the Proposed VGA

VGAs are the critical component in vector-sum phase shifters, which play a

significant role for the overall performance of the phase shifter, in terms of phase

control range, phase resolution, insertion loss, phase error, group delay. General

design considerations of VGAs for vector-sum phase shifter applications are

summarized as follows [9]:

 High gain control range, in order to reach the phase range borders.

 Minimum insertion phase variations versus the controlled gain.

 Minimum control complexity and preferably one single DC control signal.

 The relationship between gain and control signal should be as linear as possible.

 Good in-band input and output impedance matching to 50 Ω, within the full gain

control range.

To fulfill above-listed requirements, a wideband VGA is presented which

consists of three stages: a common gate input stage, a programmable

transconductance multiplier, and an output buffer based on the modified Cherry-

Hooper amplifier. The simplified schematic diagram of the proposed VGA is shown

in Fig. 5.2, where the required gain is set by the control voltage VCTL. Note that on-

chip MIM capacitors and poly-resistors are used for AC coupling and DC bias, and

are not shown in Fig. 5.2.

A. Common Gate Input Stage

The common gate (CG) amplifier, common drain feedback amplifier, and

resistive shunt feedback amplifier are widely used topologies that can achieve

102
wideband input matching as well as flat and moderate gain over a wide operating

frequency. Here, we utilize the common gate topology as the input stage for wideband

input matching. Ignoring the loading effect of the second stage, the input impedance

of the common gate stage is given by

1
Zin  (5.2)
g m,NM1  sCgs,NM1  1 / R S

where gm,NM1 and Cgs,NM1 are the transconductance and the gate to source capacitance

of the common gate transistor NM1. By selecting RS = 150 Ω and optimizing the size

of NM1 for input matching, an input return loss larger than 10 dB can be easily

achieved up to 10 GHz in a standard 0.13-µm CMOS process.

Transconductance
CG Input Multiplier Modified Cherry-Hooper Buffer

VDD VDD VDD VDD VDD VDD VDD

RD
PM3 PM4 PM5 PM6 PM7 PM8
PM1
RF1 RF2 LF RF3 RFout
NM1
RFin VCTL
PM2 NM2 NM3 NM4 NM5 NM6 NM7
RS

Fig. 5.2 Schematic diagram of the proposed VGA (DC biasing and decoupling capacitors are
not shown).

B. Transconductance Multiplier

The linear-in-magnitude control curve is obtained by the proposed

transconductance multiplier. PM1 operates in the linear region and acts as a resistor

Rlinear, while PM2 operates in the saturation region with the gate biased by the control

voltage VCTL. To find the drain source voltage of PM1, PM2 can be considered as a

103
source follower loaded by the equivalent resistor Rlinear of PM1. Applying the basic

transistor model for simplicity, the drain-source voltage of PM1 is derived as:

g m,PM2  R linear
Vds,PM1  VCTL (5.3)
1  g m,PM2  R linear

where gm,PM2 is the transconductance of the PM2 transistor. By properly adjusting the

size of PM2 and the control voltage, the condition gm,PM2×Rlinear »1 can be satisfied.

Therefore, within a certain range of the control voltage VCTL,

Vds,PM1  VCTL (5.4)

The current flowing through PM1 can be found as:

 1 2 
I ds,PM1  K Vgs,PM1  Vth Vds,PM1  Vds,PM1  (5.5)
 2

where the parameter K is determined by the technology and the size of the transistor,

and Vth denotes the threshold voltage. Vgs,PM1 is the gate-source voltage of PM1,

containing the RF signal. Following (5.4) and (5.5), it can be seen that the linear

variation of the RF signal’s magnitude is realized through the multiplication of Vgs,PM1

and VCTL.

It is worth noting that in Cadence simulations it is observed that the proposed

topology inherently reduces the transmission phase error. When the control voltage

increases, the transmission phase of the PM1 stage, which operates in the linear

region, increases; and the transmission phase of the PM2 stage, which operates in the

saturation region, decreases. These two effects are in opposite direction, and the net

result is a reduction of the overall phase error.

104
C. Output Buffer

To ensure bandwidth broadening and output matching simultaneously, the output

buffer utilizes a modified three-stage Cherry-Hooper amplifier. The traditional

Cherry-Hooper amplifier with a resistive load is shown in Fig. 5.3(a). The local

feedback resistor RF raises the pole frequencies and enables high-speed operation. The

low-frequency small-signal voltage gain and the output resistance are given by:

Vout g
 g m1R F - m1
Vin g m2 (5.6)
R out  g -1
m2

where gm1 and gm2 are the transconductances of NMOS transistors M1 and M2. To

further improve the small-signal voltage gain and reduce the output resistance, the

circuit can be modified as shown in Fig. 5.3(b). Replacing NMOS transistors M1 and

M2 by the inverter (M1P, M1N) and (M2P, M2N), the effective gm1 and gm2 can be

increased,

gm1 =gm1N +gm1P , gm2 =gm2N +gm2P (5.7)

where gm1N , gm1P, gm2N , gm2P are the transconductance of the imverter transistors M1P,

M1N, M2P, M2N, respectively. Thus, the small-signal gain and output matching can be

improved simultaneously. Note that the inductive peaking technique is also employed

in the local feedback loop of the last stage (see LF in Fig. 5.2), which is an effective

approach to improve the bandwidth and gain flatness. A reasonable set of values for

the transistor’ aspect ratios, RF, LF, and the number of stages is determined through

circuit simulation and optimization. The optimized design values of the proposed

VGA are summarized in Table 5.1.

105
 VDD VDD

IB
M2P
RF Vout
M1P R Vout
F
Vin
M2
M2N
Vin
M1 M1N

(a) (b)
Fig. 5.3 (a) Traditional Cherry-Hooper amplifier. (b) Proposed buffer stage based on the
modified Cherry-Hooper amplifier.

TABLE 5.1
DESIGN VALUES OF WIDEBAND VGA

NM1 (µm) 35 PM1 (µm) 10 PM8 (µm) 25

NM2 (µm) 20 PM2 (µm) 12 RD (Ω) 800
NM3 (µm) 12 PM3 (µm) 4 RS (Ω) 150
NM4 (µm) 20 PM4 (µm) 12 RF1 (Ω) 500
NM5 (µm) 12 PM5 (µm) 4 RF2 (Ω) 500
NM6 (µm) 24 PM6 (µm) 12 RF3 (Ω) 150
NM7 (µm) 25 PM7 (µm) 18 LF (nH) 3.8

5.2.2 Circuit Implementation and Experimental Results

The proposed VGA was designed and fabricated in a standard 0.13-µm CMOS

process. Fig. 5.4 shows the chip microphotograph. The overall chip area is 0.7 × 0.85

mm2 including the test pads. The VGA was on-wafer measured with ground-signal-

ground probes, and the DC bias pads were all connected to the PCB by bond wires.

106
Operated with a DC supply of 1.2 V, the whole VGA draws 5 mA with a VCTL from

0.3 V to 0.7 V.

The measured power gain S21 is from -8 dB to 6 dB, with a 3 dB bandwidth

from 2 GHz to 6.5 GHz, as shown in Fig. 5.5. Note that the maximum gain always

occurs around 6.1 GHz, due to the inductive peaking technique. The magnitude and

phase of the power gain versus the control voltage VCTL are shown in Fig. 5.6, which

demonstrates a linear-in-magnitude controlled gain and phase error less than 4ºfrom

0.3 V to 0.7 V. The measured S11 remains below -10 dB up to more than 8 GHz, and

the measured S22 is lower than -6 dB across the entire band, as shown in Fig. 5.7.

The measured input referred 1-dB compression point (IP1-dB) is between -25 and -15

dBm at 6 GHz, with VTCL from 0.3 V to 0.7 V.

RFout
RFin

Core Circuit

Fig. 5.4 Chip microphotograph of the VGA.

107
 5

-5
|S21| (dB)

-10
VCTL= 0.3 V
-15
VCTL= 0.4 V
VCTL= 0.5 V
-20
VCTL= 0.6 V
-25 VCTL= 0.7 V

0 1 2 3 4 5 6 7 8
Frequency (GHz)

Fig. 5.5 Measured |S21| for various control voltages VCTL.

2.0 160
phase(S21) @ 2GHz
1.8

1.6
80
1.4
phase(S21) @ 3GHz
phase(S21)
|S21|

1.2
0
phase(S21) @ 4GHz
1.0
2 GHz
phase(S21) @ 5GHz
0.8 3 GHz
4 GHz -80
0.6
5 GHz
0.4 6 GHz phase(S21) @ 6GHz

0.2 -160
0.3 0.4 0.5 0.6 0.7
VCTL (V)

Fig. 5.6 Magnitude and phase of S21 versus control voltage VCTL.

108
 0

-4

|S22|
|S11|, |S22| (dB)
-8

-12
|S11|

-16

-20

-24
0 1 2 3 4 5 6 7 8
Frequency (GHz)

Fig. 5.7 Measured |S11| and |S22|.

5.2.3 Conclusions

A wideband CMOS linear-in-magnitude controlled VGA is presented for vector-

sum phase shifter applications. The proposed VGA exhibits a 3-dB bandwidth and

good input/output matching simultaneously from 2 GHz to 6.5 GHz and consumes

only 6 mW. Within the gain control range of 14 dB, the absolute phase variation is

less than 4º, which makes it suitable for wideband vector-sum phase shifter

applications.

109
5.3 Wideband Phase-reversible VGA with Linearly Controlled

Gain

5.3.1 Motivation

Employing the proposed voltage-controlled VGA in Section 5.2, every phase

between 0° and 90° can be achieved by properly weighing the path gains.

Nevertheless, to achieve a 360°full phase control, a fully-differential architecture is

typically adopted, as shown in Fig. 5.8 [91]. In conventional 360°phase shifters, a

single-ended to differential converter (balun) is placed at the input before all critical

blocks of the vector-sum phase shifter, which are designed differentially, including

the quadrature coupler, VGAs and analog adder. Nevertheless, there are several

drawbacks of this traditional topology, such as gain and bandwidth degradation

caused by the inevitable input balun and switch, especially when using lossy CMOS

technology. Secondly, the fully differential configuration requires larger power

consumption and chip area.

Switch Iout+
Iin+ +
VGA

Iout-
Quadrature

-
Iin-
Splitter

+
Balun

Balun

RFin RFout
Qin-
Switch Qout-
Qin+ +
VGA

- Qout+

DAC Control Unit

Fig. 5.8 Typical architecture of the full 360ºphase shifter [91].

110
 To alleviate the above-mentioned design issues, we propose a phase-reversible

VGA, where differential phases are realized by the role of transistors. Fig. 5.9(a)

shows the topology of the full 360°phase shifter using the proposed phase-reversible

VGA. It is noteworthy that the new topology is single-ended and eliminates the input

balun and switch. By properly setting the variable gains CI and CQ of the two VGAs,

the output phase can be continuously tuned, and the output amplitude remains

constant. An illustration of the full-360°phase shift is shown in Fig. 5.9(b).

VI=sin(ωt) VOI = CI•VI

CI
I-path
VGA1

+
Vin Vout
Quadrature CI,CQ  -max,+max 
Splitter

VQ=cos(ωt) VOQ = CQ•VQ

CQ
Q-path
VGA2

(a)

111
 VOQ,90º

VOQ ,90o  VOI ,180o  VOI ,0o  VOQ ,90o 

VOI,180º VOI,0º

VOI ,180o  VOQ ,270o  VOQ ,270o  VOI ,0o 

VOQ,270º

(b)

Fig. 5.9 (a) Block diagram of a full 360ºvector-sum phase shifter using the phase-reversible
VGA. (b) Vector diagram of the full-360ºphase control.

5.3.2 Design Considerations of the Phase-reversible VGA

The block diagram of the proposed VGA is shown in Fig. 5.10. The VGA is

divided into four functional blocks: a DC-control generator, a single-balanced

multiplier cell [18] with input matching stage, a differential amplifier for common-

mode signal suppression, and output buffer. Note that the required phase-reversible

gain is set by only one control voltage VCTL. In the following parts of this section, the

functional principle and design considerations of each circuit block will be discussed

respectively. The circuits are designed and simulated using the GlobalFoundries 0.13-

µm CMOS design kit. All component values are optimized through Cadence

SPECTRE simulations.

112
 RFin VMO+
Common-Gate VMI Gilbert-cell Common-mode
Input Stage Multiplier VMO- suppression circuit

VDC+ VDC- VCO+ VCO-

DC Control Output
Generator Buffer

VCTL RFout

Fig. 5.10 Block diagram of the proposed phase-invertible VGA.

A. Single-balanced Multiplier with CG Input Stage

Since it is preferable to realize a linear-in-magnitude control characteristic of the

VGA for the vector-sum phase shifter application, RF multipliers are suitable

candidates due to the linear relationship between the product signal and the two input

signals. The source-coupled pair is a stage which is widely used in op-amps and other

linear circuits. Here, it is modified to act as a single-balanced multiplier circuit, as

shown in Fig. 5.11. Note that a common gate (CG) input stage is also designed before

the multiplier cell for wideband impedance matching, as discussed in Section 5.2. The

gate of tail transistor M1 is driven by the output signal of the preceding CG stage vMI.

Upper transistors M2 and M3 are identical and biased with quasi-differential DC

voltages generated by the DC control generator, as will be discussed in Section

5.3.2.B. For convenience of circuit analysis, the simplified MOS square-law model is

applied in the saturation region, thus the drain source current ID=K(VGS - VT)2, where

VT is the transistor's threshold voltage, and the parameter K = (µnCox/2)·(W/L) is

determined by the technology and the size of the transistor. The drain current of each

branch is given by:

113
 2
K  i V2 V 
i2  2  1  DC  DC  (5.8)
2  K1 2 2 

2
K  i V2 V 
i3  2  1  DC  DC  (5.9)
2  K1 2 2 

2i1
iout  i2  i3  K 2 VDC  VDC
2
(5.10)
K1

 2i1 
Vout  iout  RD  K2 VDC   VDC
2
 RD (5.11)
 K1 

where K1 and K2 are determined by the technology and size of transistor M1 and M2,

respectively. And VDC = VDC+ - VDC-, i.e., the difference between the two DC control

voltages VDC+ and VDC-. Whereas, the tail current i1 can be expressed as

i1  K1 (VMI  VT )2 (5.12)

where VMI is the superposition of the small-signal RF voltage vMI and the DC bias

voltage VMI, at the gate of M1. Substituting (5.12) into (5.11), the output voltage of

the multiplier is obtained,

VMO  (i2  i3 )  RD  K2 VDC  

2(VMI  VT ) 2  VDC
2
RD (5.13)

Furthermore, within a certain range of the control voltage VDC, 2(VMI  VT )2 2

VDC is

satisfied. And (5.13) can be approximated as

VMO  2 K2VDC (VMI  VT ) RD (5.14)

The output voltage, therefore, has a product term of the DC control voltage VDC and

the RF input vMI, which indicates a linear control of the RF signal’s magnitude. As

114
expected, the output voltage VMO is an odd function of VDC, falling to zero when VDC+

= VDC-, thus the phase-reversible gain can be obtained by properly setting VDC+ and

VDC-. It is observed from Cadence simulations that the proposed topology has low

transmission phase variation within the DC control range. The reason is that the quasi-

differential control voltage VDC is limited to achieve a linear-in-magnitude controlled

gain and all transistors operate within the saturation region, which altogether ensures

a low overall transmission phase variation.

Single-Balanced Multiplier
VDD

CG Input Stage RD RD
VDD vMO+ vMO-
RCG i2 i3
M2 M3
VDC+ VDC-
MCG

RFin i1
RS M1
vMI

VMI

Fig. 5.11 Schematic diagram of the differential multiplier.

B. DC Control Circuit

The special requirement of a quasi-differential DC voltage pair (VDC+ and VDC-,

seen in Fig. 5.11) makes it necessary to design a DC control circuit to minimize the

control complexity. The design of the DC control circuit is critical because it affects

the linearity of the gain control curve and gain tuning range. Here, the source-coupled

pair is adopted to generate the required quasi-differential DC control voltages VDC+

115
and VDC-, which requires only one external control terminal VCTL. As shown in Fig.

5.12, one of the differential inputs is biased at a fixed voltage V G2 = 0.9 V and the

other is connected to the control voltage VCTL.

VDD

RT

RB RB

VDC+ VDC-
IDC+ IDC-
VCTL MD2 MD3 VG2

ISS
VG1
MD1

Fig. 5.12 Schematic diagram of the DC control generator.

1.12

1.10

VDC+
VDC+ & VDC- (V)

1.08
VDC-

1.06

1.04

1.02
0.7 0.8 0.9 1.0 1.1

VCTL (V)

Fig. 5.13 Simulated voltage transfer curve of the DC control circuit.

116
 The functional principle is explained as follows: tail transistor MD1 works as a

current source, for a fixed tail current ISS. Varying the voltage of VCTL, ISS is switched

alternatively between each branch. When VCTL = VG2, IDC+ = IDC- = 1/2·ISS, while for

other cases, the DC current changes in the opposite direction of each branch, and

therefore generates the quasi-differential DC outputs. Note that resistor RB determines

the tuning range of VDC+ and VDC-. The simulated DC voltage transfer curve is shown

in Fig. 5.13, which implies a linear transfer relationship when VCTL ranges from 0.8 to

1 V.

The common gate input stage, single-balanced multiplier core, and DC control

circuit are designed and simulated using the GlobalFoundries 0.13-µm CMOS design

kit. The component values are obtained through Cadence SPECTRE simulations for

the optimized control curve, in terms of linear-in-magnitude gain-control

characteristic and large gain tuning range. The optimized component values are given

in Table 5.2. The typical simulation conditions are: VDD = 1.2 V, and gates of

transistor MCG, M1and MD1 are all biased at 0.6 V. Sweeping the DC control voltage

VCTL from 0.7 V to 1.1 V, the small-signal voltage gain in linear scale are plotted in

Fig. 5.14, as well as the calculated differential gain. It is observed that the variable

differential gain exhibits a linear-in-magnitude gain control curve, for VCTL within the

range of 0.8 to 1 V. Fig. 5.15 shows the phase of the simulated differential gain. It is

seen that the phase shifts 180ºin the vicinity of VCTL = 0.9 V, which indicates the

realization of phase-reversible output, with only one external DC control terminal.

117
 TABLE 5.2
DESIGN VALUES OF PHASE-REVERSIBLE VGA

MCG (µm) 35
M1 (µm) 30

M2, M3 (µm) 15

MD1 (µm) 9

MD2, MD3 (µm) 35

RS (Ω) 150

RCG (Ω) 1000

RD (Ω) 600

RT (Ω) 2000

RB (Ω) 4000

13
Voltage Gain at Output VMO+
12
Voltage Gain at Output VMO-
11
Voltage Gain at Differential Output (VMO+-VMO-)
10
9
8
Voltage Gain

7
6
5
4
3
2
1
0
0.7 0.8 0.9 1.0 1.1

VCTL (V)

Fig. 5.14 Simulated small-signal voltage gain versus the DC control voltage VCTL.

118
 0
Phase(Voltage Gain) ( )
o

-50

-100

-150

-200
0.7 0.8 0.9 1.0 1.1

VCTL (V)

Fig. 5.15 Simulated phase of the differential voltage gain versus VCTL.

C. Common-Mode Suppression Circuit

With the proposed single-balanced multiplier and DC control generator, a

variable gain with reversible phase is realized. However, there is a large common-

mode (CM) component in the multiplier's output vMO+ and vMO-, as indicated in Fig

5.14. A source-coupled pair loaded by resistors RC and the symmetric center-tapped

inductor LCT is proposed to provide high common-mode rejection, and to improve the

signal-to-noise-ratio as well as overall gain tuning range of the proposed VGA. To

improve the gain flatness, inductor peaking is applied. Instead of applying two

identical spiral inductors LC in each branch, as shown in Fig. 5.16(a), a center-tapped

symmetric inductor LCT is adopted, as shown in Fig. 5.16(b). This reduces the layout

size, improves the quality factor, and suppresses the common-mode signals

effectively.

119
 VDD VDD

LC LC LCT
RC RC
RC RC
vCO+ vCO-
vCO+ vCO-
vMO+ MC2 MC3 vMO-
vMO+ MC2 MC3 vMO-

VG1
VG1 MC1
MC1

(a) (b)

Fig. 5.16 Schematic diagram of: (a) conventional inductive peaking circuit. (b) peaking
circuit with common-mode suppression.

To illustrate how the common-mode component of the input signals vMO+ and

vMO- is removed effectively from the differential output vCO+ and vCO-, the working

principle of a symmetric center-tapped inductor is studied. As shown in Fig. 5.17,

under differential-mode (DM) excitation, the magnetic coupling between the

inductors increases the total inductance, because the current has the same direction.

However, with common-mode excitation, these currents are in the opposite direction

which reduces the overall inductance [1]. Consequently, for the common-mode

excitation, the effective load impedance at any frequency is lower than the impedance

of the differential-mode excitation. That is, the common-mode gain is lower than the

differential-mode gain, which enhances the common-mode suppression.

120
 Common-mode Current

Differential-mode Current

Fig. 5.17 Typical layout of the differential center-tapped inductor.

Simulations are performed to find the component values for this stage which

shows reasonable tradeoff between higher common-mode rejection ratio and small-

signal voltage gain, as well as in-band gain flatness. Increasing the value of RC could

increase the overall voltage gain, whereas, it affects the gain peaking at higher

frequency which reduces the bandwidth, and limits the common-mode suppression.

Increasing LCT could improve the common-mode suppression and gain flatness to

some extent. However, due to the increasing parasitics with larger value inductors, the

bandwidth drops rapidly. The final optimized RC and LCT values are 40 Ω and 12 nH

at 6 GHz.

D. Output Buffer

The output buffer consists of two functional units: differential-to-single-ended

(D-to-S) converter and the modified three-stage Cherry Hooper amplifier for the

121
bandwidth enhancement and output matching purpose. The working principles of

these two circuits are discussed in Section 4.2.3.B and Section 5.2.1.C of this thesis.

The simplified schematic diagram is sketched in Fig. 5.18. On-chip MIM capacitors

and poly-resistors used for AC coupling and DC bias, are not shown in the figure. A

reasonable set of transistors’ aspect ratios, RF, LF, and number of stages are

determined through circuit simulation and optimization, which are summarized in

Table 5.3.

D-to-S Converter Modified Cherry-Hooper Buffer

VDD VDD VDD VDD VDD VDD VDD

vCO+ MB2 MB4 MB6 MB8 MB10 MB12 MB14

RF1 RF2 LF RF3 RFout

vCO- MB1 MB3 MB5 MB7 MB9 MB11 MB13

Fig. 5.18 Schematic diagram of the output buffer.

TABLE 5.3
DESIGN VALUES OF OUTPUT BUFFER

MB1 (µm) 16 MB7 (µm) 20 MB13 (µm) 20

MB2 (µm) 16 MB8 (µm) 4 MB14 (µm) 20
MB3 (µm) 20 MB9 (µm) 16 RF1 (Ω) 1000
MB4 (µm) 4 MB10 (µm) 10 RF2 (Ω) 1000
MB5 (µm) 16 MB11 (µm) 12 RF3 (Ω) 200
MB6 (µm) 10 MB12 (µm) 16 LF (nH) 12
The length of all transistors is 0.13 µm

122
5.3.3 Measurement Results and Discussion

The proposed phase-reversible VGA was fabricated in GlobalFoundries 0.13-µm

CMOS process. Fig. 5.19 shows the chip microphotograph, which occupies a die area

of about 1.3 × 0.64 mm2 including bonding pads and on-chip decoupling capacitor

arrays, while the core VGA circuit area is only 0.29 mm2.

Active Area

RFin RFout

Fig 5.19 Microphotograph of the proposed phase-invertible VGA.

A direct on-wafer measurement of the CMOS prototype was carried out using

coplanar ground-signal-ground (GSG) RF probes, and all the DC pads are biased

through the bond wires to the PCB. The VGA consumes approximately 12 mW of

power from a 1.2 V supply throughout the full DC control range from 0.8 to 1 V. Fig.

5.20 shows the simulated and measured |S21| of the VGA for different control voltages

from 0.8 to 1 V in steps of 0.05 V. At 6 GHz the gain varies from -6 to 12 dB. The

gain deviation is less than 5 dB over the 0.6 to 6.8 GHz bandwidth, while the

maximum gain always occurs around 6 GHz due to the inductive peaking at that

123
frequency. Fig. 5.21 shows the simulated and measured input and output reflection

coefficients |S11| and |S22| of the VGA, indicating an input return loss of more than 10

dB over the full 0.6–6.8 GHz bandwidth. However, the 10-dB bandwidth of |S22| is

from 0.6 to 4.6 GHz only, and the worst case always occurs around 6 GHz, which

implies that a tradeoff could be made between the gain peaking and output return loss.

Simulations indicate that the output mismatch and over-peaking of |S21| at 6 GHz can

be improved by further optimizing the peaking inductor LF. Note that the input and

output return loss remain the same at all gain levels, since the input and output stage

are designed independently and therefore are not affected by the control voltage. The

measured phase of |S21| versus the control voltage VCTL is plotted in Fig. 5.22. It can

be observed that a phase shift of 180ºis achieved in the vicinity of 0.9 V, where the

VGA drops to its minimum gain level. To estimate the transmission phase error of the

proposed phase-reversible VGA, the absolute phases of the last two states (VCTL=0.95

and 1 V) are shifted down by 180º, and the equivalent transmission phase against the

control voltage VCTL is plotted in Fig. 5.23. The largest phase variation along the

control voltage is measured to be 8º, at the frequency of 0.5 GHz. Note that the phase

fluctuation around VCTL = 0.9 V is not important since the output voltage of that state

is a nearly zero vector for which the phase can be arbitrary. Lastly, the magnitude of

S21 on a linear-scale is plotted against VCTL at various frequencies in Fig. 5.24, which

demonstrates a linear-in-magnitude controlled gain from 0.8 V to 1 V. The measured

results are summarized in Table 5.4. The 1-dB input compression point and the noise

figure are measured at 6 GHz, which are better than -25 dBm and 25 dB respectively,

for all gain levels.

124
 Measured performance of the two designed CMOS VGAs are given in Table 5.5,

and compared with recently published VGAs intended for phase control systems. It is

shown that the proposed VGAs exhibit competitive gain control and phase error

performance, while having the largest bandwidths. Note that the gain control ranges

of our proposed VGAs are restricted by the requirement of linear-in-magnitude

controlled gain, to avoid complex calibration and tabulation procedures.

20

10

-10
|S21| (dB)

-20

-30
Measure @800 mV Sim@800 mV
-40 Measure @850 mV Sim@850 mV
Measure @900 mV Sim@900 mV
Measure @950 mV Sim@950 mV
-50
Measure @1 V Sim@1 V

0 2 4 6 8 10

Frequency (GHz)

Fig. 5.20 Simulated and measured |S21|.

-10

-20
|S11|, |S22| (dB)

-30 Measured |S11|

Measured |S22|
-40
Simulated |S11|
Simulated |S22|
-50

-60
0 2 4 6 8 10

Frequency (GHz)

Fig. 5.21 Simulated and measured |S11| and |S22|.

125
 0.5 GHz
0

-200
Phase(S21) (o)

-400

-600 7 GHz

-800
0.80 0.85 0.90 0.95 1.00
VCTL (V)

Fig. 5.22 Measured transmission phase versus control voltage VCTL.

-100
0.5 GHz
Equivalent Transmission Phase ( )
o

-200

-300

-400

-500

-600

-700
7 GHz
-800
0.80 0.85 0.90 0.95 1.00
VCTL (V)

Fig. 5.23 Equivalent transmission phase versus VCTL.

126
 4.0
1 GHz
3.5 2 GHz
3 GHz
3.0 4 GHz
5 GHz
2.5 6 GHz
Mag(S21)

2.0

1.5

1.0

0.5

0.0
0.80 0.85 0.90 0.95 1.00
VCTL (V)

Fig. 5.24 Magnitude of S21 versus control voltage VCTL.

TABLE 5.4
PERFORMANCE SUMMARY OF THE PROPOSED PHASE-REVERSIBLE VGA

Frequency (GHz) 0.6~6.8

In-band gain variation 5 dB
Gain control (dB) -6 ~ 12
Gain control characteristic Linear-in-magnitude
Phase control characteristic Phase-invertible
*Equivalent phase error (º) 8
In-band input return loss (dB) >10
IP1dB (dBm) -25 ~ -15
Noise (dB) 14-25
Power Consumption (mW) 12.0
Process 0.13-µm CMOS

127
 TABLE 5.5
COMPARISON TABLE

[98] [99] [100] This work.VGA1 This work.VGA2

Frequency
5.2~5.9 1.9 5.2~5.7 2~6.5 0.6~6.8
(GHz)

Gain control
20 22 23 14 18
(dB)

Gain control Linear-in- Linear-in- Linear-in-magnitude

N/A N/A
characteristic dB magnitude Phase-invertible

Phase error (º) 6 7.4 >8 4 <8

IP1-dB (dBm) N/A N/A -30~-15 -25~-15 -25 ~ -15

Power (mW) 1.6 5.0 9.0 6.0 12.0

0.25-µm 0.18-µm 0.18-µm 0.13-µm 0.13-µm

Process
SiGe CMOS CMOS CMOS CMOS

5.3.4 Conclusions

A wideband phase-reversible VGA is presented to realize a phase-reversible and

linear-in-magnitude controlled gain, with only one control voltage. To the best of our

knowledge, it is the first time that the phase-reversible concept in VGAs is proposed,

which facilitates a novel and simpler architecture of the full 360°vector-sum phase

shifter. A CMOS prototype is implemented and measured with an operating frequency

ranging from 0.6 to 6.8 GHz, while the gain variation is less than 5 dB. Throughout

the DC control range of 0.8 to 1 V, the measured VGA exhibits a linear-in-magnitude

gain control range of 18 dB and maximum transmission phase variation of 8º. The

phase reversion characteristic is observed in the vicinity of 0.9 V. The measured input

128
return loss is better than 10 dB at frequencies of interest and the chip draws only 10

mA with a supply voltage of 1.2 V.

5.4 A 2-16 GHz Vector-Sum Phase Shifter with Over 400ºPhase

Range

5.4.1 Introduction

Phase shifters are essential elements in beam-steering systems such as radar

systems, phased-array antennas, and measurement instruments. Recent advances in

CMOS technology have resulted in a strong interest in phase shifters demonstrated in

CMOS technologies [91], [102]. However, the substrate losses and the low Q-factors

of the passive components still impede the realization of CMOS phase shifters in

passive networks. Therefore, CMOS phase shifters based on active networks have

become mainstream and occupy a very small chip area. The vector-sum approach is a

good topology of choice, due to its capability of continuous and adjustable phase

control, and elimination of varactor diodes. Additionally, the output phase error

resulting from the I/Q amplitude mismatch in the vector-sum phase shifter can be

compensated by adjusting the I- and Q-path gains accordingly. This results in a design

which is robust against process, supply voltage and temperature variations.

In previous works of the 360° vector sum phase shifter, the fully differential

topology is typically adopted, as illustrated in Fig. 5.8 [91], [93], [94]. The quadrature

splitter, two variable gain amplifiers (VGAs) and the analog summing circuit are the

core part of the phase shifter and are designed differentially. Baluns (single-to-

differential, and differential-to-single) are placed at the input and output ports to

129
provide a single-ended 50 Ω interface to the measurement system. A digital-to-analog

converter (DAC) synthesizes the necessary control logic signals for switches and

VGAs to provide the desired gains and polarities of each I/Q path. After adding up the

weighted I- and Q-vectors, an interpolated output signal with a synthetic phase θ and

magnitude M is obtained,

 Qout  
   tan 1   and M  Iout  +Qout 
2 2
(5.15)
 Iout  

Nevertheless, there are three major drawbacks of this traditional topology. The first

drawback is the limitation in small-signal gain and bandwidth due to the inevitable

passive components, such as the input balun and switch, especially when using lossy

CMOS technology. Secondly, a multi-channel digital-to-analog converter (DAC)

circuit is usually required to control switches and VGAs, which increases the control

complexity, design cost, power consumption and chip size. Note that it is desirable to

have the variable phase shift with only one DC control signal, in order to minimize

control complexity. Lastly, the fully differential configuration requires larger power

consumption and chip area.

In this section, a novel and simple scheme to realize a single-ended configuration

of the 360ºvector-sum phase shifter is presented, employing the proposed phase-

reversible VGA. To the best of the authors' knowledge, it is the first full-360ºvector-

sum phase shifter using the single-ended configuration and only one control voltage.

To verify the proposed scheme, a design example for wideband applications is

demonstrated in a standard 0.13-µm CMOS process. Section 5.4.2 describes the phase

shifter architecture and performance requirements. Design considerations of the key

building blocks are discussed in Section 5.4.3, while measurement results are

130
presented and compared with recently published wideband vector-sum phase shifters

in Section 5.4.4.

5.4.2 System Overview

Fig. 5.25 illustrates the block diagram of the proposed 360ºvector-sum phase

shifter, in which most building blocks are single-ended, requiring no input balun and

switches.

vI = sin(ωt) Wideband vFI +

Input Stage CI vOI
I-path -
VGA1

+
vin Quadrature Output vout
Splitter CI,CQ  -max,+max  Buffer

vQ = cos(ωt) Wideband vFQ +

Input Stage CQ vOQ
Q-path -
VGA2
DC-Control
Circuit

Fig. 5.25 Block diagram of the proposed 360ºvector-sum phase shifter using the phase-
reversible VGA.

The proposed vector-sum phase shifter consists of six functional blocks: the

external quadrature splitter, input stage for wideband impedance matching, phase-

reversible VGA core, DC-control circuit, analog adder, and output buffer. Assuming

that the magnitude of the input I- and Q-signals is unity and all circuit blocks have a

fixed gain of unity except the VGA, the output vout with the desired phase shift θ can

expressed as

131
 vout  CI  vI  CQ  vQ
 CI  sin  ωt   CQ  cos  ωt  (5.16)
 M  sin  ωt  θ 

where M denotes the maximum differential gain of the VGA, and gains of the I- and

Q-path should be set as CI = M·cos(θ) and CQ = M·sin(θ), accordingly. Owing to the

phase-reversible property of the VGA, a full-360ºphase shift can be accomplished.

Furthermore, to obtain the required CI and CQ and also to facilitate a continuously

adjustable phase shift, a compact DC control circuit is also proposed to replace the

digitized, costly, power- and size-consuming DAC. The proposed DC control

generator exhibits sine- and cosine-like voltage transfer curves simultaneously with

only one external control voltage. Therefore, the proposed 360ºvector-sum phase

shifter can be implemented with a single-ended input signal and controlled by only

one DC voltage, which is advantageous regarding the control complexity, chip size,

power consumption and costs.

Employing the proposed phase-reversible VGA, the phase reversal is obtained by

the role of transistors rather than passive balun and switches. Unfortunately, the

output signal (vOI or vOQ) of the phase-reversible VGA inherently contains a large

common-mode component. Thus, in order to realize the desired phase shift and

maintain a constant magnitude, the analog adder and output buffer should provide

sufficient common-mode suppression as well as differential gains. To evaluate the

effects caused by the suppressed common-mode component, an error analysis in

phase and magnitude performance for certain phase states is performed. Taking into

account the unwanted common-mode component in the phase shifter output, (5.16) is

rewritten as,

132
 vout  CI  vI  CQ  vQ
  Mcosθ+M CM  sin  ωt    Msinθ+M CM  cos  ωt  (5.17)
 M'  sin  ωt +φ 

where MCM = M/CMRR denotes the common-mode gain of the whole phase shifter,

and the common-mode rejection ratio (CMRR) is defined as the overall differential

gain over the common-mode gain. By varying the angle parameter θ, the locus of the

output vector is illustrated in Fig. 5.26.

Provided that MCM is much smaller than M, a phase control range of full-360ºis

attainable. However, the output magnitude is no longer constant. The output

magnitude can be expressed as

M'   Mcosθ+M CM    Msinθ+M CM 

2 2

(5.18)
 M  2 2MM CM sin  θ+45  2 M
2 2
CM

Msinθ+MCM

M
θ
M’
(MCM, MCM)
φ
Mcosθ+MCM 0 I

Fig. 5.26 Locus of the output vector with the presence of a small common-mode component.

133
From (5.18) it can be seen that the output magnitude is a function of θ. The maximum

output magnitude M'max = M  2MCM , at θ=45º; whereas the minimum output

magnitude M'min = M - 2M CM , at θ=135º. The magnitude variation of the output is

within 2 2M CM , which can be reduced by increasing the CMRR of the whole phase

shifter.

5.4.3 Design Considerations of Circuit Blocks

In this section, the functional principle and design considerations of key building

blocks are discussed. Circuits are designed using the standard 0.13-µm CMOS

process models and all component values are optimized through Cadence SPECTRE

simulations. Note that the single-ended configuration allows the commercial

quadrature couplers to be applied in the 360°vector-sum phase shifter. It extensively

facilitates the overall performance, since the external quadrature coupler module can

easily achieve multi-octave bandwidth and exhibit less I/Q mismatch, compared to its

on-chip counterparts. The I/Q generation in our phase shifter is realized by a

commercial Krytar 90ºhybrid coupler with operating bandwidth from 1 to 18 GHz.

Thus, the design of the wideband quadrature splitter is not given, as it is beyond the

scope of this thesis.

A. Current-Reuse Input Stage with Resistive Shunt Feedback

Common gate (CG) stage and resistive shunt feedback amplifier are two

commonly used topologies for wideband input matching [103]-[107]. As discussed in

Section 5.2.1, the common gate (CG) input stage can feature desirable properties for

wideband operation by achieving a wideband input matching. However, the

134
transconductance gm,CG of a CG stage is restricted by the input matching condition,

and cannot be freely traded off with other performance parameters, such as the 3-dB

bandwidth. Therefore, the current-reuse amplifier with resistive shunt feedback is

employed here as the input stage for both I- and Q-path. After a 50 Ω-matched

quadurature splitter, the input RF signal is divided into I- and Q-path with 90ºoffset.

For each path, a current-reuse shunt feedback amplifier is employed as the input stage.

As shown in Fig. 5.27, the complementary pair MNF-MPF are stacked to efficiently

boost the transconductance with a certain DC current, where the effective

transconductance gm,in = gm,nf+gm,pf. A local feedback resistor RF, connected between

the input and output nodes, offers the feasibility of self-biasing of the gate voltage.

Moreover, the input impedance matching is achieved by means of the feedback

resistor RF and the effective transconductance. The impedance seen at the input of the

unloaded shunt feedback current-reuse stage excluding its parasitics is given by

R F  rds
Zin  (5.19)
1  g m,in  rds

where rds denotes the parallel combination of channal resistances of the

complementary pair. Theoretically, the 3-dB bandwidth can be improved by reducing

the transconductance gm,in, while unlike the common gate input stage, the matching

condition of the feedback topology can still be maintained by properly selecting the

feedback resistor RF.

135
 VDD

MPF

RFI(Q) RF vI(Q)

MNF

Fig. 5.27 The current-reuse resistive shunt feedback stage for I/Q path.

To verify the presented analysis, Cadence SPECTRE simulations are performed.

Both common gate input stage and resistive shunt feedback input stage are unloaded

in simulations. Note that when connected to the latter stages, the gate parasitic

capacitance Cgs of the following stage is normally a well-estimated load impedance,

which is similar to an open circuit at low frequencies. The element values for both

topologies are optimized for input impedance matching and similar small-signal

voltage gain at low frequencies for fair comparison. Fig. 5.28 plots the simulated

input reflection coefficient S11 and small-signal voltage gain on a linear scale, for both

topologies. From the figure it is observed that, with a similar low-frequency voltage

gain of 4, the CG input stage exhibits a worse gain roll-off against frequency,

compared to the current-reuse input stage with resistive shunt feedback. Whereas both

topologies could achieve a simulated input return loss better than 10 dB up to 15 GHz.

In summary, the resistive shunt feedback stage is a favorable topology for UWB

applications regarding gain flatness and wideband input matching, and is therefore

adopted in our design.

136
 0

-2
4

Small-signal Voltage Gain

-4

-6

-8
|S11| (dB)

Common gate stage

Resistive shunt feedback stage 3
-10

-12

-14
2
-16

-18
0 3 6 9 12 15

Frequency (GHz)

Fig. 5.28 Simulated |S11| and small-signal voltage gain.

B. DC Control Generator

The middle state of the voltage transition in the conventional folding ADC circuit

(as shown in Fig. 5.29, two-staged folding circuit), is employed here for generating a

sine and cosine-shaped DC transfer curve [108]. The proposed sine-cosine DC

generator is shown in Fig. 5.30, which consists of six source coupled pairs, with

various reference voltages at a step voltage ΔVref of 0.2 V. The maximum reference

voltage becomes large and tends to drive the upper transistor into the linear region and

therefore distorts the voltage transfer curve when using thin-gate transistors in a 0.13-

µm CMOS. Although the step of reference voltage ΔVref can be further lowered by

increasing the aspect ratio of the input transistors, the circuit will suffer from more

power consumption and lower precision due to the process variations and device

mismatch. To address the problem and improve current matching, thick-gate

137
transistors which allow a supply voltage of 3 V, are used here to design the proposed

DC control circuit. Note that the reference voltages are generated by a resistor ladder

composed by 15 identical resistors, hence the reference voltages can follow on the

supply voltage VEE of 3 V, in a step of 0.2 V.

VDD

VDC+ VDC-

VRef1 VRef2

VCTL

Fig. 5.29 Conventional two-staged folding circuit [108].

VEE
RT

RB RB

VS+ VS-

MD2 MD3 1V MD2 MD3 1.4 V MD2 MD3 1.8 V

VG0 MD1
VG0 MD1 VG0 MD1

VCTL VEE
RT

RB RB

VC+ VC-

MD2 MD3 1.2 V MD2 MD3 1.6 V MD2 MD3 2V

VG0 MD1 VG0 MD1

VG0 MD1

Fig. 5.30 Schematic diagram of the proposed sine-cosine generator.

138
 Optimized device values are obtained through co-simulations with other

functional blocks. It is noteworthy that the quasi-differential DC control signals VS+-

VS- and VC+-VC- are properly designed, to ensure that the I-path and Q-path VGAs

(Fig. 5.32) operate within the linear-in-magnitude gain range. Therefore, the sine and

cosine-shaped voltage transfer curves of the DC control generator can be translated to

VGAs. The simulated quasi-differential control signals are shown in Fig. 5.31, which

indicates that within a control voltage ranging from 1 to 2 V, sine and cosine-like

transfer curves can be obtained simultaneously for more than a full period.

1.30
VS+
1.25 VS-
VC+
Output Control Signal (V)

1.20 VC-

1.15

1.10

1.05

1.00

0.95
1.0 1.2 1.4 1.6 1.8 2.0

VCTL (V)

Fig. 5.31 Simulated voltage transfer curves of the DC sine-cosine generator.

C. The Phase-Reversible VGA Core

The VGA plays a significant role for the overall performance of vector-sum

phase shifters, with respect to insertion loss, phase error and phase control range.

Here, the phase-reversible VGA core based on the single-balanced multiplier

(discussed in Section 5.3.2) is employed for weighing the amplitude of the I- and Q-

139
signal, which realizes the linear-in-magnitude controlled gain and reversible output

phase. The simplified circuit schematic is shown in Fig. 5.32. The inter-stage node D1

is identified as a dominant pole of the source-coupled structure due to the large

parasitic capacitance and relatively low node resistance presenting at the source of the

upper stage transistors (MM2-MM3). Therefore, an inter-stage inductor LM is added to

reduce the effect of the parasitic capacitance at node D1 and therefore achieves a

flatter gain frequency response.

Furthermore, since the quasi-differential DC signals VS+-VS- and VC+-VC-,

provided by the proposed DC control generator, ensure that the two VGAs operate

within the linear-in-magnitude gain range, the sine and cosine-shaped voltage transfer

curves of the DC control generator can be translated to the output of VGAs. To verify

the analysis and insights, Cadence AC simulations at 3 GHz are performed on the

proposed I- and Q-path VGAs together with the DC control circuit. The small-signal

voltage gain of two VGAs is plotted in linear scale against VCTL, as shown in Fig.

5.33. It indicates that the sine-shaped (vOI+, vOI-) and cosine-shaped (vOQ+, vOQ-) gain

control curves can be obtained for more than one cycle, with only one DC control

voltage VCTL ranging from 1 to 2 V. Therefore, the output phase, which relies on the

sine- and cosine-like gain of the I- and Q-path, can be continuously adjusted, while

the output magnitude changes little.

140
 VDD VDD

RM RM RM RM

vOI+ vOI- vOQ+ vOQ-

VS+ VS- VC+ VC-
MM2 MM3 MM2 MM3
D1 D1

CP CP
LM LM

vI MM1 vQ MM1

(a) (b)

Fig. 5.32 Schematic diagram of (a) I-path VGA. (b) Q-path VGA.

10
vOI+
vOI-
8 vOQ+
Small-Signal Voltage Gain

vOQ-

0
1.0 1.2 1.4 1.6 1.8 2.0

VCTL (V)

Fig. 5.33 Simulated gain control curves of both I- and Q-path.

141
D. Gilbert-Cell Adder With Common-Mode Suppression

The Gilbert-cell topology is employed here to realize summation of the

differential I- and Q-signals in the current domain [11]. The simplified schematic is

shown in Fig. 5.34, where the four output signals (vOI+-vOI- and vOQ+-vOQ-) from the I-

and Q-path VGAs are fed to the gate of upper transistors. The four branches are cross-

connected to have one differential output. Note that the inductive peaking technique is

also applied here for the bandwidth enhancement. The peaking inductance LS and

other component values are optimized for the targeted bandwidth. Fig. 5.35 shows the

differential voltage gain versus VCTL, for both phase and magnitude performance. It

indicates that the continuous phase shift of over 400º is accomplished in the

differential output (vsum+-vsum-), while the magnitude varies little.

VDD

LS LS

RS RS
vsum+ vsum-

vOI+ vOI- vOQ+ vOQ-

MS2 MS3 MS2 MS3

VG1 MS1 VG1 MS1

Fig. 5.34 Schematic diagram of the differential summing circuit.

142
 0 1.5
Phase of the differential gain@3 GHz
Magnitude of the differential gain@3 GHz
-100 1.4

Simulated Magnitude
Simulated Phase (o)

-200 1.3

-300 1.2

-400 1.1

-500 1.0
1.0 1.2 1.4 1.6 1.8 2.0

VCTL (V)

Fig. 5.35 Simulated small-signal voltage gain at 3 GHz.

As shown in Fig. 5.33, there is a large common-mode (CM) component in the

small-signal voltage gain of VGAs. The Gilbert-cell adder based on two source-

coupled differential pairs, inherently suppresses the CM component before summation.

Ignoring any effects caused by device or process mismatch, the CMRR of this stage,

which is defined as the ratio between differential-mode gain Adm and the common-

mode gain Acm, can be derived,

A dm
CMRR  20lg( )
A cm
gmZL
 20lg( ) (5.20)
1
Z L /( +2Zds,S1 )
gm
 20lg(1+2g m Zds,S1 )

where gm denotes the transconductance of upper transistors MS2-MS3. ZL is the load

impedance composed of RS in series with LS, and Zds,S1 is the equivalent impedance

seen at the drain node of lower transistor MS1, which consists of the drain-source

143
resistance of MS1 in parallel with the parasitic capacitance present at this node. Owing

to the large drain-source impedance Zds,S1 up to a certain frequency, gm·Zds,S1 »1 can

be satisfied, i.e., the common-mode gain is lower than the differential-mode gain,

which enhances the common-mode suppression. The simulated CMRR is shown in

Fig. 5.36, which drops when frequency increases, caused by the decreased Zds,S1.

30

Gilbert-cell Adder
D-to-S Converter
25
Simulated CMRR (dB)

20

15

10

5
0 5 10 15 20
Frequency (GHz)

Fig. 5.36 Simulated CMRR versus frequency of the stages after the VGAs.

E. Output Buffer Stage Incorporating D-to-S Converter

To interface with the single-ended 50 Ω measurement system, an output buffer

consisting of a differential-to-single-ended (D-to-S) converter and output matching

network is designed. The simplified schematic is shown in Fig. 5.37. The bias

circuitry and decoupling capacitors are not shown. Note that, the D-to-S converter

exhibits common-mode rejection [84]. As shown in Fig. 5.36, the simulated CMRR of

the D-to-S converter is larger than 10 dB throughout the target band, which further

suppresses the common-mode signals generated in the I- and Q-path VGAs.

144
 D-to-S Converter Modified 2-Stage Cherry-Hooper Buffer

VDD VDD VDD VDD VDD

vsum+ MB2 MB4 MB10

MB6 MB8
RF1 LF RF2 vout

vsum- MB1 MB3 MB5 MB7 MB9

Fig. 5.37 Simplified schematic of the output buffer stage.

A two-stage Cherry-Hooper amplifier is synthesized with the local feedback

inductor LF in the last stage for inductive peaking purposes at the higher passband,

which successfully alleviates the severe gain roll-off against frequency. All

component values are optimized through SPECTRE simulations considering

bandwidth, small-signal gain and input/output matching criteria. The design values for

the entire vector-sum phase shifter are summarized in Table 5.6. Note that gate length

of the thick-gate transistors MD1-MD3 is 0.28 µm, and for the other transistors is 0.13

µm.

145
 TABLE 5.6
DESIGN VALUES OF THE PROPOSED VECTOR-SUM PHASE SHIFTER

MD1 (µm) 52 MB3 (µm) 12 RB (Ω) 1000

MD2, MD3 (µm) 50 MB4 (µm) 9 RF (Ω) 300

MNF (µm) 20 MB5 (µm) 16 RM (Ω) 400

MPF (µm) 20 MB6 (µm) 16 RS (Ω) 40

MM1 (µm) 12 MB7 (µm) 16 RF1 (Ω) 600

MM2, MM3 (µm) 20 MB8 (µm) 12 RF2 (Ω) 100

MS1 (µm) 16 MB9 (µm) 20 LM (nH) 9@18 GHZ

MS2, MS3 (µm) 12 MB10 (µm) 20 LS (nH) 5@22 GHz

MB1, MB2 (µm) 16 RT (Ω) 900 LF (nH) 7.5@22 GHz

5.4.4 Measurement Results

The vector-sum phase shifter and DC control generator are realized in

GlobalFoundries 0.13-µm CMOS technology in separated chips, to facilitate a

flexible and robust measurement. Die microphotographs of the phase shifter and DC

control generator are shown in Fig. 5.38 (a) and (b). The die size is 1.20×1.10 mm2

and 0.64×0.47 mm2 respectively, mainly determined by the pad frame. The core area,

excluding DC decoupling capacitors and pads, only takes up approximately 30% of

the total area. The chips are mounted on Rogers RO4003 substrate with DC pads

wire-bonded for bias and tuning purposes, while RF signals are measured through

coplanar ground-signal-ground (GSG) on-wafer probes. The phase shifting and large-

signal performance are measured using Rohde and Schwarz ZVA50 vector network

analyzer, and Agilent 8565EC spectrum analyzer.

146
 (a)

(b)

Fig. 5.38 Microphotographs of: (a) vector-sum phase shifter. (b) DC control generator.

The CMOS prototype is measured as a two-port network by means of an external

90ºhybrid coupler (Krytar, amplitude imbalance ≤ ±0.5 dB, phase imbalance ≤ ±10º

@ 1-18 GHz) for generating the single-ended I- and Q-signal. The following

measurements have been carried out under supply voltages of 1.5 V and 3V, for the

phase shifter and DC control generator, respectively. The current consumption of the

147
phase shifter is 14 mA, and 1.5 mA is consumed by the DC control generator, which

leads to an overall power consumption of 25.5 mW.

A total of thirty states of the two-port S parameters are measured by tuning the

control voltage VCTL from 1 to 2 V. Since the external 90ºhybrid coupler isolates the

input terminal from the rest of the chip, the phase tuning by the control voltage VCTL

does not disturb the |S11| performance. Similarly, |S22| also changes very little among

different phase states, since a constant output impedance is set by the output buffer

stage. Fig. 5.39 displays the typical simulation and measurement results of |S11| and

|S22|, which indicates that the measured input and output return loss are better than 10

dB and 5 dB from 2 to 16 GHz. Note that the measured output return loss of this

phase shifter is still acceptable, if the subsequent circuit block after the phase shifter

should possess a good input matching. Fig. 5.40 shows the measured insertion loss,

together with the simulated curves. It can be observed that the maximum measured

|S21| always occurs around 14 GHz, which ranges from -3.5 and -1 dB for all the 30

states, and the 3-dB gain bandwidth is measured slightly larger than 2-16 GHz. Here,

we can find a general agreement between simulated and measured S-parameters. The

relatively large discrepancies at high frequencies are due to the lack of EM models of

interconnects.

148
 0

-10

|S11|, |S22| (dB)

-20

-30
Simulated S11
Simulated S22
-40 Measured S11
Measured S22

-50
0 4 8 12 16 20

Frequency (GHz)

Fig. 5.39 |S11| and |S22| versus frequency.

0
Simulated

-5
Measured

-10
S21 (dB)

-15

-20

-25
0 2 4 6 8 10 12 14 16 18 20

Frequency (GHz)

Fig. 5.40 Simulated and measured |S21|.

Subsequently, using the measured |S21| in Fig. 5.40, the root-mean-square (RMS)

amplitude error is calculated at each measured frequency [93] and shown in Fig. 5.41,

which has a maximum value of 1.05 dB throughout the 2-16 GHz band.

149
 1.1

1.0 Measurement
Simulation
RMS Amplitude Error (dB) 0.9

0.8

0.7

0.6

0.5

0.4

0.3
2 4 6 8 10 12 14 16

Frequency (GHz)

Fig. 5.41 Measured and simulated RMS amplitude error versus frequency.

The phase performance of this CMOS prototype is also characterized. Note that

the phase shift of this CMOS prototype is continuously adjustable. In total, thirty

states of insertion phases are measured by tuning the control voltage VCTL from 1 to 2

V, which are equally distributed in steps of 15°at the center frequency of 9 GHz. The

reference state is set at VCTL = 1 V, and therefore subtracted from all the measured

phase responses. Fig. 5.42 shows the relative phase shift versus frequency for all

phase states, indicating an adjustable phase shift over 400°within the 2-16 GHz band.

The RMS phase error, which is commonly used to characterize the phase performance

of digital phase shifters [93], is also applied here. As shown in Fig. 5.43, the measured

RMS phase error is less than 6.3ºover the 2-16 GHz band.

150
 450

400

Relative Phase Shift (o)

350

300

250

200

150

100

50

0
2 4 6 8 10 12 14 16
Frequency (GHz)

Fig. 5.42 Measured relative phase shifts versus frequency.

6 Measurement
Simulation
o
RMS Phase Error ( )

2 4 6 8 10 12 14 16
Frequency (GHz)

Fig. 5.43 Measured and simulated RMS phase error versus frequency.

The large-signal performance of the proposed phase shifter is measured from 2 to

16 GHz in steps of 1 GHz, when the control voltage VCTL = 1.5 V. The measured

input referred 1-dB compression point (IP1-dB) versus frequency is plotted in Fig. 5.44,

which reveals a minimum value of -20 dBm at the frequency of 2 GHz, and a

151
maximum value of -15 dBm at 16 GHz.

-10

Measured P1-dB (dBm) VCTL=1.5 V

-15

-20

-25
2 4 6 8 10 12 14 16
Frequency (GHz)

Fig. 5.44 Measured input-referred P1-dB versus frequency.

A performance summary and comparison between this work and other recently-

published vector-sum phase shifters is shown in Table 5.7. Note that our work and [94]

report a phase range of more than 360°, which is beneficial for narrow-band true time

delay (TTD) applications by realizing a larger time delay range. The proposed vector

phase shifter exhibits the largest bandwidth, while still possessing some advantages in

terms of low control complexity, good in-band input matching, low RMS amplitude

and phase error. With all the competitive performance figures, the proposed CMOS

vector-sum phase shifter is an excellent candidate for wideband phased array

applications.

152
 TABLE 5.7
PERFORMANCE SUMMARY AND COMPARISON TABLE

This
[94] [93] [95] [91] [96] [97]
Work
Bandwidth
2-16 2-3 2.3-4.8 4.3-6.1 5-18 6-18 18-32
(GHz)
Gain (dB) -5~-2 0~5.5 -8~-3 2~4 -2~-0.2 11~19.5 -2~0
Input return loss > 10, only @
> 10 >10 >2 > 10 >3 N.A.
(dB) 11.2~15.2 GHz
Phase range (°) 435 360 360 360 360 360 810
RMS amplitude
≤ 1.05 ≤ 1.2 ≤ 1.1 ≤ 0.5 ≤ 1.7 ≤ 1.05 N.A.
error (dB)
RMS phase
≤ 6.3 ≤5 ≤ 1.4 ≤ ±9 ≤ 10 ≤ 5.6 N.A.
error (º)
Power (mW) 25.5 24 19 29.2 8.7 61.7 800
1 3 5 3 10 8 1
Control voltages
analog analog analog analog analog digital analog
IP1-dB (dBm) -20~-15 -13.5 0.6~3 3 -6.7~-4 -39~-36 N.A.

CMOS CMOS CMOS GaAs CMOS SiGe InP/InGaAs

Process
0.13-µm 0.18-µm 0.18-µm 0.6-µm 0.13-µm 0.18-µm HBT

5.4.5 Conclusions

A new wideband CMOS vector-sum phase shifter is presented employing the

proposed phase-reversible VGA and the DC control generator, which successfully

realizes a continuously adjustable phase control range of more than 400ºwith only

one DC control voltage. The CMOS prototype exhibits a measured 3-dB bandwidth of

2-16 GHz, and the average insertion loss ranges from 5 to 2 dB, associated with all

measured states. The RMS gain and phase error are less than 1.05 dB and 6.3°over

the measured frequency span. The total power consumption is 25.5 mW, where 21

mW is dissipated by the phase shifter core and 4.5 mW is consumed by the DC

control circuit. Wideband matching networks are also adopted to ensure good

impedance-matching. The measured input and output reflection coefficient are better

than -10 and -5 dB, respectively, throughout the entire band. To the best of the

153
authors' knowledge, it is the first full-360ºphase shifter demonstrated in CMOS

technology using the single-ended configuration and one control voltage, without

input balun and switches. Measured results show that this proposed work competes

quite well with other full-360ºvector-sum phase shifters, especially for wideband

applications.

154
Chapter 6

Conclusions and Recommendations

6.1 Summary

The demand for higher frequency and larger bandwidth operation of RF front-end

circuits has stimulated tremendous research in innovative circuit topologies and

techniques to overcome design challenges for RF and microwave ICs.

In this thesis, a subharmonic mixer with a novel biasing scheme is proposed using

the conventional cascode FET cell. The proposed SHM, operating at a low supply voltage

with reduced optimum LO power, could be an attractive solution for frequency

conversion in microwave and millimeter-wave communication systems.

Next, to address the design issues of wideband mixer regarding both the RF and IF

bandwidths, a 1-10 GHz Gilbert-cell based mixer with cross-coupled feedback is

proposed and implemented in a standard 0.13-µm CMOS technology. The proposed

mixer exhibits an RF bandwidth from 1 GHz to 10 GHz and IF bandwidth from 100 MHz

to 1 GHz with a conversion gain of 5.5±2.5 dB. Due to the superiority of the proposed

155
topology, both port impedance matching and good gain flatness are achieved throughout

the wide RF and IF band.

Lastly, the vector-sum phase shifter, which is among the most popular active phase

shifter architectures, is investigated, especially to improve the bandwidth, phase control

range, as well as minimizing the control complexity. Two wideband VGAs with linear-

in-magnitude controlled gain are proposed for vector-sum phase shifter applications, one

of which also exhibits the reversible output phase. Based on the proposed phase-

reversible VGA, a 2-16 GHz vector-sum phase shifter with over 400°phase control range

is demonstrated in 0.13-µm CMOS.

6.2 Review of Contributions

This thesis has contributed to the field of microwave engineering in several ways

regarding the design and application of low voltage subharmonic mixer, wideband mixer,

and wideband phase control circuits.

Subharmonic mixers have applications in superheterodyne systems as a method of

reducing the local oscillator frequency, as well as in direct-conversion architectures

where the use of a subharmonic mixer can reduce the significant problem of LO self-

mixing. In Chapter 3, a novel biasing scheme is proposed to implement a subharmonic

mixer employing the conventional cascode FET cell. The implementation in discrete

circuit form with measurement results was presented. Furthermore, due to the superiority

of the proposed biasing scheme, this subharmonic mixer had a conversion gain and other

156
performance metrics similar to fundamental mixers using the conventional cascode FET

cell, and the performance comparison was made and summarized. This circuit was the

first subharmonic mixer using Class-B biasing on a conventional mixer topology, and it

achieves low voltage and low LO power requirement as well as the high conversion gain,

regardless of fabrication technology used. Note that the aim of the discrete design is to

validate and demonstrate the feasibility of the proposed technique. Implementation in an

integrated circuit can drastically reduce these problems and increase the frequency of

operation further. This circuit also provides the foundation for a more advanced higher-

order and higher-frequency SHM.

Next, the RF bandwidth is an important parameter for a mixer as it determines the

spectral coverage of the RF band with a proper adjustment of the LO frequency for a

fixed IF. Meanwhile, the IF bandwidth also needs to be sufficiently large as it limits the

allowed spectral width of individual channels in UWB systems. For a wideband mixer

design, it is desirable but challenging to have broadband impedance matching at the input

and output ports to ensure effective power transfers. Chapter 4 provided a CMOS 1-10

GHz mixer based on the modified Gilbert-cell topology. Adopting the CG transistor as

the RF stage, the proposed mixer inherently has wideband impedance matching at the RF

port, however the transconductance of the RF stage is limited and therefore degrades the

conversion gain. Furthermore, by incorporating the cross-coupled active feedback into

the RF stage, high conversion gain can be achieved while maintaining excellent gain

flatness. Meanwhile, owing to the current-bleeding mechanism realized by the added

complementary transistor pair, the linearity tends to be improved as well as the

157
conversion gain. An interstage inductor is also employed to alleviate the conversion gain

roll-off at higher frequencies. In addition, the proposed mixer adopts on-chip LO and IF

active baluns to facilitate the interface with single-ended 50 Ω measurement systems, and

achieve LO and IF port impedance matching. Fabricated in a standard 0.13 µm CMOS

process, the proposed wideband mixer is measured with an RF bandwidth of 9 GHz from

1 to 10 GHz and IF bandwidth of 900 MHz from 100 MHz to 1 GHz, with a conversion

gain of 5.5±2.5 dB. Note that the reflection coefficients for both RF and IF ports

throughout the whole band are lower than -10 dB. With a compact circuit layout, it can be

integrated with other RF building blocks and the baseband digital circuitry for system-on-

chip (SOC) applications.

In Chapter 5, design considerations of wideband VGAs are first investigated,

regarding gain flatness and wideband impedance matching. Next, the feasibility of output

phase-reversal of VGAs is also studied, in order to facilitate a 360°vector-sum phase

shifter with the single-ended input signal. Subsequently, employing the proposed phase-

reversible VGA, a full 360ºvector-sum phase shifter is presented in the single-ended

configuration. It is noteworthy that, continuously adjustable phase is achieved with only

one DC control voltage, by means of the quasi-sine and cosine DC control generator.

Fabricated in a standard 0.13-µm CMOS technology, the proposed vector-sum phase

shifter exhibits a continuously adjustable phase shift of more than 400ºthroughout the

entire band of 2-16 GHz, and the average in-band insertion loss varies from 5 to 2 dB,

associated with all measured phase states. The RMS gain and phase error is less than 1.05

dB and 6.3° respectively, over the measured frequency span. The total power

158
consumption is 25.5 mW. The measured input and output reflection coefficient are lower

than -10 and -5 dB throughout the 2-16 GHz band. To the best of the authors' knowledge,

it is the first full-360ºphase shifter demonstrated in CMOS technology using single-

ended configuration, and also exhibiting the minimum control complexity.

6.3 Recommendations

There are several suggestions for future work on related topics.

The proposed 2× subharmonic mixer topology becomes even more attractive when

the operational frequency increases, since it is more difficult to design a local oscillator at

higher frequencies. Therefore, the proposed 2× subharmonic mixer could be implemented

and verified at a much higher frequency, for example, 40 GHz or above, in monolithic IC

form. Moreover, a direct-conversion receiver could be designed using the proposed 2×

subharmonic mixer in order to determine the maximum performance that is attainable

with the use of the proposed subharmonic mixer. An increase in the order of subharmonic

mixing could be investigated and compared. For example, a 4× or 8× subharmonic mixer

using the basic concept provided for the proposed 2× subharmonic mixer. However, this

may be challenging using the proposed topologies since it would require splitting the LO

into 4 or 8 phases. Furthermore, a study into increasing the performance of the proposed

subharmonic mixers could be undertaken.

Regarding the CMOS wideband mixer design, gain flatness can be further improved,

as well as the RF and IF bandwidth. Additionally, a low-noise, low voltage or high-

159
linearity version of the proposed wideband mixer could be designed to further increase

the attractiveness of using the proposed topology in a variety of applications, besides the

superior features of wideband matching and flat conversion gain.

Last but not least, it is challenging to design the on-chip quadrature coupler for

wideband applications, due to the substrate losses and the inferior Q-factors of the

passive components of CMOS technology. Therefore, a study into the design of

wideband quadrature coupler as the I/Q splitter for vector-sum phase shifter applications

using CMOS technology could be undertaken.

160
References

[1] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edition.

New York: Cambridge University Press, 2004.

[2] H. Bennett, R. Brederlow, J. Costa et al., “Device and technology evolution for Si-

based RF integrated circuits,” IEEE Trans. on Electron Devices, vol. 52, no. 7, pp.

1235-1258, July 2005.

[3] A. Joseph, D. Harame, B. Jagannathan et al., “Status and Direction of

Communication Technologies: SiGe BiCMOS and RFCMOS,” Proceedings of the

IEEE, vol. 93, no. 9, pp. 1539-1558, Sept. 2005.

[4] S. Lee, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R.

Williams, L. Wagner, J. Kim, J.-O. Plouchart, J. Pekarik, S. Springer, and G.

Freeman, “Record RF Performance of 45-nm SOI CMOS Technology,” IEEE

International Electron Devices Meeting, pp. 255–258, Dec. 2007.

161
[5] G. J. Foschini and M. J. Gans, “On limits of wireless communications in a fading

environment when using multiple antennas,” Wireless Personal Communications,

vol. 6, no. 3, pp. 311-335, Mar. 1998.

[6] A. F. Molisch and M. Z. Win, “MIMO systems with antenna selection,” IEEE

Microwave Magazine, vol. 5, no. 1, pp. 46-56, Mar. 2004.

[7] J. Paramesh, R. Bishop, K. Soumyanath, and D. J. Allstot, “A four-antenna receiver

in 90 nm CMOS for beamforming and spatial diversity,” IEEE J. Solid-State

Circuits, vol. 40, no. 12, pp. 2515–2524, Dec. 2005.

[8] A. Hajimiri, H. Hashemi, A. Natarajan, X. Guan, and A. Komijani, “Integrated

phased array systems in silicon,” Proc. IEEE, vol. 93, no. 9, pp. 1637–1655, Sep.

2005.

[9] D. Parker and D. C. Zimmermann, “Phased arrays—Part I: Theory and

architectures,” IEEE Trans. on Microw. Theory Tech., vol. 50, no. 3, pp. 678–687,

Mar. 2002.

[10] J. Roderick, H. Krishnaswamy, K. Newton, and H. Hashemi, “Silicon based ultra-

wideband beamforming,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1726–

1739, Aug. 2006.

[11] A. Natarajan, A. Komijani, and A. Hajimiri, “A fully integrated 24-GHz phased-

array transmitter in CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp.

2502–2514, Dec. 2005.

162
[12] B. E. Tullson, “Alternative applications for a 77 GHz automotive radar,” in Record

IEEE Radar Conf., May 2000, pp. 273–277.

[13] M. Chua and K. Martin, “A 1 GHz programmable analog phase shifter for adaptive

antennas,” in Proc. IEEE Custom Integrated Circuits Conf., May 1998, pp. 11–14.

[14] P.-S. Wu, H.-Y. Chang, M.-D. Tsai, T.-W. Huang, and H. Wang, “New miniature

15–20-GHz continuous-phase/amplitude control MMICs using 0.18-μm CMOS

technology,” IEEE Trans. on Microw. Theory Tech., vol. 54, no. 1, pp. 10–19, Jan.

2006.

[15] H. Zarei and D. J. Allstot, “A low-loss phase shifter in 180 nm CMOS for multiple-

antenna receivers,” in IEEE ISSCC Dig. Tech. Papers, Feb.2004, pp. 392–393.

[16] D.K.A Kpogla, C.Y. Ng and I.D. Robertson, “Shifted Quadrant Vector Modulator”

IEEE Electronics Letters, vol. 39, no: 14, July 2003.

[17] K. Miyaguchi, M. Hieda, M. Hangai, T. Nishino, N. Yunoue, Y.Sasaki, and M.

Miyazaki, “An ultra compact C-band 5-bit MMIC phase shifter based on all-pass

network,” in Proc .Eur. Microw. Integr. Circuits Conf., Sep. 2006, pp. 277–280.

[18] D.Viveiros Jr., D. Consonni, and A.K.Jastrzebski, “A tunable all-pass MMIC active

phase shifter,” IEEE Trans. on Microw. Theory Tech., vol. 50, no. 8, pp.1885-1889,

Aug. 2002.

163
[19] J. B. Hacker, R. E. Mihailovich, M. Kim and J. F. DeNatale, “A Ka-band 3-bit RF

MEMS true-time-delay network,” IEEE Trans. on Microw. Theory Tech., vol. 51,

no. 1, pp. 305–309, Jan. 2003.

[20] Y. Zheng and C.E.Saavedra, “An ultra-compact CMOS variable phase shifter for

2.4-GHz ISM applications,” IEEE Trans. on Microw. Theory Tech., vol. 56, no. 6,

pp. 1349–1354, Jun. 2008.

[21] F. Ellinger, R. Vogt and W. Bachtold, “Ultra compact reflective-type phase shifter

MMIC at C-band with 360 phase-control range for smart antenna combining,”

IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 481–486, Apr. 2002.

[22] H. Zarei, C. T. Charles and D. J. Allstot, “Reflective-type phase shifters for

multiple-antenna transceivers,” IEEE Trans. Circuits Systems I—Reg. Papers, vol.

54, no. 8, pp. 1647–1656, Aug. 2007.

[23] K.Miyaguchi , M. Hieda, K.Nakahara, H.Kurusu, M.Nii, M.Kasahara, T.Takagi

and S.Urasaki, “An ultra-broadband reflection-type phase shifter MMIC with series

and parallel LC circuits ,” IEEE Trans on Microw. Theory tech., vol. 49, no. 12, pp.

2446-2454, Dec. 2001

[24] G. Velu, K. Blary, L. Burgnies, A.Marteau, G. Houzet, D. Lippens and J. C. Carru,

“A 360 BST phase shifter with moderate bias voltage at 30 GHz,” IEEE Trans. on

Microw. Theory Tech., vol. 55, no. 2, pp. 438–444, Feb. 2007.

164
[25] M. Abdalla, G. V. Eleftheriades and K. Phang, “A differential 0.13-µm CMOS

active inductor for high-frequency phase shifters,” in Proc. IEEE Int. Symp.

Circuits Syst. (ISCAS), May 2006, pp. 3341–3344.

[26] Alireza Asoodeh and Mojtaba Atarodi, “A Full 360 Vector-Sum Phase Shifter

With Very Low RMS Phase Error Over a Wide Bandwidth,” IEEE Trans. on

Microw. Theory Tech., vol. 60, no. 6, pp. 1626–1634, June. 2012.

[27] E. Armstrong, “Method of Receiving High Frequency Oscillation,” U.S. Patent

1,342,885, June 8, 1920.

[28] A. A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communications,”

IEEE J. Solid-State Circuits, vol. 30, pp. 1399–1410, December 1995.

[29] R. Svitek and S. Raman, “DC Offsets in Direct-Conversion Receivers:

Characterization and Implications,” IEEE Microwave Magazine, vol. 6, pp. 76–86,

September 2005.

[30] B. Jackson and C. E. Saavedra, “A CMOS Ku-Band 4x Subharmonic Mixer,” IEEE

J. Solid-State Circuits, vol. 43, pp. 1351–1359, June 2008.

[31] H.-M. Hsu and T.-H. Lee, “A Zero-IF Sub-Harmonic Mixer with High LO-RF

Isolation using 0.18 µm CMOS Technology,” in IEEE European Microwave

Integrated Circuits Conference, (Manchester, UK), pp. 336–339, September 2006.

[32] S. A. Maas, Microwave Mixers, 2nd Edition. Boston, MA: Artech House, 1993.

165
[33] P. H. Siegel, R. P. Smith, S. Martin, and M. Gaidis, “2.5-THz GaAs monolithic

membrane-diode mixer,” IEEE Trans. on Microw. Theory Tech., vol. 47, pp. 596–

604, May 1999.

[34] M. Morgan and S. Weinreb, “A monolithic HEMT diode balanced mixer for 100-

140 GHz,” IEEE MTT-S Intl. Microwave Symp. Digest, pp. 99-102, 2001.

[35] B. Gilbert, “A precise four-quadrant multiplier with subnanosecond response,”

IEEE J. Solid-State Circuits, vol. SC-3, pp. 365–373, Dec. 1968.

[36] R. G. Meyer, W. D. Mack, and J. J. E. M. Hageraats, “A 2.5-GHz BiCMOS

Transceiver for Wireless LAN’s,” IEEE J. Solid-State Circuits, vol. 32, pp. 2097–

2104, December 1997.

[37] C.-R. Wu, H.-H. Hsieh, and L.-H. Lu, “An Ultra-Wideband Distributed Active

Mixer MMIC in 0.18-µm CMOS Technology,” IEEE Trans. on Microw. Theory

Tech., vol. 55, no. 4, pp. 625–632, Apr. 2007.

[38] J. Park, C.-H. Lee, B.-S. Kim, and J. Laskar, “Design and Analysis of Low Flicker-

Noise CMOS Mixers for Direct-Conversion Receivers,” IEEE Trans. on Microw.

Theory Tech., vol. 54, no. 12, pp. 4372-4380, Dec. 2006.

[39] S.-G. Lee and J.-K. Choi, “Current-reuse bleeding mixer,” Electron. Lett., vol. 36,

no. 8, pp. 696–697, April 2000.

166
[40] C.-R. Wu, H.-H. Hsieh and L.-H. Lu, “An ultra-wideband distributed active mixer

MMIC in 0.18- m CMOS technology,” IEEE Trans. on Microw. Theory Tech., vol.

55, no. 4, pp. 625–632, Apr. 2007.

[41] M. Terrovitis and R. Meyer, “Intermodulation distortion in current-commutating

CMOS mixers,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1461-1473, Oct

2000.

[42] Q. Li and J. Yuan, “Linearity analysis and design optimization for 0.18 µm CMOS

RF mixer,” IEE Proceedings Circuits, Devices and Systems, vol. 149, no. 2, pp.

112-118, April 2002.

[43] B. Gilbert, “The multi-tanh principle: A tutorial overview,” IEEE J. Solid-State

Circuits, vol. 33, pp. 2–17, Jan. 1998.

[44] H.-C. Wei, R.-M. Weng and K.-Y. Lin, “A 1.5 V high-linearity CMOS mixer for

2.4 GHz applications,” Proceedings of the International Symposium on Circuits and

Systems, May 2004.

[45] O. Mitrea, C. Popa, A. Manolescu and M. Glesner, “A linearization technique for

radio frequency CMOS Gilbert-type mixers," Proceedings of the IEEE

International Conference on Electronics, Circuits and Systems, vol. 3, pp. 1086-

1089, Dec. 2003.

[46] H.-C. Chen, T. Wang, S.-S. Lu and G.-W. Huang, “A Monolithic 5.9-GHz CMOS

I/Q Direct-Down Converter Utilizing a Quadrature Coupler and Transformer-

167
 Coupled Subharmonic Mixers,” IEEE Microwave and Wireless Components

Letters, vol. 16, pp. 197–199, April 2006.

[47] J.-H. Tsai, H.-Y. Yang, T.-W. Huang, and H. Wang, “A 30–100 GHz Wide-band

Sub-Harmonic Active Mixer in 90 nm CMOS Technology,” Microwave and

Wireless Components Letters, IEEE, vol. 18, pp. 554–556, Aug. 2008.

[48] T.-H. Wu, S.-C. Tseng, C.-C. Meng, and G.-W. Huang, “GaInP/GaAs HBT Sub-

Harmonic Gilbert Mixers Using Stacked-LO and Leveled-LO Topologies,” IEEE

Trans. on Microw. Theory Tech., vol. 55, pp. 880–889, May 2007.

[49] L. Sheng, J. C. Jensen, and L. E. Larson, “A wide-bandwidth Si/SiGe HBT direct

conversion subharmonic mixer/downconverter,” IEEE J. Solid-State Circuits, vol.

35, pp. 1329-1337, September 2000.

[50] K. Nimmagadda and G. Rebeiz, “A 1.9 GHz double-balanced subharmonic mixer

for direct conversion receivers,” IEEE Radio Frequency Integrated Circuits (RFIC)

Symposium, pp. 253-256, 2001.

[51] R. M. Kodkani, L. E. Larson and E. Lawrence, “A 24-GHz CMOS direct-

conversion sub-harmonic downconverter,” in IEEE Radio Frequency Integrated

Circuits (RFIC) Symposium, pp. 485–488, June 2007.

[52] K.-J. Koh, M.-Y. Park, C.-S. Kim and H.-K. Yu, “Subharmonically Pumped CMOS

Frequency Conversion (Up and Down) Circuits for 2-GHz WCDMA Direct-

168
 Conversion Transceiver,” IEEE J. Solid-State Circuits, vol. 39, pp. 871-884, June

2004.

[53] M.-Y. Lee, C.-Y. Jeong, C. Yoo, Y.-H. Kim, J.-H. Hwang and J.-S. Park, “Fully-

integrated CMOS Direct-Conversion Receiver for 5GHz Wireless LAN,” in IEEE

Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, January

2007.

[54] B. G. Perumana, C.-H. Lee, J. Laskar and S. Chakraborty, “A Subharmonic CMOS

Mixer Based on Threshold Voltage Modulation,” IEEE MTT-S International

Microwave Symposium Digest, pp. 33-36, June 2005.

[55] K. Kawakami, M. Shimozawa, H. Ikematsu, K. Itoh, Y. Isota and O. Ishida, “A

millimeter-wave broadband monolithic even harmonic image rejection mixer,” in

Proc. IEEE MTT-S International Microwave Symposium Digest, vol. 3, pp. 1443–

1446, Jun. 1998.

[56] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill,

2000.

[57] M. Goldfarb, E. Balboni, and J. Cavey, “Even harmonic double-balanced active

mixer for use in direct conversion receivers,” IEEE J. Solid-State Circuits, vol. 38,

no. 10, pp.1762 -1766, Oct. 2003.

169
[58] T. Hui Teo and W. G. Yeoh “Low-power short range radio CMOS subharmonic RF

front-end using CG-CS LNA”, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55,

pp. 658-662, Jul. 2008.

[59] T.-H. Wu, S.-C. Tseng, C.-C. Meng and G.-W. Huang, “GalnP/GaAs HBT sub-

harmonic Gilbert mixers using stacked-LO and levelled-LO topologies,” IEEE

Trans. on Microw. Theory Tech., vol. 55, pp. 880-889, May 2007.

[60] S.-Y. Lee, M.-F. Huang, and C. J. Kuo, “Analysis and implementation of a CMOS

even harmonic mixer with current reuse for heterodyne/direct conversion receivers,”

IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 9, pp.1741 -1751, Sept.

2005.

[61] A. Anakabe, J. M. Collantes, J. Portilla, J. Jugo, S. Mons, A. Mallet, and L.

Lapierre, “Analysis of odd-mode parametric oscillations in HBT multi-stage power

amplifiers,” Eur. Microw. 11th GaAs Symp., pp.533 -536, 2003.

[62] J. Kim, M.-S. Jeon, D. Kim, J. Jeong, and Y. Kwon, “High-performance V-band

cascode HEMT mixer and downconverter module,” IEEE Trans. on Microw.

Theory Tech., vol. 51, no.3, pp. 805-810, Mar. 2003.

[63] J. H. Kim and Y. Kwon, “Intermodulation analysis of dual-gate FET mixers,” IEEE

Trans. on Microw. Theory Tech., vol. 50, pp.1544-1555, June.2002.

170
[64] P. H. Woerlee, M. J. Knittel, R. van Langevelde, D. B. M. Klaassen, and L. F.

Tiemeijer, “RF-CMOS performance trends,” IEEE Trans. Electron Devices, vol. 48,

no. 8, pp. 1776–1782, Aug. 2001.

[65] R. M. Weng, J. C. Wang, S. Y. Li, and H. C. Wei, “A Low Power Folded Mixer

Using Even Harmonic Technology,” IEEE International Workshop on Radio-

Frequency Integration Technology, pp. 247–249, Dec. 2007.

[66] T.-H. Wu, S.-C. Tseng, C.-C. Meng, and G.-W. Huang, “GalnP/GaAs HBT sub-

harmonic Gilbert mixers using stacked-LO and levelled-LO topologies,” IEEE

Trans. on Microw. Theory Tech., vol. 55, no. 5, pp. 880–889, May 2007.

[67] K. Nimmagadda and G. Rebeiz, “A 1.9 GHz double-balanced subharmo-nic mixer

for direct conversion receivers,” IEEE Radio Frequency Integrated Circuits (RFIC)

Symposium Digest, pp. 253–256, May 2001.

[68] J. Kim and J. Choi, “Design of a resistive cascode FET direct-conversion mixer

with zero bias-current,” Microwave and Optical Tech. Letters vol. 42, pp.516–518,

2004.

[69] J. Kim and J. Choi, “Design of a subharmonic cascode FET mixer for IMT-2000,”

Microwave and Optical Tech. Letters vol. 39, pp.515–518, 2003.

[70] Barquinero, C., Suarez, A., Herrera, A., Garcia, J.L., Indra Espacio, “Complete

Stability Analysis of Multifunction MMIC Circuits,” IEEE Trans. on Microw.

Theory Tech., vol. 55, pp. 2024-2033, Oct. 2007.

171
[71] F. Giannini and G. Leuzzi, Nonlinear Microwave Circuit Design. New York: Wiley,

2004.

[72] A. Suarez, V. Iglesias, J. M. Collantes, J. Jugo, and J. L. Garcia, “Nonlinear

stability analysis of microwave circuits using commercial software,” Electron. Lett.,

vol. 34, no. 13, pp.1333 -1334, June 1998.

[73] A. Anakabe , J. M. Collantes , J. Portilla , S. Mons and A. Mallet, “Detecting and

avoiding odd-mode parametric oscillations in microwave power amplifiers, ” Int.

J .RF Microw. Compupter-Aided Eng., vol. 15, pp.469-478, 2005.

[74] M. Arasu, Y. Zheng, and W. G. Yeoh, “A 3 to 9-GHz Dual-band Up-Converter for

a DS-UWB Transmitter in 0.18-µm CMOS,” IEEE Radio Frequency Integrated

Circuits (RFIC) Symposium, pp. 497-500, June 2007.

[75] M. D. Tsai and H. Wang, “A 0.3-25-GHz ultra-wideband mixer using commercial

0.18-µm CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 14, no.

11, pp. 522–524, Nov. 2004.

[76] C.-S. Lin, P.-S.Wu, H.-Y. Chang, and H.Wang, “A 9-50 GHz Gilbert-cell down-

conversion mixer in 0.13-µm CMOS technology,” IEEE Microw. Wireless Compon.

Lett., vol. 16, no. 5, pp. 293–295, May 2006.

[77] A. Verma, K. K. O, and J. Lin, “A low-power up-conversion CMOS mixer for 22–

29-GHz ultra-wideband applications,” IEEE Trans. on Microw. Theory Tech., vol.

54, no. 8, pp. 3295–3300, Aug. 2006.

172
[78] P.Y. Chiang, C.W. Su, S.Y. Luo, R.Hu, and C. F. Jou, “Wide-IF-Band CMOS

mixer design,” IEEE Trans. on Microw. Theory Tech., vol. 58, no. 4, pp. 831–840,

Apr. 2010.

[79] D.-H. Kim, S.-J. Kim and J.-S. Rieh, “A 60 GHz Wideband Quadrature-Balanced

Mixer Based on 0.13 µm RFCMOS Technology,” IEEE Microw. Wireless Compon.

Lett., vol. 21, no. 4, pp. 215–217, April 2011.

[80] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B. Nauta,

“Wideband balun-LNA with simultaneous output balancing, noise-canceling and

distortion-canceling,” IEEE J. Solid-State Circuits, vol. 43, pp. 1341–1350, June

2008.

[81] W. Zhuo, X. Li, S. H. K. Embabi, J. P. de Gyvez, D. J. Allstot, and E. Sanchez-

Sinencio, “A capacitor cross-coupled common-gate low noise amplifier,” IEEE

Trans. Circuits Syst. II, vol. 52, pp. 875–879, Dec. 2005.

[82] L. A. MacEachern and T. Manku, “A charge-injection method for Gilbert cell

biasing,” in IEEE Can. Elect. Comput. Eng. Conf., 1998, pp. 365–368.

[83] P.-Z. Rao, T.-Y. Chang, C.-P. Liang, and S.-J. Chung, “An ultra-wideband high-

linearity CMOS mixer with new wideband active baluns,” IEEE Trans. on

Microwave Theory Tech., vol. 57, no. 9, pp. 2184–2192, September 2009.

173
[84] D. Im, I. Nam, and K. Lee, “A CMOS active feedback balun-LNA with high IIP2

for wideband digital TV receivers,” IEEE Trans. on Microw. Theory Tech., vol. 99,

pp. 3566–3579, Dec. 2010.

[85] W. Liu, Z. Zhang, Z. Feng, and M. F. Iskander, “A compact wideband microstrip

crossover,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 5, pp. 254–256,

May 2012.

[86] F. Lin, Q-X, Chu, S. W. Wong, “Dual-band planar crossover with two-section

branch-line structure,” IEEE Trans. on Microw. Theory Tech., vol. 61, no. 6, pp.

2309–2316, June 2013.

[87] A. M. Abbosh, “Wideband planar crossover using two-port and four-port microstrip

to slotline transitions,”IEEE Microw. Wireless Compon. Lett., vol. 22, no. 9, pp.

465–467, Sep. 2012.

[88] J.-B. Seo, J.-H. kim, H. Sun, and T.-Y. Yun, “A low-power and high-gain mixer for

UWB systems,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 12, pp. 803–

805, Dec. 2008.

[89] A. Q. Safarian, A. Yazdi, and P. Heydari, “Design and analysis of an ultra

wideband distributed CMOS mixer,” IEEE Trans. Very Large Scale Integr. (VLSI)

Syst., vol. 13, no. 5, pp. 618–629, May 2005.

174
[90] P.-Z. Rao, T.-Y. Chang, C.-P. Liang, and S.-J. Chung, “A wideband CMOS mixer

with feedforward compensated differential transconductor,” in IEEE Int. Circuits

Syst. Symp., May 2007.

[91] K. J. Koh and G. M. Rebeiz, “0.13-µm CMOS phase shifters for X-, Ku-, and K-

band phased arrays,” IEEE J. Solid-State Circuits, vol.42, no. 11, pp. 2535–2546,

Nov. 2007.

[92] C. Wang , H. Wu and C. Tzuang, “CMOS passive phase shifter with group-delay

deviation of 6.3 ps at K-band,” IEEE Trans. on Microw. Theory Tech., vol. 59, no.

7, pp. 1778–1786, July 2011.

[93] A. Asoodeh and M.Atarodi, “A full 360ºvector-sum phase shifter with very low

RMS phase error over a wide bandwidth,” IEEE Trans. on Microw. Theory Tech.,

vol. 60, no. 6, pp. 1626–1634, Jun. 2012.

[94] Y. Zheng and C. E. Saavedra, “Full 360ºvector- sum phase shifter for microwave

system applications,” IEEE Trans. Circuits Systems I—Reg. Papers, vol. 57, no. 4,

pp. 1–7, Apr. 2009.

[95] F. Ellinger, R. Vogt, and W. Bächtold, “Calibratable adaptive antenna combiner at

5.2 GHz with high yield for laptop interface card,” IEEE Trans. on Microw. Theory

Tech. (Special Issue), vol. 48, no. 12, pp. 2714–2720, Dec. 2000.

[96] K. J. Kohl and G. M. Rebeiz, “A 6–18 GHz 5-bit active phase shifter,” IEEE MTT-

S Intl. Microwave Symp. Digest, pp. 792–795, 2010.

175
[97] H. Nosaka, M. Nagatani, K. Sano, T. Ito, S. Tsunashima, and K. Murata, “Voltage-

controlled phase shifter in a surface mount package for 40- and 100-Gb/s optical

transceivers,” in IEEE Compound Semiconductor Integrated Circuit Symposium

(CSICS), pp. 1-4, Oct. 2010.

[98] F. Ellinger, U. Jorges, U. Mayer and R. Eickhoff, “Analysis and compensation of

phase variations versus gain in amplifiers verified by SiGe HBT cascode RFIC,”

IEEE Trans. Microw. on Theory Tech., vol. 57, no. 8, pp. 1885–1894, Aug. 2009.

[99] Charles C.T. and Allstot D.J., “A calibrated phase and amplitude control system for

a 1.9 GHz phased-array transmitter element,” IEEE Trans. Circuits Syst. I: Regular

Papers, vol. 56, no. 12, pp. 2728–2737, Dec. 2009.

[100] U. Mayer, F. Ellinger and R. Eickhoff, “Analysis and Reduction of Phase

Variations of Variable Gain Amplifiers verified by CMOS Implementation at C-

Band,” IET J. Circuits, Devices Syst., vol. 4, no. 5, pp. 433–439, May 2010.

[101] Behzad Razavi, Design of integrated circuits for optical communications, McGraw-

Hill, 2003.

[102] C. F. Campbell and S. A. Brown "A compact 5-bit phase-shifter MMIC for K-band

satellite communication systems", IEEE Trans. Microw. on Theory Tech., vol. 48,

no. 12, pp.2652 -2656 2000.

176
[103] G. Sapone and G. Palmisano, “A 3–10-GHz low-power CMOS low-noise amplifier

for ultra-wideband communication,” IEEE Trans. on Microw. Theory Tech., vol. 59,

pp. 678–686, 2011.

[104] J. Kim, S. Hoyos, and J. Silva-Martinez, “Wideband Common-Gate CMOS LNA

Employing Dual Negative Feedback With Simultaneous Noise, Gain, and

Bandwidth Optimization,” IEEE Trans. on Microw. Theory Tech., vol. 58, no. 9, pp.

2340-2351, Sep. 2010.

[105] C.-F. Liao and S. I. Liu, “A broadband noise-canceling MOS LNA for 3.1–10.6-

GHz UWB receiver,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 329–339, Feb.

2007.

[106] H. Wang, L. Zhang, and Z. Yu, “A wideband inductorless LNA with local feedback

and noise cancelling for low-power low-voltage applications,” IEEE Trans.

Circuits Systems I—Reg. Papers, vol. 57, no. 8, Aug. 2010.

[107] Z. Hu and K. Mouthaan, "A 2-6.5 GHz CMOS variable gain amplifier for vector-

sum phase shifters," in IEEE Asia Pacific Microwave Conf., Dec. 2012.

[108] Rudy van de plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog

Converters, Kluwer academic publishers, 2003.

177