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ZYNQ MPSoC Development Platform FPGA Tutorial

2021.1.7 08:33:18
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ZYNQ MPSoC Development Platform FPGA Tutorial

Copyright Notice

Copyright © 2012-2020 Xinyi Electronic Technology (Shanghai) Co., Ltd.

Company
website: Http://www.alinx.com.cn

Technical
Forum: http://www.heijin.org

Official flagship
store: http://alinx.jd.com

Email:
avic@alinx.com.cn

Telephone:

021-67676997

fax:
021-37737073

ALINX WeChat Official Account:

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Document Revision History:

Version time description

1.01
2020/6/16 Initial version
1.02
2020/10/9 Modify the chip model of AXU3EG/AXU5EV
1.03
2021/1/5 Modify RAM simulation diagram, modify 7-inch screen instructions

We promise that this tutorial is not a one-time, fixed document. We will take feedback from the forum and

And the actual development practice experience accumulates to continuously revise and optimize the tutorials.

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sequence

First of all, thank you for purchasing the ZYNQ development board AXU3EG produced by Xinyi Electronic Technology (Shanghai) Co., Ltd.

AXU4EV, AXU5EV! Your support and trust in us and our products give us the confidence and courage to move forward.

gas.

Someone asked if it is possible to learn ZYNQ without any basic knowledge? It depends on where the zero is. If you can't even understand the schematic diagram, how can you learn C language?

I don't know what an array is, and I have no idea about pointers. This is a negative foundation. Learning ZYNQ requires basic hardware.

Knowledge, proficiency in C language.

This tutorial is about the FPGA part. Through continuous practice, you can master the basic process of FPGA development.

It’s a very simple truth, but practice makes perfect. Practice more and you will gradually master the secrets.

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Table of contents

Copyright Statement..................................................................................................................2
Preface..........................................................................................................................................4
Contents..................................................................................................................................5
Chapter 1 Introduction to Ultrascale+ MPSoC..................................................................................11
PS and PL Interconnection Technology...........................................................................11
Introduction to ZYNQ Chip Development Process............................................................17
What skills are required to learn ZYNQ...................................................................18 1.3.1
Software Developers...............................................................................................18
1.3.2 Logic Developers...............................................................................................18
Chapter 2 Introduction to Development Board Hardware...................................................................19
ACU3EG Core Board.................................................................................................22
2.1.1 Introduction.........................................................................................................22
2.1.2 ZYNQ Chip.........................................................................................................22
2.1.3 DDR4 DRAM......................................................................................................................24
2.1.4 QSPI Flash......................................................................................................................29
2.1.5 eMMC Flash............................................................................................................................30

2.1.6 Clock Configuration..................................................................................31 2.1.7

LED Light..................................................................................................................32
2.1.8 Power Supply..................................................................................................33
2.1.9 Block Diagram..................................................................................................35
2.1.10 Connector Pin Definition..................................................................................35
Expansion Board...................................................................................................41 2.2.1
Introduction...............................................................................................................41
2.2.2 M.2 Interface...................................................................................................42
2.2.3 DP Display Interface..................................................................................................42
2.2.4 USB3.0 Interface..................................................................................................43
2.2.5 Gigabit Ethernet Interface..................................................................................45
2.2.6 USB Uart Interface..................................................................................................46
2.2.7 SD 2.2.8 40-pin expansion port..........................................................................................48
2.2.9 CAN communication interface.....................................................................49 2.2.10
485 communication interface..................................................................................50
2.2.11 MIPI interface..................................................................................................51
2.2.12 JTAG debug port..................................................................................................52
2.2.13 RTC real-time clock..................................................................................................52
2.2.14 EEPROM and temperature sensor........................................................................53

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2.2.15 LED Light..................................................................................................................53

2.2.16 Buttons..................................................................................................................54
2.2.17 DIP Switch Configuration..................................................................................55
2.2.18 Power Supply..................................................................................................................56
2.2.19 Fan..................................................................................................................................57
2.2.20 Structure Dimensions.................................................................................................58
Chapter 3 Introduction to Verilog Basic Modules...................................................................................59
Introduction................................................................................................................................59
Data Types........................................................................................................................59
3.2.1 Constants..................................................................................................................................59
Variables..................................................................................................................................60
1.1.1 Wire Type..................................................................................................................................60
1.1.2 Reg Type..................................................................................................................................60
1.1.3 Memory 3.4.1 Arithmetic Operators 61 3.4.2 Assignment Operators 61 3.4.3
Relational Operators 63 3.4.4 Logical Operators 63 3.4.5 Conditional Operators 63
3.4.6 Bitwise Operators 63 3.4.7 Shift Operators 63 3.4.8 Concatenation Operators
63 3.4.9 Precedence Levels 63 Combinational Logic 64 3.5.1 AND Gates 64 3.5.2
3.5.3 OR Gate ..................................................................................................65
3.5.4 XOR Gate ...............................................................................................................66
3.5.5 Comparator ...............................................................................................................67
3.5.6 Half Adder ................................................................................................................68
3.5.7 Full Adder ................................................................................................................69
3.5.8 Multiplier ................................................................................................................70
3.5.9 Data Selector ................................................................................................................70
3.5.10 3-8 Decoder ................................................................................................................72
3.5.11 Tri-State Gate ......................................................................................................73
Sequential Logic ................................................................................................................74
3.6.1 D Flip-Flop ................................................................................................................75

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3.6.2 Two-stage D flip-flop..................................................................................75 3.6.3 D flip-

flop with asynchronous reset........................................................76 3.6.4 D flip-flop with
asynchronous reset and synchronous clear........78 3.6.5 Shift
register....................................................................................................79 3.6.6 Single-port
RAM.................................................................................................80 3.6.7 Pseudo-dual-port
RAM.................................................................................80 3.6.8 True dual-port

RAM.................................................................................81 3.6.9 Single-port

ROM.................................................................................................83 3.6.10 Finite state
machine..................................................................................................84
Summary................................................................................................................88 Chapter
4 PL's "Hello World" LED Experiment...........................................................................89 LED Hardware
Introduction.................................................................................................89 Creating Vivado
Project..................................................................................................90 Create Verilog HDL

File to Light Up LED ..............................................................96 Add Pin

Constraints.........................................................................................................101 Add
Timing Constraints..........................................................................................104 Generate
BIT Files....................................................................................................107 Vivado

Simulation....................................................................................................109
Download...................................................................................................114 Online
Debugging................................................................................................117 4.9.1 Add ILA IP
Core..................................................................................................117
4.9.2 MARK DEBUG......................................................................................................121
Experimental Summary..................................................................................................124
Chapter 5 PLL Experiment in Vivado..........................................................................................125
Experimental Principles.........................................................................................................125
Create a Vivado Project..................................................................................................126
Simulation..................................................................................................................131 On-
Board Verification..................................................................................................132 Chapter
6 FPGA On-Chip RAM Read and Write Test Experiment.................................133 Experimental
Principles..................................................................................................133 Create a Vivado
Project..................................................................................................133 RAM Port Definition

and Timing..................................................................................136 Test Program

Writing..................................................................................................137
Simulation..................................................................................................................139 On-
Board Verification..................................................................................................140 Chapter
7 FPGA On-Chip ROM Test Experiment..................................................................141 Experimental
Principles..................................................................................................141
Programming..................................................................................................................141
7.2.1 Creating ROM Initialization Files...........................................................................141

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7.2.2 Add ROM IP Core..................................................................................142 ROM

Test Program Writing..........................................................................................145
Simulation........................................................................................................................146
On-board Verification..................................................................................................146
Chapter 8 FPGA On-chip FIFO Read and Write Test Experiment.................................148
Experimental Principles.................................................................................................148
Create Vivado Project...................................................................................149 8.2.1
Add FIFO IP Core.................................................................................................149
8.2.2 FIFO Port Definition and Timing..................................................................151
FIFO Test Program Writing..................................................................................153
Simulation..................................................................................................................158
On-board Verification..................................................................................................159
Chapter 9 Vivado Key Press Experiment.................................................................................161
11.1.1 Asynchronous Serial Communication Protocol.........................................111
11.1.2 Baud Rate..................................................................................................111
11.1.3 Receiving Module Design..................................................................................111
11.1.4 Sending Module Design..................................................................................112
Chapter 11 UART Experiment..................................................................................................113
Program Design.........................................................................................................113
11.1.1 Asynchronous Serial Communication Protocol..................................................113
11.1.2 Baud Rate..................................................................................................................113
11.1.3 Receiving Module Design..................................................................................113 11.1.4
Sending Module Design..................................................................................114 11.1.5
Baud Rate Generation..................................................................................173 11.1.6
Test Program......................................................................................................173
Simulation........................................................................................................................175
Experimental Test..................................................................................................................176
Chapter 12 RS485 Experiment.................................................................................................179
Experimental Principle.................................................................................................179
Program Design.......................................................................................................180
Experimental Test.......................................................................................................181
Chapter 13 PL-side DDR4 Read and Write Test Experiment.................................................183
Hardware Introduction..................................................................................................183
Vivado Project Creation.................................................................................................183

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13.2.1 Create a PL-side DDR4 test project and configure DDR4 IP..........183 13.2.2
Add other test codes..................................................................................185
Download and debug..................................................................................................186
Experimental summary..................................................................................................186
Chapter 14 HDMI output experiment..................................................................................187
Hardware introduction..................................................................................................187
Program design..................................................................................................188
Add XDC constraint file..................................................................................190
Download and debug..................................................................................................191
Experimental summary..................................................................................................192
Chapter 15 HDMI character display experiment..................................................................193
Experimental principle..................................................................................................193
Program design..................................................................................................193
Experimental phenomenon........................................................................................199
Chapter 16 7 17.1.1 AD7606 Timing Sequence..................................................................204
17.1.2 AD7606 Timing Sequence..................................................................204

17.1.2 AD7606 Configuration...................................................................................205

17.1.3 AD7606 AD conversion..................................................................206 Program
design..................................................................................................206 Experimental
phenomenon..................................................................................212 Chapter 18
AD9238 dual-channel waveform display experiment..................................213 Hardware
introduction..................................................................................213 18.1.1 Two-
channel AD module description........................................................213 18.1.2 Module
function description..................................................................214 Program
design..................................................................................................216 Experimental
phenomenon..................................................................................220 Chapter 19
ADDA test experiment..................................................................................222 Hardware
introduction..................................................................................222 19.1.1 Digital-to-
analog conversion (DA) circuit..................................................223 19.1.2 Analog-to-
digital conversion (AD) circuit...................................................224 Program
design.........................................................................................................225
Experimental phenomena..................................................................................................230
Chapter 20 AD9767 dual-channel sine wave generation experiment..................................233

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Hardware Introduction..................................................................................................233
20.1.1 Parameter Description of AN9767 Module..................................................................234
20.1.2 Principle Block Diagram of AN9767 Module..................................................................234
20.1.3 Introduction to AD9767 Chip..................................................................................235
20.1.4 Current-to-Voltage Conversion and Amplification................................................236
20.1.5 Current-to-Voltage Conversion and Amplification................................................237
Program Design..................................................................................................237 20.2.1
Generate ROM Initialization File..................................................................238 20.2.2 Dual
Channel Sine Wave Generator Program..................................................240 Experimental
Phenomenon..................................................................................................241

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Chapter 1 Ultrascale+ MPSoC Introduction

The Zynq UltraScale+ MPSoC series is Xilinx's second-generation Zynq platform. Its highlight is that the FPGA contains a complete

The ARM processing subsystem (PS) includes a quad-core Cortex-A53 processor or a dual-core Cortex-A53 plus a dual-core Cortex-R5 processor.

The entire processor is built around the processor, and the processor subsystem integrates a memory controller and a large number of peripherals,

making the processor core completely independent of the programmable logic unit in Zynq. In other words, if the programmable logic unit (PL) is not

used for the time being, the ARM processor subsystem can also work independently. This is fundamentally different from the previous FPGA, which

is processor-centric.

Zynq consists of two functional blocks, the PS part and the PL part. To put it simply, it is the ARM SOC part and the FPGA part. Among

them, the PS integrates the APU ARM Cortex™-A53 processor, the RPU Cortex-R5 processor, the AMBA® interconnect, the internal memory

(OCM), the external memory interface (DDR Controller) and the peripherals (IOU). These peripherals (IOU) mainly include USB bus interface,

Ethernet interface, SD/eMMC interface, I2C bus interface, CAN bus interface, UART interface, GPIO, etc. High-speed interfaces such as PCIe, SATA,

Display Port.

Overall block diagram of the ZYNQ MPSoC chip

PS: Processing System, PL: Programmable Logic, which It is the part of ARM's SoC that has nothing to do with FPGA.

is the FPGA part.

PS and PL interconnect technology

ZYNQ is a product that closely combines high-performance ARM Cortex-A53 series processors with high-performance FPGAs in a single chip.

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In order to achieve high-speed communication and data exchange between ARM processor and FPGA, the ARM processor and FPGA are used to play their

To achieve performance advantages, it is necessary to design efficient interconnection paths between the on-chip high-performance processor and the FPGA.

The PL and PS data interaction path is the top priority of ZYNQ chip design and one of the keys to the success or failure of product design.

In this section, we will mainly introduce the connection between PS and PL, so that users can understand the connection technology between PS and PL.

In fact, in the specific design, we often do not need to do too much work on the connection. After we add the IP core,

The system will automatically use the AXI interface to connect our IP core to the processor. We only need to do a little bit of supplementation.

AXI stands for Advanced eXtensible Interface, an interface protocol introduced by Xilinx starting with the 6 series FPGA.

It mainly describes the data transmission method between the master device and the slave device. It is still used in ZYNQ, and the version is AXI4.

We often see AXI4.0, and Zynq internal devices all have AXI interfaces. In fact, AXI is proposed by ARM.

AMBA (Advanced Microcontroller Bus Architecture) is a high-performance, high-bandwidth, low-latency

AXI3 is a new on-chip bus that replaces the previous AHB and APB buses.

The second version of AXI, AXI4, was included in AMBA 4.0, which was released in 2010.

The AXI protocol mainly describes the data transmission method between the master device and the slave device. The master device and the slave device communicate through handshake.

The slave device sends a READY signal when it is ready to receive data.

The VALID signal is sent and maintained to indicate that the data is valid. Data is valid only when both the VALID and READY signals are valid.

When these two signals remain valid, the master device will continue to transmit the next data. The master device can cancel

The VALID signal is sent from the slave device, or the slave device cancels the READY signal to terminate the transmission. The AXI protocol is shown in the figure. At T2, the READY signal of the slave device

The signal is valid. At T3, the VILID signal of the master device is valid and data transmission begins.

AXI handshake timing diagram

In Zynq, AXI-Lite, AXI4 and AXI-Stream are supported. From Table 5-1, we can see that these three

Characteristics of the AXI interface.

Interface Protocol characteristic Applications

AXI4-Lite
Address/single data Low-speed peripherals or controls

AXI4
transfer Address/burst data Bulk transfer of addresses

AXI4-Stream
transfer only data transfer, burst data transfer data stream and media stream transfer

AXI4-Lite:

It is lightweight and simple in structure, suitable for small batches of data and simple control situations. It does not support batch transmission, reading and writing

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Only one word (32 bits) can be read and written at a time. It is mainly used to access some low-speed peripherals and control peripherals.

AXI4:

The interface is similar to AXI-Lite, but with the addition of a batch transfer function, which can continuously transfer a piece of address

One-shot read and write. In other words, it has the burst function of data reading and writing.

Both of the above two methods use memory mapping control, that is, ARM programs the user-defined IP into a certain address for access, and reads

When writing, it is just like reading and writing your own on-chip RAM, programming is also very convenient, and the development difficulty is relatively low. The cost is that too many

resources are occupied, and additional signal lines such as read address lines, write address lines, read data lines, write data lines, and write response lines are required.

AXI4-Stream:

This is a continuous stream interface that does not require address lines (much like FIFO, just keep reading or writing). For this type of IP, ARM

cannot control it through the above memory mapping method (FIFO has no concept of address at all), and there must be a conversion device, such as the

AXI-DMA module, to achieve the conversion from memory mapping to streaming interface. AXI-Stream is applicable to many occasions: video stream

processing; communication protocol conversion; digital signal processing; wireless communication, etc. Its essence is a data path built for numerical

streams, building a continuous data stream from the source (such as ARM memory, DMA, wireless receiving front end, etc.) to the sink (such as HDMI display,

high-speed AD audio output, etc.). This interface is suitable for real-time signal processing.

The AXI4 and AXI4-Lite interfaces consist of five

different channels: ÿ Read
Address Channel ÿ Write
Address Channel ÿ Read
Data Channel ÿ Write Data
Channel ÿ Write Response Channel

Each channel is an independent AXI handshake protocol. The following two figures show the read and write models respectively:

AXI Read Data Channel

AXI write data channel

The AXI bus protocol is implemented in hardware inside the ZYNQ chip, including 12 physical interfaces, namely

S_AXI_HP{0:3}_FPD, S_AXI_LPD, S_AXI_ACE_FPD, S_AXI_ACP_FPD,

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S_AXI_HPC{0,1}_FPD, M_AXI_HPM{0,1}_FPD, M_AXI_HPM0_LPD interfaces.

S_AXI_HP{0:3}_FPD interface is a high-performance/bandwidth AXI4 standard interface. There are four of them in total. The PL module is used as

Connected to the main device. Mainly used for PL to access the memory on the PS (DDR and FPD Main Switch)

S_AXI_LPD interface, high-performance port, connects PL to LPD. Low latency access to OCM and TCM, access to PS side

DDR.

S_AXI_HPC{0,1}_FPD interface, connects PL to FPD, can be connected to CCI, access L1 and L2 Cache, by

Because accessing the DDR controller through CCI will have a larger delay.

M_AXI_HPM{0,1}_FPD interface, high-performance bus, PS is the master, connecting FPD to PL, can be used for CPU, DMA, PCIe, etc. to

push large amounts of data from PS to PL.

M_AXI_HPM0_LPD interface, low latency interface bus, PS is the master, connects LPD to PL, can directly access

Ask about the BRAM, DDR, etc. on the PL side, and are also often used to configure the registers on the PL side.

Only M_AXI_HPM{0,1}_FPD and M_AXI_HPM0_LPD are Master Ports, i.e. host interfaces, and the rest are Slave Ports. The host interface has the

authority to initiate reads and writes. ARM can use the two host interfaces to actively access the PL logic, which is actually mapping the PL to a certain

address. Reading and writing PL registers is like reading and writing its own memory. The rest of the slave interfaces are passive interfaces, accepting

reads and writes from the PL. In PS and PL interconnection applications, the most commonly used interfaces are S_AXI_HP{0:3}_FPD, M_AXI_HPM{0,1}

_FPD, and M_AXI_HPM0_LPD.

The ARM on the PS side directly supports the AXI interface with hardware, while the PL needs to use logic to implement the corresponding AXI protocol.

Xilinx provides ready-made IPs in the Vivado development environment, such as AXI-DMA, AXI-GPIO, AXI-Dataover, and AXI-Stream, which all

implement corresponding interfaces. When using them, you can directly add them from the Vivado IP list to implement the corresponding functions. The

following figure shows various DMA IPs under Vivado:

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The following is an introduction to the functions of several commonly used AXI interface IPs:

AXI-DMA: realizes the conversion from PS memory to PL high-speed transmission high-speed channel AXI-HP<---->AXI-Stream

AXI-FIFO-MM2S: Implements the conversion from PS memory to PL general transmission channel AXI-HPM<----->AXI-Stream

AXI-Datamover: AXI-HP<---->AXI-Stream conversion from PS memory to PL high-speed transmission channel.

However, this time it is completely controlled by PL, and PS is completely passive.

AXI-VDMA: realizes the conversion from PS memory to PL high-speed transmission high-speed channel AXI-HP<---->AXI-Stream, but does not

However, it is specifically designed for two-dimensional data such as videos and images.

AXI-CDMA: This is done by the PL to move data from one location in memory to another without the CPU intervening. We will give examples of how to

use

these IPs in the following chapters. Sometimes, users need to develop their own

IP communicates with PS, and the corresponding IP can be generated by the wizard. User-defined IP cores can have AXI4-Lite, AXI4, AXI-Stream, PLB

and FSL interfaces. The latter two are not used because they are not supported by ARM.

With the above official IPs and custom IPs generated by the wizard, users do not need to know too much about AXI timing (unless they really encounter

problems), because Xilinx has encapsulated all the details related to AXI timing, and users only need to focus on their own logic implementation.

Strictly speaking, the AXI protocol is a point-to-point master-slave interface protocol. When multiple peripherals need to exchange data with each other,

we need to add an AXI Interconnect module, which is the AXI interconnect matrix. Its function is to provide a switching mechanism that connects one or more

AXI master devices to one or more AXI slave devices (somewhat similar to the switching matrix in a switch).

This AXI Interconnect IP core can support up to 16 master devices and 16 slave devices. If more interfaces are needed, you can add more IP cores.

The basic AXI Interconnect connection modes are

as follows: ÿ N-to-1
Interconnect ÿ to-N
Interconnect ÿ N-to-M Interconnect (Crossbar
Mode) ÿ N-to-M Interconnect (Shared Access Mode)

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Many-to-one situation

One-to-many situation

Many-to-many read and write address channels

Many-to-many read and write data channels

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The AXI interface devices inside ZYNQ are interconnected through an interconnection matrix, which ensures the transmission of data.

In Vivado, Xilinx provides the IP core axi_interconnect to realize this interconnection matrix, which can be called by calling.

AXI Interconnect IP

Introduction to Zynq Chip Development Process

Since Zynq integrates CPU and FPGA, developers need to design ARM operating system applications.

In addition to developing the device drivers, the hardware logic design of the FPGA part needs to be designed. In the development process, it is necessary to understand

the Linux operating system and the system architecture, and to build a hardware design platform between the FPGA and ARM systems. Therefore, the development of ZYNQ

requires the collaborative design and development of software personnel and hardware personnel. This is the so-called "software and hardware collaborative design" in ZYNQ

development.

The design and development of the ZYNQ system's hardware and software systems require the following development environments and debugging tools:

Xilinx Vivado.

The Vivado design suite implements the design and development of the FPGA part, pin and timing constraints, compilation and

simulation, and the design process from RTL to bitstream. Vivado is not a simple upgrade of the ISE design suite, but a brand new design

suite. It replaces all the important tools of the ISE design suite, such as Project Navigator, Xilinx Synthesis

Technology, Implementation, CORE Generator, Constraint, Simulator, Chipscope Analyzer,

Design tools such as FPGA Editor.

Xilinx SDK (Software Development Kit), SDK is Xilinx software development kit (SDK), in Vivado hardware system

Based on the system, the system automatically configures some important parameters, including tool and library paths, compiler options, JTAG and

flash settings, debugger connections, and bare metal board support packages (BSP). The SDK also provides drivers for all supported Xilinx IP hard

cores. The SDK supports co-debugging of IP hard cores (on FPGA) and processor software. We can use high-level C or C++ languages to develop

and debug ARM and FPGA systems and test whether the hardware system is working properly. The SDK software is also an automatic Vivado software.

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No need to install separately.

The development of ZYNQ is also a hardware-first, software-later approach. The specific

process is as follows: 1) Create a new project on Vivado and add an embedded source

file. 2) Add and configure some basic peripherals of PS and PL in Vivado, or add custom peripherals if necessary. 3) Generate the

top-level HDL file in Vivado and add constraint files. Then compile and generate a bitstream file (*.bit). 4) Export the hardware information

to the SDK software development environment, where you can write some debugging software to verify the hardware.

and software, combined with the bitstream file to debug the ZYNQ system alone.

5) Generate FSBL file in SDK. 6) Generate u-

boot.elf and bootloader image in VMware virtual machine. 7) Generate a BOOT.bin in SDK

through FSBL file, bitstream file system.bit and u-boot.elf file

document.

8) Generate Ubuntu kernel image file Zimage and Ubuntu root file system in VMware.

It is necessary to write a driver for the customized FPGA IP.

9) Put the BOOT, kernel, device tree, and root file system files into the SD card, power on the development board, and Linux

The operating system will boot from the SD card.

The above is a typical ZYNQ development process, but ZYNQ can also be used as an ARM alone, so there is no need to close

ZYNQ can also use only the PL part, but the PL configuration still needs to be completed by PS, which means that it is impossible to solidify the

firmware of only PL through the traditional solidification Flash method.

What skills are required to learn ZYNQ?

Learning ZYNQ requires higher standards than learning traditional development tools such as FPGA, MCU, ARM, etc., and learning ZYNQ well is not something that

can be achieved overnight.

1.3.1 Software Developers

ÿ Principles of computer

organization ÿ C, C++

language ÿ Computer operating

system ÿ Tcl script

ÿ Good English reading foundation

1.3.2 Logic Developer

ÿ Principles of Computer Organization

ÿ C Language ÿ

Fundamentals of Digital Circuits

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Chapter 2 Development Board Hardware Introduction

The 2020 version of the development board (model: AXU3EG) based on the XILINX Zynq UltraScale+ MPSoCs development platform has been officially

released by Xinyi Electronic Technology (Shanghai) Co., Ltd. In order to let you quickly understand this development platform, we have compiled this user manual.

This MPSoCs

development platform adopts the mode of core board plus expansion board, which is convenient for users to secondary develop and utilize the core board.

The core board uses the XILINX Zynq UltraScale+ EG chip ZU3EG solution, which uses Processing System (PS) + Programmable Logic

(PL) technology to integrate dual-core ARM Cortex-A53 and FPGA programmable logic on a single chip. In addition, the PS side of the core board has 4

high-speed DDR4 SDRAM chips with a total of 4GB, 1 8GB eMMC storage chip and 1 256Mb QSPI FLASH chip; the PL side of the core board has a 1GB

DDR4 SDRAM chip. In the baseboard design, we have expanded a wealth of peripheral interfaces for users, such as 1 FMC LPC interface, 1 SATA M.2

interface, 1 DP interface, 1 USB3.0 interface, 1 Gigabit Ethernet interface, 1 UART serial port interface, 1 SD card interface, 2 40-pin expansion interfaces, 2

CAN bus interfaces, 2 RS485 interfaces, etc. It is a "professional-level" ZYNQ development platform that meets users' requirements for high-speed data

exchange, data storage, video transmission processing, deep learning, artificial intelligence, and industrial control. It provides the possibility for high-speed data

transmission and exchange, early verification of data processing, and later application.

I believe that such a product is very suitable for students, engineers and other groups engaged in MPSoCs development.

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Here, a brief functional introduction to this AXU3EG MPSoCs development platform is given.

The entire structure of the development board inherits our usual core board + expansion board model.

High-speed board-to-board connectors are used to connect them.

The core board is mainly composed of the minimum system of ZU3EG + 5 DDR4 + eMMC +1 QSPI FLASH. ZU3EG adopts

Xilinx's Zynq UltraScale+ MPSoCs EG series chip, model number is XCZU3EG-1SFVC784I. ZU3EG chip

It can be divided into the processor system (PS) and the programmable logic (PL).

Four DDR4 chips are connected to the PS and one DDR4 chip is connected to the PL of the ZU3EG chip. Each DDR4 chip has a capacity of up to 1G bytes.

The ARM system and FPGA system can independently process and store data. The 8GB eMMC FLASH storage chip on the PS side and

One 256Mb QSPI FLASH is used to statically store the MPSoCs' operating system, file system, and user data.

The baseboard expands the core board with a variety of peripheral interfaces, including 1 M.2 interface, 1 DP interface, 4

USB3.0 interface, 2 Gigabit Ethernet interfaces, 2 UART serial ports, 1 SD card interface, 2 40-pin expansion connectors

port, 2 CAN bus interfaces, 2 RS485 interfaces, 1 MIPI interface and some key LEDs.

The following figure is a schematic diagram of the structure of the entire development system:

40-pin expansion port 40-pin expansion port

USB3.0
Interface x2
USB3320
DP output Core board
QSPI eMMC
C
FLASH FLASH
GL3523
USB3.0
USB
CP2102 33.333M hz
port x2
UART
XILINX
USB
CP2102
UltraScale+ Ethernet port
UART 200Mhz KSZ9031R
MPSoC
XCZU3EG/
DDR4
SN65HVD
CANx2 XCZU4EV
232 KSZ9031R Ethernet port

DDR4 DDR4 DDR4 DDR4

RS485x2
MAX3485
M.2 Connector

TXS0261
SD Card
MIPI
JTAG LED&KEY Si5332 2RTW
Connectors

Through this schematic diagram, we can see the interfaces and functions that our development platform can contain.

ÿ ZU3EG core board

It consists of ZU3EG+4GB DDR4 (PS)+1GB DDR4 (PL)+8GB eMMC FLASH+256Mb QSPI FLASH.

There are also two crystal oscillators to provide clocks, a single-ended 33.3333MHz crystal oscillator for the PS system and a differential 200MHz crystal oscillator

Provides DDR reference clock to PL logic.

ÿ M.2 interface

1 PCIEx1 standard M.2 interface, used to connect M.2 SSD solid state drives, with a communication speed of up to 6Gbps.

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ÿ DP output interface

1 standard Display Port output interface for video image display. Supports up to 4K@30Hz or 1080P@60Hz output. ÿ USB3.0

interface

4 USB3.0 HOST ports, USB port type is TYPE A. Used to connect external USB peripherals, such as mouse

ÿ Gigabit Ethernet interface

2 10/100M/1000M Ethernet RJ45 interfaces, 1 each for PS and PL. Used to exchange Ethernet data with computers or other network

devices. ÿ USB Uart interface

2-way Uart to USB interface, 1 for PS and 1 for PL. Used to communicate with the computer, convenient for user debugging.

Silicon Labs CP2102GM USB-UAR chip, the USB interface uses a MINI USB interface.

ÿ Micro SD card holder

1 Micro SD card slot, used to store operating system images and file systems.

ÿ 40-pin expansion port

2 expansion ports with 40 pins and 2.54mm pitch, which can be connected to various modules of Heijin (binocular camera, TFT LCD screen,

High-speed AD module, etc.). The expansion port includes 1 5V power supply, 2 3.3V power supplies, 3 grounds, and 34 IO ports.

ÿ CAN communication interface

2-way CAN bus interface, using TI's SN65HVD232 chip, the interface uses a 4-pin green terminal block. ÿ 485 communication

interface

2-way 485 communication interface, using MAXIM's MAX3485 chip. The interface uses a 6-pin green terminal block. ÿ MIPI interface

2 LANE MIPI camera input interfaces, used to connect to MIPI camera module (AN5641). ÿ JTAG debug port

1 10-pin 2.54mm standard JTAG port for downloading and debugging FPGA programs. Users can use XILINX

The downloader debugs and downloads the ZU3EG system. ÿ Temperature

and humidity sensor The board has

a temperature and humidity sensor chip LM75, which is used to detect the temperature and humidity of the board's surrounding environment.

ÿ EEPROM

1 piece of IIC interface EEPROM 24LC04;

ÿ RTC Real-time clock

1 built-in RTC real-time clock; ÿ LED

light

5 LEDs, 2 on the core board and 3 on the base board. 1 power indicator and 1 DONE indicator on the core board

Configuration indicator light. There is 1 power indicator light and 2 user indicator lights on the bottom

panel. ÿ Button

3 buttons, 1 reset button, 2 user buttons.

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ACU3EG core board

2.1.1 Introduction

ACU3EG (core board model, the same below) core board, ZYNQ chip is based on XILINX's Zynq UltraScale+

XCZU3EG-1SFVC784I from the MPSoCs EG series.

This core board uses 5 Micron DDR4 chips MT40A512M16GE, of which 4 DDR4 chips are mounted on the PS side, forming a 64-

bit data bus bandwidth and 4GB capacity. One chip is mounted on the PL side, with a 16-bit data bus width and 1GB capacity. The

maximum operating speed of the DDR4 SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the maximum operating

speed of the DDR4 SDRAM on the PL side can reach 1066MHz (data rate 2132Mbps). In addition, a 256MBit QSPI FLASH and an

8GB eMMC FLASH chip are also integrated on the core board for boot storage configuration and system files. In order to connect to the

baseboard, the 4 board-to-board connectors of this core board extend the USB2.0 interface on the PS side, with Gigabit and higher speeds.

Ethernet interface, SD card interface and other remaining MIO ports; 4 pairs of PS MGT high-speed transceiver interfaces are also

expanded; and almost all IO ports on the PL side (HP I/O: 96, HD I/O: 84). The routing between the XCZU3EG chip and the interface is

equal-length and differential, and the core board size is only 80*60 (mm), which is very suitable for secondary development.

Front view of ACU3EG core board

2.1.2 Zynq Chip

The development board uses the Zynq UltraScale+ MPSoCs EG series chip from Xilinx.

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XCZU3EG-1SFVC784I. The PS system of the ZU3EG chip integrates four ARM Cortex™-A53 processors with a speed of up to 1.2Ghz and

supports 2-level cache; it also includes two Cortex-R5 processors with a speed of up to 500Mhz.

ZU3EG chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 memory chips.

The PL end has a rich set of high-speed interfaces such as PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0, Gigabit Ethernet,

SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end contains a rich set of programmable logic units, DSP and internal RAM.

The overall block diagram of the ZU3EG chip is shown in Figure 2-2-1

Figure 2-2-1 Overall block diagram of the ZYNQ ZU3EG chip

The main parameters of the PS system are as follows:

- ARM quad-core Cortex™-A53 processor, up to 1.2GHz, 32KB level 1 instruction and data cache per CPU

Memory, 1MB L2 cache shared by 2 CPUs.

- ARM dual-core Cortex-R5 processor, up to 500MHz, 32KB level 1 instruction and data cache per CPU,

and 128K tightly coupled memory.

- External storage interface, supports 32/64bit DDR4/3/3L, LPDDR4/3 interface. - Static storage

interface, supports NAND, 2xQuad-SPI FLASH. - High-speed connection

interface, supports PCIe Gen2 x4, 2xUSB3.0, Sata 3.1, DisplayPort, 4x Tri-mode Gigabit

Ethernet.

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- Common connection interfaces: 2xUSB2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO.

- Power management: Supports the division of four power supplies: Full/Low/PL/Battery.

- Encryption algorithm: Support RSA, AES and SHA.

- System monitoring: 10-bit 1Mbps AD sampling for temperature and voltage detection.

The main parameters of the PL logic part are as follows:

-Logic Cells: 154K;

- Flip-flops: 141K;

- Lookup tables LUTs: 71K;

- Block RAM: 9.4Mb;

- Clock Management Units (CMTs): 3

- Multiplier 18x25MACCs: 360

The speed grade of the XCZU3EG-1SFVC784I chip is -1, industrial grade, and the package is SFVC784.

2.1.3 DDR4 DRAM

The ACU3EG core board is equipped with five Micron 512MB DDR4 chips, model MT40A512M16GE-

083E, where the PS side mounts 4 DDR4s, forming a 64-bit data bus bandwidth and 4GB capacity. The PL side mounts 1 16-bit

The data bus width and capacity of 1GB. The maximum operating speed of DDR4 SDRAM on the PS side can reach 1200MHz (data rate

2400Mbps), 4 DDR4 memory systems are directly connected to the memory interface of BANK504 of PS.

The maximum operating speed of SDRAM can reach 1066MHz (data rate 2133Mbps), and one DDR4 is connected to the BANK64 of the FPGA.

The specific configuration of DDR4 SDRAM is shown in Table 2-3-1.

Position No. Chip Model capacity factory

U12,U14,U15,U16 MT40A512M16GE-083E 512M x 16bit Micron

Table 2-3-1 DDR4 SDRAM Configuration

The hardware design of DDR4 requires strict consideration of signal integrity. We have fully considered the signal integrity in circuit design and PCB design.

Matching resistors/terminal resistors, trace impedance control, and trace equal length control are taken into consideration to ensure high-speed and stable operation of DDR4.

The hardware connection method of DDR4 on the PS side is shown in Figure 2-3-1:

U1

U12,U14,U15,U16

Data 64 bits
QUR
Ultra BANK
504 DDR4
Scale+ Clock address line, control line
(MT40A512M1
6GE-083E)

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Figure 2-3-1 PS-side DDR4 DRAM schematic diagram

The hardware connection method of DDR4 DRAM on the PL side is shown in Figure 2-3-2:
U1

U17

Data 16 bits

QUR BANK DDR4

Ultra 64 (MT40A512M1
6GE-083E)

Scale+ Clock address line, control line

Figure 2-3-2 PL-side DDR4 DRAM schematic diagram

PS side DDR4 SDRAM pinout:

Signal name Pin Name Pin Number

PS_DDR4_DQS0_P PS_DDR_DQS_P0_504 AF21

PS_DDR4_DQS0_N PS_DDR_DQS_N0_504 AG21
PS_DDR4_DQS1_P PS_DDR_DQS_P1_504 AF23
PS_DDR4_DQS1_N PS_DDR_DQS_N1_504 AG23
PS_DDR4_DQS2_P PS_DDR_DQS_P2_504 AF25
PS_DDR4_DQS2_N PS_DDR_DQS_N2_504 AF26
PS_DDR4_DQS3_P PS_DDR_DQS_P3_504 AE27
PS_DDR4_DQS3_N PS_DDR_DQS_N3_504 AF27
PS_DDR4_DQS4_P PS_DDR_DQS_P4_504 N23
PS_DDR4_DQS4_N PS_DDR_DQS_N4_504 M23
PS_DDR4_DQS5_P PS_DDR_DQS_P5_504 L23
PS_DDR4_DQS5_N PS_DDR_DQS_N5_504 K23
PS_DDR4_DQS6_P PS_DDR_DQS_P6_504 N26
PS_DDR4_DQS6_N PS_DDR_DQS_N6_504 N27
PS_DDR4_DQS7_P PS_DDR_DQS_P7_504 J26
PS_DDR4_DQS7_N PS_DDR_DQS_N7_504 J27
PS_DDR4_DQ0 PS_DDR_DQ0_504 AD21
PS_DDR4_DQ1 PS_DDR_DQ1_504 AE20
PS_DDR4_DQ2 PS_DDR_DQ2_504 AD20
PS_DDR4_DQ3 PS_DDR_DQ3_504 AF20
PS_DDR4_DQ4 PS_DDR_DQ4_504 AH21
PS_DDR4_DQ5 PS_DDR_DQ5_504 AH20
PS_DDR4_DQ6 PS_DDR_DQ6_504 AH19
PS_DDR4_DQ7 PS_DDR_DQ7_504 AG19
PS_DDR4_DQ8 PS_DDR_DQ8_504 AF22

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PS_DDR4_DQ9 PS_DDR_DQ9_504 AH22

PS_DDR4_DQ10 PS_DDR_DQ10_504 AE22
PS_DDR4_DQ11 PS_DDR_DQ11_504 AD22
PS_DDR4_DQ12 PS_DDR_DQ12_504 AH23
PS_DDR4_DQ13 PS_DDR_DQ13_504 AH24
PS_DDR4_DQ14 PS_DDR_DQ14_504 AE24
PS_DDR4_DQ15 PS_DDR_DQ15_504 AG24
PS_DDR4_DQ16 PS_DDR_DQ16_504 AC26
PS_DDR4_DQ17 PS_DDR_DQ17_504 AD26
PS_DDR4_DQ18 PS_DDR_DQ18_504 AD25
PS_DDR4_DQ19 PS_DDR_DQ19_504 AD24
PS_DDR4_DQ20 PS_DDR_DQ20_504 AG26
PS_DDR4_DQ21 PS_DDR_DQ21_504 AH25
PS_DDR4_DQ22 PS_DDR_DQ22_504 AH26
PS_DDR4_DQ23 PS_DDR_DQ23_504 AG25
PS_DDR4_DQ24 PS_DDR_DQ24_504 AH27
PS_DDR4_DQ25 PS_DDR_DQ25_504 AH28
PS_DDR4_DQ26 PS_DDR_DQ26_504 AF28
PS_DDR4_DQ27 PS_DDR_DQ27_504 AG28
PS_DDR4_DQ28 PS_DDR_DQ28_504 AC27
PS_DDR4_DQ29 PS_DDR_DQ29_504 AD27
PS_DDR4_DQ30 PS_DDR_DQ30_504 AD28
PS_DDR4_DQ31 PS_DDR_DQ31_504 AC28
PS_DDR4_DQ32 PS_DDR_DQ32_504 T22
PS_DDR4_DQ33 PS_DDR_DQ33_504 R22
PS_DDR4_DQ34 PS_DDR_DQ34_504 P22
PS_DDR4_DQ35 PS_DDR_DQ35_504 N22
PS_DDR4_DQ36 PS_DDR_DQ36_504 T23
PS_DDR4_DQ37 PS_DDR_DQ37_504 P24
PS_DDR4_DQ38 PS_DDR_DQ38_504 R24
PS_DDR4_DQ39 PS_DDR_DQ39_504 N24
PS_DDR4_DQ40 PS_DDR_DQ40_504 H24
PS_DDR4_DQ41 PS_DDR_DQ41_504 J24
PS_DDR4_DQ42 PS_DDR_DQ42_504 M24
PS_DDR4_DQ43 PS_DDR_DQ43_504 K24
PS_DDR4_DQ44 PS_DDR_DQ44_504 J22
PS_DDR4_DQ45 PS_DDR_DQ45_504 H22
PS_DDR4_DQ46 PS_DDR_DQ46_504 K22
PS_DDR4_DQ47 PS_DDR_DQ47_504 L22
PS_DDR4_DQ48 PS_DDR_DQ48_504 M25
PS_DDR4_DQ49 PS_DDR_DQ49_504 M26
PS_DDR4_DQ50 PS_DDR_DQ50_504 L25
PS_DDR4_DQ51 PS_DDR_DQ51_504 L26
PS_DDR4_DQ52 PS_DDR_DQ52_504 K28
PS_DDR4_DQ53 PS_DDR_DQ53_504 L28
PS_DDR4_DQ54 PS_DDR_DQ54_504 M28
PS_DDR4_DQ55 PS_DDR_DQ55_504 N28
PS_DDR4_DQ56 PS_DDR_DQ56_504 J28

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PS_DDR4_DQ57 PS_DDR_DQ57_504 K27

PS_DDR4_DQ58 PS_DDR_DQ58_504 H28
PS_DDR4_DQ59 PS_DDR_DQ59_504 H27
PS_DDR4_DQ60 PS_DDR_DQ60_504 G26
PS_DDR4_DQ61 PS_DDR_DQ61_504 G25
PS_DDR4_DQ62 PS_DDR_DQ62_504 K25
PS_DDR4_DQ63 PS_DDR_DQ63_504 J25
PS_DDR4_DM0 PS_DDR_DM0_504 AG20
PS_DDR4_DM1 PS_DDR_DM1_504 AE23
PS_DDR4_DM2 PS_DDR_DM2_504 AE25
PS_DDR4_DM3 PS_DDR_DM3_504 AE28
PS_DDR4_DM4 PS_DDR_DM4_504 R23
PS_DDR4_DM5 PS_DDR_DM5_504 H23
PS_DDR4_DM6 PS_DDR_DM6_504 L27
PS_DDR4_DM7 PS_DDR_DM7_504 H26
PS_DDR4_A0 PS_DDR_A0_504 W28
PS_DDR4_A1 PS_DDR_A1_504 Y28
PS_DDR4_A2 PS_DDR_A2_504 AB28
PS_DDR4_A3 PS_DDR_A3_504 AA28
PS_DDR4_A4 PS_DDR_A4_504 Y27
PS_DDR4_A5 PS_DDR_A5_504 AA27
PS_DDR4_A6 PS_DDR_A6_504 Y22
PS_DDR4_A7 PS_DDR_A7_504 AA23
PS_DDR4_A8 PS_DDR_A8_504 AA22
PS_DDR4_A9 PS_DDR_A9_504 AB23
PS_DDR4_A10 PS_DDR_A10_504 AA25
PS_DDR4_A11 PS_DDR_A11_504 AA26
PS_DDR4_A12 PS_DDR_A12_504 AB25
PS_DDR4_A13 PS_DDR_A13_504 AB26
PS_DDR4_WE_B PS_DDR_A14_504 AB24
PS_DDR4_CAS_B PS_DDR_A15_504 AC24
PS_DDR4_RAS_B PS_DDR_A16_504 AC23
PS_DDR4_ACT_B PS_DDR_ACT_N_504 Y23
PS_DDR4_ALERT_B PS_DDR_ALERT_N_504 U25
PS_DDR4_BA0 PS_DDR_BA0_504 V23
PS_DDR4_BA1 PS_DDR_BA1_504 W22
PS_DDR4_BG0 PS_DDR_BG0_504 W24
PS_DDR4_CS0_B PS_DDR_CS_N0_504 W27
PS_DDR4_ODT0 PS_DDR_ODT0_504 U28
PS_DDR4_PARITY PS_DDR_PARITY_504 V24
PS_DDR4_RESET_B PS_DDR_RST_N_504 U23
PS_DDR4_CLK0_P PS_DDR_CK0_P_504 W25
PS_DDR4_CLK0_N PS_DDR_CK0_N_504 W26
PS_DDR4_CKE0 PS_DDR_CKE0_504 V28

PL-side DDR4 SDRAM pinout:

Signal name Pin Name Pin Number

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PL_DDR4_DQS0_P IO_L22P_T3U_N6_DBC_AD0P_64 AE2

PL_DDR4_DQS0_N IO_L22N_T3U_N7_DBC_AD0N_64 AF2
PL_DDR4_DQS1_P IO_L16P_T2U_N6_QBC_AD3P_64 AD2
PL_DDR4_DQS1_N IO_L16N_T2U_N7_QBC_AD3N_64 AD1
PL_DDR4_DQ0 IO_L24N_T3U_N11_64 AG1
PL_DDR4_DQ1 IO_L24P_T3U_N10_64 AF1
PL_DDR4_DQ2 IO_L23N_T3U_N9_64 AH1
PL_DDR4_DQ3 IO_L23P_T3U_N8_64 AH2
PL_DDR4_DQ4 IO_L21N_T3L_N5_AD8N_64 AF3
PL_DDR4_DQ5 IO_L21P_T3L_N4_AD8P_64 AE3
PL_DDR4_DQ6 IO_L20N_T3L_N3_AD1N_64 AH3
PL_DDR4_DQ7 IO_L20P_T3L_N2_AD1P_64 AG3
PL_DDR4_DQ8 IO_L18N_T2U_N11_AD2N_64 AC1
PL_DDR4_DQ9 IO_L18P_T2U_N10_AD2P_64 AB1
PL_DDR4_DQ10 IO_L17N_T2U_N9_AD10N_64 AC2
PL_DDR4_DQ11 IO_L17P_T2U_N8_AD10P_64 AB2
PL_DDR4_DQ12 IO_L15N_T2L_N5_AD11N_64 AB3
PL_DDR4_DQ13 IO_L15P_T2L_N4_AD11P_64 AB4
PL_DDR4_DQ14 IO_L14N_T2L_N3_GC_64 AC3
PL_DDR4_DQ15 IO_L14P_T2L_N2_GC_64 AC4
PL_DDR4_DM0 IO_L19P_T3L_N0_DBC_AD9P_64 AG4
PL_DDR4_DM1 IO_L13P_T2L_N0_GC_QBC_64 AD5
PL_DDR4_A0 IO_L8N_T1L_N3_AD5N_64 AG8
PL_DDR4_A1 IO_L3P_T0L_N4_AD15P_64 AB8
PL_DDR4_A2 IO_L8P_T1L_N2_AD5P_64 AF8
PL_DDR4_A3 IO_L3N_T0L_N5_AD15N_64 AC8
PL_DDR4_A4 IO_L11P_T1U_N8_GC_64 AF7
PL_DDR4_A5 IO_L4P_T0U_N6_DBC_AD7P_64 AD7
PL_DDR4_A6 IO_L9N_T1L_N5_AD12N_64 AH7
PL_DDR4_A7 IO_L2P_T0L_N2_64 AE9
PL_DDR4_A8 IO_L9P_T1L_N4_AD12P_64 AH8
PL_DDR4_A9 IO_L1P_T0L_N0_DBC_64 AC9
PL_DDR4_A10 IO_L4N_T0U_N7_DBC_AD7N_64 AE7
PL_DDR4_A11 IO_L7N_T1L_N1_QBC_AD13N_64 AH9
PL_DDR4_A12 IO_L6N_T0U_N11_AD6N_64 AC6
PL_DDR4_A13 IO_L1N_T0L_N1_DBC_64 AD9
PL_DDR4_BA0 IO_T1U_N12_64 AH6
PL_DDR4_BA1 IO_L5N_T0U_N9_AD14N_64 AC7
PL_DDR4_RAS_B IO_T2U_N12_64 AB5
PL_DDR4_CAS_B IO_L5P_T0U_N8_AD14P_64 AB7
PL_DDR4_WE_B IO_L11N_T1U_N9_GC_64 AF6
PL_DDR4_ACT_B IO_L13N_T2L_N1_GC_QBC_64 AD4
PL_DDR4_CS_B IO_L6P_T0U_N10_AD6P_64 AB6
PL_DDR4_BG0 IO_L2N_T0L_N3_64 AE8
PL_DDR4_RST IO_L7P_T1L_N0_QBC_AD13P_64 AG9
PL_DDR4_CLK_N IO_L10N_T1U_N7_QBC_AD4N_64 AG5
PL_DDR4_CLK_P IO_L10P_T1U_N6_QBC_AD4P_64 AG6
PL_DDR4_CKE IO_T3U_N12_64 AE4

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PL_DDR4_OTD IO_L19N_T3L_N1_DBC_AD9N_64 AH4

2.1.4 QSPI Flash

The ACU3EG core board is equipped with a 256MBit Quad-SPI FLASH chip to form an 8-bit bandwidth data bus.

The FLASH model is MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard.

Features, in use, it can be used as the system boot device to store the system boot image. These images mainly include

FPGA bit files, ARM application code and other user data files.

See Table 2-4-1 for relevant parameters.

Position No. Chip Type capacity factory

U5 MT25QU256ABA1EW9 256M bit Winbond

Table 2-4-1 QSPI Flash models and parameters

QSPI FLASH is connected to the GPIO port of BANK500 in the PS part of ZYNQ chip. This needs to be configured in system design.

The GPIO port function of the PS end is the QSPI FLASH interface. Figure 4-1 shows the QSPI Flash part in the schematic diagram.

U1

U5

QUR QSPI0_CS

Ultra BANK QSPI0_SCK QSPI FLASH

(MT25QU256)
Scale+ 500 QSPI0_D0~QSPI0_D3

Figure 2-4-1 QSPI Flash connection diagram

Configuration chip pin assignment:

Signal name Pin Name Pin Number

MIO0_QSPI0_SCLK PS_MIO0_500 AG15

MIO1_QSPI0_IO1 PS_MIO1_500 AG16
MIO2_QSPI0_IO2 PS_MIO2_500 AF15
MIO3_QSPI0_IO3 PS_MIO3_500 AH15
MIO4_QSPI0_IO0 PS_MIO4_500 AH16
MIO5_QSPI0_SS_B PS_MIO5_500 AD16

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2.1.5 eMMC Flash

The ACU3EG core board is equipped with a large-capacity 8GB eMMC FLASH chip, model

MTFC8GAKAJCN-4M, it supports the HS-MMC interface of JEDEC e-MMC V5.0 standard, the level supports 1.8V or

3.3V. The data width of the connection between eMMC FLASH and ZYNQ is 8bit. Due to the large capacity and non-volatile nature of eMMC FLASH

In the ZYNQ system, it can be used as a large-capacity storage device for the system, such as storing ARM applications,

System files and other user data files. The specific models and related parameters of eMMC FLASH are shown in Table 2-5-1.

Position No. Chip Type capacity factory

U19 MTFC8GAKAJCN-4M 8G Byte Micron

Table 2-5-1 eMMC Flash models and parameters

eMMC FLASH is connected to the GPIO port of BANK500 of the PS part of ZYNQ UltraScale+.

To configure the GPIO ports of these PS terminals as EMMC interfaces, see Figure 2-5-1 for the schematic diagram of the eMMC Flash.

point.

U1

U19
MMC_CCLK
QUR MMC_CMD eMMC
Ultra BANK
500
(MTFC8GAKAJ
CN-4M)
Scale+ MMC_DAT0~MMC_DAT7

Figure 2-5-1 eMMC Flash connection diagram

Configuration chip pin assignment:

Signal name Pin Name Pin Number

MMC_DAT0 PS_MIO13_500 AH18

MMC_DAT1 PS_MIO14_500 AG18
MMC_DAT2 PS_MIO15_500 AE18
MMC_DAT3 PS_MIO16_500 AF18
MMC_DAT4 PS_MIO17_500 AC18
MMC_DAT5 PS_MIO18_500 AC19
MMC_DAT6 PS_MIO19_500 AE19
MMC_DAT7 PS_MIO20_500 AD19
MMC_CMD PS_MIO21_500 AC21
MMC_CCLK PS_MIO22_500 AB20
MMC_RSTN PS_MIO23_500 AB18

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2.1.6 Clock Configuration

The core board provides reference clock and RTC real-time clock for PS system and PL logic respectively, making PS system and PL logic

The clock circuit design diagram is shown in Figure 2-6-1 below:

U1
Y2

Passive crystal
oscillator 32.768Khz
BANK
503 X1
QUR PS_CLK Single-ended clock

Ultra 33.33Mhz

Scale+ G1

BANK PL_CLK0_P
Differential Clock
PL_CLK0_N
64 200Mhz

Figure 2-6-1 Core board clock source

PS system RTC real time clock

The passive crystal Y2 on the core board provides a 32.768KHz real-time clock source for the PS system.

The chip's BANK503's PS_PADI_503 and PS_PADO_503 pins are connected to the chip's BANK503's PS_PADI_503 and PS_PADO_503 pins. The schematic diagram is shown in Figure 2-6-2:

Figure 2-6-2 Passive crystal oscillator of RTC

Clock pin assignment:

Signal name Pinout

PS_PADI_503 N17

PS_PADO_503 N18

PS System clock source

The X1 crystal oscillator on the core board provides a 33.333MHz clock input for the PS part. The clock input is connected to the ZYNQ chip

The PS_REF_CLK_503 pin of BANK503 is shown in Figure 2-6-3:

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Figure 2-6-3 Active crystal oscillator of PS part

Clock pin assignment:

Signal name Pinout

PS_CLK R16

PL system clock source

A differential 200MHz PL system clock source is provided on the board for the reference clock of the DDR4 controller.

Connected to the global clock (MRCC) of PL BANK64, this global clock can be used to drive the DDR4 controller and

User logic circuit. The schematic diagram of the clock source is shown in Figure 2-6-4

Figure 2-6-4 PL system clock source

PL clock pin assignment:

Signal name Pinout

PL_CLK0_P AE5

PL_CLK0_N AF5

2.1.7 LED Lights

The ACU3EG core board has a red power indicator light (PWR) and a configuration LED light (DONE).

After the FPGA is configured, the power indicator will light up; after the FPGA is configured, the configuration LED will light up.

As shown in Figure 2-7-1:

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U1
3.3V
1.8V

D21

QUR BANK (Power indicator light)

Ultra 503
D2
Scale+ (DONE indicator light)

Figure 2-7-1 Core board LED light hardware connection diagram

2.1.8 Power supply

The ACU3EG core board is powered by +12V, which is connected to the baseboard.

The chip TPS6508641 generates all the power required by the XCZU3EG chip. For the TPS6508641 power design, please refer to the power chip

Manual, the design block diagram is as follows:

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In addition, the VCCIO power supply of BANK65 and BANK66 of the XCZU3EG chip is provided by the baseboard, which is convenient for users to modify.

The maximum power supply cannot exceed 1.8V.

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2.1.9 Structure diagram

Top View

2.1.10 Connector Pin Definition

The core board has a total of 4 high-speed expansion ports, using 4 120-pin board connectors (J29~J32) and the bottom board connector.

The connector used is Panasonic's AXK5A2137YG, and the corresponding connector model of the baseboard is AXK6A2337YG.

BANK65, BANK66 IO, J30 connects BANK25, BANK26, BANK66 IO and BANK505 MGT transceiver signal

No., J31 connects to IO of BANK24, BANK44, J32 connects to MIO of PS, VCCO_65, VCCO_66 and +12V power supply.

The IO level standard of BANK43~46 is 3.3V, and the level standard of BANK65,66 is determined by VCCO_65 of the baseboard.

The voltage level of MIO is determined by the VCCO_66 power supply, but cannot exceed +1.8V; the voltage level of MIO is also 1.8V.

J29 Connector Pinout

J29 Pin Signal Name Pin Number J29 Pin Signal Name Pin Number

1 B65_L2_N V9 2 B65_L22_P K8
3 B65_L2_P U9 4 B65_L22_N K7
5 GND - 6 GND -

7 B65_L4_N T8 8 B65_L20_P J6
9 B65_L4_P R8 10 B65_L20_N H6
11 GND - 12 GND -

13 B65_L1_N Y8 14 B65_L6_N T6
15 B65_L1_P W8 16 B65_L6_P R6
17 GND - 18 GND -

19 B65_L7_P L1 20 B65_L17_P N9

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twenty one
B65_L7_N K1 twenty two
B65_L17_N N8
twenty three GND - twenty four GND -

25 B65_L15_P N7 26 B65_L9_P K2
27 B65_L15_N N6 28 B65_L9_N J2
29 GND - 30 GND -

31 B65_L16_P P7 32 B65_L3_N V8
33 B65_L16_N P6 34 B65_L3_P U8
35 GND - 36 GND -

37 B65_L14_P M6 38 B65_L19_P J5
39 B65_L14_N L5 40 B65_L19_N J4
41 GND - 42 GND -

43 B65_L5_N T7 44 B65_L18_P M8
45 B65_L5_P R7 46 B65_L18_N L8
47 GND - 48 GND -

49 B65_L11_N K3 50 B65_L8_P J1
51 B65_L11_P K4 52 B65_L8_N H1
53 GND - 54 GND -

55 B65_L10_N H3 56 B65_L24_N H8
57 B65_L10_P H4 58 B65_L24_P H9
59 GND - 60 GND -

61 B66_L3_P F2 62 B65_L12_P L3
63 B66_L3_N E2 64 B65_L12_N L2
65 GND - 66 GND -

67 B66_L1_P G1 68 B65_L13_N L6
69 B66_L1_N F1 70 B65_L13_P L7
71 GND - 72 GND -

73 B66_L6_P G5 74 B65_L21_P J7
75 B66_L6_N F5 76 B65_L21_N H7
77 GND - 78 GND -

79 B66_L16_P G8 80 B65_L23_P K9
81 B66_L16_N F7 82 B65_L23_N J9
83 GND - 84 GND -

85 B66_L15_P G6 86 B66_L5_N E3
87 B66_L15_N F6 88 B66_L5_P
89 GND - 90 GND -

91 B66_L4_P G3 92 B66_L2_P E1
93 B66_L4_N F3 94 B66_L2_N D1
95 GND - 96 GND -

97 B66_L11_P D4 98 B66_L20_P C6
99 B66_L11_N C4 100 B66_L20_N B6
101 GND - 102 GND -

103 B66_L12_P C3 104 B66_L7_P C1

105 B66_L12_N C2 106 B66_L7_N B1
107 GND - 108 GND -

109 B66_L13_P D7 110 B66_L10_P B4

111 B66_L13_N D6 112 B66_L10_N A4
113 GND - 114 GND -

115 B66_L8_P A2 116 B66_L9_P B3

117 B66_L8_N A1 118 B66_L9_N A3
119 GND - 120 GND -

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Pinout of the J30 connector

J30 Tube Signal name Pin No. J30 Pin Signal Name Pin Number

foot

1 B66_L14_P E5 2 FPGA_TDI R18

3 B66_L14_N D5 4 FPGA_TCK R19
5 GND - 6 GND -

7 B66_L22_P C8 8 FPGA_TDO T21

9 B66_L22_N B8 10 FPGA_TMS N21
11 GND - 12 GND -

13 B66_L19_N A5 14 B66_L21_N A6
15 B66_L19_P B5 16 B66_L21_P A7
17 GND - 18 GND -

19 B66_L24_P C9 20 B66_L17_P F8
twenty one
B66_L24_N B9 twenty two
B66_L17_N E8
twenty three GND - twenty four GND -

25 B66_L23_N A8 26 B25_L9_P C11

27 B66_L23_P A9 28 B25_L9_N B10
29 GND - 30 GND -

31 B25_L5_N F10 32 B25_L10_P B11

33 B25_L5_P G11 34 B25_L10_N A10
35 GND - 36 GND -

37 B66_L18_N D9 38 B25_L12_P D12

39 B66_L18_P E9 40 B25_L12_N C12
41 GND - 42 GND -

43 B25_L4_N H12 44 B25_L11_P A12

45 B25_L4_P J12 46 B25_L11_N A11
47 GND - 48 GND -

49 B26_L11_P K14 50 B25_L6_N F11

51 B26_L11_N J14 52 B25_L6_P F12
53 GND - 54 GND -

55 B26_L10_N H13 56 B26_L6_N E13

57 B26_L10_P H14 58 B26_L6_P E14
59 GND - 60 GND -

61 B26_L7_N F13 62 B26_L3_N A13

63 B26_L7_P G13 64 B26_L3_P B13
65 GND - 66 GND -

67 B26_L9_N G14 68 B26_L2_N A14

69 B26_L9_P G15 70 B26_L2_P B14
71 GND - 72 GND -

73 B26_L5_N D14 74 B26_L4_N C13

79 B26_L5_P D15 76 B26_L4_P C14
77 GND - 78 GND -

79 B26_L1_P B15 80 B26_L12_P L14

81 B26_L1_N A15 82 B26_L12_N L13
83 GND - 84 GND -

85 505_CLK2_P C21 86 505_CLK1_P E21

87 505_CLK2_P C22 88 505_CLK1_P E22
89 GND - 90 GND -

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91 505_CLK0_P F23 92 505_CLK3_P A21

93 505_CLK0_N F24 94 505_CLK3_N A22
95 GND - 96 GND -

97 505_TX3_P B23 98 505_TX1_P D23

99 505_TX3_N B24 100 505_TX1_N D24
101 GND - 102 GND -

103 505_RX3_P A25 104 505_TX0_P E25

105 505_RX3_N A26 106 505_TX0_N E26
107 GND - 108 GND -

109 505_TX2_P C25 110 505_RX1_P D27

111 505_TX2_N C26 112 505_RX1_N D28
113 GND - 114 GND -

115 505_RX2_P B27 116 505_RX0_P F27

117 505_RX2_N B28 118 505_RX0_N F28
119 GND - 120 GND -

Pinout of J31 Connector

J31 Pin Signal Name Pin Number J31 Pin Signal Name Pin Number

1 B24_L10_P Y14 2 B24_L7_P AA13

3 B24_L10_N Y13 4 B24_L7_N AB13
5 GND - 6 GND -

7 B24_L6_P AC14 8 B44_L6_P AC12

9 B24_L6_N AC13 10 B44_L6_N AD12
11 GND - 12 GND -

13 B24_L5_P AD15 14 B44_L7_P AD11

15 B24_L5_N AD14 16 B44_L7_N AD10
17 GND - 18 GND -

19 B24_L1_P AE15 20 B44_L8_N AC11

twenty one
B24_L1_N AE14 twenty two
B44_L8_P AB11
twenty three GND - twenty four GND -

25 B24_L12_P Y12 26 B24_L2_P AG14

27 B24_L12_N AA12 28 B24_L2_N AH14
29 GND - 30 GND -

31 AG13 32 - -
B24_L3_P
33 AH13 34 - -
B24_L3_N
35 GND - 36 GND -

37 B44_L12_N AB9 38 B44_L9_P AA11

39 B44_L12_P AB10 40 B44_L9_N AA10
41 GND - 42 GND -

43 B44_L10_N Y10 44 B44_L3_P AH12

45 B44_L10_P W10 46 B44_L3_N AH11
47 GND - 48 GND -

49 B24_L11_N W11 50 B44_L1_N AH10

51 B24_L11_P W12 52 B44_L1_P AG10
53 GND - 54 GND -

55 B24_L9_N W13 56 B24_L4_P AE13

57 B24_L9_P W14 58 B24_L4_N AF13
59 GND - 60 GND -

61 B24_L8_P AB15 62 B44_L5_P AE12

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63 B24_L8_N AB14 64 B44_L5_N AF12

65 GND - 66 GND -

67 B44_L2_N AG11 68 B44_L4_N AF10

69 B44_L2_P AF11 70 B44_L4_P AE10
71 GND - 72 GND -

73 VBAT_IN Y18 74 B44_L11_P Y9

75 MR - 76 AA8
B44_L11_N
77 GND - 78 GND -

79 - - 80 P16
PS_POR_B
81 - - 82 - -

83 GND - 84 GND -

86 - - 86 - -

87 - - 88 - -

89 GND - 90 GND -

91 224_CLK0_P Y6 92 224_CLK1_P V6
93 224_CLK0_N Y5 94 224_CLK1_N V5
95 GND - 96 GND -

97 224_RX3_P P2 98 224_TX3_P N4
99 224_RX3_N P1 100 224_TX3_N N3
101 GND - 102 GND -

103 224_RX2_P T2 104 224_TX2_P R4

105 224_RX2_N T1 106 224_TX2_N R3
107 GND - 108 GND -

109 224_RX1_P V2 110 224_TX1_P U4

111 224_RX1_N V1 112 224_TX1_N U3
113 GND - 114 GND -

115 224_RX0_P Y2 116 224_TX0_P W4

117 224_RX0_N Y1 118 224_TX0_N W3
119 GND - 120 GND -

J32 Connector Pinout

J32 Pin Signal Name Pin Number J32 Pin Signal Name Pin Number

1 PS_MIO35 H17 2 PS_MIO30 F16

3 PS_MIO29 G16 4 PS_MIO31 H16
5 GND - - GND -

7 - - 8 F18
PS_MIO58
9 - - 10 D16
PS_MIO53
11 GND - 12 GND -

13 PS_MODE0 P19 14 PS_MIO52 G18

15 PS_MODE1 P20 16 PS_MIO55 B16
17 GND - 18 GND -

19 PS_MODE2 R20 20 PS_MIO56 C16

twenty one
PS_MODE3 T20 twenty two
PS_MIO57 A16
twenty three GND - twenty four GND -

25 PS_MIO36 K17 26 PS_MIO54 F17

27 PS_MIO37 J17 28 PS_MIO27 J15
29 GND - 30 GND -

31 - - 32 K15
PS_MIO28
33 PS_MIO77 F20 34 PS_MIO59 E17

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35 GND - 36 GND -

37 PS_MIO76 B20 38 PS_MIO60 C17

39 - - 40 D17
PS_MIO61
41 GND - 42 GND -

43 PS_MIO39 H19 44 PS_MIO62 A17

45 PS_MIO38 H18 46 PS_MIO63 E18
47 GND - 48 GND -

49 - - 50 A18
PS_MIO65
51 PS_MIO40 K18 52 PS_MIO66 G19
53 GND - 54 GND -

55 PS_MIO44 J20 56 PS_MIO67 B18

57 PS_MIO45 K20 58 PS_MIO68 C18
59 GND - 60 GND -

61 PS_MIO47 H21 62 PS_MIO64 E19

63 PS_MIO48 J21 64 PS_MIO69 D19
65 GND - 66 GND -

67 PS_MIO41 J19 68 PS_MIO74 D20

69 PS_MIO32 J16 70 PS_MIO73 G21
71 GND - 72 GND -

73 PS_MIO46 L20 74 PS_MIO72 G20

75 PS_MIO50 M19 76 PS_MIO71 B19
77 GND - 78 GND -

79 PS_MIO49 M18 80 PS_MIO75 A19

81 PS_MIO34 L17 82 PS_MIO70 C19
83 GND - 84 GND -

85 PS_MIO26 L15 86 PS_MIO43 K19

87 PS_MIO24 AB19 88 PS_MIO51 L21
89 GND - 90 GND -

91 PS_MIO25 AB21 92 PS_MIO42 L18

93 - - 94 L16
PS_MIO33
95 GND - 96 GND -

97 - - 98 - -

99 - 100 -
VCCO_65 VCCO_66
101 - 102 -
VCCO_65 VCCO_66
103 - 104 -
VCCO_65 VCCO_66
105 GND - 106 GND -

107 +12V - 108 +12V -

109 +12V - 110 +12V -

111 +12V - 112 +12V -

113 +12V - 114 +12V -

115 +12V - 116 +12V -

117 +12V - 118 +12V -

119 +12V - 120 +12V -

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Expansion Board

2.2.1 Introduction

Through the previous function introduction, we can understand the

functions of the

expansion board: 1 M.2

interface 1 DP output

interface 4 USB3.0 interfaces

2 Gigabit Ethernet interfaces

2 USB Uart interfaces 1

Micro SD card holder 1 MIPI

camera interface 2 40-pin

expansion ports 2 CAN

communication interfaces 2

485 communication

interfaces JTAG

debugging port 1

temperature sensor 1

EEPROM 1 RTC

real-time clock; 3 LED lights 3 buttons

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2.2.2 M.2 interface

The AXU3EG development board is equipped with a PCIE x1 standard M.2 interface for connecting to an M.2 SSD solid state drive.

The communication speed is up to 6Gbps. The M.2 interface uses an M key slot and only supports PCI-E, not SATA. Users can choose SSD solid state

When choosing a hard drive, you need to choose a PCIE type SSD solid state drive.

The PCIE signal is directly connected to the ZU3EG BANK505 PS MGT transceiver. Both the TX signal and the RX signal are connected in

The differential signal is connected to LANE1 of MGT. The PCIE clock is provided by Si5332 chip with a frequency of 100Mhz.

The schematic diagram of the road design is shown in Figure 3-2-1 below:

U1

PCIE_TX_P PCIE_TX_C_P

PCIE_TX_N PCIE_TX_C_N

QUR BANK
505
PCIE_RX_P

Ultra MGT PCIE_RX_N

Scale+ 505_PCIE_REFCLK_P PCIE_REFCLK_P

505_PCIE_REFCLK_N Si5332 PCIE_REFCLK_N

PCIE_RSTn_MIO37 M2_PCIE_RST_N
Level conversion

3-2-1 M.2 interface design diagram

The pinout of the ZYNQ M.2 interface is as follows:

Signal name Pin Name Pin Number Remark

PCIE_TX_P 505_TX0_P E25 PCIE data is sending

PCIE_TX_N 505_TX0_N E26 PCIE data transmission negative

PCIE_RX_P 505_RX0_P F27 PCIE data receiving

PCIE_RX_N 505_RX0_N F28 PCIE data receiving negative

505_PCIE_REFCLK_P 505_CLK0_P F23 PCIE reference clock positive

505_PCIE_REFCLK_N 505_CLK0_N F24 PCIE reference clock negative

PCIE_RSTn_MIO37 PS_MIO37_501 J17 PCIE reset signal

2.2.3 DisplayPort

The AXU3EG development board has a standard DisplayPort output interface for video image display.

Supports VESA DisplayPort V1.2a output standard, supports up to 4K x 2K@30Fps output, supports Y-only, YCbCr444, YCbCr422, YCbCr420 and RGB video

formats, and supports 6, 8, 10, or 12 bits per color.

The DisplayPort data transmission channel is directly driven by ZU3EG's BANK505 PS MGT output, and the MGT's LANE2 and

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LANE3 TX signal is connected to the DP connector as a differential signal. DisplayPort auxiliary channel is connected to the MIO pin of PS

The schematic diagram of DP output interface design is shown in Figure 3-3-1 below:

U1
DP reference clock

27Mhz
Si5332

GT0_DP_TX_P GT0_DP_TX_C_P
BANK
GT0_DP_TX_N GT0_DP_TX_C_N
505
MGT
QUR GT1_DP_TX_P GT1_DP_TX_C_P

Ultra GT1_DP_TX_N GT1_DP_TX_C_N

Scale+ U46
U37
DP_AUX_OUT DP_AUX_OUT_LS
DPAUX_P
DP_AUX_IN DP_AUX_IN_LS
BANK Level
Single-ended to
DPAUX_N
differential
DP_OE DP_OE_LS
501 Conversion

DP_HPD DP_HPD_LS

3-3-1 DP interface design diagram

The pinout of the DisplayPort interface ZYNQ is as follows:

Signal name ZYNQ Pin Name ZYNQ Pin Number Remark

GT0_DP_TX_P 505_TX3_P B23 DP data low bit is sent positive

GT0_DP_TX_N 505_TX3_N B24 DP data low bit sends negative

GT1_DP_TX_P 505_TX2_P C25 DP data high bit is sent positive

GT1_DP_TX_N 505_TX2_N C26 DP data high bit sends negative

505_CLK1_P 505_CLK2_P C21 DP reference clock positive

505_CLK1_N 505_CLK2_N C22 DP reference clock negative

DP_AUX_OUT PS_MIO27 J15 DP auxiliary data output

DP_AUX_IN PS_MIO30 F16 DP Auxiliary Data Input

DP_OE PS_MIO29 G16 DP Auxiliary Data Output Enable

DP_HPD PS_MIO28 K15 DP insertion signal detection

2.2.4 USB3.0 interface

The AXU3EG expansion board has 4 USB3.0 interfaces, supports HOST working mode, and the data transmission speed is up to

5.0Gb/s. USB3.0 is connected via the PIPE3 interface, and USB2.0 is connected to the external USB3320C chip via the ULPI interface.

It supports high-speed USB3.0 and USB2.0 data communication.

The USB interface is a flat USB interface (USB Type A), which is convenient for users to connect different USB Slave peripherals (such as USB

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Mouse, keyboard or USB flash drive). The schematic diagram of USB3.0 connection is shown in 3-4-1:
U1

U69
U5

USB_CLK

USB_STP
DP/DM
USB_NXT
BANK USB PHY
502 USB__DIR (USB3320C)
USB3.0 HUB

QUR USB_DATA0~USB_DATA7 (GL3523T)

Ultra 501
USB_RESET_N

Scale+
USB_SSTXP USB_TXP_UP
USB_SSTXN USB_TXN_UP

BANK
505 USB_SSRXP USB_RXP_UP
U1
MGT USB_SSRXN USB_RXN_UP

26Mhz
Si5332

USB3.0 reference clock

3-4-1 USB3.0 interface diagram

USB interface pinout:

Signal name Pin Name Pin Number Remark

USB_SSTXP 505_TX1_P D23 USB3.0 data transmission

USB_SSTXN 505_TX1_N D24 USB3.0 data transmission negative

USB_SSRXP 505_RX1_P D27 USB3.0 data receiving

USB_SSRXN 505_RX1_N D28 USB3.0 data receiving negative

USB_DATA0 PS_MIO56 C16 USB2.0 data bit 0

USB_DATA1 PS_MIO57 A16 USB2.0 data bit1

USB_DATA2 PS_MIO54 F17 USB2.0 Data Bit2

USB_DATA3 PS_MIO59 E17 USB2.0 data bit3

USB_DATA4 PS_MIO60 C17 USB2.0 data bit4

USB_DATA5 PS_MIO61 D17 USB2.0 Data Bit5

USB_DATA6 PS_MIO62 A17 USB2.0 Data Bit6

USB_DATA7 PS_MIO63 E18 USB2.0 Data Bit7

USB_STP PS_MIO58 F18 USB2.0 stop signal

USB_DIR PS_MIO53 D16 USB2.0 data direction signal

USB_CLK PS_MIO52 G18 USB2.0 clock signal

USB_NXT PS_MIO55 B16 USB2.0 Next Data Signal

USB_RESET_N PS_MIO31 H16 USB2.0 reset signal

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2.2.5 Gigabit Ethernet Interface

The AXU3EG expansion board has two Gigabit Ethernet interfaces, one connected to the PS end and the other connected to the PL end.

The chip uses Micrel's KSZ9031RNX Ethernet PHY chip to provide users with network communication services.

The chip supports 10/100/1000 Mbps network transmission rate and communicates with the MAC layer of the ZU3EG system through the RGMII interface.

Communication. KSZ9031RNX supports MDI/MDX adaptation, various speed adaptation, Master/Slave adaptation, and supports MDIO

The bus performs register management of the PHY.

When KSZ9031RNX is powered on, it will detect the level status of some specific IOs to determine its own working mode. Table 3-5-1

Describes the default settings of the GPHY chip after power-on.

Configuration Pin illustrate Configuration Values

PHYAD[2:0]
PHY address for MDIO/MDC mode PHY Address is 011

CLK125_EN
Enable 125Mhz clock output selection enable

LED_MODE
LED Light Mode Configure a single LED light mode

MODE0~MODE3
Link auto-adaptation and full-duplex configuration 10/100/1000 auto-adaptation, compatible with full-duplex

Duplex, Half-duplex

Table 3-5-1 PHY chip default configuration values

When the network is connected to Gigabit Ethernet, data transmission between ZYNQ and PHY chip KSZ9031RNX is done through RGMII bus.

The transmission clock is 125Mhz and data is sampled on the rising and falling edges of the clock.

When the network is connected to 100M Ethernet, the data transmission between ZYNQ and PHY chip KSZ9031RNX is through RMII bus

Communication, the transmission clock is 25Mhz. Data is sampled on the rising and falling edges of the clock.

Figure 3-5-1 is a schematic diagram of the ZYNQ Ethernet PHY chip connection:

U1
U4
J6
RGMII TX
GPHY
BANK
(KSZ9031RNX)
502
RGMII RX
QUR
Ultra U22

Scale+ RGMII TX
J11

BANK GPHY
66 (KSZ9031RNX)
RGMII RX

Figure 3-6-1 Schematic diagram of ZYNQ and GPHY connection

The Gigabit Ethernet pinout is as follows:

Signal name Pin Name Pin Number Remark

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PHY1_TXCK PS_MIO64 E19 Ethernet 1RGMII transmit clock

PHY1_TXD0 PS_MIO65 A18 Ethernet 1 sends data bit 0

PHY1_TXD1 PS_MIO66 G19 Ethernet 1 sends data bit 1

PHY1_TXD2 PS_MIO67 B18 Ethernet 1 sends data bit 2

PHY1_TXD3 PS_MIO68 C18 Ethernet 1 sends data bit 3

PHY1_TXCTL PS_MIO69 D19 Ethernet 1 sends enable signal

PHY1_RXCK PS_MIO70 C19 Ethernet 1RGMII receive clock

PHY1_RXD0 PS_MIO71 B19 Ethernet 1 Receive data Bit 0

PHY1_RXD1 PS_MIO72 G20 Ethernet 1 Receive data Bit 1

PHY1_RXD2 PS_MIO73 G21 Ethernet 1 Receive data Bit2

PHY1_RXD3 PS_MIO74 D20 Ethernet 1 Receive data Bit3

Ethernet 1 receives data valid signal

PHY1_RXCTL PS_MIO75 A19
Number

PHY1_MDC PS_MIO76 B20 Ethernet 1MDIO Management Clock

PHY1_MDIO PS_MIO77 F20 Ethernet 1MDIO Management Data

PHY2_TXCK B66_L17_N E8 Ethernet 2 RGMII Transmit Clock

PHY2_TXD0 B66_L18_P E9 Ethernet 2 sends data bit 0

PHY2_TXD1 B66_L18_N D9 Ethernet 2 sends data bit 1

PHY2_TXD2 B66_L23_P A9 Ethernet 2 sends data bit 2

PHY2_TXD3 B66_L23_N A8 Ethernet 2 sends data bit3

PHY2_TXCTL B66_L24_N B9 Ethernet 2 sends enable signal

PHY2_RXCK B66_L14_P E5 Ethernet 2 RGMII Receive Clock

PHY2_RXD0 B66_L19_N A5 Ethernet 2 Receive data Bit0

PHY2_RXD1 B66_L19_P B5 Ethernet 2 Receive data Bit 1

PHY2_RXD2 B66_L17_P F8 Ethernet 2 Receive data Bit2

PHY2_RXD3 B66_L24_P C9 Ethernet 2 Receive data Bit3

Ethernet 2 receives data valid signal

PHY2_RXCTL B66_L22_N B8
Number

PHY2_MDC B66_L21_N A6 Ethernet 2 MDIO Management Clock

PHY2_MDIO B66_L22_P C8 Ethernet 2 MDIO Management Data

PHY2_RESET B66_L14_N D5 Ethernet 2 reset signal

2.2.6 USB Uart Interface

The AXU3EG expansion board is equipped with two Uart to USB interfaces, one connected to the PS end and one connected to the PL end.

The chip is replaced with Silicon Labs CP2102GM USB-UAR chip, and the USB interface uses a MINI USB interface, which can be used with USB

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Connect it to the USB port of the PC through a cable for serial data communication. The schematic diagram of the USB Uart circuit design is shown below:
U1

U10 U9
PS_UART1_RX

J7

PS_UART0_TX U9_RXD
RxD VBUS
BANK
UART-USB REGIN
501 PS_UART0_RX
Level conversion
U9_TXD (CP2102-GM)
TXD
D+/-

QUR Micro USB

Ultra
U11
Scale+ J8

PL_UART_RX
RxD VBUS
BANK UART-USB REGIN
43 PL_UART_TX (CP2102-GM)
TXD
D+/-
Micro USB

3-6-1 USB to serial port diagram

USB to Serial ZYNQ Pinout:

Signal name Pin Name Pin Number Remark

PS_UART0_TX PS_MIO43 K19 PS Uart Data Output

PS_UART0_RX PS_MIO42 L18 PS Uart Data Input

PL_UART_TX B43_L3_P AH12 PL Uart data output

PL_UART_RX B43_L3_N AH11 PL Uart Data Input

2.2.7 SD card slot

The AXU3EG expansion board includes a Micro SD card interface to provide users with access to the SD card memory for storing

ZU3EG chip BOOT program, Linux operating system kernel, file system and other user data files.

The SDIO signal is connected to the IO signal of the PS BANK501 of ZU3EG, because the VCCIO of 501 is set to 1.8V, but the data of the SD card is

The data level is 3.3V, so we use the TXS02612 level converter to connect. The schematic diagram of the ZU3EG PS and SD card connector is as follows:

As shown in Figure 3-7-1.

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U1

U24

SD_D0~D3 D0~D3
QUR CLK
Ultra BANK SD_CLK
TXS02612
CMD
Scale+ 501 SD_CMD

SD_CD
MICRO SD

Figure 3-7-1 SD card connection diagram

SD card slot pinout

Signal name Pin Name Pin Number Remark

SD_CLK PS_MIO51 l21 SD clock signal

SD_CMD PS_MIO50 M19 SD command signal

SD_D0 PS_MIO46 L20 SD Data0

SD_D1 PS_MIO47 H21 SD Data1

SD_D2 PS_MIO48 J21 SD Data2

SD_D3 PS_MIO49 M18 SD Data3

SD_CD PS_MIO45 K20 SD card detection signal

2.2.8 40-pin expansion port

The AXU3EG expansion board has two 2.54mm standard pitch 40-pin expansion ports J45 and J46 reserved for connecting the black gold

The expansion port has 40 signals, including 1 5V power supply, 1 3.3V power supply, and 1 5V power supply.

2 sources, 3 grounds, 34 IO ports. The IO of the expansion port is connected to the IO of the ZYNQ chip BANK44, 24, 25, 26, and the level is

The standard is 3.3V.

The pin assignment of J45 expansion port ZYNQ is as follows:

J45 Pin Signal Name Pin Number J17 Pin Signal name Pin Number

1 GND - 2 +5V -

3 B45_L9_N B10 4 B45_L9_P C11

5 B45_L5_N F10 6 B45_L5_P G11
7 B45_L12_N C12 8 B45_L12_P D12
9 B45_L11_N A11 10 B45_L11_P A12
11 B45_L6_N F11 12 B45_L6_P F12
13 B46_L6_N E13 14 B46_L6_P E14
15 B46_L3_N A13 16 B46_L3_P B13
17 B46_L2_N A14 18 B46_L2_P B14
19 B46_L4_N C13 20 B46_L4_P C14
twenty one
B46_L12_N L13 twenty two
B46_L12_P L14
twenty three
B45_L4_N H12 twenty four
B45_L4_P J12

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25 B46_L11_N J14 26 B46_L11_P K14

27 B46_L10_N H13 28 B46_L10_P H14
29 B46_L7_N F13 30 B46_L7_P G13
31 B46_L9_N G14 32 B46_L9_P G15
33 B46_L5_N D14 34 B46_L5_P D15
35 B46_L1_N A15 36 B46_L1_P B15
37 GND - 38 GND -

39 +3.3V - 40 +3.3V -

The pin assignment of J46 expansion port ZYNQ is as follows:

J46 Pin Signal Name Pin Number J13 Pin Signal Name Pin Number
1 GND - 2 +5V -

3 B43_L2_N AG11 4 IO2_1P Y14

5 B44_L8_N AB14 6 IO2_2P AA13
7 B44_L9_N W13 8 IO2_3P AC12
9 B44_L11_N W11 10 IO2_4P AD11
11 B43_L10_N Y10 12 IO2_5P AB11
13 B43_L12_N AB9 14 IO2_6P AG14
15 B44_L3_N AH13 16 IO2_7P AC14
17 B44_L12_N AA12 18 IO2_8P AD15
19 B44_L1_N AE14 20 IO2_9P AH12
twenty one
B44_L5_N AD14 twenty two
IO2_10P AA11
twenty three
B44_L6_N AC13 twenty four
IO2_11P Y9
25 B44_L10_N Y13 26 IO2_12P AE10
27 B44_L2_N AH14 28 IO2_13P AE12
29 B43_L8_N AC11 30 IO2_14P AG10
31 B43_L7_N AD10 32 IO2_15P AF11
33 B43_L6_N AD12 34 IO2_16P W10
35 B44_L7_N AB13 36 IO2_17P AB10
37 GND - 38 GND -

39 +3.3V - 40 +3.3V -

2.2.9 CAN communication interface

There are 2 CAN communication interfaces on the AXU3EG expansion board, which are connected to the MIO interface of BANK501 on the PS system side.

The CAN transceiver chip uses TI's SN65HVD232C chip to provide user CAN communication services.

Figure 3-9-1 is the connection diagram of the CAN transceiver chip on the PS side

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U1
U28

PS_CAN1_RX RxD CANH

SN65HVD232
PS_CAN1_TX TXD CANL

QUR BANK
Ultra 501
U30
Scale+
PS_CAN2_RX RxD CANH

SN65HVD232
PS_CAN2_TX TXD CANL

Figure 3-10-1 Connection diagram of CAN transceiver chip at PS end

The CAN communication pin assignments are as follows:

Signal name Pin Name Pin Number Remark

PS_CAN1_TX PS_MIO32 J16 CAN1 Transmitter

PS_CAN1_RX PS_MIO33 L16 CAN1 Receiver

PS_CAN2_TX PS_MIO39 H19 CAN2 Transmitter

PS_CAN2_RX PS_MIO38 H18 CAN2 Receiver

2.2.10 485 Communication Interface

There are two 485 communication interfaces on the AXU3EG expansion board. The 485 communication ports are connected to the IO interfaces of BANK43~45 at the PL end.

The 485 transceiver chip uses MAXIM's MAX3485 chip to provide user 485 communication services.

Figure 3-11-1 is the connection diagram of the PL end 485 transceiver chip

U1
U12

PL_485_RXD1
RO B

PL_485_TXD1 MAX3485
DI A

/RE
QUR PL_485_DE1
DE
BANK
Ultra 43,44
U2
Scale+ 45
PL_485_RXD2
RO B

PL_485_TXD2 MAX3485
DI A

/RE
PL_485_DE2
DE

Figure 3-11-1 PL terminal 485 communication connection diagram

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RS485 communication pin assignments are as follows:

Signal name Pin Name Pin Number Remark

PL_485_TXD1 B43_L1_N AH10 The first 485 transmitter

PL_485_RXD1 B44_L4_P AE13 The first 485 receiving end

PL_485_DE1 B45_L10_P B11 The first 485 transmission enable

PL_485_TXD2 B43_L1_N AG10 Second 485 sender

PL_485_RXD2 B44_L4_N AF13 Second 485 receiving end

PL_485_DE2 B45_L10_N A10 The second 485 transmission enable

2.2.11 MIPI interface

The baseboard contains a MIPI camera interface, which can be used to connect our MIPI OV5640 camera module

(AN5641). MIPI interface 15PIN FPC connector, for 2 LANE data and 1 pair of clock, connected to BANK65

The voltage level of the differential IO pins is 1.2V; other control signals are connected to the IO of BANK43, and the voltage level is

3.3V.

U1
J23

MIPI_CLK_P/N
BANK
65 MIPI_LAN0_P/N
MIPI_LAN1_P/N

QUR MIPI

Ultra Connectivity

Device

Scale+ BANK
CAM_GPIO
CAM_CLK
43 CAM_SCL
CAM_SDA

Figure 3-11-1 HDMI interface design schematic

MIPI Interface Pinout

Signal name ZYNQ Pin Name ZYNQ Pin Number Remark

MIPI_CLK_P B65_L1_P W8 MIPI input clock positive

MIPI_CLK_N B65_L1_N Y8 MIPI input clock negative

MIPI_LAN0_P B65_L2_P U9 MIPI input data LANE0 positive

MIPI_LAN0_N B65_L2_N V9 MIPI input data LANE0 negative

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MIPI_LAN1_P B65_L3_P U8 MIPI input data LANE1 positive

MIPI_LAN1_N B65_L3_N V8 MIPI input data LANE1 negative

CAM_GPIO B43_L4_P AE10 GPIO control of the camera

CAM_CLK B43_L4_N AF10 Camera clock input

CAM_SCL B43_L11_P Y9 Camera I2C clock

CAM_SDA B43_L11_N AA8 I2C data from the camera

2.2.12 JTAG Debug Port

A JTAG interface is reserved on the AXU3EG expansion board for downloading ZYNQ UltraScale+ programs or firmware.

To prevent damage to the ZYNQ UltraScale+ chip caused by live plugging and unplugging, we added protection to the JTAG signal.

The diode ensures that the signal voltage is within the range accepted by the FPGA to avoid damage to the ZYNQ UltraScale+ chip.

Figure 3-12-1 JTAG interface part in the schematic diagram

2.2.13 RTC Real-time Clock

The ZU3EG chip has an internal RTC real-time clock function, which has year, month, day, hour, minute, second and week timekeeping functions.

Connect a 32.768KHz passive clock to provide an accurate clock source to the internal clock circuit so that the RTC can accurately

To provide clock information. At the same time, in order to ensure that the real-time clock can still operate normally after the product loses power, it is generally necessary to equip it with a power supply.

The battery supplies power to the clock chip. The BT1 on the development board is a 1.5V button battery (model LR1130, voltage is 1.5V).

The button battery can also power the RTC system and provide continuous time information. Figure 3-12-1 shows the RTC system.

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Real-time clock schematic

U1
Y2

Passive crystal oscillator

QUR BANK 32.768Khz

Ultra 503 BT1

Scale+ VBAT_IN

Figure 3-13-1 is the RTC real-time clock schematic diagram

2.2.14 EEPROM and Temperature Sensor

The AXU3EG development board has an EEPROM onboard, model 24LC04, capacity: 4Kbit (2*256*8bit), through IIC

The bus is connected to the PS end for communication. In addition, the board also has a high-precision, low-power, digital temperature sensor chip, model

The temperature accuracy of the LM75 chip is 0.5 degrees. The EEPROM and temperature sensor are

The I2C bus is mounted on the Bank500 MIO of ZYNQ UltraScale+. Figure 3-14-1 is the schematic diagram of the EEPROM and temperature sensor.

U27
U1
LM75

QUR BANK U26 U25

Ultra 500 PS_IIC1_SCL

PS_IIC1_SDA
Level Conversion

Change
PS_IIC_B_SCL
PS_IIC_B_SDA
EEPROM

Scale+

Figure 3-14-1 Schematic diagram of EEPROM and sensor

The EEPROM communication pin assignments are as follows:

Signal name Pin Name Pin Number Remark

PS_IIC1_SCL PS_MIO24 AB19 I2C clock signal

PS_IIC1_SDA PS_MIO25 AB21 I2C Data Signal

2.2.15 LED Lights

There are 3 LEDs on the AXU3EG expansion board. They include 1 power indicator, 1 PS control indicator, and 1

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The user can control the on and off of the indicator light through the program. When the IO voltage connected to the user LED light is low, the user

When the IO voltage is high, the user LED will be lit. The user LED hardware connection diagram is as follows:

As shown in Figure 3-15-1:

3.3V

U1 3.3V
PS_LED

QUR BANK PL_LED

Ultra 501
Scale+ BANK
43

Figure 3-15-1 User LED light hardware connection diagram

Pin assignment for user LEDs

Signal name Pin Name Pin Number Remark

PS_LED1 PS_MIO40 K18 User PS LED Light

PL_LED1 B43_L5_P AE12 User PL LED Light

2.2.16 Buttons

The AXU3EG expansion board has a reset button RESET and two user buttons. The reset signal is connected to the reset pin of the core board.

Chip input, user can use this reset button to reset the ZYNQ system. User button 1 connected to the MIO of PS

The reset button and user button are both low level effective. The connection diagram of the user button is as follows:

As shown in Figure 3-16-1:

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U1

PS KEY
BANK PS_KEY1
501
QUR
Ultra
PL KEY
Scale+ BANK PL_KEY1

43

Figure 3-16-1 Reset button connection diagram

ZYNQ pin assignment for buttons

Signal name Pin Name Pin Number Remark

PS_KEY1 PS_MIO26 L15 PS button 1 input

PL_KEY1 B43_L5_N AF12 PL button 1 input

2.2.17 DIP switch configuration

There is a 4-bit DIP switch SW1 on the development board to configure the startup mode of the ZYNQ system.

The platform supports 4 boot modes. These 4 boot modes are JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card.

Startup mode. After the ZU3EG chip is powered on, it will detect the level of (PS_MODE0~3) to determine the startup mode. Users can

Use the DIP switch SW1 on the expansion board to select different startup modes. The SW1 startup mode configuration is shown in Table 3-17-1 below.

Show.

SW1 MODE[3:0]
DIP switch position (1, 2, 3, 4) Startup Mode

0000 PS JTAG
ON, ON, ON, ON

0010 QSPI FLASH

ON, ON, OFF, ON

0101
ON, OFF, ON, OFF SD Card

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0110 EMMC
ON, OFF, OFF, ON

Table 3-17-1 SW1 startup mode configuration

2.2.18 Power supply

The power input voltage of the AXU3EG development board is DC12V. The baseboard is connected via a DC/DC power chip TPS54620 and 2

The DC/DC power chip MP1482 converts it into +5V, +3.3V, +1.8V. In addition, the baseboard generates +1.2V through LDO to the core board

BANK65 is powered by +1.8V, and BANK66 is powered by +1.8V. The power supply design diagram on the board is shown in Figure 3-18-1:

U38

+12V 2A +5.0V/6A
12V power supply TPS54620

U35
+1.2V
LDO

U40

+3.3V/2A
MP1482

U39

+1.8V/2A
MP1482

Figure 3-18-1 Power supply interface part in the schematic diagram

The functions of each power distribution are shown in the following table:

power supply Function

+5.0V
USB Power Supply

+1.8V Ethernet, USB2.0, core board BANK66

+3.3V Ethernet, USB2.0, SD, DP, CAN, RS485

+1.2V Core board BANK65

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2.2.19 Fan

Because ZU3EG generates a lot of heat when it is working normally, we added a heat sink and fan to the chip on the board.

The fan is controlled by the ZYNQ chip, and the control pin is connected to the IO of BANK43.

(AA11), if the IO level output is low, the MOSFET is turned on and the fan works; if the IO level output is high, the fan stops.

The fan design on the board is shown in Figure 3-19-1:

Figure 3-19-1 Fan design in the development board schematic

The fan has been fixed to the development board with screws before leaving the factory. The power supply of the fan is connected to the J42 socket, with the red one being the positive pole

and the black one being the negative pole.

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2.2.20 Structural dimensions

Figure 3-20-1 Top View

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Chapter 3 Introduction to Verilog Basic Modules

Introduction

This article mainly introduces the basic modules of Verilog, which will lay a solid foundation and will be of great help in in-depth study of FPGA.

Data Types

3.2.1 Constants

Integer: Integers can be represented by binary b or B, octal o or O, decimal d or D, hexadecimal h or H,

For example, 8'b00001111 represents a binary integer with a width of 8 bits, and 4'ha represents a hexadecimal integer with a width of 4 bits.

X and Z: X represents an indeterminate value, and z represents a high resistance value. For example, 5'b00x11, the third digit is an indeterminate value, and 3'b00z represents the lowest resistance value.

The bit is high resistance.

Underscore: When the number of bits is too long, it can be used to split the number of bits to improve program readability, such as 8'b0000_1111

Parameter parameter: parameter can use identifiers to define constants. When using it, only the identifier is used, which improves readability.

For example, if parameter width = 8 is defined, register reg [width-1:0] a is defined, which means that the register width is 8 bits.

register.

Parameter passing: If a module has defined parameters, the parameters can be passed when other modules call this module.

You can modify the parameters as shown below, indicated by #() after module.

For example, define a module as

follows to call the module

module rom module top() ;

#(
parameter depth =15, wire [31:0] addr ;
parameter width = 8 ) wire [15:0] data ;
wire result ;
(
input [depth-1:0] addr , rom
input [width-1:0] data output result ) , #(
.depth(32),
; .width(16) )

endmodule r1
(
,
,
.addr(addr) .data(data) .result(result)
);
endmodule

Parameter can be used to pass parameters between modules, while localparam is only used within this module and cannot be used to pass parameters between modules.

Localparam is mostly used to define the state of the state machine.

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variable

A variable is a quantity whose value can be changed while a program is running. The following mainly introduces several commonly used variable types.

1.1.1 Wire Type

Wire type variables, also called network type variables, are used for physical connections between structural entities, such as between doors.

It can store values and use the continuous assignment statement assign to assign values. It is defined as wire [n-1:0] a; where n represents the bit width.

For example, if we define wire a; assign a = b;, it connects the node of b to the wire a. As shown in the figure below, the wire between two entities is a wire

type variable.

1.1.2 Reg type

Reg type variables, also called register variables, can be used to store values and must be used in an always statement.

for

reg [n-1:0] a; indicates a register with a width of n bits, such as reg [7:0] a; indicates a register a with a width of 8 bits.

The register q is defined as shown below. The generated circuit is sequential logic. The right figure
shows its structure, which is a D flip-
flop. module
top(d, clk, q) ;
input d ; input clk ; output reg q ;

always @(posedge clk) begin q <= d ;

end

endmodule

It is also possible to generate combinational logic, such as data selectors, where sensitive signals have no clocks, define reg mux, and finally generate electrical

The path is combinational logic.

module top(a, b, c, d, sel, Mux) ; input a ; input b ; input c ; input

d ; input [1:0] sel ;
output reg Mux ;

always @(sel or a or b or c or d) begin case(sel) 2'b00 : Mux =

a ; 2'b01 :
Mux = b ;

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2'b10 : Mux = c ; 2'b11 : Mux

= d ; endcase

end

endmodule

1.1.3 Memory Type

The memory type can be used to define RAM, ROM and other memories. Its structure is reg [n-1:0] memory name [m-1:0],

It means m registers with a width of n bits. For example, reg [7:0] ram [255:0] means 256 8-bit registers are defined, 256 is the depth of the

memory, and 8 is the data width.

Operators

Operators can be divided into the following categories:

(1) Arithmetic operators (+, -, *, /, %)

(2) Assignment operators (=, <=)

(3) Relational operators (>, <, >=, <=, ==, !=)

(4) Logical operators (&&, ||, !)

(5) Conditional operator (?:)

(6) Bitwise operators (~, |, ^, &, ^~)

(7) Shift operators (<<, >>)

(8) Concatenation operator ({ })

3.4.1 Arithmetic operators

"+" (addition operator), "-" (subtraction operator), "*" (multiplication operator), "/" (division operator, such as 7/3 = 2),

"%" (modulo operator, i.e., remainder operator, e.g., 7%3=1, remainder is 1)

3.4.2 Assignment Operators

"=" is blocking assignment, "<=" is non-blocking assignment. Blocking assignment means executing one assignment statement before executing the next one.

It is executed sequentially, and the assignment is executed immediately; non-blocking assignment can be understood as parallel execution, regardless of the order, and the assignment

is performed after the always block statement is executed. For example, the following blocking assignment:

The code is The incentive file is as follows

as follows: module top(din,a,b,c,clk); `timescale 1 ns/1 ns

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module top_tb() ; reg din ; reg

input din; input clk ; wire a,b,c ;
clk; output reg
a,b,c;

always @(posedge clk) begin initial begin

din = 0 ;
a = din; b = a; clk = 0 ; forever
c = b;

end begin
#({$random}%100) din = ~din ;
endmodule end

end

always #10 clk = ~clk ;

top
t0(.din(din),.a(a),.b(b),.c(c),.clk(clk)) ;
endmodule

It can be seen from the simulation results that at the rising edge of clk, the value of a is equal to din and is immediately assigned to b, and the value of b is assigned to c.

If it is changed to non-blocking assignment, the simulation results are as follows: at the rising edge of clk, the value of a is not immediately assigned to b, and b is the original value of a.

Similarly, c is the original value of b.

You can see obvious differences from the RTL diagrams of the two:

Blocking assignment RTL diagram Non-blocking assignment RTL diagram In general, non-blocking

assignment is used in sequential logic circuits to avoid competition hazards during simulation.

Blocking assignment is used in logic, and changes are made immediately after the assignment statement is executed; blocking assignment must be used in the assign statement.

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3.4.3 Relational Operators

Used to express the relationship between two operands, such as a>b, a<b, and is often used to determine conditions, for example:

If (a>=b) q <=1'b1 ; else q <=

1'b0 ; means if the value

of a is greater than or equal to the value of b, the value of q is 1, otherwise the value of q is 0

3.4.4 Logical Operators

“&&” (logical AND of two operands), “||” (logical OR of two operands), “!” (logical NOT of a single operand) For example: If (a>b && c <d) means the condition

is a>b and c<d; if (!a) means the condition is that the value of a is not 1, that is, 0.

3.4.5 Conditional Operators

“?:” is a conditional judgment, similar to if else, for example, assign a = (i>8)?1'b1:1'b0; judge whether the value of i is greater than 8, such as

If it is greater than 8, the value of a is 1, otherwise it is 0.

3.4.6 Bitwise Operators

"~" bitwise inversion, "|" bitwise OR, "^" bitwise XOR, "&" bitwise AND, "^" bitwise XOR, except for "~" which only needs one

In addition to the operand, the others all require two operands, such as a&b, a|b. The specific application will be explained in the later section on combinational logic.

3.4.7 Shift Operators

“<<” is the left shift operator, and ”>>” is the right shift operator. For example, a<<1 means shifting 1 bit to the left, and a>>2 means shifting two bits to the right.

3.4.8 Concatenation Operator

The "{ }" concatenation operator concatenates multiple signals bit by bit, such as {a[3:0], b[1:0]}, which concatenates the lower 4 bits of a and the lower 2 bits of b.

In addition, {n{a[3:0]}} means splicing n a[3:0], and {n{1'b0}} means splicing n bits of 0. For example, {8{1'b0}} means 8'b0000_0000.

3.4.9 Priority

The precedence of various operators is as follows:

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Combinational Logic

This section mainly introduces combinational logic. The characteristic of combinational logic circuit is that the output at any time depends only on the input signal.

When the input signal changes, the output changes immediately, independent of the clock.

3.5.1 AND Gate

In Verilog, "&" represents bitwise AND, such as c=a&b, the truth table is as follows, the result is only when a and b are both equal to 1

1. RTL means as shown on the right

The code is The stimulus file is as

implemented as follows: module follows: `timescale 1 ns/1 ns module
top(a, b, c) ; top_tb() ; reg a ; reg b ; wire c ;
input a ; input
b ; output c ;

assign c = a & b ; endmodule

initial
begin a
=0;b=0;
forever

begin

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#({$random}%100)
a = ~a ;
#({$random}%100) b = ~b ; end

end

top t0(.a(a), .b(b),.c(c)) ;

endmodule

The simulation results are as follows:

If the bit width of a and b is greater than 1, for example, if we define input [3:0] a, input [3:0]b, then a&b refers to the pair of a and b.

The bitwise AND operation should be performed, such as a[0]&b[0], a[1]&b[1].

3.5.2 OR Gate

In Verilog, "|" represents bitwise OR, such as c = a|b, the truth table is as follows, the result is only when a and b are both 0

0.

The code is The incentive file is as follows

implemented as follows: module top(a, b, c); `timescale 1 ns/1 ns module

input a ; top_tb() ;
input b ; reg a ;
output c ; reg b ;
wire c ;
assign c = a | b ;
endmodule initial
begin
a=0;
b=0;
forever
begin
#({$random}%100)
a = ~a ;
#({$random}%100) b = ~b ; end

end

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top t0(.a(a), .b(b),.c(c)) ;

endmodule

The simulation results are as follows:

Similarly, if the bit width is greater than 1, it is bitwise OR.

3.5.3 NOT Gate

In Verilog, “~” represents bitwise inversion, such as b=~a, the truth table is as follows, b is equal to the opposite of a.

The code is implemented as follows:

The stimulus file is as

module top(a, b) ; input a ; output follows: `timescale 1 ns/1 ns module

b; top_tb() ; reg a ; wire b ;

assign b = ~a ; endmodule
initial begin

a=0;
forever begin
#({$random}

%100)

a = ~a ; end

end

top t0(.a(a), .b(b)) ;

endmodule

The simulation results are as follows:

3.5.4 XOR

In Verilog, “^” represents XOR, such as c= a^b, the truth table is as follows, when a and b are the same, the output is 0.

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The incentive files are as follows:

The code is
implemented as follows: module top(a, b, c); `timescale 1 ns/1 ns module top_tb() ;
input a ;
input b ; reg a ;
output c ; reg b ;
wire c ;
^
assign c = a endmodule b;
initial
begin
a=0;
b=0;
forever
begin
#({$random}%100)
a = ~a ;
#({$random}%100) b = ~b ; end

end

top t0(.a(a), .b(b),.c(c)) ;

endmodule

The simulation results are as follows:

3.5.5 Comparator

In Verilog, the symbols are greater than ">", equal to "==", less than "<", greater than or equal to ">=", less than or equal to "<=", and not equal to "!="

Indicates, taking greater than as an example, such as c = a > b; if a is greater than b, then the value of c is 1, otherwise it is 0. The truth table is as follows

Down:

The incentive files are as follows:

The code is
implemented as follows: module top(a, b, c); `timescale 1 ns/1 ns

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input a ; input b ; module top_tb() ;

output c ; reg a ;
reg b ; wire
c;
assign c = a > b ; endmodule
initial begin

a=0;b
= 0 ; forever

begin
#({$random}%100)
a = ~a ;
#({$random}%100) b = ~b ; end

end

top t0(.a(a), .b(b),.c(c)) ;

endmodule

The simulation results are as follows:

3.5.6 Half Adder

Half adder and full adder are the basic units in arithmetic operation circuits. Since the half adder does not consider the carry from the low bit,

It is called a half adder, sum represents the addition result, count represents the carry, and the truth table can be expressed as follows:

The code can be written based on The stimulus file is as

the truth table as follows: module top(a, b, follows: `timescale 1 ns/1 ns module
sum, count) ; top_tb() ; reg a ; reg b ; wire sum ;
input a ; input wire count ;
b ; output sum ;
output count ;

^
assign sum = a assign b;
count = a & b ; initial

begin a =
endmodule 0;b=0;
forever begin

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#({$random}%100)
a = ~a ;
#({$random}%100) b = ~b ; end

end

top t0(.a(a), .b(b),

.sum(sum), .count(count)) ;

endmodule

The simulation results are as follows:

3.5.7 Full Adder

The full adder needs to add the carry signal cin from the low bit, and the truth table is as follows:

The code is as follows: The incentive files are as follows:

module top(cin, a, b, sum, count) ; `timescale 1 ns/1 ns module

input cin ; top_tb() ;
input a ; reg a ;
input b ; reg b ;
output sum ; reg cin ;
output count ; wire sum ;
wire count ;
assign {count,sum} = a + b + cin ;
initial
endmodule begin
a=0;
b=0;
cin = 0 ;
forever
begin
#({$random}%100)
a = ~a ;
#({$random}%100)
b = ~b ;
#({$random}%100) cin =
~cin ;

end

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end

top t0(.cin(cin),.a(a), .b(b), .sum(sum), .count(count)) ;

endmodule

The simulation results are as follows:

3.5.8 Multiplier

The representation of multiplication is also very simple, just use "*",

such as a*b. The example code `timescale 1 ns/1 ns module top_tb() ;
is as follows: module reg [1:0] a ; reg [1:0] b ; wire
top(a, b, c) ; input [3:0] c ;
[1:0] a ; input [1:0] b ; output [3:0] c ;

assign c = a endmodule * b ;
initial
begin a
=0;b=0;
forever

begin
#({$random}%100)
a = ~a ;
#({$random}%100) b = ~b ; end

end

top t0(.a(a), .b(b),.c(c)) ;

endmodule

The simulation results are as follows:

3.5.9 Data Selector

Data selectors are often used in Verilog. By selecting signals, different input signals are selected and output to the output end. As shown

in the truth table below, there is a four-to-one data selector, sel[1:0] is the selection signal, a, b, c, d are input signals, and Mux is the output signal.

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The code is as follows: The stimulus file is as

module top(a, b, c, d, sel, Mux) ; input a ; input b ; input c ; input d ; follows: `timescale 1 ns/1 ns module
top_tb() ; reg a ; reg b ; reg c ; reg
d ; reg [1:0]
sel ; wire Mux ;

input [1:0] sel ;

output reg Mux ;

initial

always @(sel or a or b or c or d) begin case(sel) 2'b00 : Mux = begin a =

a ; 2'b01 : 0;b=0;c=
Mux = b ; 2'b10 : 0;d=0;
Mux = c ; 2'b11 : Mux = d ; endcase forever

begin
#({$random}%100) a = {$random}
end %3 ; #({$random}%100) b =
{$random}%3 ; #({$random}
endmodule %100) c = {$random}%3 ;
#({$random}%100) d = {$random}
%3 ; end

end

initial begin

sel =
2'b00 ; #2000 sel = 2'b01 ;
#2000 sel = 2'b10 ; #2000 sel = 2'b11 ;
end

top
t0(.a(a), .b(b),.c(c),.d(d), .sel(se l),

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.Mux(Mux)) ;

endmodule

The simulation results are as follows

3.5.10 3-8 Decoder

3-8 The decoder is a very commonly used device. Its truth table is shown below. Different results are obtained according to the values of A2, A1, and A0.

fruit.

The code is as The stimulus file is as

follows: module top(addr, decoder) ; input [2:0] addr ; follows: `timescale 1 ns/1 ns module
output reg [7:0] decoder ; top_tb() ; reg [2:0] addr ; wire
[7:0] decoder ;

always @(addr) begin

case(addr) initial
3'b000 : decoder = begin
addr = 3'b000 ;

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8'b1111_1110 ; 3'b001 : # 2000 addr = 3'b001 ; # 2000 addr =

decoder = 3'b010 ; # 2000 addr = 3'b011 ; # 2000
8'b1111_1101 ; 3'b010 : addr = 3'b100 ; # 2000 addr = 3'b101 ;
decoder =

8'b1111_1011 ; 3'b011 :
decoder = 8'b1111_0111 ; 3'b100 :

decoder =

8'b1110_1111 ; 3'b101 :
decoder = top
8'b1101_1111 ; 3'b110 : t0(.addr(addr),.decoder(decoder)) ;
decoder = 8'b1011_1111 ; 3'b111 :

decoder = endmodule

8'b0111_1111 ; endcase

end

endmodule

The simulation results are as follows:

3.5.11 Three-state gate

In FPGA use, bidirectional IO is often used, and a tri-state gate is required, such as bio = en? din: 1'bz; where en is the enable signal, which is used to open

and close the tri-state gate. The following RTL diagram implements bidirectional IO, and you can refer to the code. The stimulus file realizes the connection between two

bidirectional IOs.

module top(en, din, dout, bio) ; input din ; input en ; output `timescale 1 ns/1 ns module top_tb() ;
dout ; inout bio ; reg en0 ; reg din0 ; wire dout0 ;
reg en1 ; reg
din1 ; wire dout1 ;
wire bio ;

assign bio = en? din : 1'bz ; assign dout = bio ;

endmodule
initial begin
din0 = 0 ;
din1 = 0 ; forever

begin
#({$random}%100) din0 =
~din0 ; #({$random}%100)
din1 = ~din1 ;

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end
end

initial
begin
en0 = 0 ; en1 =
1 ; #100000 en0
= 1 ; en1 =
0 ; end

top
t0(.en(en0),.din(din0),.dout(dout0), .bi

o(bio)) ; top

t1(.en(en1),.din(din1),.dout(dout1), .bi

o(bio)) ;

endmodule

The incentive file structure is as follows

The simulation results are as follows: when en0 is 0 and en1 is 1, channel 1 is open, and the bidirectional IO bio is equal to din1 of channel 1, 1

Channel 0 sends data outward, channel 0 receives data, dout0 equals bio; when en0 is 1 and en1 is 0, channel 0 is turned on, the bidirectional IO bio equals

din0 of channel 0, channel 0 sends data outward, channel 1 receives data, dout1 equals bio

Sequential Logic

The characteristic of combinational logic circuit in terms of logic function is that the output at any time depends only on the input at the current time, and has

nothing to do with the original state of the circuit. The characteristic of sequential logic in terms of logic function is that the output at any time depends not only on the

current input signal, but also on the original state of the circuit. The following is an analysis of typical sequential logic.

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3.6.1 D Flip-Flop

The D flip-flop stores data on the rising or falling edge of the clock, and the output is the same as the state of the input signal before the clock jumps. The code is

as follows The stimulus file

module top(d, clk, q); input d ; input clk ; is as follows : timescale 1 ns/1
output reg q ; ns module top_tb() ; reg
always @(posedge d ; reg
clk) begin q <= d ; end clk ; wire q ;

initial
begin d =
0 ; clk = 0 ;
endmodule forever

begin
#({$random}%100) d = ~d ; end

end

always #10 clk = ~clk ;

top t0(.d(d),.clk(clk),.q(q)) ;

endmodule

The RTL diagram is shown below

The simulation results are as follows. It can be seen that at time t0, the value of d is 0, and the value of q is also 0; at time t1, d has

If the value of q changes to 1, then q also changes accordingly and becomes 1. It can be seen that in a clock cycle between t0 and t1, no matter how the value of the input

signal d changes, the value of q remains unchanged, that is, it has a storage function, and the saved value is

The value of d at the transition edge of the clock.

3.6.2 Two-stage D flip-flop

The software performs timing analysis based on the model of a two-stage D flip-flop. Specifically, it can analyze the timing of two D flip-flops at the same time.

The data output by the device is different. The RTL diagram is as follows:

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The code is as The stimulus file is as

follows: module top(d, clk, q, q1) ; input d ; input clk ; follows: `timescale 1 ns/1 ns module
output reg q ; top_tb() ; reg d ; reg clk ; wire q ;
output reg q1 ; wire q1 ;

always @(posedge clk) begin q <= d ;

end initial begin

d = 0 ; clk
= 0 ; forever

always @(posedge clk) begin q1 <= q ;

end begin
#({$random}%100) d = ~d ; end

endmodule end

always #10 clk = ~clk ;

top
t0(.d(d),.clk(clk),.q(q),.q1(q1)) ;

endmodule

The simulation results are as follows. It can be seen that at t0, d is 0 and q output is 0. At t1, q changes with the data change of d, and the

value of q is still 0 before the clock jump, so the value of q1 is still 0. At t2, the value of q is 1 before the clock jump, so the value of q1 is 1

accordingly. q1 lags behind q by one cycle.

3.6.3 D Flip-Flop with Asynchronous Reset

Asynchronous reset is independent of the clock. Once the asynchronous reset signal is valid, the reset operation is triggered. This function is written in the code

It is often used to reset and initialize the signal. Its RTL diagram is as follows:

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The code is as follows. Note that the asynchronous reset signal should be placed in the sensitive list. If it is a low-level reset, it is negedge.

If it is a high level reset, it is posedge

module top(d, rst, clk, q); input d ; input rst ; input clk ; `timescale 1 ns/1 ns module top_tb() ;
output reg q ; reg d ;

reg rst ; reg clk ;

wire q ;
always @(posedge clk or negedge rst) begin if (rst == 1'b0)
q <=
0 ; else q initial
<= d ; end begin d =
0 ; clk = 0 ;
forever

begin
#({$random}%100) d = ~d ; end
endmodule end

initial begin

rst = 0 ;
#200 rst = 1 ; end

always #10 clk = ~clk ;

top
t0(.d(d),.rst(rst),.clk(clk),.q(q))
;

endmodule

The simulation results are as follows. It can be seen that before the reset signal, although the input signal d data has changed,

Bit state, the input signal q is always 0, and the value of q is normal after reset.

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3.6.4 D Flip-Flop with Asynchronous Reset and Synchronous Clear

As mentioned above, asynchronous reset is independent of the clock operation, while synchronous clear is synchronized with the clock signal.

It is limited to synchronous clearing, and can also be other synchronous operations. The RTL diagram is as follows:

The code is as follows. Unlike asynchronous reset, synchronous operation cannot

put the signal into the sensitivity list. module top(d, `timescale 1 ns/1 ns module top_tb() ;
rst, clr, clk, q); reg d ; reg rst ; reg clr ; reg clk ;
input d ; input wire q ;
rst ; input clr ;
input clk ; output
reg q ;

always @(posedge clk or negedge rst) begin if (rst == 1'b0) q

<= 0 ; initial

else if (clr begin d =

== 1'b1) q <= 0 ; else 0 ; clk = 0 ;
forever

begin
#({$random}%100) d = ~d ; end
q <= d ; end

end
endmodule
initial begin

rst = 0 ;
clr = 0 ; #200 rst
= 1 ; #200 clr =
1 ; #100 clr = 0 ; end

always #10 clk = ~clk ;

top
t0(.d(d),.rst(rst),.clr(clr),.clk(cl k),

.q(q)) ;

endmodule

The simulation results are as follows. It can be seen that after the clr signal is pulled high, q is not cleared immediately, but is executed after the next clk rising edge.

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Perform a clear operation, that is, clr is synchronized with clk.

3.6.5 Shift Register

A shift register is a register that moves one bit to the left or right when each clock pulse comes. Due to the characteristics of the D flip-flop, the data

The output is synchronized with the clock edge, and its structure is as follows: when each clock comes, the output q of each D flip-flop is equal to the value of the

output of the previous D flip-flop, thereby realizing the shift function.

Code Stimulus file:

implementation: module top(d, rst, clk, q); input d ; `timescale 1 ns/1 ns module top_tb() ;
input rst ; input clk ; reg d ;
output reg [7:0] q ;

reg rst ; reg clk ;

wire [7:0] q ;
always @(posedge clk or negedge rst) begin if (rst == 1'b0)
q <=
0 ; else q initial begin
<= {q[6:0], d} ; // shift left //q d = 0 ; clk
<= {d, q[7:1]} ; // = 0 ; forever
shift

right
begin
end #({$random}%100) d = ~d ; end

endmodule
end

initial

begin rst
= 0 ; #200 rst =
1 ; end

always #10 clk = ~clk ;

top
t0(.d(d),.rst(rst),.clk(clk),.q(q))
;

endmodule

The simulation results are as follows. It can be seen that after reset, each clk rising edge shifts left by one position.

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3.6.6 Single-port RAM

The write address and read address of the single-port RAM share the same address. The code is as follows, where reg [7:0] ram [63:0] means

64 8-bit width data are defined. Addr_reg is defined to hold the read address and return the data after a delay of one cycle.

According to sent.

module top ( `timescale 1 ns/1 ns module top_tb() ;

input [7:0] data, reg [7:0] data ; reg [5:0]

input [5:0] addr, addr ; reg wr ;
input wr,
input clk, reg clk ;
output [7:0] q ); wire [7:0] q ;

initial
reg [7:0] ram[63:0]; //declare ram reg [5:0] addr_reg; //addr register begin
data = 0 ;
addr = 0 ;
wr = 1 ;
always @ (posedge clk) clk = 0 ;
begin end
if (wr) //write ram[addr] <= data;
always #10 clk = ~clk ;

addr_reg <= addr; always @(posedge clk)

end begin
data <= data + 1'b1 ;
assign q = ram[addr_reg]; //read data addr <= addr + 1'b1 ;
end
endmodule
top t0(.data(data),
.addr(addr),
.clk(clk),
.wr(wr),
.q(q)) ;
endmodule

The simulation results are as follows. It can be seen that the output of q is consistent with the written data.

3.6.7 Pseudo Dual-Port RAM

The read and write addresses of the pseudo dual-port RAM are independent, and the write or read address can be randomly selected to perform read and write operations at the same time.

As shown below, the en signal is defined in the stimulus file, and the read address is sent when it is valid.

module top ( `timescale 1 ns/1 ns module top_tb() ;

input [7:0] data, reg [7:0] data ; reg [5:0]

input [5:0] write_addr, write_addr ;

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input [5:0] read_addr, input wr, input rd, reg [5:0] read_addr ; reg wr ;
input clk, output
reg [7:0] q ); reg clk ; reg rd ;
wire [7:0] q ;

initial begin
reg [7:0] ram[63:0]; //declare ram reg [5:0] addr_reg; //addr register data = 0 ;
write_addr = 0 ;
read_addr = 0 ; wr = 0 ; rd =
0 ; clk = 0 ; #100 wr = 1 ;
always @ (posedge clk) begin //write if #20 rd = 1 ;
(wr) end
ram[write_addr] <= data; if (rd) //read q <=
ram[read_addr];

end
always #10 clk = ~clk ;
endmodule
always @(posedge clk) begin if (wr)
begin
data <= data
+ 1'b1 ;
write_addr <= write_addr +

1'b1 ;
if (rd)
read_addr <= read_addr +
1'b1 ; end

end

top

t0(.data(data), .write_addr(write_addr), .read_addr(read_addr), .clk(clk), .wr(wr), .

The simulation results are as follows. It can be seen that when rd is valid, the read address is operated and the data is read out.

3.6.8 True Dual-Port RAM

True dual-port RAM has two sets of control lines and data lines, allowing two systems to read and
module top ( write it. The code is as follows:
`timescale 1 ns/1 ns
input [7:0] data_a, data_b, input [5:0] addr_a, module top_tb() ; reg [7:0] data_a,
addr_b, input wr_a, wr_b, input rd_a, rd_b, input data_b ; reg [5:0] addr_a, addr_b ; reg
clk, wr_a, wr_b ; reg rd_a,
rd_b ; reg clk ;

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output reg [7:0] q_a, q_b ); wire [7:0] q_a, q_b ;

initial
reg [7:0] ram[63:0]; //declare ram begin
data_a = 0 ;
//Port A data_b = 0 ;
always @ (posedge clk) addr_a = 0 ;
begin addr_b = 0 ;
if (wr_a) begin //write wr_a = 0 ;
wr_b = 0 ;
ram[addr_a] <= data_a; rd_a = 0 ;
q_a <= data_a ; rd_b = 0 ;
end clk = 0 ;
if (rd_a) //read #100 wr_a = 1 ;
q_a <= #100 rd_b = 1 ;
ram[addr_a]; end
end
always #10 clk = ~clk ;

//Port B always @(posedge clk)

always @ (posedge clk) begin
begin if (wr_a)
if (wr_b) begin //write begin
data_a <= data_a + 1'b1 ;
ram[addr_b] <= data_b; addr_a <= addr_a + 1'b1 ;
q_b <= data_b ; end
end else

if (rd_b) //read begin

q_b <= data_a <= 0 ;
ram[addr_b]; addr_a <= 0 ;
end end
end
endmodule
always @(posedge clk)
begin
if (rd_b)
begin
addr_b <= addr_b + 1'b1 ; end

else addr_b <= 0 ;

end

top
t0(.data_a(data_a), .data_b(data_b),
.addr_a(addr_a), .addr_b(addr
_b
),
.wr_a(wr_a), .wr_b(wr_b),
.rd_a(rd_a), .rd_b(rd_b),

.clk(clk), .q_a(q_a), .q_b(q_b)) ;

endmodule

The simulation results are as follows

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3.6.9 Single-port ROM

ROM is used to store data. You can initialize ROM in the following code form, but this method cannot handle large capacity

ROM is more troublesome, it is recommended to use the ROM IP core that comes with the FPGA and add an initialization

file. Code Stimulus

implementation file`timescale 1 ns /1 ns module

module top ( top_tb() ; reg [3:0] addr ; reg clk ;
input [3:0] addr, input clk, output wire [7:0] q ;
reg [7:0] q );

initial
always @(posedge clk) begin case(addr) begin
4'd0 : q addr = 0 ; clk = 0 ;
<= 8'd15 ; 4'd1 : q end
<= 8'd24 ; 4'd2 : q <= 8'd100 ; 4'd3 : q
<= 8'd78 ; 4'd4 : q <= 8'd98 ; 4'd5 : q <=
8'd105 ; 4'd6 : q <= 8'd86 ; 4'd7 : q <= always #10 clk = ~clk ;
8'd254 ; 4'd8 : q <= 8'd76 ; 4'd9 : q <=
8'd35 ; 4'd10 : q <= 8'd120 ; 4'd11 : q <= always @(posedge clk) begin addr <=
8'd85 ; 4'd12 : q <= 8'd37 ; 4'd13 : q <= addr +
8'd19 ; 4'd14 : q <= 8'd22 ; 4'd15 : q <= 1'b1 ;
8'd67 ; default: q <= 8'd0 ; endcase end

top t0(.addr(addr), .clk(clk), .q(q)) ;

endmodule

end

endmodule

The simulation results are as follows

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3.6.10 Finite State Machine

Finite state machines are often used in Verilog to handle relatively complex logic, set different states, and

The finite state machine mainly uses always and

case statement. The following is an example of a four-state finite state machine.

An 8-bit shift register is designed in the program. In the Idle state, it is determined whether the shift_start signal is high. If

High, enter the Start state, delay 100 cycles in the Start state, enter the Run state, and perform shift processing. If

When the shift_stop signal is valid, the system enters the Stop state. In the Stop state, the value of q is cleared and the system jumps to the Idle state.

Mealy finite state machine, the output is not only related to the current state, but also to the input signal.

No. is connected.

module top (

input shift_start,
input shift_stop,
input rst,
input clk,
input d,
output reg [7:0] q );

parameter Idle = 2'd0 ; //Idle state parameter Start = 2'd1 ; //Start

state parameter Run = 2'd2 ; //Run state parameter Stop = 2'd3 ; //
Stop state

reg [1:0] state ; reg [4:0] //statement //delay

delay_cnt ; counter

always @(posedge clk or negedge rst)

begin
if (!rst)
begin
state <= Idle ;
delay_cnt <= 0 ;
q <= 0 ;
end
else
case(state)
Idle : begin
if (shift_start)
state <= Start ;
end
Start : begin

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if (delay_cnt == 5'd99)
begin
delay_cnt <= 0 ;
state <= Run ;
end
else
delay_cnt <= delay_cnt + 1'b1 ;
end
Run : begin
if (shift_stop)
state <= Stop ;
else
q <= {q[6:0], d} ;
end
Stop : begin
q <= 0 ;
state <= Idle ;
end
default: state <= Idle ;
endcase
end
endmodule
Moore finite state machine, the output is only related to the current state, not the input signal, and the input signal only affects the change of state.

Changes do not affect the output, for example, the processing of delay_cnt and q is only related to the state.

module top (

input shift_start,
input shift_stop,
input rst,
input clk,
input d,
output reg [7:0] q );

parameter Idle = 2'd0 ; parameter Start //Idle state

= 2'd1 ; parameter Run = 2'd2 ; //Start state
parameter Stop = 2'd3 ; //Run state
//Stop state

reg [1:0] current_state ; reg [1:0] //statement

next_state ;
reg [4:0] delay_cnt ; //delay counter //First part: statement transition
always @(posedge clk or negedge rst)

begin
if (!rst)
current_state <= Idle ;
else
current_state <= next_state ;
end
//Second part: combination logic, judge statement transition
condition
always @(*)
begin
case(current_state)
Idle : begin
if (shift_start)
next_state <= Start ;
else
next_state <= Idle ;

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end
Start : begin
if (delay_cnt == 5'd99) next_state <= Run ;
else

next_state <= Start ;

end

Run : begin if (shift_stop)

next_state <= Stop ; else

next_state <= Run ;

end
Stop : next_state <= Idle ; next_state <= Idle ;
default:
endcase
end

//Last part: output data always @(posedge clk

or negedge rst) begin if (!rst) delay_cnt <= 0 ;

else if (current_state == Start) delay_cnt <= delay_cnt + 1'b1 ;

else

delay_cnt <= 0 ; end

always @(posedge clk or negedge rst) begin if (!rst) q <= 0 ; else if

(current_state ==
Run) q <=
{q[6:0], d} ; else

q <= 0 ; end

endmodule

In the above two programs, two writing methods are used. The first Mealy state machine adopts a one-segment writing method,

which uses only one always statement. All state transitions, state transition conditions, and data output are in one always statement. The

disadvantage is that if there are too many states, the whole program will be lengthy. The second Moore state machine adopts a three-

segment writing method. State transition uses an always statement, and the state transition condition is combinatorial logic, which uses an

always statement. Data output is also a separate always statement. This is more intuitive and clear to write, and it will not be cumbersome

when there are many states.

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Mealy finite state machine RTL diagram

Moore finite state machine RTL diagram

The stimulus file is as

follows: `timescale 1 ns/1 ns module
top_tb() ; reg shift_start ; reg
shift_stop ; reg rst ; reg clk ; reg
d ; wire [7:0] q ;

initial

begin rst
= 0 ; clk = 0 ; d =
0 ; #200 rst = 1 ;
forever

begin
#({$random}%100) d = ~d ; end
end

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initial
begin
shift_start = 0 ; shift_stop = 0 ;
#300 shift_start = 1 ; #1000
shift_start = 0 ; shift_stop = 1 ; #50
shift_stop = 0 ; end

always #10 clk = ~clk ;

top t0 (

.shift_start(shift_start), .shift_stop(shift_stop), .rst(rst), .clk(clk), .d(d), .q(q) ); endmodule

The simulation results are as follows:

Summarize

This document introduces the commonly used modules in combinational logic and sequential logic. Among them, the finite state machine is relatively complex but often used.

I hope everyone can have a deep understanding, apply more in the code, think more, which will help to quickly improve their level.

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Chapter 4 PL 's "Hello World" LED Experiment

The experimental Vivado project is "led".

PL (FPGA) development is crucial for ZYNQ, and this is also where ZYNQ has an advantage over other ARMs. It can customize many ARM-

side peripherals. Before customizing the ARM-side peripherals, let us first use an LED routine to get familiar with the PL (FPGA) development process

and the basic operations of Vivado software. This development process is exactly the same as that of FPGA chips without ARM.

In this example, we are going to do an LED light control experiment, controlling the LED light on the development board to flip once per second.

Now I can control the LED lights, and other peripherals will be controlled gradually.

LED Hardware Introduction

1) The PL part of the development board is connected to a red user LED. This light is completely controlled by the PL. If PL_LED1

If the voltage is high, the transistor will be turned on and the light will be on, otherwise it will be off.

2) We can determine the binding relationship between the LED and PL pins based on the wiring relationship in the schematic diagram.

Base Plate

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Core board

3) PS_MIO
In the schematic diagram IO Both PS endIO , no need to bind, and can not bind
At the beginning

Create a Vivado project

1) Start Vivado. In Windows, you can double-click the Vivado shortcut to start Vivado.

2) Click “Create New Project” in the Vivado development environment to create a new project.

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3) A wizard for creating a new project pops up, click "Next"

4) In the pop-up dialog box, enter the project name and the directory where the project is stored. Here we choose a project name of LED.

Please note that the project location cannot have any Chinese spaces and the path name cannot be too long.

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5) Select "RTL Project" in the project type

6) Select "Verilog" for the target language. Although Verilog is selected, VHDL can also be used, supporting multi-

language mixed programming.

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7) Click "Next" without adding any files

8) Take the AXU3EG development board as an example. In the “Part” option, select “Zynq UltraScale+

MPSoCs", select "sfvc784" for package type, "-1" for speed, and "I" for temperature.

Select "xczu3eg-sfvc784-1-i" in the drop-down list. "-1" indicates the rate level. The larger the number, the higher the rate level.

The better the performance, the higher the speed of the chip is, and the lower the speed of the chip is. (The model selected in the example is "xazu3eg-

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sfvc784-1-i", the two are compatible)

AXU4EV development board, in the "Part" option, select "Zynq UltraScale+ MPSoCs" for the device family, select

"sfvc784" for the package type, select "-1" for the speed, and select "I" for the temperature to reduce the selection range.

Select "xczu4ev-sfvc784-1-i" in the drop-down list;

AXU5EV development board, in the "Part" option, select "Zynq UltraScale+ MPSoCs" for the device family, "sfvc784" for

the package type, "-1" for the speed, and "I" for the temperature to reduce the selection range. Select "xczu5ev-sfvc784-1-

i" in the drop-down list; (The model selected in the example is "xazu5ev-sfvc784-1-i", the two are

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compatible)

9) Click “Finish” to complete the creation of the project named “led”.

10) Vivado software interface

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Create a Verilog HDL file to light up the LED

1) Click the Add Sources icon under Project Manager (or use the shortcut Alt+A)

2) Select “Add or create design sources” and click “Next”

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3) Select Create File

4) Set the file name to "led" and click "OK"

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5) Click "Finish" to complete adding the "led.v" file

6) In the pop-up module definition "Define Module", you can specify the module name of the "led.v" file "Module

"name", the default is "led", you can also specify some ports, but don't specify them here for now, click "OK".

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7) Select "Yes" in the pop-up dialog box

8) Double-click "led.v" to open the file and edit it.

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9) Write "led.v", which defines a 32-bit register timer for loop counting from 0 to 199999999 (1 second).

When the count reaches 199999999 (1 second), the register timer becomes 0 and flips the four LEDs. In this way, if the

original LED is off, it will light up, and if the original LED is on, it will go out. Since the input clock is a 200MHz differential clock,

it is necessary to add an IBUFDS primitive to connect the differential signal. The written code is as follows:

`timescale 1ns / 1ps module

led(
//Differential system clock input sys_clk_p,
input sys_clk_n, input
rst_n, output reg led );
reg[31:0] timer_cnt;
wire sys_clk ;

IBUFDS IBUFDS_inst
( .O(sys_clk), // Buffer output .I(sys_clk_p), //
Diff_p buffer input (connect directly to top-level port)

.IB(sys_clk_n) // Diff_n buffer input (connect directly to

top-level port) );

always@(posedge sys_clk) begin if (!rst_n)

begin led
<= 1'b0 ; timer_cnt
<= 32'd0 ;
end else if(timer_cnt >=
32'd199_999_999) //1 second counter,

200M-1=199999999 begin led <= ~led; timer_cnt <= 32'd0;

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end
else
begin led
<= led; timer_cnt <=
timer_cnt + 32'd1; end

end
endmodule

10) Save the code after writing it

Add pin constraints

The constraint file format used by Vivado is xdc file. The xdc file mainly completes the pin constraints, clock constraints,

Here we need to assign the input and output ports in the led.v program to the real pins of the FPGA.

1) Click “Open Elaborated Design”

2) Click the "OK" button in the pop-up window

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3) Select "Window -> I/O Ports" from the menu

4) You can see the pin assignment in the pop-up I/O Ports

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5) Bind the reset signal rst_n to the button on the PL side, assign pins and level standards to the LED and clock, and click Save when finished.

Save Icon

6) A window pops up asking you to save the constraint file. Enter "led" as the file name and "XDC" as the default file type. Click

"OK"

7) Open the "led.xdc" file just generated, we can see that it is a TCL script. If we understand these languages

You can constrain the pins by writing the led.xdc file yourself.

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The following is an introduction to the most basic XDC syntax. For common IO ports, only pin numbers and voltages need to be constrained.

as follows:

"
set_property PACKAGE_PIN Pin Number
" [get_ports Port Name ]

The constraints of the level signal are as follows:

"
set_property IOSTANDARD " [get_ports
Level Standard Port Name ]

Pay attention to the capitalization of the text here. If the port name is an array, use { } to enclose it. The port name must be the same as in the source code.

The port name must be consistent with the keyword, and the port name cannot be the same as the keyword.

The number after "LVCMOS33" in the voltage level standard refers to the BANK voltage of the FPGA. The BANK voltage of the LED is 3.3.

IO Assign the correct level standards and pin numbers

Volts, so the voltage level standard is "LVCMOS33". Vivado The default requirement is all

.
Number

Adding Timing Constraints

In addition to pin allocation, an FPGA design also has an important constraint, which is timing constraint.

The guided method demonstrates how to make a timing constraint.

1) Click “Run Synthesis” to start synthesis

2) Click "OK" in the pop-up dialog box

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3) After the integration is completed, click "Cancel"

4) Click “Constraints Wizard”

5) Click "Next" in the pop-up window

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6) The Timing Constraint Wizard analyzes the clock in the design. Here, set the frequency of "sys_clk_p" to 200Mhz, and then click

"Skip to Finish" ends the Timing Constraint Wizard.

7) Click "OK" in the pop-up window

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8) Click “Finish”

9) At this time, the led.xdc file has been updated. Click "Reload" to reload the file and save the file.

Generate BIT file

1) The compilation process can be divided into synthesis, layout and routing, bit file generation, etc. Here we directly click "Generate

Bitstream”, directly generate bit file.

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2) In the pop-up dialog box, you can select the number of tasks. This is related to the number of CPU cores. Generally, the larger the number, the faster the compilation.

Quick, click "OK"

3) Start compiling at this time. You can see a status message in the upper right corner. During the compilation process, anti-virus software, computer

Brain Manager intercepts the running, resulting in failure to compile or failure to compile successfully for a long time.

4) There are no errors in the compilation. After the compilation is completed, a dialog box pops up for us to choose the follow-up operation. We can choose

"Open Hardware Manger". Of course, you can also choose "Cancel". We choose "Cancel" here and do not download it yet.

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Vivado Simulation

Next, let's try it out and use the simulation tool provided by Vivado to output waveforms to verify the design results of the pipeline lamp program.

Check whether the result is consistent with our expectation (Note: simulation can also be performed before generating the bit file). The

specific steps are as follows: 1) Set the simulation configuration of Vivado, right-click Simulation Settings in SIMULATION.

2) In the Simulation Settings window, configure as shown below. Here, it is set to 50ms (set as needed).

Keep other settings as default and click OK to finish.

3) Add the stimulus test file, click the Add Sources icon under Project Manager, set it as shown below and click Next.

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4) Click Create File to generate the simulation stimulus file.

In the pop-up dialog box, enter the name of the stimulus file. Here we enter the name vtf_led_test.

5) Click the Finish button to return.

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We will not add IO Ports here, click OK.

There is a new vtf_led_test file in the Simulation Sources directory. Double-click to open this file.

You can see that there is only the definition of the module name, nothing else.

6) Next we need to write the contents of the vtf_led_test.v file. First, define the input and output signals, then instantiate the led_test

module and make the led_test program part of this test program. Then add reset and clock stimuli.

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The completed vtf_led_test.v file is as follows:

`timescale 1ns /
1ps //////////////////////////////////////////////////////////////////////// /////////////

// Module Name:
vtf_led_test ///////////////////////////////////////////////////////////////////////// /////////////

module vtf_led_test;
// Inputs reg
sys_clk_p; reg rst_n ;
wire sys_clk_n;

// Outputs wire
led;

// Instantiate the Unit Under Test (UUT) led uut

( .sys_clk_p(sys_clk_p), .sys_clk_n(sys_clk_n), .rst_n(rst_n), .led(led)

);

initial begin //
Initialize
Inputs sys_clk_p = 0; rst_n = 0; // Wait
for global reset to finish
#1000; rst_n = 1;
end //Create clock always #2.5 sys_clk_p = ~ sys_clk_p; assign
sys_clk_n
= ~sys_clk_p ;

endmodule
7) After writing and saving, vtf_led_test.v automatically becomes the top level of the simulation hierarchy, and below it are the design files

led_test.v.

8) Click the Run Simulation button, and then select Run Behavioral Simulation. Here we will do a behavioral simulation.

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That's all.

If there are no errors, the simulation software in Vivado starts working.

10. When the simulation interface pops up as shown below, the simulation software automatically runs to the 50ms waveform set for simulation.

Since the state change time of LED[3:0] in the program is long and the simulation is time-consuming, observe the change of timer[31:0]

counter here. Put it into Wave to observe (click uut under Scope interface, then right-click and select timer under Objects interface,

and select Add Wave Window in the pop-up drop-down menu).

After adding, the timer is displayed on the Wave interface, as shown in the figure below.

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11. Click the Restart button marked below to reset, and then click the Run All button. (Patience is required!!!), and you can see that the simulation waveform is

consistent with the design. (Note: The longer the simulation time, the more disk space the simulation waveform file occupies. The waveform file is in the xx.sim

folder of the project directory)

We can see that the LED signal will become 1, which means the LED light will become brighter.

download

1) Connect the JTAG interface of the development board and power on the development board

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Note that the DIP switches must be in JTAG mode, that is, all of them should be pulled to "ON". The value represented by "ON" is 0. If the JTAG mode is not used, the

download will report an error.

2) Click "Auto Connect" on the "HARDWARE MANAGER" interface to automatically connect the device

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3) You can see that JTAG scans the arm and FPGA cores

4) Select the chip, right click "Program Device..."

5) Click "Program" in the pop-up window

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6) Wait for download

7) After the download is complete, we can see that the PL LED starts to change once a second. This is the end of the Vivado simple process experience

Completed. The following chapters will introduce how to burn the program to Flash. It requires the cooperation of the PS system to complete it. Only PL

projects cannot be burned directly to Flash. It is introduced in the FAQ of the chapter "Experience ARM, bare metal output "Hello World".

Online debugging

Simulation and downloading were introduced above, but simulation does not require the program to be burned into the board, which is a more ideal

result. The following introduces the Vivado online debugging method to observe the changes of internal signals. Vivado has an embedded logic analyzer called

ILA, which can be used to observe the changes of internal signals online, which is very helpful for debugging. In this experiment, we observe the signal

changes of timer_cnt and LED.

4.9.1 Add ILA IP core

1) Click IP Catalog, search for ila in the search box, and double-click the IP of ILA

2) Change the name to ila. Since two signals are to be sampled, the number of Probes is set to 2. Sample Data Depth refers to

The higher the sampling depth is set, the more signals are collected, and the more resources are consumed.

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3) On the Probe_Ports page, set the Probe width and set the PROBE0 bit width to 32 for sampling timer_cnt.

Set the PROBE1 bit width to 1 for sampling LED. Click OK

A pop-up interface will appear, select OK

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Set it up as follows and click Generate

4) Instantiate ila in led.v and save

5) Regenerate Bitstream

6) Download the program

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7) Now you will see bit and ltx files, click program

8) At this time, the online debugging window pops up and the signal we added appears.

Click the Run button and the signal data will appear.

You can also trigger the acquisition, click "+" in the Trigger Setup window, and select the timer_cnt signal in depth.

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Change Radix to U, which is decimal, and set Value to 199999999, which is the maximum value of timer_cnt count.

Click Run again, and you can see that the trigger is successful. At this time, timer_cnt is displayed in hexadecimal, and the LED is also flipped at this

time.

4.9.2 MARK DEBUG

The above describes how to add ILA IP to debug online. The following describes how to add comprehensive attributes to the code to achieve online debugging.

try.

1) First open led.v and comment out the instantiation of ila

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2) Add (* MARK_DEBUG="true" *) before the definition of led and timer_cnt, and save the file.

3) Click Comprehensive

4) After the synthesis is completed, click Set Up Debug

5) Click Next in the pop-up window

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Click Next as default

In the Sampling Depth window, select Next

Click Finish

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Click Save

The added ila core constraints can be seen in the xdc file

5) Regenerate the bitstream

6) The debugging method is the same as before and will not be repeated here.

Experimental Summary

This chapter introduces how to develop programs on the PL side, including project establishment, constraints, simulation, online debugging, etc.

This method can be used as a reference in subsequent code development.

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Chapter 5 PLL Experiment under Vivado

The experimental Vivado project is "pll_test".

Many beginners are confused when they see that there is only one 200Mhz clock input on the board. Why is the clock 200Mhz?

What if you want to work at 100Mhz or 150Mhz? In fact, many FPGA chips have PLL integrated inside. Other manufacturers may not call it PLL, but

they have similar functional modules. PLL can multiply and divide the frequency to generate many other clocks. This experiment uses PLL IP core to

learn how to use PLL and vivado IP core.

Experimental Principle

PLL (phase-locked loop) is an important resource in FPGA. Since a complex FPGA system often requires multiple clock signals with different

frequencies and phases, the number of PLLs in an FPGA chip is an important indicator to measure the capabilities of the FPGA chip. In the design of

FPGA, the high-speed design of the clock system is extremely important. A low-jitter, low-latency system clock will increase the success rate of FPGA

design.

This experiment will use PLL to output a square wave to the expansion port on the development board to demonstrate how to use PLL in

Vivado software.

Ultrascale+ series FPGAs use dedicated global and regional IO and clock resources to manage various clock requirements in the design. Clock

Management Tiles (CMT) provide clock frequency synthesis, deskew, and jitter filtering functions.

Each CMTs contains a MMCM (mixed-mode clock manager) and a PLL. As shown in the figure below, the input of the CMT can be BUFR,

IBUFG, BUFG, GT, BUFH, local wiring (not recommended), and the output needs to be connected to BUFG or BUFH before use.

ÿ Mixed-Mode Clock Manager (MMCM)

MMCM is used to generate different clock signals with a set phase and frequency relationship with a given input clock. MMCM

provides extensive and powerful clock management functions. The functional

block diagram inside MMCM is shown in the figure below:

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ÿ Digital Phase-Locked Loop (PLL)

Phase-locked loops (PLLs) are mainly used for frequency synthesis. Using a PLL, multiple clocks can be generated from one input clock signal.

Compared with MMCM, deskew cannot perform clocking, does not have advanced phase adjustment, and has a smaller adjustable range of multipliers and

dividers.

The PLL functional block diagram is shown below:

For more information about clock resources, I recommend you to read the document "7 Series FPGAs Clocking

Resources User Guide".

Create a Vivado project

This experiment demonstrates how to use the PLL IP core provided by Xilinx to generate clocks of different frequencies and

A clock is output to the external IO of FPGA. The following are the detailed steps of program design. 1)

Create a new pll_test project and click IP Catalog under the Project Manager interface.

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2) In the IP Catalog interface, select Clocking Wizard under FPGA Features and Design\Clocking and double-click

Open the configuration interface.

3) By default, the name of the Clocking Wizard is clk_wiz_0, so we will not modify it here. In the first interface, Clocking Options, enter the clock

frequency as 200Mhz and select Differential clock capable pin, because the clock input

The input is differential.

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4) In the Output Clocks interface, select the output of the four clocks clk_out1~clk_out4, with the frequency of 200Mhz,

100Mhz, 50Mhz, 25Mhz. You can also set the phase of the clock output here. We do not set it and keep the default phase.

Click OK to finish.

5) In the pop-up dialog box, click the Generate button to generate the design file of the PLL IP.

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6) At this time, a clk_wiz_0.xci IP will be automatically added to our pll_test project. The user can double-click it to modify

The configuration of this IP.

Select the IP Sources page and double-click to open the clk_wiz_0.veo file, which provides an example of this IP.

We just need to copy the content in the box into our Verilog program to instantiate the IP.

7) Let's write a top-level design file to instantiate this PLL IP, and write the pll_test.v code as follows. Note that the reset of the PLL

is high level effective, that is, when the level is high, it is always in the reset state, and the PLL will not work. Many novices

will ignore this. Here we bind rst_n to a button, and the button is a low level reset, so it needs to be reversely connected to

the reset of the PLL.

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`timescale 1ns / 1ps

module pll_test(
input sys_clk_p, input //system clock 200Mhz on board
sys_clk_n, input rst_n, output //system clock 200Mhz on board
clk_out //reset ,low active
//PLL clock output

);

wire locked;

clk_wiz_0 clk_wiz_0_inst
(
// Clock out ports
// output clk_out1
// output clk_out2
// output clk_out3
// output clk_out4
.clk_out1(), .clk_out2(), .clk_out3(), .clk_out4(clk_out), // Status and control signals
.reset(~rst_n), // input reset
.locked(locked), // Clock // output locked
in ports
// input clk_in1_p
.clk_in1_p(sys_clk_p), .clk_in1_n(sys_clk_n)); // input clk_in1_n

endmodule

In the program, first instantiate clk_wiz_0, input the differential 200Mhz clock signal to clk_in1_p and clk_wiz_0

clk_in1_n, assign the output of clk_out4 to clk_out.

Note: The purpose of instantiation is to call the instantiated module in the upper-level module to complete the codeVerilog
function. Instantiated Letter

The format of the module name must be consistent with the module name to be instantiated, such as the name clk_wiz_0 , including module signals

clk_in1
in the program must also be consistent, ,
such as clk_out1 , clk_out2..... TOP
The connection signal is

The signals transmitted between the program and the modules, and the connection signals between modules cannot conflict with each other, otherwise compilation errors will occur.

8) After saving the project, pll_test automatically becomes the top file, and clk_wiz_0 becomes a submodule of the Pll_test file.

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9) Add the xdc pin constraint file pll.xdc to the project. The adding method is as shown in the "PL "Hello World" LED experiment".

You can directly copy the following content and compile it to generate bitstream.

##################Compress Bitstream########################### set_property

BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property PACKAGE_PIN AE5 [get_ports sys_clk_p] set_property

IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p]

create_clock -period 5.000 -name sys_clk_p -waveform {0.000 2.500} [get_ports sys_clk_p]

set_property PACKAGE_PIN AF12 [get_ports rst_n] set_property

IOSTANDARD LVCMOS33 [get_ports rst_n]

set_property PACKAGE_PIN AG11 [get_ports clk_out] set_property

IOSTANDARD LVCMOS33 [get_ports clk_out]

simulation

Add a vtf_pll_test simulation file. After running, the PLL lock signal will become high, indicating that the PLL IP phase-locked loop has been

initialized. clk_out has a clock signal output, and the output frequency is 1/8 of the input clock frequency, which is 25Mhz. The simulation method can

refer to "PL's "Hello World" LED experiment".

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On-board verification

Compile the project and generate the pll_test.bit file, then download the bit file to the FPGA.

An oscilloscope is used to measure the output clock waveform.

Use the ground wire of the oscilloscope probe to connect to the ground on the development board (PIN1 of J46 of the development board), and the signal end to connect to

PIN3 of J46 of the development board (be careful when measuring to avoid the oscilloscope head touching other pins and causing a short circuit between the power supply and the ground).

At this time, we can see the 25Mhz clock waveform in the oscilloscope. The amplitude of the waveform is 3.3V, the duty cycle is 1:1, and the waveform

The display is as shown below:

If you want to output waveforms of other frequencies, you can modify the clock output to clk_out2 or clk_out3 of clk_wiz_0.

Or clk_out4. You can also modify clk_out4 of clk_wiz_0 to the frequency you want. Here you also need to pay attention, because the clock output is obtained by PLL's

multiplication and division coefficients of the input clock signal, so not all clock frequencies can be accurately generated by PLL, but PLL will also automatically calculate the

actual output clock frequency for you.

It should also be noted that the bandwidth and sampling rate of some users' oscilloscopes are too low, which will cause the high-frequency part to attenuate too much when

measuring high-frequency clock signals, and the amplitude of the measured waveform will become lower.

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Chapter 6 FPGA On-Chip RAM Read and Write Test Experiment

The experimental Vivado project is "ram_test".

RAM is a commonly used basic module in FPGA and can be widely used to cache data. It is also the core of ROM and FIFO.

This experiment will introduce how to use the RAM inside the FPGA and how to read and write data to the RAM through the program.

Experimental Principle

Xilinx has provided us with a RAM IP core in VIVADO. We only need to instantiate a RAM through the IP core and write and read the data stored

in the RAM according to the RAM read and write timing. In the experiment, we can observe the RAM read and write timing and the data read from the

RAM through the online logic analyzer ila integrated in VIVADO.

Create a Vivado project

Before adding RAM IP, create a new ram_test project, and then add RAM IP to the project as follows:

1) Click IP Catalog in the figure below, search for ram in the interface that pops up on the right, find Block Memory Generator, and double-click

Open.

2) Change Component Name to ram_ip, and under Basic, change Memory Type to Simple Dual Port

RAM, also known as pseudo dual-port RAM. Generally speaking, "Simple Dual Port RAM" is the most commonly used because it has two ports

with independent input and output signals.

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3) Switch to the Port A Options column and change the RAM bit width Port A Width to 16, which is the data width.

RAM depth Port A Depth is changed to 512. Depth refers to how much data can be stored in the RAM. Enable pin

Enable Port Type is changed to Always Enable.

4) Switch to Port B Options, change the RAM bit width Port B Width to 16, change the Enable Port Type to Always Enable, and of course, you

can also Use ENB Pin, which is equivalent to the read enable signal. Uncheck Primitives Output Register, which is to add registers to

the output data, which can effectively improve the timing, but the read

In many cases, do not enable this function and keep the data behind the address by one cycle.

Expect.

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5) In the Other Options column, unlike ROM, we don’t need to initialize the RAM data here. We can write it in the

program, so just configure the default and click OK.

6) Click “Generate” to generate RAM IP.

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RAM port definition and timing

The Simple Dual Port RAM module ports are described as follows:

Signal name direction illustrate

clka in
Port A Clock Input
wea in
Port A Enable
addra in
Port A address input
dina in
Port A Data Input
clkb in
Port B Clock Input
addrb in
Port B address input
doutb out
Port B Data input and output

The data writing and reading of RAM are operated according to the rising edge of the clock. Port A needs to be set high when writing data.

wea signal, providing both the address and the data to be written. The following figure is the timing diagram of input writing to RAM.

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RAM Write Timing

Port B cannot write data, but can only read data from RAM. As long as the address is provided, it is usually

In this case, valid data can be collected in the next cycle.

RAM Read Timing

Test program writing

Next, we will write a RAM test program. To test the function of RAM, we write a

A string of continuous data is written only once and read from port B. Use a logic analyzer to view the data. The code is as follows

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////
////////////
module ram_test(
input sys_clk_p, //system clock 200Mhz on
board
input sys_clk_n, //system clock 200Mhz on board
input rst_n //Reset signal, low level is valid
);

//-------------------------------------------------------------
reg [8:0] w_addr; //RAM PORTA write address
reg [15:0] w_data; //RAM PORTA write data
reg wea; //RAM PORTA enable
reg [8:0] r_addr; //RAM PORTB read address
wire [15:0] r_data; //RAM PORTB read data

wire clk ;

IBUFDS IBUFDS_inst (
.O(clk), // Buffer output
.I(sys_clk_p), // Diff_p buffer input (connect directly to top-level port)

.IB(sys_clk_n) // Diff_n buffer input (connect directly to top-level port)

);

//Generate RAM PORTB read address

always @(posedge clk or negedge rst_n)
begin
if(!rst_n)

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r_addr <= 9'd0;

else if (|w_addr) r_addr <= //w_addr bitwise OR, not equal to 0
r_addr+1'b1;
else
r_addr <= 9'd0;
end

//Generate RAM PORTA write enable signal

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
wea <= 1'b0;
else
begin
if(&w_addr) wea <= //The bits of w_addr are all 1, a total of 512 data are written, and the writing is completed
1'b0; else

wea <= 1'b1; //RAM write enable

end
end

//Generate the address and data written to RAM PORTA

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
w_addr <= 9'd0;
w_data <= 16'd1;
end
else
begin
if(wea) //RAM write enable is valid
begin if
(&w_addr) begin //The bits of w_addr are all 1, a total of 512 data are written, and the writing is completed

w_addr <= w_addr ; //Keep the address and data values and write RAM only once
w_data <= w_data ;
end
else
begin
w_addr <= w_addr + 1'b1;
w_data <= w_data + 1'b1;
end
end
end
end

//-------------------------------------------------------------
//Instantiate RAM
ram_ip ram_ip_inst (
(clk .clka // input clka
.wea (wea (w_addr // input [0 : 0] wea
.addra (w_data (clk // input [8 : 0] addra
.dina (r_addr // input [15 : 0] dina
.clkb (r_data // input clkb
.addrb // input [8 : 0] addrb
.doutb ); ), ), ), ), ), ),//),output
), [15 : 0] doublet

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//Instantiate ila logic analyzer

ila_0 ila_0_inst ( .clk
(clk ), .probe0 .probe1
(r_data ), (r_addr )

);

endmodule

In order to see the data value read from RAM in real time, we add the ila tool to observe the data of RAM PORTB

For more information on how to generate ila, please refer to the "PL's "Hello World" LED Experiment".

The program structure is as follows:

Binding Pins

##################Compress Bitstream########################### set_property

BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property PACKAGE_PIN AE5 [get_ports sys_clk_p] set_property

IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p]

create_clock -period 5.000 -name sys_clk_p -waveform {0.000 2.500} [get_ports sys_clk_p]

set_property PACKAGE_PIN AF12 [get_ports rst_n] set_property

IOSTANDARD LVCMOS33 [get_ports rst_n]

simulation

The simulation method refers to the "PL's "Hello World" LED experiment". The simulation results are as follows. From the figure, we can see that address 1 is written

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The data is 0002, and in the next cycle, that is, time 2, valid data is read out.

On-board verification

Generate bitstream and download the bit file to FPGA. Next, we use ila to observe the data read from RAM.

Is the data initialized by us?

In the Waveform window, set the r_addr address to 0 as the trigger condition. We can see that r_addr is constantly increasing from 0 to

1ff. As r_addr changes, r_data also changes. The data in r_data is exactly the 512 data we wrote into RAM. It should be noted here that when

a new address appears in r_addr, the data corresponding to r_data will be delayed by two clock cycles before it appears. The data appears

two clock cycles later than the address, which is consistent with the simulation results.

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Chapter 7 FPGA On-Chip ROM Test Experiment

The experimental Vivado project is "rom_test".

FPGA itself is SRAM architecture, after power off, the program will disappear, so how to use FPGA to realize a ROM? We can use the RAM

resources inside FPGA to realize ROM, but it is not a real ROM, but each time the power is turned on, the initialization value will be written into RAM.

This experiment will introduce how to use the ROM inside FPGA and the program to read the data of the ROM.

Experimental Principle

Xilinx has provided us with a ROM IP core in VIVADO. We only need to instantiate a ROM through the IP core.

The data stored in the ROM is read according to the ROM read timing. In the experiment, we can observe the ROM read timing and the data read

from the ROM through the online logic analyzer ila integrated in VIVADO.

Programming

7.2.1 Create ROM initialization file

Since it is a ROM, we must prepare the data for it in advance, and then when the FPGA is actually running, we directly

Just read the pre-stored data in these ROMs. The on-chip ROM of Xilinx FPGA supports initialization data configuration. As shown in the figure below,

we can create a file named rom_init.coe. Note that the suffix must be ".coe", and the name in front can be arbitrary.

The content format of the ROM initialization file is very simple, as shown in the figure below. The first line defines the data format, and 16

represents the ROM data format is hexadecimal. From line 3 to line 34, it is the initialization data of this 32*8bit ROM. Each line of numbers is followed

by a comma, and the last line of numbers ends with a semicolon.

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After writing rom_init.coe, save it. Next, we will start designing and configuring the ROM IP core.

7.2.2 Add ROM IP core

Before adding ROM IP, create a new project called rom_test, and then add ROM IP to the project. The method is as follows: 1)

Click IP Catalog in the figure below, search for rom in the pop-up interface on the right, find Block Memory Generator, and double-click

Open.

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2) Change the Component Name to rom_ip, and under the Basic column, change the Memory Type to Single Port ROM.

3) Switch to Port A Options, change the ROM Width to 8 and the ROM Depth to

Change Depth to 32, change Enable Port Type to Always, and cancel Primitives Output Register

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4) Switch to the Other Options column, check Load Init File, click Browse, and select the .coe file you created previously.

Piece.

5) Click OK and click Generate to generate the IP core.

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ROM test program writing

The ROM program design is very simple. In the program, we only need to change the address of the ROM at each clock, and the ROM will output the current

The internal storage data of the previous address is instantiated to observe the changes of address and data.

Down:

`timescale 1ns / 1ps

module rom_test(
input sys_clk_p, //system clock 200Mhz postive pin
reset, low level is effective //system clock 200Mhz negetive pin input sys_clk_n, //
input rst_n );

wire [7:0] rom_data; //ROM read data

reg [4:0] rom_addr; //ROM input address

wire sys_clk ;

IBUFDS IBUFDS_inst (
.O(sys_clk), // Buffer output
.I(sys_clk_p), // Diff_p buffer input (connect directly to top-level port)

.IB(sys_clk_n) // Diff_n buffer input (connect directly to top-level port)

);

//Generate ROM address to read data

always @ (posedge sys_clk or negedge rst_n)
begin

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if(!rst_n) rom_addr
<= 10'd0; else

rom_addr <= rom_addr+1'b1;

end //

Instantiate ROM
rom_ip rom_ip_inst (

.clka (sys_clk ), .addra //inoput clka //input

(rom_addr ), .douta (rom_data ) [4:0] addra //output [7:0] douta

); //Instantiate logic
analyzer ila_0
ila_m0 (
.clk (sys_clk), .probe0
(rom_addr), .probe1 (rom_data)

);

endmodule

Binding Pins

##################Compress Bitstream########################### set_property

BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property PACKAGE_PIN AE5 [get_ports sys_clk_p] set_property

IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p]

create_clock -period 5.000 -name sys_clk_p -waveform {0.000 2.500} [get_ports sys_clk_p]

set_property PACKAGE_PIN AF12 [get_ports rst_n] set_property

IOSTANDARD LVCMOS33 [get_ports rst_n]

simulation

The simulation results are as follows, which are in line with expectations. Like the RAM read data, the data also lags behind the address by one cycle.

On-board verification

Using address 0 as the trigger condition, we can see that the read data is consistent with the simulation.

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Chapter 8 FPGA On-Chip FIFO Read and Write Test Experiment

The experimental Vivado project is "fifo_test".

FIFO is a very important module in FPGA applications and is widely used in data caching and cross-clock domain data processing.

A good FIFO is the key to FPGA, and using FIFO flexibly is a necessary skill for an FPGA engineer. This chapter mainly introduces the use of FIFO IP

provided by XILINX for read and write testing.

Experimental Principle

FIFO: First in, First out means that the first-in data is first out, and the last-in data is last out. Xilinx has provided us with the FIFO IP core in VIVADO.

We only need to instantiate a FIFO through the IP core, and write and read the data stored in the FIFO according to the read and write timing of the FIFO. In

fact, FIFO also adds many

functions on the basis of RAM. The typical structure of FIFO is as follows. It is mainly divided into two parts: read and write. In addition, there are

status signals, empty and full signals, and data quantity status signals. The biggest difference from RAM is that FIFO has no address line and cannot read

data at random addresses. What is random data reading? That is, data at a certain address can be read at will. FIFO is different. It cannot be read randomly.

The advantage of this is that the address line does not need to be controlled frequently.

Although the user cannot see the address lines, there are still address operations inside the FIFO to control the read and write interfaces of the RAM.

The address of the FIFO is shown in the following figure during read and write operations, where the depth value is the maximum number of data that can be stored in a FIFO.

In the initial state, both the read and write addresses are 0. After a data is written into the FIFO, the write address is incremented by 1. After a data is read out

from the FIFO, the read address is incremented by 1. At this time, the FIFO state is empty because a data is written and a data is read out.

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You can think of FIFO as a pool. The write channel is to add water, and the read channel is to drain water. If you keep adding and draining water,

If the speed of adding water is faster than the speed of draining water, then the FIFO will be full. If you continue to add water when it is full, it will overflow. If

the speed of draining water is faster than the speed of adding water, then the FIFO will be empty. Therefore, it is a very difficult task to grasp the timing and

speed of adding and draining water to ensure that there is always water in the pool. That is, to judge the empty and full states and choose the right time to

write or read data.

According to the read and write clocks, it can be divided into synchronous FIFO (the read and write clocks are the same) and asynchronous FIFO (the read and write clocks are different).

FIFO control is relatively simple, so I will not introduce it here. This section mainly introduces the control of asynchronous FIFO, where the read clock is

75MHz and the write clock is 100MHz. In the experiment, we can observe the read and write timing of FIFO and the data read from FIFO through the logic

analyzer ila integrated in VIVADO.

Create a Vivado project

8.2.1 Add FIFO IP core

Before adding FIFO IP, create a new fifo_test project, and then add FIFO IP to the project as follows:

1) Click IP Catalog in the figure below, search for fifo in the interface that pops up on the right, find FIFO Generator, and double-click to open it.

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2) In the pop-up configuration page, you can choose to separate the read and write clocks or use the same one. Generally speaking, we use

FIFO to cache data, and the clock speeds on both sides are usually different. Therefore, independent clocks are the most commonly

used. Here we select "Independent Clocks Block RAM" and click "Next" to the next configuration page.

3) Switch to the Native Ports column, select 16 for data width and 512 for FIFO depth. You can set it according to your needs in actual

use. There are two Read Modes: Standard FIFO, which is the common FIFO, where the data lags behind the read signal by one

cycle, and First Word Fall Through, a data pre-fetch mode, referred to as FWFT mode. That is, FIFO will pre-fetch a data, and when

the read signal is valid, the corresponding data is also valid. Let's first do the standard FIFO experiment.

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4) Switch to the Data Counts column and enable Write Data Count (how much data has been written to the FIFO) and Read Data Count

(how much data can be read from the FIFO). In this way, we can use these two values to see how much data is inside the FIFO.

Click OK, Generate to generate the FIFO IP.

8.2.2 FIFO port definition and timing

Signal name direction illustrate

rst in
Reset signal, high effective

wr_clk in
Write clock input

rd_clk in
Read clock input
din in
Writing Data

wr_en in
Write enable, high effective

rd_en in
Read enable, high effective

dout out
Read Data

full
out Full signal

empty out empty signal

rd_data_count out The amount of readable data

wr_data_count out The amount of data written

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The writing and reading of data in FIFO are both operated on the rising edge of the clock. When the wr_en signal is high, the FIFO data is

written. When the almost_full signal is valid, it means that only one more data can be written into the FIFO. Once a data is written, the full signal will be

pulled high. If wr_en is still valid in the full case, that is, data continues to be written to the FIFO, then the overflow of the FIFO will be valid, indicating

an overflow.

Standard FIFO write timing

When the rd_en signal is high, read the FIFO data, and the data is valid in the next cycle. valid is the data valid signal, almost_empty means there is

one more data to read, when reading another data, the empty signal is valid, if you continue to read, underflow is valid, indicating underflow, and the data

read out at this time is invalid.

Standard FIFO read timing

From the FWFT mode data reading timing diagram, it can be seen that when the rd_en signal is valid, the valid data D0 is already on the data line.

Once it is ready to be effective, it will not be delayed for another cycle. This is the difference from the standard FIFO.

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FWFT FIFO Read Timing

For details about FIFO, please refer to the pg057 document, which can be downloaded from the Xilinx official website.

FIFO test program writing

We design it according to asynchronous FIFO and use PLL to generate two clocks, 100MHz and 75MHz respectively, for

Write clock and read clock, that is, the write clock frequency is higher than the read clock frequency.

`timescale 1ns / 1ps

module fifo_test
(
input sys_clk_p, //system clock 200Mhz postive pin
input sys_clk_n, //system clock 200Mhz negetive
pin
input rst_n //Reset signal, low level is valid
);

reg [15:0] wire w_data ; //FIFO write data

wr_en ; //FIFO write enable
wire rd_en ; //FIFO read enable
wire [15:0] r_data ; //FIFO read data
wire full ; //FIFO full signal
wire empty ; //FIFO empty signal
wire [8:0] wire rd_data_count ; //Number of readable data

[8:0] wr_data_count ; //The amount of data written

wire clk_100M ; //PLL generates 100MHz clock

wire clk_75M wire ; //PLL generates 100MHz clock
locked signal, high level means locked ; //PLL lock signal, can be used as system reset

wire fifo_rst_n ; //fifo reset signal, low level is effective

wire wr_clk ; //Write FIFO clock

wire rd_clk ; //Read FIFO clock
reg [7:0] reg wcnt ; //Write FIFO after reset wait counter
[7:0] rcnt ; //Read FIFO and wait for counter after reset

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//Instantiate PLL to generate 100MHz and 75MHz clocks

clk_wiz_0 fifo_pll
(
// Clock out ports
// output clk_out1
// output clk_out2
.clk_out1(clk_100M), .clk_out2(clk_75M), // Status and control signals
// input reset
// output locked
.reset(~rst_n), .locked(locked), // Clock in ports
// input clk_in1
// input clk_in1
.clk_in1_p(sys_clk_p), .clk_in1_n(sys_clk_n) );

assign fifo_rst_n ; //Assign = locked ; //Assign the PLL LOCK signal to the reset signal of the fifo
assign wr_clk = clk_100M =100MHz
clk_75Mclock
; // to write clock
assign rd_clk Assign 75MHz clock to read clock

/* Write FIFO state machine */

localparam W_IDLE =1 ;
localparam W_FIFO =2;

reg[2:0] write_state;
reg[2:0] next_write_state;

always@(posedge wr_clk or negedge fifo_rst_n)

begin
if(!fifo_rst_n)
write_state <= W_IDLE;
else
write_state <= next_write_state;
end

always@(*)
begin
case(write_state)
W_IDLE:
begin
if(wcnt == 8'd79) the //Wait for a certain period of time after reset, safety
slowest clock in circuit mode is 60 cycles
next_write_state <= W_FIFO;
else
next_write_state <= W_IDLE;
end
W_FIFO:
next_write_state <= W_FIFO; default: //Always writing FIFO status

next_write_state <= W_IDLE;

endcase
end
//In IDLE state, that is, after reset, the counter counts
always@(posedge wr_clk or negedge fifo_rst_n)
begin
if(!fifo_rst_n)
wcnt <= 8'd0;
else if (write_state == W_IDLE)
wcnt <= wcnt + 1'b1 ;
else
wcnt <= 8'd0;

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end
//In write FIFO state, if not full, write data to FIFO assign wr_en =
(write_state == W_FIFO) ? ~full : 1'b0; //When write enable is valid, add 1 to the write data value
always@(posedge wr_clk or negedge fifo_rst_n)
begin if(!fifo_rst_n) w_data <= 16'd1; else if (wr_en) w_data <= w_data + 1'b1;

end

/* Read FIFO state machine */

localparam R_IDLE =1 ;
localparam R_FIFO =2;
reg[2:0] read_state; reg[2:0]
next_read_state;

///Generate FIFO read data

always@(posedge rd_clk or negedge fifo_rst_n) begin if(!fifo_rst_n) read_state <=
R_IDLE;
else

read_state <= next_read_state;

end

always@(*)
begin
case(read_state)
R_IDLE:
begin if
(rcnt == 8'd59) //Wait for a certain period of time after reset,

In safety circuit mode, the slowest clock is 60 cycles. next_read_state

<= R_FIFO; else next_read_state <= R_IDLE;

end
R_FIFO:
next_read_state <= R_FIFO ; default: //Always reading FIFO status

next_read_state <= R_IDLE; endcase

end

//In IDLE state, that is, after reset, the counter counts
always@(posedge rd_clk or negedge fifo_rst_n) begin if(!fifo_rst_n) rcnt <= 8'd0;

else if (write_state == W_IDLE) rcnt <= rcnt + 1'b1 ; else

rcnt <= 8'd0;

end //

In read FIFO state, if it is not empty, read data from FIFO assign rd_en
= (read_state == R_FIFO) ? ~empty : 1'b0;

//-------------------------------------------------------------

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//Instantiate FIFO
fifo_ip fifo_ip_inst (

.rst (~fifo_rst_n ), // input rst

(wr_clk ), // input wr_clk
(rd_clk ), // input rd_clk
.wr_clk .rd_clk .din (w_data ), // input [15 : 0] din
(wr_en ), // input wr_en
(rd_en ), // input rd_en
.wr_en .rd_en .dout (r_data .full ), // output [15 : 0] dout
(full ), // output full
(empty ), // output empty
.empty .rd_data_count (rd_data_count), // output [8 : 0] rd_data_count
.wr_data_count (wr_data_count) // output [8 : 0] wr_data_count
);

//Write channel logic analyzer

ila_m0 ila_wfifo (
.clk(wr_clk),
.probe0(w_data),
.probe1(wr_en),
.probe2(full),
.probe3(wr_data_count)
);
//Read channel logic analyzer
ila_m0 ila_rfifo (
.clk(rd_clk),
.probe0(r_data),
.probe1(rd_en),
.probe2(empty),
.probe3(rd_data_count)
);

endmodule

In the program, the lock signal of PLL is used as the reset of fifo, and the 100MHz clock is assigned to the write clock.

75MHz clock is assigned to the read clock.

One thing to note is that the FIFO setting defaults to using the safety circuit. This function is to ensure that the data reaches the internal RAM.

The input signal is synchronous. In this case, if an asynchronous reset is performed, it is necessary to wait for 60 slowest clock cycles.

In the experiment, that is 60 cycles of 75MHz, so a 100MHz clock will require approximately (100/75)x60=80 cycles.

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Therefore, in the write state machine, wait for 80 cycles to enter the write FIFO state

In the read state machine, wait 60 cycles to enter the read state

If the FIFO is not full, keep writing data to the FIFO

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If the FIFO is not empty, keep reading data from the FIFO

Instantiate two logic analyzers and connect the signals of the write channel and the read channel respectively.

simulation

The following is the simulation result. It can be seen that after the write enable wr_en is valid, data starts to be written. The initial value is 0001. It takes

a certain period of time from the beginning of writing to the empty state, because internal synchronization processing is required. After the empty state is not empty,

data is read. The read data lags one cycle relative to rd_en.

You can see later that if the FIFO is full, according to the design of the program, no data will be written to the FIFO when it is full, and wr_en will be pulled

low. Why is it full? It is because the write clock is faster than the read clock. If the write clock and the read clock are swapped, that is, the read clock is faster, the

read will be empty. You can try it.

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If you change the FIFO Read Mode to First Word Fall Through

The simulation results are as follows. It can be seen that when rd_en is valid, the data is also valid, without a cycle difference.

On-board verification

Generate the bit file, download the bit file, and two ila will appear. Let's look at the write channel first. You can see that the full signal is high.

When the level is high, wr_en is low and no more data is written into it.

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The read channel is also consistent with the simulation

If the rising edge of rd_en is used as the trigger condition, click Run, then press Reset, which is the PL we bound

KEY1, the following result will appear, which is consistent with the simulation. In standard FIFO mode, the data lags behind rd_en by one cycle.

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Chapter 9 Vivado Keyboard Experiment

The experimental Vivado project is "key_test".

The button is the most commonly used and simplest peripheral in FPGA design. This chapter uses the button detection experiment to detect the development board.

Check whether the key functions are normal, understand the specific relationship between hardware description language and FPGA, and learn the use of Vivado RTL ANALYSIS.

use.

Button hardware circuit

AXU3EG/AXU4EV/AXU5EV development board button circuit

As can be seen from the figure, the circuit is at a high level when the button is released and at a low level when it is pressed.

AXU3EG/AXU4EV/AXU5EV development board LED part circuit and LED part, high

level lights up, low level turns off

Programming

This program is not designed to be complicated. It uses simple hardware description language to understand the hardware description language and FPGA hardware.

First, we pass the key input through a NOT gate and then through two sets of D flip-flops. The signal passing through the D flip-flop will be latched on the rising edge of the

D flip-flop clock input and then sent to the output.

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First level Second level

Key input
Reverse D trigger D trigger led
Device Device

Clock Input

Before coding in hardware description language, we have already built the hardware, which is a normal development process.

The hardware design idea can be completed by drawing, Verilog HDL or VHDL.

Choose a tool based on the program and familiarity with a language.

Create a Vivado project

1) First, create a button test project, add Verilog test code, and complete the compilation and pin allocation processes.

`timescale 1ns / 1ps

module key_test
(
input sys_clk_p, //system clock 200Mhz
postive pin
input sys_clk_n, //system clock 200Mhz
negative pin input
key, keydown, the value is 0 //input four key signal,when the

output led lighten //LED display ,when the siganl low,LED

);

reg led_r; //define the first stage register, generate four

D Flip-flop reg
led_r1; //define the second stage register,generate four
D Flip-flop

wire clk ;

IBUFDS IBUFDS_inst (
.O(clk), // Buffer output
.I(sys_clk_p), // Diff_p buffer input (connect directly to top-

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level port)
.IB(sys_clk_n) // Diff_n buffer input (connect directly to top-level port) );

always@(posedge clk) begin

led_r
<= ~key; //first stage latched data
end

always@(posedge clk) begin led_r1

<= led_r;
end //second stage latched data

assign led = led_r1;

endmodule

2) We can use the RTL ANALYSIS tool to view the design

3) Analyzing the RTL diagram, we can see that the first-stage D flip-flop is input after inversion, and the second-stage is directly input, which is the same as the expected design.

To.

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On-board verification

After the Bit file is downloaded to the development board, the "PL LED" on the development board is off. Press the "PL KEY" button to turn on the "PL LED".

The LED is on.

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Chapter 10 PWM Breathing Light Experiment

The experimental Vivado project is "pwm_led".

This article mainly explains how to use PWM to control LED to achieve the effect of breathing light.

Experimental Principle

As shown in the figure below, using an N-bit counter, the maximum value can be expressed as 2 to the power of N, and the minimum value is 0.

The accumulation is performed with "period" as the step value. When the maximum value is reached, it will overflow and enter the next accumulation cycle.

When the pulse is on duty, the pulse output is high, otherwise the output is low, so that the pulse duty cycle can be adjusted as shown by the red line in the figure.

Pulse output, while "period" can adjust the pulse frequency, which can be understood as the step value of the counter.

PWM pulse width modulation diagram

When the square wave output with different pulse duty ratios is added to the LED, the LED light will show different brightness.

The duty cycle of the square wave is adjusted to adjust the brightness of the LED lamp.

Experimental design

The PWM module design is very simple, which has been explained in the above principle, so I will not explain the principle here.

Signal Name Direction illustrate

clk
in Clock input

rst
in Asynchronous reset input, high reset

period in
PWM Pulse Width Period (Frequency) Control. period = PWM output frequency

rate*(2 to the power of N)/system clock frequency. Obviously, the larger N is, the higher the frequency will be.

The higher the rate accuracy.

duty
In duty cycle control, duty cycle = duty / (2 to the power of N) * 100%

PWM module (ax_pwm) ports

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`timescale 1ns / 1ps module ax_pwm

#(

parameter N = 16 //pwm bit width

)(

input clk, rst,

input
input[N - 1:0]period,//pwm step value //duty value input[N - 1:0]duty,
output ); output pwm_out //pwm

reg[N - 1:0] period_r; reg[N - 1:0] duty_r; //period register //duty register
reg[N - 1:0] period_cnt; //period counter
reg pwm_r; assign pwm_out = pwm_r; always@(posedge clk or posedge rst)
begin if(rst==1)
begin period_r <= { N {1'b0} }; duty_r <= { N
{1'b0} }; end

else
begin
period_r <= period; duty_r <= duty;
end

end
//period counter, step is period value always@(posedge clk or posedge rst)
begin if(rst==1) period_cnt <= { N {1'b0} }; else

period_cnt <= period_cnt + period_r;

end

always@(posedge clk or posedge rst) begin if(rst==1) begin pwm_r

<= 1'b0;
end

else

begin
if(period_cnt >= duty_r) //if period counter is bigger or equals to duty value, then set pwm value to high pwm_r <=
1'b1; else pwm_r <= 1'b0;

end
end

So how do we achieve the effect of breathing light? We know that the effect of breathing light is that it changes from dark to bright, and then from bright to dark.

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The process of light and dark, and the light and dark effect is adjusted by the duty cycle, so we mainly control the duty cycle, that is, control the duty

The value of .

In the following test code, by setting the value of period, the PWM frequency is set to 200Hz, and the PWM_PLUS state is

The duty value is increased. If it reaches the maximum value, pwm_flag is set to 1 and the duty value is reduced.

The minimum value starts to increase the duty value and the cycle continues. The PWM_GAP state is the adjustment interval, and the time is 100us.

`timescale 1ns / 1ps

module pwm_test(
input sys_clk_p, //system clock
200Mhz postive pin
input sys_clk_n, //system
clock 200Mhz negetive pin input rst_n, output
led ); localparam CLK_FREQ = //low active
200 ; //high-on, low-off

//200MHz
localparam US_COUNT = CLK_FREQ ; //1 us counter
localparam MS_COUNT = CLK_FREQ*1000 ; //1 ms counter

localparam DUTY_STEP = 32'd100000 ; //duty step

localparam DUTY_MIN_VALUE = 32'h6fffffff ; localparam //duty minimum value
DUTY_MAX_VALUE = 32'hffffffff ; //duty maximum value

localparam IDLE = 0; //IDLE state

localparam PWM_PLUS = 1; //PWM duty plus state
localparam PWM_MINUS = 2; //PWM duty minus state
localparam PWM_GAP = 3; //PWM duty adjustment gap

wire pwm_out; //pwm output

reg[31:0] period; reg[31:0] //pwm step value
duty; //duty value
pwm_flag ; //duty value plus and minus flag, 0: plus; 1: reg minus

reg[3:0] state;
reg[31:0] timer; //duty adjustment counter

assign led = pwm_out ; //led high active

wire clk ;

IBUFDS IBUFDS_inst (
.O(clk), // Buffer output
.I(sys_clk_p), // Diff_p buffer input (connect directly to top-level port)

.IB(sys_clk_n) // Diff_n buffer input (connect directly to top-level port)

);

always@(posedge clk or negedge rst_n)

begin
if(rst_n == 1'b0)
begin
period timer <= 32'd0;
<= 32'd0;
duty <= 32'd0;
pwm_flag <= 1'b0 ;
state <= IDLE;
end

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else
case(state)
IDLE:
begin
period <= 32'd17179; //The pwm step value, pwm
200Hz(period = 200*2^32/50000000) state
<= PWM_PLUS;
duty <= DUTY_MIN_VALUE;
end
PWM_PLUS :
begin if
(duty > DUTY_MAX_VALUE - DUTY_STEP) //if duty is bigger than DUTY MAX VALUE minus
DUTY_STEP , begin to minus duty value begin pwm_flag <= 1'b1 ; duty <= duty - DUTY_STEP ; end

else
begin
pwm_flag <= 1'b0 ; duty <= duty +
DUTY_STEP ;
end

state <= PWM_GAP ;

end
PWM_MINUS :
begin if
(duty < DUTY_MIN_VALUE + DUTY_STEP) //if duty is
little than DUTY MIN VALUE plus duty step, begin to add duty value begin pwm_flag <= 1'b0 ; duty

<= duty + DUTY_STEP ;

end
else
begin
pwm_flag <= 1'b1 ; duty <= duty -
DUTY_STEP ; end

state <= PWM_GAP ;

end
PWM_GAP:
begin
if(timer >= US_COUNT*100) begin if (pwm_flag) //adjustment gap is 100us
state <=
PWM_MINUS ; else
state <= PWM_PLUS ;

timer <= 32'd0;

end
else
begin
timer <= timer + 32'd1;
end
end
default:
begin
state <= IDLE;
end
endcase

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end

//Instantiate pwm module ax_pwm #( .N(32) )

ax_pwm_m0( .clk

(clk),
.rst (~rst_n), .period
(period), .duty (duty), .pwm_out
(pwm_out) ); endmodule

Download Verification

Generate bitstream and download bit file, you can see the PL LED light produces breathing light effect. PWM is a commonly

used module, such as fan speed control, motor speed control and so on.

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Chapter 11 UART Experiment

The experimental Vivado project is "rs232_test".

This chapter uses the UART interface circuit on the PL side of the development board to implement UART data transmission.

Programming

The serial port described in this article refers to asynchronous serial communication, and asynchronous serial refers to UART (Universal

Asynchronous Receiver/Transmitter), universal asynchronous reception/transmission. This experimental program is designed to send "HELLO ALINX" to the serial

port every second. If the data received by RXD is received, the received data will be sent out to realize the loopback function.

FPGA

RxD
UART Receive

Program
USB Serial Port
USB to Serial CP2102
UART control
chip
program

TXD UART Transmitter

Program

11.1.1 Asynchronous Serial Communication Protocol

The message frame starts with a low start bit, followed by 7 or 8 data bits, an optional parity bit and one or more

When the receiver sees the start bit it knows that data is ready to be sent and tries to synchronize with the transmitter clock frequency.

If parity is selected, the UART adds a parity bit after the data bits. The parity bit can be used to assist in error detection.

During this process, the UART removes the start and end bits from the message frame, performs a parity check on the incoming bytes, and sends the data bytes out of the

Serial to parallel conversion. UART transmission timing is shown in the figure below:

From the waveform, we can see that the start bit is low level, the stop bit and the idle bit are both high level, which means there is no data transmission.

When it is high level, we can use this feature to receive data accurately. When a falling edge event occurs, we think that it will enter

Perform a data transmission.

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11.1.2 Baud Rate

Common serial communication baud rates include 2400, 9600, 115200, etc. The sending and receiving baud rates must be consistent.

Correct communication. Baud rate refers to the maximum number of data bits transmitted in 1 second, including start bit, data bit, check bit, and stop bit.

If the communication baud rate is set to 9600, then the duration of a data bit is 1/9600 seconds. The baud rate in this experiment is

50MHz clock generation.

11.1.3 Receiving Module Design

The serial port receiving module uart_rx is a parameterized configurable module. The parameter "CLK_FRE" defines the system clock of the receiving module.

Frequency, the unit is Mhz, parameter "BAUD_RATE" is the baud rate. The state transition diagram of the receiving state machine is as follows:

The "S_IDLE" state is the idle state. After power-on, it enters "S_IDLE". If the signal "rx_pin" has a falling edge, we

It is considered as the start bit of the serial port and enters the state "S_START". After a BIT time, the start bit ends and enters the data bit receiving state.

The data bit design in this experiment is 8 bits. After receiving, it enters the "S_STOP" state.

"S_STOP" does not wait for a BIT cycle, Only waited half a BIT time , this is because if you wait for one cycle,

It is possible to miss the start bit judgment of the next data, and finally enter the "S_DATA" state, sending the received data to other

Module. In this module, we mention one thing: in order to satisfy the sampling theorem, each data is received in the baud rate counter

Sampling is performed at the midpoint of time to avoid data errors:

//receive serial data bit data

always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
rx_bits <= 8'd0;
else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
rx_bits[bit_cnt] <= rx_pin;
else
rx_bits <= rx_bits;
end

Notice: .
There is no parity bit in this experiment

Signal Name Direction Width illustrate

(bit)
clk in
1 System clock

rst_n in
1 Asynchronous reset, low level reset

rx_data out
8 Received serial port data (8-bit data)

rx_data_valid out
1 The received serial port data is valid (high effective)

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rx_data_ready in
1 means the user can receive data from the receiving module.

When rx_data_ready and rx_data_valid are both high, the data

Send

rx_pin in
1 Serial port receives data input

Serial port receiving module uart_rx port

11.1.4 Sending module design

The design of the sending module uart_tx is similar to that of the receiving module, and it also uses a state machine. The state transition diagram is as follows:

After power-on, it enters the "S_IDLE" idle state. If there is a send request, it enters the send start bit state "S_START".

After the start bit is sent, it enters the send data bit state "S_SEND_BYTE", and after the data bit is sent, it enters the send stop bit state

"S_STOP", after the stop bit is sent, it enters the idle state. In the data sending module, the data written from the top module

Directly pass to register 'tx_reg', and simulate the conditional transition of the serial port transmission protocol in the state machine through the 'tx_reg' register

Data transmission is performed as follows:

always@(posedge clk or negedge rst_n)

begin
if(rst_n == 1'b0)
tx_reg <= 1'b1;
else
case(state)
S_IDLE,S_STOP:
tx_reg <= 1'b1;
S_START:
tx_reg <= 1'b0;
S_SEND_BYTE:
tx_reg <= tx_data_latch[bit_cnt];
default:
tx_reg <= 1'b1;
endcase
end

Signal Name Direction Width illustrate

(bit)
clk in
1 System clock

rst_n in
1 Asynchronous reset, low level reset

tx_data in 8
Serial port data to be sent (8-bit data)

tx_data_valid in
1 The serial port data sent is valid (high effective)

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tx_data_ready out
1 The sending module is ready to send data. The user can

tx_data_valid signal is pulled high to send data to the

sending module. When tx_data_ready and tx_data_valid are both

high, data is sent 1

tx_pin out
Serial port sends data

Serial port sending module uart_tx port

11.1.5 Baud rate generation

In the sending and receiving modules, the parameter CYCLE is declared, which is the count value of one cycle of UART. Of course, the count is

It is performed under 50MHz clock. The user only needs to set the two parameters CLK_FRE and BAUD_RATE.

11.1.6 Test Procedure

The test program is designed to send "HELLO ALINX\r\n" to the serial port once every 1 second. If it receives

Serial port data directly sends the received data to the sending module and then returns. "\r\n" here is consistent with the C language, both are carriage

return and line feed. The

test program instantiates the sending module and the receiving module respectively, and passes the parameters in. The baud rate is set to

115200.

always@(posedge sys_clk or negedge rst_n) begin

if(rst_n
== 1'b0) begin

wait_cnt <= 32'd0; tx_data <=

8'd0; state <= IDLE;
tx_cnt <= 8'd0;
tx_data_valid <=
1'b0;
end
else
case(state)
IDLE:
state <= SEND;
SEND:
begin

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wait_cnt <= 32'd0;

tx_data <= tx_str;

if(tx_data_valid == 1'b1 && tx_data_ready == 1'b1 && tx_cnt < 8'd12)//Send 12 bytes
data
begin
tx_cnt <= tx_cnt + 8'd1; //Send data counter
end
else if(tx_data_valid && tx_data_ready)//last byte sent is complete begin tx_cnt <= 8'd0;

tx_data_valid <= 1'b0; state

<= WAIT;

end
else if(~tx_data_valid) begin

tx_data_valid <= 1'b1;

end
end
WAIT:
begin
wait_cnt <= wait_cnt + 32'd1;

if(rx_data_valid == 1'b1) begin

tx_data_valid <= 1'b1; tx_data <=

rx_data; // send uart received data
end
else if(tx_data_valid && tx_data_ready) begin

tx_data_valid <= 1'b0;

end
else if(wait_cnt >= CLK_FRE * 1000000) // wait for 1 second state <= SEND;

end
default:
state <= IDLE;
endcase
end

//combinational logic
//Send "HELLO ALINX\r\n"
always@(*)
begin
case(tx_cnt)
8'd0 : tx_str <= "H"; 8'd1 :
tx_str <= "E"; 8'd2 : tx_str
<= "L"; 8'd3 : tx_str <= "L";
8'd4 : tx_str <= "O"; 8'd5 :
tx_str <= " "; 8'd6 : tx_str <=
"A"; 8'd7 : tx_str <= "L";
8'd8 : tx_str <= "I"; 8'd9 :
tx_str <= "N"; 8'd10: tx_str
<= "X"; 8'd11: tx_str <= "\r";
8'd12: tx_str <= "\n";
default:tx_str <= 8'd0; endcase

end
uart_rx# (

.CLK_FRE(CLK_FRE), .BAUD_RATE(115200) ) uart_rx_inst

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(
.clk (sys_clk ),
(rst_n ),
(rx_data ),
(rx_data_valid ),
(rx_data_ready ),
.rst_n .rx_data .rx_data_valid .rx_data_ready
(uart_rx
.rx_pin )
);

uart_tx#
(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(115200)
) uart_tx_inst
(
(sys_clk ),
(rst_n ),
(tx_data ),
(tx_data_valid ),
(tx_data_ready ),
(uart_tx
.clk .rst_n .tx_data .tx_data_valid .tx_data_ready .tx_pin )
);

simulation

Here we add a serial port receiving stimulus program vtf_uart_test.v file to simulate uart serial port receiving.

Here, the data 0xa3 is sent to the uart_rx of the serial port module. Each bit of data is sent at a baud rate of 115200, starting with bit 1.

bits, 8 data bits and 1 stop bit.

The simulation results are as follows: when the program receives 8 bits of data, rx_data_valid is valid, and the data of rx_data[7:0] is

Position a3.

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Experimental testing

Connect the PL_UART interface to the computer via USB

Find the serial port number "COM5" in the device manager

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Open the serial port debugging, select "COM79" as the port (select according to your own situation), set the baud rate to 115200, and check the bit

Select None, select 8 for data bits, select 1 for stop bits, and then click "Open Serial Port". This software is in the example folder.

After opening the serial port, you can receive "HELLO ALINX" every second. Enter the text you want to send in the sending area input box, click

"Manual Send", and you can see that the characters you sent are received.

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Chapter 12 RS485 Experiment

The experimental Vivado project is "rs485_test".

This chapter introduces RS485 data transmission using the AN3485 module.

Experimental Principle

In the previous UART experiment, RS485 uses differential signal transmission, but RS485 is half-duplex transmission, that is, data can only be transmitted

in one direction at the same time. There are only differential signals A and B, and the signals connected to ARM or FPGA are DE (direction selection), DI (input signal

TXD), and RO (output signal RXD).

From the MAX3485 document, the sending direction, if DE is 1, that is, output enable, DI value is 1, for

The differential signals A and B have values of 1 and 0, otherwise they are 0 and 1.

From the receiving point of view, if DE is 0 and the difference between A and B is greater than or equal to +0.2V, the RO value is 1, otherwise it is 0.

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Programming

Since RS485 is half-duplex transmission, we need to formulate a transmission protocol for handshake. Set the first byte to 8'h55,

indicating the beginning of a frame of data, followed by the length of the transmitted data. Due to the FIFO size limit (256), the range is 1~255,

followed by the data. The format is: start 8'h55+data length+data.

uart_tx and uart_rx are the same as the UART experiment, so here we only need to modify uart_test.

In the initial state, DE is set to 0, that is, input, waiting to receive data sent by the host computer and cache it in FIFO. The FIFO size is set to

256, and then switch DE to 1, that is, output, read the received data from FIFO and send it out. Note that the cached data is minus the starting 8'h55

and quantity information. In the RCV_HEAD state, determine whether the received data

is "S".

In the RCV_COUNT state, if the data length is less than 0, it jumps to the IDLE state; if it is greater than 0, it enters the

Receive data status.

In the RCV_DATA state, write the data into the FIFO, check the data length, and switch the direction of RS485 to output.

And jump state.

When switching bus states, in order to ensure reliable operation, in the WAIT state, a delay of 1ms is applied to switch the direction.

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Then the data in the FIFO is sent. The SEND_WAIT state controls the read enable signal fifo_rden and determines the data

After sending, it will enter the IDLE state.

Experimental testing

We use a USB to serial device to connect the A and B of RS485_1 to the A and B of the device respectively through Dupont cables.

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Open the serial port tool, set the serial port number and baud rate, select hexadecimal transmission, and send data starting with 8'h55. Click

Send, and you can see the returned data in the receiving window.

On this basis, another interface can be tested.

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Chapter 13 PL-side DDR4 read and write test experiment

The experimental VIvado project is "pl_ddr4_test".

Hardware Introduction

The PL side of the development board has a 16-bit DDR4, which greatly facilitates us to migrate the previous FPGA project to the ZYNQ system.

system, while also providing greater bandwidth.

Vivado Project Creation

13.2.1 Create a PL-side DDR4 test project and configure the DDR4 IP

1) Search for "mig" in the search box of "IP Catalog" and quickly find "Memory Interface Generator".

hit

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2) Component Name can be modified, Controller/PHY Mode select "Controller and physical layer",

Select 200MHz for reference clock, i.e. 5003ps, select "MT40A512M16HA-083E" for Mother Part, and select "MT40A512M16HA-083E" for Data

Select 16 for Width, keep other settings as default, and click OK

3) Generate

4) The generated results are as follows

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13.2.2 Adding other test code

The main function of other codes is to read and write ddr3 and compare whether the data is consistent. I will not go into details here. Please refer to the engineering code

code.

Add mark_debug debugging in mem_test.v. For the specific operation process, please refer to PL's "Hello World" LED experiment

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Download and debug

After the bit file is generated, use JTAG to download it to the development board. The MIG_1 window will display DDR4 calibration information.

In hw_ila_1 you can view the debug signal

Experimental Summary

This experiment uses the PL-side Verilog code to directly read and write ddr4. We can also configure ddr4 as an AXI interface.

Then complete data interaction with the ARM system.

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Chapter 14 HDMI Output Experiment

The experimental VIvado project is "hdmi_out_test".

Earlier, we introduced the LED flashing experiment, just to understand the basic development process of Vivado.

The LED flash experiment is more complicated. It makes a color bar for HDMI output, which is also the basis for our later study of display and video

processing. The experiment does not involve the PS system. From the experimental design, it can be seen that if you want to use the ZYNQ chip very well,

you need a good basic knowledge of FPGA.

Hardware Introduction

Since the development board only has DP for display, but it is on the PS side, and the PL side does not have an HDMI interface, we use

The HDMI expansion module of AN9134 realizes HDMI display. It encodes 24-bit RGB and outputs TMDS differential signals. SIL9134 has powerful

functions, and this experiment only uses a small part of it to display RGB24 video data.

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SI9134 chip needs to configure registers through I2C bus to work properly. From the schematic diagram, we can see that I2C bus connection

The IO connected to the PL side can be directly configured through the PL.

Programming

video_clk
8-bit R data Tmds_data0_p/n

sys_clk video_clk
video_pll 8-bit G data

color_bar Tmds_data1_p/n
8-bit B data

clk_100MHz HS/VS/DE
SI9134
Tmds_data2_p/n

SCL
lut_data Tmds_clk_p/n
i2c_config SDA
Lut_si9134 lut_index

This experiment realizes the display of color bars through HDMI. The video timing generation and color bar generation modules are designed in the experiment.

"color_bar.v", I2C Master register configuration module "i2c_config.v", configuration data lookup table module "lut_si9134.v".

The specific codes are not introduced here one by one, you can go and see them yourself.

A brief introduction:

The top-level module top.v is the top-level file of the project, which mainly instantiates four sub-modules (clock module vidio_pll, color bar generator

It is composed of module color_bar, I2C configuration module i2c_config and configuration lookup table module lut_si9134.

The color bar generation module color_bar.v generates 8 colors of VGA format color bars, namely white, yellow, cyan,

Green, purple, red, blue and black. Generates color bars with a resolution of 1920x1080 and a refresh rate of 60Hz, which is the so-called 1080P high-

definition video image. Therefore, this module will output R (8 bits) G (8 bits) B (8 bits) image signals, row synchronization, column synchronization and

data valid signals. The clock

module video_pll calls a clock IP provided by Xilinx, which generates a

100Mhz clock and a 1080P pixel clock of 148.5Mhz. To generate the clock IP, click IP Catalog under the Project Manager directory, and then select FPGA

Features and Design->Clocking->Clocking Wizard icon.

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Add XDC constraint file

Add the following xdc constraint file to the project, and add clock and HDMI related pins in the constraint file.

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

############# clock define################# create_clock
-period 5.000 [get_ports sys_clk_p] set_property
PACKAGE_PIN AE5 [get_ports sys_clk_p] set_property
IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p]

set_property PACKAGE_PIN H12 [get_ports hdmi_clk] set_property

PACKAGE_PIN G13 [get_ports {hdmi_d[0]}] set_property
PACKAGE_PIN H13 [get_ports {hdmi_d[1]}] set_property
PACKAGE_PIN H14 [get_ports {hdmi_d[2]}] set_property
PACKAGE_PIN J14 [get_ports {hdmi_d[3]}] set_property
PACKAGE_PIN K14 [get_ports {hdmi_d[4]}] set_property
PACKAGE_PIN J12 [get_ports {hdmi_d[5]}] set_property
PACKAGE_PIN L13 [get_ports {hdmi_d[6]}] set_property
PACKAGE_PIN L14 [get_ports {hdmi_d[7]}] set_property
PACKAGE_PIN C13 [get_ports {hdmi_d[8]}] set_property
PACKAGE_PIN C14 [get_ports {hdmi_d[9]}] set_property
PACKAGE_PIN A14 [get_ports {hdmi_d[10]}] set_property
PACKAGE_PIN B14 [get_ports {hdmi_d[11]}] set_property
PACKAGE_PIN A13 [get_ports {hdmi_d[12]}] set_property
PACKAGE_PIN B13 [get_ports {hdmi_d[13]}] set_property
PACKAGE_PIN E13 [get_ports {hdmi_d[14]}] set_property
PACKAGE_PIN E14 [get_ports {hdmi_d[15]}] set_property
PACKAGE_PIN F11 [get_ports {hdmi_d[16]}] set_property
PACKAGE_PIN F12 [get_ports {hdmi_d[17]}] set_property
PACKAGE_PIN A11 [get_ports {hdmi_d[18]}]

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set_property PACKAGE_PIN A12 [get_ports {hdmi_d[19]}]

set_property PACKAGE_PIN C12 [get_ports {hdmi_d[20]}]
set_property PACKAGE_PIN D12 [get_ports {hdmi_d[21]}]
set_property PACKAGE_PIN F10 [get_ports {hdmi_d[22]}]
set_property PACKAGE_PIN G11 [get_ports {hdmi_d[23]}]
set_property PACKAGE_PIN F13 [get_ports hdmi_de]
set_property PACKAGE_PIN G15 [get_ports hdmi_hs]
set_property PACKAGE_PIN G14 [get_ports hdmi_vs]
set_property PACKAGE_PIN B10 [get_ports hdmi_scl]
set_property PACKAGE_PIN C11 [get_ports hdmi_sda]
set_property PACKAGE_PIN D14 [get_ports hdmi_nreset]

set_property IOSTANDARD LVCMOS33 [get_ports hdmi_scl]

set_property IOSTANDARD LVCMOS33 [get_ports hdmi_sda]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_d[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_clk]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_de]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_vs]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_hs]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_nreset]

set_property PULLUP true [get_ports hdmi_scl]

set_property PULLUP true [get_ports hdmi_sda]

set_property SLEW FAST [get_ports {hdmi_d[*]}]

set_property DRIVE 8 [get_ports {hdmi_d[*]}]
set_property SLEW FAST [get_ports hdmi_clk]
set_property SLEW FAST [get_ports hdmi_de]
set_property SLEW FAST [get_ports hdmi_hs]
set_property SLEW FAST [get_ports hdmi_scl]
set_property SLEW FAST [get_ports hdmi_sda]
set_property SLEW FAST [get_ports hdmi_vs]

Download and debug

Save the project and compile to generate a bit file, connect the HDMI module to the J45 expansion port, and connect the HDMI interface to the HDMI display.

Please note that 1920x1080@60Hz is used here, please make sure your monitor supports this resolution.

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Hardware connection diagram (J45 expansion port)

After downloading, the monitor displays the following image

Experimental Summary

This experiment is a preliminary contact with video display and video knowledge, which is not the focus of Zynq learning, so it is not

introduced in detail, but Zynq is widely used in the field of video processing, and learners need to have a good basic knowledge. In the experiment,

only PL is used to drive the HDMI chip, including I2C register configuration. Of course, it is more appropriate to use PS to configure I2C.

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Chapter 15 HDMI Character Display Experiment

The experimental Vivado project is "hdmi_char".

In the HDMI output experiment, the HDMI display principle and display mode were explained. This experiment introduces how to use FPGA to realize digital

Through this experiment, we can have a deeper understanding of HDMI display mode.

Experimental Principle

The experiment uses a character conversion tool to convert characters into hexadecimal coe files and stores them in a single-port ROM IP core.

The converted data is read out from the ROM and displayed on the HDMI.

Programming

The character display routine adds an osd_display module based on the HDMI display.

It is used to read the converted character information stored in the Rom ip core and display it in the specified area. The program flowchart is shown below:

osd_display
8-bit R data 8-bit R data Tmds_data0_p/n

sys_clk video_clk
video_pll 8-bit G data timing_gen 8-bit G data
_xy
color_bar Tmds_data1_p/n
8-bit B data 8-bit B data

HS/VS/DE HS/VS/DE
clk_100MHz osd_rom SI9134
video_clk Tmds_data2_p/n
video_clk

SCL
lut_data Tmds_clk_p/n
i2c_config SDA
lut_si9134 lut_index

1) In the "timing_gen_xy" module, two counters "x_cnt" and "y_cnt" are defined according to the HDMI timing standard and are

These two counters generate the "x" and "y" coordinates of the HDMI display. The program uses "vs_edge" and "de_falling"

They represent the field synchronization start signal and the data valid end signal respectively. The principle is shown in the figure below:

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Signal name direction illustrate

rst_n in
Asynchronous reset input, low reset

clk in
External clock input

i_hs in
Line sync signal

i_vs in
Field sync signal

i_de in
Data valid signal

i_data in
color_bar data

o_hs out Output line synchronization signal

o_vs out Output field synchronization signal

o_de out Output data valid signal

o_data out Output data

x
out generates the X coordinate

y out generates the Y coordinate

timing_gen_xy module ports

2) The following describes how to store text information in ROM IP. First, you need to generate a .coe file that can be recognized by XILINX FPGA.

First, find the "FPGA Font Extraction" tool in the project folder.

Double-click the .exe file to open the tool

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Enter the characters you want to display in the "Character Input" box of the extraction tool. The font and character height can be customized.

After the settings are completed, click the "Convert" button. You can see the converted character dot matrix size, dot matrix width and height in the lower left corner of the interface.

It is necessary to use it in the program

The width and height of the dot matrix are 144x32 here, which needs to be consistent with the definition in the osd_display program:

Click the "Save" button to save the file to the source file directory of this example. It should be noted that the save type should be

Select Xilinx (*.coe) and click the “Save” button.

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Find the generated .coe file and open it, and you can see the following:

The process of calling the single-port ROM IP core has been introduced in the previous ROM usage. Set it to Single Port ROM

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In the PortA Options tab, set the following:

Add the osd.coe file as shown below (find the coe file generated earlier), and click the "OK" button when completed:

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3) The osd_display module includes the timing_gen_xy module and the osd_rom module. The character data stored in osd_rom, such as

If the data is 1, the OSD area displays the foreground red in the ROM (displaying ALINX core station), if the data is 0, OSD

The area showing data is the background color (color bar).

Set the area valid signal, that is, the characters are displayed in this area, the starting coordinates are set to (9, 9), and the area size can be

According to the locale set by the character generation tool.

Many people may not understand why the ROM read address is [15:3], which means that it takes eight clock cycles to read one.

This is because one dot of a character represents only 1 bit, and the storage data width of ROM is 8 bits, so eight cycles are needed.

Periodically take out a data and compare the value of each bit, converting a character point into a pixel on the image.

Signal name direction illustrate

rst_n in
Asynchronous reset input, low reset

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pclk in
External clock input

i_hs in
Line sync signal

i_vs in
Field sync signal

i_de in
Data valid signal

i_data in
color_bar data

o_hs out Output line synchronization signal

o_vs out Output field synchronization signal

o_de out Output data valid signal

o_data out Output data

osd_display module ports

Experimental phenomenon

Connect the development board and the display. For the connection method, refer to the "HDMI Output Experiment" tutorial. Note that the various

Do not hot-swap the connectors while they are powered on. After downloading the experimental program, you can see the display showing characters with a color bar as the background.

The board is used as an HDMI output device and can only be displayed through an HDMI display device. Do not try to use the HDMI of a laptop.

The interface is used for display, because the notebook is also an output device.

The default character display position is at coordinates (9, 9). In addition, users can modify the following pos_y and pos_x judgments

Conditions to display characters anywhere on the display:

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Chapter 16 7-inch LCD display experiment

The experimental Vivado project is "lcd7_test".

Based on the HDMI output experiment, this chapter introduces the display of 7-inch LCD screen.

Hardware Introduction

AN970 LCD touch screen module consists of TFT LCD screen, capacitive touch screen and driver board. For details, please refer to

AN970 User Manual. The actual photos of AN970 are as follows:

Programming

The experiment in this chapter is actually very simple. The biggest difference from HDMI display is that it does not require i2c configuration and the output can be RGB.

Following is the file structure.

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At the same time, because the resolution of the LCD screen is 800x480, the macro definition of video_define.v needs to be modified.

At the same time, the output clock frequency of the PLL is modified to 33MHz, which is the pixel clock of 800x480.

At the same time, ax_pwm is instantiated in top.v to adjust the brightness of the LCD screen, which is set to 200Hz and 30% dot-to-space ratio.

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Experimental phenomenon

Connect the LCD screen to the J45 expansion port, download the program, and you can see the color bar display.

At the same time, a character display routine is also prepared:

Character Display

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Chapter 17 AD7606 Multi-channel Waveform Display Experiment

The experimental Vivado project is "ad7606_hdmi_test".

This experiment uses ADC. The ADC module model used in the experiment is AN706, with a maximum sampling rate of 200Khz and an accuracy of

16 bits. In the experiment, the two inputs of AN706 are displayed on HDMI in the form of waveforms. We can observe the waveforms in a more intuitive

way. It is a prototype of a digital oscilloscope.

8-channel 200K sampling 16-bit ADC module

Expected results of the experiment

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Experimental Principle

The AD7606 is an integrated 8-channel simultaneous sampling data acquisition system that integrates input amplifiers, overvoltage protection

circuits, second-order analog antialiasing filters, analog multiplexers, a 16-bit 200 kSPS SAR ADC and a digital filter, 2.5 V reference voltage source,

reference voltage buffer, and high speed serial and parallel interfaces.

The AD7606 is powered by a single +5V power supply and can handle ±10V and ±5V true bipolar input signals.

Sampling at throughput rates up to 200KSPS. Input clamp protection circuitry can tolerate voltages up to ±16.5V.

Regardless of the sampling frequency, the analog input impedance of AD7606 is 1M ohm. It uses a single power supply.

On-chip filtering and high input impedance eliminate the need for a driver op amp and external bipolar power supply.

The AD7606 anti-aliasing filter has a 3dB cutoff frequency of 22kHz; when the sampling rate is 200kSPS, it has a 40dB anti-aliasing filter.

Aliasing suppression features. Flexible digital filters are pin-driven to improve signal-to-noise ratio (SNR) and reduce 3dB bandwidth.

17.1.1 AD7606 Timing

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The AD7606 can sample all eight analog input channels simultaneously.

CONVSTB) together, all channels are sampled synchronously. The rising edge of this common CONVST signal starts sampling on all analog inputs.

Synchronous sampling of channels (V1 to V8).

AD7606 has an internal oscillator for conversion. The conversion time for all ADC channels is tCONV. The BUSY signal

The user knows that the conversion is in progress, so when the rising edge of CONVST is applied, BUSY becomes a logic high level.

The falling edge of the BUSY signal is used to return all eight sample-and-hold amplifiers to tracking mode.

The falling edge also indicates that the data of the 8 channels can now be read from the parallel bus DB[15:0].

17.1.2 AD7606 Configuration

In the AN706 8-channel AD module hardware circuit design, we add pull-up resistors to the three configuration pins of AD7606.

Or pull-down resistor to set the operating mode of AD7606.

The AD7606 chip supports external reference voltage input or internal reference voltage. If an external reference voltage is used, the chip

REFIN/REFOUT requires an external 2.5V reference source. If the internal reference voltage is used, the REFIN/REFOUT pin is

The internal reference voltage output is 2.5V. The REF SELECT pin is used to select the internal reference voltage or the external reference voltage.

In the circuit design, the internal reference voltage of AD7606 is chosen because of its high accuracy (2.49V~2.505V).

An internal reference voltage is used.

Pin Foot name Setting the Level illustrate

REF SELECT
High level Using the internal reference voltage 2.5V

The AD7606 AD conversion data acquisition can be in parallel mode or serial mode. The user can set

PAR/SER/BYTE SEL pin level to set the communication mode. When we design, we choose parallel mode to read AD7606

AD data.

Pin Foot name Setting the Level illustrate

PAR/SER/BYTE SEL
Low level Select Parallel Interface

The input range of the AD7606 AD analog signal can be set to ±5V or ±10V. When the ±5V input range is set,

1LSB=152.58uV; when the input range is set to ±10V, 1LSB=305.175uV. Users can set the RANGE pin voltage

When designing, we choose the analog voltage input range of ±5V.

Pin Foot name Setting the Level illustrate

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RANGE
Low level Analog signal input range selection: ±5V

The AD7606 contains an optional digital first-order sinc filter that can be used in applications where lower throughput rates are used or where a higher signal-to-noise ratio is required.

In the case of oversampling, a filter should be used. The oversampling ratio of the digital filter is controlled by the oversampling pin OS[2:0]. The following table provides the

oversampling bit decoding to select different oversampling ratios.

In the hardware design of the AN706 module, OS[2:0] has been introduced to the external interface, and the FPGA or CPU can control

The OS[2:0] pin level is used to select whether to use the filter to achieve higher measurement accuracy.

17.1.3 AD7606 AD Conversion

The output coding of AD7606 is two's complement. The designed code conversion is in the middle of consecutive LSB integers (i.e. 1/2LSB).

and 3/2LSB). The LSB size of AD7606 is FSR/65536. The ideal transfer characteristic of AD7606 is shown in the figure below:

Programming

The display part of this experiment is based on the previous HDMI display color bar experiment. Grid lines and waveforms are superimposed on the color bar.

The block diagram of the project is shown below:

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video_pll

Second Road
First Road

Grid Line Overlay AD waveform superposition

AD waveform superposition

video_r wave0_r wave1_r

grid_r
video_g wave0_g wave1_g TMDS HDMI
grid_g
video_b wav_dis wave1_b wave0_b Display
color_b grid_b wav_dis SI9134
video_hs wave0_hs play wave1_hs
ar grid_displaygrid_hs play
video_vs wave0_vs wave1_vs
grid_vs
video_de wave0_de wave1_de
grid_de

buf_addr
buf_data
buf_addr
buf_data

buf_wr
buf_wr

SDA

SCL
adc_pll i2c_config
ad7606_sample ad7606_sample
Channel 1 acquisition Channel 2 acquisition

ad7606_if

AN706 Module

The ad7606_if module is the interface module of AN706, which completes the data acquisition of 8-way AD input of AD706.

The timing of the AD706 chip generates the AD conversion signal ad_convstab, and after the ADC busy signal is invalid, it generates the chip select signal.

Read 8 channels of AD data in sequence.

Signal Name Direction Width illustrate

(bit)
clk in
1 System clock
rst_n in
1 Asynchronous reset, low reset
adc_data in 16
ADC Data Input
ad_busy in 1
ADC busy signal

first_data in
1 The first channel data indication signal
ad_os out 3
ADC Oversampling

ad_cs out 1
ADC chip select

ad_rd out 1
ADC read signal

ad_reset out 1
ADC reset signal
ad_convstab out 1
ADC converts the signal

adc_data_valid in 1
ADC data valid
ad_ch1 out 16
ADC Channel 1 Data
ad_ch2 out 16
ADC Channel 2 Data

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ad_ch3 out 16
ADC channel 3 data
ad_ch4 out 16
ADC Channel 4 Data
ad_ch5 out 16
ADC channel 5 data
ad_ch6 out 16
ADC channel 6 data
ad_ch7 out 16
ADC channel 7 data
ad_ch8 out 16
ADC channel 8 data

The ad7606_sample module mainly completes the single-channel data conversion of ad706. First, the input data needs to be converted to unsigned

The last data is the high 8 bits, and the data width is converted to 8 bits (to be compatible with other 8-bit AD module programs).

In addition, 1280 data are collected each time, and then the next 1280 data are collected after a period of time.

Signal Name Direction Width illustrate

(bit)
adc_clk in 1
adc system clock
rst in
1 Asynchronous reset, high reset
adc_data in 16
ADC Data Input
adc_data_valid in 1
adc data valid
adc_buf_wr out 1
ADC data write enable

adc_buf_addr out 12
ADC data write address

adc_buf_data out
8 Unsigned 8-bit ADC data

ad7606_sample module ports

The grid_display module mainly completes the grid line overlay of the video image. In this experiment, the color bar video is input and then overlaid with a

The grid area is used by the waveform display module.

Video display positions from 9 to 1018 horizontally (left to right) and from 9 to 308 vertically (top to bottom).

Signal Name Direction Width illustrate

(bit)
pclk in
1 Pixel Clock
rst_n in
1 Asynchronous reset, low level reset
i_hs in
1 Video line sync input
i_vs in
1 Video field sync input
i_de in
1 Video data valid input
i_data in
24 Video data input
o_hs out
1 Video line sync output with grid
o_vs out
1 Video field sync output with grid
o_de out
1 Valid output of grid video data
o_data out
24-band grid video data output

grid_display module ports

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The wav_display display module is mainly used to complete the superposition display of waveform data. The module contains a dual-port RAM, write port

It is written by the ADC acquisition module, and the read port is the display module. When the grid display area is valid, each line of display will read

Get the AD data value stored in RAM and compare it with the Y coordinate to determine whether to display the waveform or not.

Signal Name Direction Width illustrate

(bit)
pclk in
1 Pixel Clock
rst_n in
1 Asynchronous reset, low level reset
wave_color in twenty four

Waveform color, rgb

adc_clk in 1
adc module clock

adc_buf_wr in 1
adc data write enable

adc_buf_addr in 12
adc data write address

adc_buf_data in 8
adc data, unsigned
i_hs in
1 Video line sync input
i_vs in
1 Video field sync input
i_de in
1 Video data valid input
i_data in
24 Video data input
o_hs out
1 Video line sync output with grid
o_vs out
1 Video field sync output with grid
o_de out
1 Valid output of grid video data
o_data out
24-band grid video data output

wav_display module ports

The RAM configuration is as follows:

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The timing_gen_xy module is a submodule of other modules, which completes the coordinate generation of the video image, the x coordinate, increasing from left to right.

The y coordinate increases from top to bottom.

Signal name Direction Width illustrate

(bit)
clk in
1 System clock
rst_n in
1 Asynchronous reset, low level reset
i_hs in
1 Video line sync input
i_vs in
1 Video field sync input
i_de in
1 Video data valid input
i_data in
24 Video data input
o_hs out
1 Video line sync output
o_vs out
1 Video field sync output
o_de out
1 Video data is output effectively
o_data out
24 Video data output
x out
12 Coordinate x output
y out
12 Coordinate y output

timing_gen_xy module ports

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Experimental phenomenon

The connection circuit is as follows. Insert the AN706 module and connect the SMA to the waveform generator. In order to observe the display effect conveniently, the

waveform generator sampling frequency is set in the range of 500Hz~10KHz, and the maximum voltage amplitude is 10V. The result is the effect diagram at the beginning of

this chapter.

Hardware connection diagram

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Chapter 18 AD9238 Dual Channel Waveform Display Experiment

The experimental Vivado project is "ad9238_hdmi_test".

Hardware Introduction

18.1.1 Two-channel AD module description

BlackGold high-speed AD module AN9238 is a 2-channel 65MSPS, 12-bit analog signal to digital signal converter

The module uses the AD9238 chip from ADI Company for AD conversion. The AD9238 chip supports 2

The module supports 2-channel AD input conversion, so one AD9238 chip supports 2-channel AD input conversion. The analog signal

input supports single-ended analog signal input, the input voltage range is -5V~+5V, and the interface is an SMA socket. The module

has a standard 2.54mm pitch 40-pin female header for connecting to the FPGA development board.

The actual photos of the AN9238 module are as follows:

AN9238 module physical picture

Parameter

Description The following are the detailed parameters of the AN9238

high-speed AD module: ÿ AD conversion chip:

1 piece of AD9238 ÿ AD conversion

channels: 2 channels; ÿ AD sampling rate:

65MSPS; ÿ AD sampling data bit number: 12 bits;

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ÿ Digital interface level standard: +3.3V CMOS level

ÿ AD analog signal input range: -5V~+5V;

ÿ Analog signal input interface: SMA interface;

ÿ Measurement accuracy: about 10mV;

ÿ Working temperature: -40°~85°;

18.1.2 Module Function Description

The principle design block diagram of the AN9238 module is as follows:

AD1 Input
SMA
12-bit AD1 data interface Single-ended to
Op amp SMA
differential
AD8065 interface
SMA
40 40

AD8138

65M AD1 clock interface

Needle
Needle

Row
Row Dual channel AD chip

mother
mother
12-bit AD2 data AD9238 AD2 Input

even SMA
even
Single-ended to
catch interface Op amp
catch SMA
differential
Device
Device 65M AD2 clock AD8065 interface
SMA AD8138

interface

For the specific reference design of AD9238 circuit, please refer to the chip manual of AD9238.

1) Single-ended input and op amp circuit

Single-ended input AD1 and AD2 are input through two SMA connectors J5 or J6. The voltage of single-ended input is

-5V~+5V.

The AD8065 chip and the voltage divider resistor on the board reduce the -5V~+5V input voltage to -1V~+1V. If

the user wants to input a wider range of voltage input, just modify the resistance value of the voltage divider resistor at the front end.

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The following table is a comparison table of analog input signals and the voltage after the AD8065 op amp output:

AD analog input value AD8065 op amp output

-5V -1V

0V 0V

+5V +1V

2) Single-ended to differential and AD conversion

The input voltage of -1V~+1V is converted into a differential signal (VIN+ ÿ VIN

ÿ), the common mode level of the differential signal is determined by the CML pin of AD.

The following table is a voltage comparison table from analog input signal to AD8138 differential output:

AD analog input value AD8065 op amp output AD8138 differential output (VIN+ÿ

VINÿ

-5V -1V -1V

0V 0V 0V

+5V +1V +1V

3) AD9238 conversion

By default, AD is configured as offset binary. The value of AD conversion is shown in the figure below:

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In the module circuit design, the VREF value of AD9238 is 1V, so the final analog signal input

And the AD conversion data are as follows:

AD analog input AD8055 Op Amp AD8138 Differential Output AD9238 Digital

Input value Output (VIN+ÿVINÿ) Output

-5V -1V -1V 000000000000

0V 0V 0V 100000000000

+5V +1V +1V 11111111111

From the table we can see that when -5V is input, the digital value converted by AD9238 is the smallest, and +5V is the smallest.

When input, the digital value converted by AD9238 is the largest.

4) AD9238 digital output timing

The digital output of the AD9238 dual-channel AD is a +3.3V CMOS output mode, with two channels (A and

B) Independent data and clock. AD data is converted on the rising and falling edges of the clock. When AD is available on the FPGA side

The sampled AD data is clocked.

Programming

The display part of this experiment is based on the previous HDMI display color bar experiment. Grid lines and waveforms are superimposed on the color bar.

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The block diagram of the project is shown below:

video_pll

Second Road
First Road
Grid Line Overlay AD waveform superposition
AD waveform superposition

video_r wave0_r wave1_r

grid_r
video_g grid_g
wave0_g wave1_g TMDS HDMI
video_b wave0_b wav_dis wave1_b Display
color_b grid_b wav_dis SI9134
wave0_hs play
ar video_hs video_vs grid_displaygrid_hs play wave1_hs
video_de wave0_vs wave1_vs
grid_vs
wave0_de wave1_de
grid_de

buf_addr
buf_data
buf_addr
buf_data

buf_wr
buf_wr
adc_pll ad9238_sample
ad9238_sample
Channel 1 acquisition Channel 2 acquisition

AN9238 Module

The ad9238_sample module mainly completes the single-channel data conversion of AN9238. The final data only takes the high 8 bits.

The data width is converted to 8 bits (to be compatible with other 8-bit AD module programs). In addition, 1280 data are collected each time.

Then wait for a while and continue to collect the next 1280 data.

Signal Name Direction Width illustrate

(bit)
adc_clk in 1
adc system clock
rst in
1 Asynchronous reset, high reset

adc_data in 12
ADC Data Input

adc_buf_wr out 1
ADC data write enable

adc_buf_addr out 12
ADC data write address

adc_buf_data out
8 Unsigned 8-bit ADC data

ad7606_sample module ports

The grid_display module mainly completes the grid line overlay of the video image. In this experiment, the color bar video is input and then overlaid with a

The grid area is used by the waveform display module.

Video display positions from 9 to 1018 horizontally (left to right) and from 9 to 308 vertically (top to bottom).

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Signal Name Direction Width illustrate

(bit)
pclk in
1 Pixel Clock
rst_n in
1 Asynchronous reset, low level reset
i_hs in
1 Video line sync input
i_vs in
1 Video field sync input
i_de in
1 Video data valid input
i_data in
24 Video data input
o_hs out
1 Video line sync output with grid
o_vs out
1 Video field sync output with grid
o_de out
1 Valid output of grid video data
o_data out
24-band grid video data output

grid_display module ports

The wav_display display module is mainly used to complete the superposition display of waveform data. The module contains a dual-port RAM, write port

It is written by the ADC acquisition module, and the read port is the display module. When the grid display area is valid, each line of display will read

Get the AD data value stored in RAM and compare it with the Y coordinate to determine whether to display the waveform or not.

Signal Name Direction Width illustrate

(bit)
pclk in
1 Pixel Clock
rst_n in
1 Asynchronous reset, low level reset
wave_color in twenty four

Waveform color, rgb

adc_clk in 1
adc module clock

adc_buf_wr in 1
adc data write enable

adc_buf_addr in 12
adc data write address

adc_buf_data in 8
adc data, unsigned
i_hs in
1 Video line sync input
i_vs in
1 Video field sync input
i_de in
1 Video data valid input
i_data in
24 Video data input
o_hs out
1 Video line sync output with grid
o_vs out
1 Video field sync output with grid

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o_de out
1 Valid output of grid video data
o_data out
24-band grid video data output

wav_display module ports

The RAM configuration is as follows:

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The timing_gen_xy module is a submodule of other modules, which completes the coordinate generation of the video image, the x coordinate, increasing from left to right.

The y coordinate increases from top to bottom.

Signal name Direction Width illustrate

(bit)
clk in
1 System clock
rst_n in
1 Asynchronous reset, low level reset
i_hs in
1 Video line sync input
i_vs in
1 Video field sync input
i_de in
1 Video data valid input
i_data in
24 Video data input
o_hs out
1 Video line sync output
o_vs out
1 Video field sync output
o_de out
1 Video data is output effectively
o_data out
24 Video data output
x out
12 Coordinate x output
y out
12 Coordinate y output

timing_gen_xy module ports

Experimental phenomenon

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The circuit is connected as follows. Adjust the frequency and amplitude of the signal generator. The input range of AN9238 is -5V-5V. For easy observation

Waveform data, the recommended signal input frequency is 200Khz to 1Mhz. Observe the display output, the red waveform is CH1 input, the blue is CH2 input,

the top horizontal line of the yellow grid represents 5V, the bottom horizontal line represents -5V, the middle horizontal line represents 0V, and each vertical line

interval is 10 sampling points.

Hardware connection diagram

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Chapter 19 ADDA Test Experiment

The experimental Vivado project is “an108_adda_hdmi_test”.

This experiment uses ADC and DAC. The ADDA module model used in the experiment is AN108. The maximum sampling rate of ADC is 32Mhz,

the precision is 8 bits, and the maximum sampling rate of DAC is 125Mhz, the precision is 8 bits. In the experiment, DAC is used to output sine waves, and

then ADC is used to collect and display the waveform on the HDMI display.

ADDA Module

Expected results of the experiment

Hardware Introduction

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19.1.1 Digital-to-Analog Conversion (DA) Circuit

As shown in the hardware structure diagram, the DA circuit consists of a high-speed DA chip, a 7th-order Butterworth low-pass filter, an amplitude

adjustment circuit, and a signal

output interface. The high-speed DA chip we use is the AD9708 launched by AD. AD9708 is an 8-bit, 125MSPS DA conversion chip with a built-in

1.2V reference voltage and differential current output. The internal structure of the chip is shown in the figure below.

After the AD9708 chip differential output, in order to prevent noise interference, a 7th-order Butterworth low-pass filter is connected to the circuit.

The bandwidth is 40MHz and the frequency response is shown in the figure below

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The filter parameters are shown in the figure below.

After the filter, we used two high-performance 145MHz bandwidth AD8056 op amps to convert differential to single-ended, and

The amplitude adjustment function maximizes the performance of the entire circuit. A 5K potentiometer is used for amplitude adjustment.

The final output range is -5V~5V (10Vpp).

Note: Since the accuracy of the circuit is not very precise, the final output has a certain error, and it is possible that the waveform amplitude cannot reach

10Vpp, there may also be problems such as waveform clipping, which are all normal
.

19.1.2 Analog-to-Digital Conversion (AD) Circuit

As shown in the hardware structure diagram, the AD circuit consists of a high-speed AD chip, an attenuation circuit, and a signal input interface.

The high-speed AD chip we use is the 8-bit AD9280 chip launched by AD Company with a maximum sampling rate of 32MSPS.

The internal structure is shown in the figure below

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According to the configuration in the figure below, we set the AD voltage input range to: 0V~2V

Before the signal enters the AD chip, we use an AD8056 chip to build an attenuation circuit. The input range of the interface is -

5V~+5V(10Vpp). After attenuation, the input range meets the input range of the AD chip (0~2V). The conversion formula is as follows:

When the input signal Vin=5(V), the signal Vad input to AD=2(V); When the input signal

Vin=-5(V), the signal Vad input to AD=0(V);

Programming

The program design of this experiment is basically similar to the AN706 waveform display experiment, except that the ADDA module is a single-

channel AD, and here it is just the superposition of the collected waveforms. In addition, the FPGA generates sine wave data through the ROM IP and outputs

it to the DA chip for DA conversion to generate a positive wave analog signal. The user only needs to connect the AD and DA ports of the module with a

BNC line to form a loop. In this way, the DA positive wave signal is displayed on the HDMI display.

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video_pll

Grid Line Overlay AD waveform superposition

video_r grid_r wave0_r

video_g wave0_g TMDS HDMI Display
grid_g

color_b
video_b grid_displaygrid_b wav_dis wave0_b play
SI9134
arvideo_hs video_vs grid_hs wave0_hs
video_de grid_vs wave0_vs

grid_de wave0_de

buf_addr

SDA

SCL
buf_wr
dac_clk adc_clk buf_data
ad9280_sample i2c_confi
ROM adc_pll
g
DA output AD Collection

ADDA module

The ad9280_sample module mainly completes the AD 8-bit data acquisition and conversion of ad9280, collecting 1280 data each time.

Then wait for a while before collecting the next 1280 data.

Signal Name Direction Width illustrate

(bit)
adc_clk in 1
adc system clock
rst in
1 Asynchronous reset, high reset
adc_data in 8
ADC Data Input
adc_buf_wr out 1
ADC data write enable

adc_buf_addr out 12
ADC data write address

adc_buf_data out
8 Unsigned 8-bit ADC data

ad9280_sample module ports

The grid_display module mainly completes the grid line overlay of the video image. In this experiment, the color bar video is input and then overlaid with a

The grid area is used by the waveform display module.

Video display positions from 9 to 1018 horizontally (left to right) and from 9 to 308 vertically (top to bottom).

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Signal Name Direction Width illustrate

(bit)
pclk in
1 Pixel Clock
rst_n in
1 Asynchronous reset, low level reset
i_hs in
1 Video line sync input
i_vs in
1 Video field sync input
i_de in
1 Video data valid input
i_data in
24 Video data input
o_hs out
1 Video line sync output with grid
o_vs out
1 Video field sync output with grid
o_de out
1 Valid output of grid video data
o_data out
24-band grid video data output

grid_display module ports

The wav_display display module is mainly used to complete the superposition display of waveform data. The module contains a dual-port RAM, write port

It is written by the ADC acquisition module, and the read port is the display module. When the grid display area is valid, each line of display will read

Get the AD data value stored in RAM and compare it with the Y coordinate to determine whether to display the waveform or not.

Signal Name Direction Width illustrate

(bit)
pclk in
1 Pixel Clock
rst_n in
1 Asynchronous reset, low level reset
wave_color in twenty four

Waveform color, rgb

adc_clk in 1
adc module clock

adc_buf_wr in 1
adc data write enable

adc_buf_addr in 12
adc data write address

adc_buf_data in 8
adc data, unsigned
i_hs in
1 Video line sync input
i_vs in
1 Video field sync input
i_de in
1 Video data valid input
i_data in
24 Video data input
o_hs out
1 Video line sync output with grid
o_vs out
1 Video field sync output with grid

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o_de out
1 Valid output of grid video data
o_data out
24-band grid video data output

wav_display module ports

The timing_gen_xy module is a submodule of other modules, which completes the coordinate generation of the video image, the x coordinate, increasing from left to right.

The y coordinate increases from top to bottom.

Signal Name Direction Width illustrate

(bit)
clk in
1 System clock
rst_n in
1 Asynchronous reset, low level reset
i_hs in
1 Video line sync input
i_vs in
1 Video field sync input
i_de in
1 Video data valid input
i_data in
24 Video data input
o_hs out
1 Video line sync output
o_vs out
1 Video field sync output
o_de out
1 Video data is output effectively
o_data out
24 Video data output
x out
12 Coordinate x output
y out
12 Coordinate y output

timing_gen_xy module ports

In addition, a ROM IP module is added in this example, and the ROM IP needs to be initialized with data.

Use the waveform data generation tool and find the tool in the software tools and driver folder. Its icon is as follows:

1. Double-click .exe to open the tool. The interface is as follows:

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2. You can select the waveform as needed. In this example, a sine wave is selected and the data length and bit width remain the default

3. Click the Save button to save the generated data file to the project directory file (pay attention to the saved file type):

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4. After saving, the following dialog box appears, indicating that the save is successful. Click OK to close the tool.

Save the .coe file to the generated Rom IP core. I will not repeat it here.

Experimental phenomenon

Connect the DAC input of AN108 to the output of the signal generator. Here we use a special shielded wire. If you use other

.
The line may have a large interference

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AN108 Connection Diagram

Hardware connection diagram

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Chapter 20 AD9767 Dual Channel Sine Wave Generation Experiment

The experimental Vivado project is “ad9767_dual_sin_wave”.

This chapter introduces the experiment of using AN9767 module to realize two-way sine wave generation.

Hardware Introduction

The dual-channel 14-bit DA output module AN9767 uses the AD9767 chip from ANALOG DEVICES and supports independent

Dual-channel, 14-bit, 125MSPS digital-to-analog conversion. The module has a 40-pin female header for connecting to the FPGA development

board and 2 BNC connectors for analog signal output.

The actual photos of the AN9767 module are as follows:

AN9767 module front view

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AN9767 module back view

20.1.1 AN9767 module parameter description

The following are the detailed parameters of the AN9767 dual-

channel DA module: ÿ DA conversion chip:

AD9767; ÿ Number of channels:

2 channels; ÿ DA conversion bit: 14bit;

ÿ DA update rate: 125 MSPS; ÿ Output voltage

range: -5V~+5V; ÿ Number of module PCB

layers: 4 layers, independent power layer and GND layer; ÿ Module interface: 40-

pin 2.54mm pitch socket, facing downward; ÿ Operating temperature: -40°~85°

The chips used in the module meet the industrial temperature range ÿ Output interface: 2 BNC

analog output interfaces (can be directly connected to an oscilloscope using a BNC cable);

20.1.2 AN9767 Module Block Diagram

The principle design block diagram of the AN9767 module is as follows:

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5V input voltage AM1117 MC34063A MC34063A

3.3V voltage +6V voltage -6V voltage

40 40

Needle
Needle
AD
AD

number
number
First
amp stage op
First stage Second
Second stage
stage op
op amp
amp
according
accordingtoto Low pass filter BBNNCC interface
op amp (current
voltage) (currenttoto voltage) (voltage
(Voltageamplification)
Amplification)
lose
lose

out
out
High
DAC -High-speed
speed dual-channel
dual-
Expand
Expand

channel
DAC chip
exhibition
exhibition

AD9767
AD9767
mouth
mouth

First
amp stage op
First stage Second
Second stage
stage op
op amp
amp
Low pass filter BBNNCC interface
op amp (current
voltage) (currenttoto voltage) (voltage
(voltage amplification)
amplification)

20.1.3 AD9767 Chip Introduction

The AD9767 is a dual-port, high speed, dual-channel, 14-bit CMOS DAC that integrates two high quality TxDAC+® cores,

The device provides excellent AC and DC performance.

The AD9767 can support an update rate of up to 125 MSPS. The functional block diagram of the AD9767 is as follows:

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20.1.4 Current-voltage conversion and amplification

The two DA outputs of AD9767 are both current outputs IoutA and IoutB in the form of complementary code.

When the DAC input 14-bit data is high, IoutA outputs the full-scale current output of 20mA.

The current is 0mA. The specific relationship between the current and the DAC data is shown in the following formula:

Where IoutFS = 32 x Iref. In the AN9767 module design, the value of Iref is determined by the value of resistor R16. If

R16=19.2K, then the value of Iref is 0.625mA, and the value of IoutFS is 20mA.

The current output by AD9767 is converted into a voltage of -1V~+1V through the first-stage operational amplifier AD6045. The specific conversion circuit is as follows

As shown in the figure:

The -1V~+1V voltage converted by the first stage op amp is converted to a higher amplitude voltage signal by the second stage op amp.

The amplitude of the amplifier can be changed by adjusting the adjustable resistor on the board. Through the second stage op amp, the output range of the analog signal is high

Reach -5V~+5V.

The following table is a comparison table of digital input signals and voltages after output of each level of op amp:

DAC Data Input Value AD9767 Current Output First Stage Op Amp Output Second Stage Op Amp Output

+20mA -1V +5V

3fff(14-bit full height)

-20mA +1V -5V

0 (14 bits all low)

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0mA 0V 0V
2000 (median value)

20.1.5 Current-voltage conversion and amplification

The digital interface of the AD9767 chip can be configured into dual-port mode (Dual) or alternating mode (AC) through the chip's mode pin (MODE).

In the AN9767 module design, the AD9767 chip works in dual-port mode, with dual-channel DA

The digital input interface is independent and separated. The data timing diagram of dual port mode (Dual) is shown below:

The DA data for the AD9767 chip is input to the chip through the rising edge of the clock CLK and the write signal WRT for DA conversion.

Change.

Programming

The example program provides the DA test program of the AN9767 module, which can realize the input of the sine wave signal through the AN9767 module.

out.

The positive wave test program reads the positive wave data stored in a ROM inside the FPGA, and then

The data is output to the AN9767 module for digital-to-analog conversion, thereby obtaining the analog signal of the positive selection wave.

The schematic diagram is as follows:

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DAC1

AN9767 BNC cable

PLL ROM Oscilloscope

Module
DAC2

FPGA

Development Boards

20.2.1 Generate ROM initialization file

In the program we will use a ROM to store 1024 14-bit sine wave data. First we need to prepare the ROM

Initialization file (if it is ALTERA development board, it is mif file; if it is Xilinx development board, it is coe file).

The following is the method to generate a sine wave ROM data file:

Find the tool in the software tools and drivers folder, its icon is as follows:

1. Double-click .exe to open the tool. The interface is as follows:

2. You can select the waveform as needed. In this example, a sine wave is selected, the data length is 1024, the data bit width is 14, and the others are the default:

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3. Click the Save button to save the generated data file to the project directory (pay attention to the saved file type):

4. After saving, the following dialog box appears, indicating that the save is successful. Click OK to close the tool.

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Save the .coe file to the generated Rom IP core. This has been introduced in the character display experiment tutorial and will not be repeated here.

repeat.

20.2.2 Dual-channel sine wave generator program

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////////////////
//Two sine wave outputs -10V ~ +10V
///////////////////////////////////////////////////////////////////////////////////////
module ad9767_test
(
//Differential system clock
input sys_clk_p,
input sys_clk_n,
output da1_clk, output //AD9767 CH1 clock
da1_wrt, //AD9767 CH1 enable
output [13:0] da1_data, //AD9767 CH1 data output

output da2_clk, output //AD9767 CH2 clock

da2_wrt, output [13:0] //AD9767 CH2 enable
da2_data //AD9767 CH2 data output

);

reg [9:0] rom_addr;

wire [13:0] rom_data;

wire clk_125M;

assign da1_clk=clk_125M;
assign da1_wrt=clk_125M;
assign da1_data=rom_data;

assign da2_clk=clk_125M;
assign da2_wrt=clk_125M;

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assign da2_data=rom_data;

//DA output sin waveform

always @(negedge clk_125M)
begin
rom_addr <= rom_addr + 1'b1 ; // rom_addr <= //The output sine wave frequency is 122Khz
rom_addr + 4; //The output sine wave frequency is 488Khz
// rom_addr <= rom_addr + 128; //The output sine wave frequency is 15.6Mhz end

ROM ROM_inst
(
.clka(clk_125M), // input clka
.addra(rom_addr), // input [8 : 0] addra
.douta(rom_data) // output [7 : 0] douta
);

PLL PLL_inst
(// Clock in ports
.clk_in1_p (sys_clk_p .clk_in1_n // IN
(sys_clk_n // Clock out ports ), ), // IN

.clk_out1 ( .clk_out2 //OUT

(clk_125M // Status and control ), ), //OUT
signals
.reset (1'b0 ( ), ) // IN
.locked
);

endmodule
The program generates a 125M DA output clock through a PLL IP, and then cyclically reads the 125M DA output clock stored in the ROM.

1024 data, and output to the DA data lines of channel 1 and channel 2 at the same time. In the program, you can add 1 to the address.

4, or add 128 to select the output of a sine wave of different frequencies.

Experimental phenomenon

Insert the AN9767 module into the J11 expansion port of the development board, and use the BNC cable we provide to connect the output of the AN9767 to the

The input of the oscilloscope is as shown below. Then power on the development board, download the program and observe the analog signal output from the DA module on the oscilloscope.

The waveform of the number.

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Hardware connection diagram

The sine wave seen on the oscilloscope is as follows:

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We can modify the address in the program to +4 as follows, so that the output point of the sine wave is

256, the frequency of the output sine wave will increase by 4 times:

After the program is modified and the FPGA is re-downloaded, the frequency of the sine wave becomes higher, and the waveform displayed by the oscilloscope is as follows:

Users can also change the amplitude of the 2-channel output waveform by adjusting the adjustable resistor on the AN9767 module.

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